Driving integrated circuit for display

Abstract

A driving integrated circuit for a display using a MIM capacitor configuration is disclosed. The driving integrated circuit includes a first circuit formed in a first area of a substrate on a chip, a second circuit formed in a second area of the substrate on the chip, a first MIM capacitor formed in a first layer above the substrate and having a first capacitance for the first circuit, and a second MIM capacitor formed in a second layer above the substrate and having a second capacitance for the second circuit.

Description

Technical Field

[0001] This disclosure relates to a driver integrated circuit for a display, and more specifically, to a driver integrated circuit for a display using a metal-insulator-metal (hereinafter referred to as "MIM") capacitor configuration. Background Technology

[0002] The display includes a driver integrated circuit that converts display data into source signals and provides the source signals to the display panel.

[0003] The driver integrated circuit has the configuration to drive and recover the display data provided by the timing controller, convert the recovered display data into a source signal with corresponding grayscale, and provide the source signal to the display panel.

[0004] Therefore, the driver integrated circuit includes a data processing circuit for converting display data into source signals, a channel circuit for outputting source signals to the display panel, and an electrostatic discharge (ESD) circuit for protecting internal circuits from ESD.

[0005] Driver integrated circuits can be configured to use full-scale drive voltage, half-scale drive voltage (i.e., the intermediate voltage of the drive voltage), etc. For example, data processing circuits can be configured to use half-scale drive voltage to reduce power consumption. Channel circuits can be configured to use full-scale drive voltage to output source signals.

[0006] Capacitors are needed for purposes such as stabilizing drive signals, driving integrated circuits' data processing circuits, channel circuits, and ESD circuits.

[0007] In driver integrated circuits, data processing circuits, channel circuits, and ESD circuits are implemented on a semiconductor substrate. Multilayer metal layers for signal transmission, power supply, etc., are formed on the substrate.

[0008] Typically, if a capacitor is formed in a substrate, the capacitor needs to have an area that is larger than the size of other components such as transistors.

[0009] Therefore, if the data processing circuitry and channel circuitry are formed in the substrate and configured to include capacitors, the capacitors occupy a large area within the chip region.

[0010] Therefore, it is necessary to design driver integrated circuits that allow for the configuration of capacitors required for data processing circuits and channel circuits without occupying a large area. Summary of the Invention

[0011] Various implementations relate to providing a driver integrated circuit for a display that can reduce the area burden from capacitors.

[0012] Furthermore, various embodiments relate to providing a driver integrated circuit for a display, wherein the same type of MIM capacitors are used to configure capacitors for data processing circuitry and channel circuitry, and the driver integrated circuit can limit the increase in chip size from the capacitors.

[0013] Furthermore, various embodiments relate to providing a driver integrated circuit for a display that can have a reduced chip size by forming MIM capacitors according to data processing circuitry and channel circuitry and forming MIM capacitors in a metal layer in a substrate region in each of the data processing circuitry and channel circuitry.

[0014] In one embodiment, the driving integrated circuit for a display includes: a first circuit formed in a first region of a substrate on a chip; a second circuit formed in a second region of the substrate on a chip; a first MIM capacitor formed in a first layer above the substrate and having a first capacitance for the first circuit; and a second MIM capacitor formed in a second layer above the substrate and having a second capacitance for the second circuit, wherein the first capacitance is formed to be larger than the second capacitance.

[0015] In one embodiment, the driving integrated circuit for a display includes: a channel circuit formed in a first region of a substrate on a chip and configured to drive a first signal using a first voltage level; a data processing circuit formed in a second region of the substrate on a chip and configured to drive a second signal using a second voltage level; a first MIM capacitor formed in a first layer above the substrate and located in the first region, and having a first capacitance for the channel circuit; and a second MIM capacitor formed in a second region of a second layer above the substrate, and having a second capacitance for the data processing circuit, wherein the second voltage level is lower than the first voltage level, and the first capacitance is formed to be greater than the second capacitance.

[0016] In the driver integrated circuit for a display according to an embodiment of the present disclosure, capacitors are formed in the overlapping portion of the regions within the data processing circuitry and the channel circuitry of the substrate. The capacitors are configured using the same type of MIM capacitors.

[0017] Therefore, the advantage of the driver integrated circuit for a display according to this disclosure is that the driver integrated circuit is configured to have a small area burden from the capacitor.

[0018] Furthermore, the driver integrated circuit for a display according to this disclosure uses a MIM capacitor capable of achieving high capacitance and having a smaller area than capacitors using MOS transistors. A MIM capacitor is formed for connection to a circuit, which corresponds to the upper portion of the area where data processing circuitry or channel circuitry is formed.

[0019] Therefore, the advantage of the driver integrated circuit for a display according to this disclosure is that it can limit the increase in chip size from the capacitor and has a reduced chip size. Attached Figure Description

[0020] Figure 1 This is a deployment diagram illustrating a preferred embodiment of a driver integrated circuit for a display according to the present disclosure.

[0021] Figure 2 This shows the MIM capacitor configuration in Figure 1 A cross-sectional view of the driver integrated circuit.

[0022] Figure 3 This is a cross-sectional view showing an example of a MIM capacitor configured to correspond to the data processing circuitry and the channel circuitry.

[0023] Figure 4 This is a cross-sectional view showing another example of the MIM capacitors configured to correspond to the data processing circuitry and the channel circuitry. Detailed Implementation

[0024] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be exhaustive and complete, and will fully convey the scope of this disclosure to those skilled in the art. Throughout this disclosure, like reference numerals denote like parts in the various drawings and embodiments.

[0025] The display includes Figure 1 The driver integrated circuit 10 converts display data into source signals and provides the source signals to the display panel.

[0026] The driver integrated circuit 10 may include various components, such as components provided by an external timing controller (not shown) for recovering display data, components for converting the recovered display data into source signals corresponding to grayscale, and components driven to provide source signals to the display panel. Furthermore, the components may be formed in a semiconductor substrate (hereinafter referred to as the "substrate") using semiconductor processes.

[0027] Figure 1 The driver integrated circuit 10 is shown to include a channel circuit 20, a data processing circuit 30, and an electrostatic discharge (ESD) circuit 40.

[0028] In this configuration, channel circuit 20 corresponds to a component configured to provide a source signal to the display panel. Data processing circuit 30 corresponds to a component configured to convert display data into a source signal corresponding to grayscale. ESD circuit 40 prevents static electricity, thus protecting channel circuit 20 or data processing circuit 30 from ESD effects.

[0029] like Figure 2 As shown, the channel circuit 20, the data processing circuit 30, and the ESD circuit 40 can be distributed and formed in partitioned areas of the substrate SUB, and each can be configured to include elements such as transistors, resistors, diodes, BJTs, and capacitors.

[0030] More specifically, the channel circuit 20 can be understood as a first circuit formed in a first region CH of the substrate SUB on the chip, and drives a first signal with a first voltage level having a maximum value of a drive voltage set to a preset level.

[0031] Furthermore, the data processing circuit 30 can be understood as a second circuit, which is formed in a second region IP of the substrate SUB on the chip, and drives the second signal at a second voltage level set to use a half-drive voltage (i.e., an intermediate voltage between the drive voltage and the ground voltage).

[0032] Therefore, it can be understood that the first voltage level is greater than the second voltage level, and the half-drive voltage has a level corresponding to 1 / 2 of the drive voltage.

[0033] Furthermore, the ESD circuit 40 can be understood as a third circuit formed in the substrate SUB corresponding to the third region ES of the chip.

[0034] As mentioned above, such as Figure 2 As shown, the first region CH, the second region IP, and the third region ES are different regions separated by a plane in the substrate SUB. These regions can be formed to be insulated from each other.

[0035] The ESD circuit 40 of the third region ES among these regions includes a capacitor C10. The capacitor C10 can be configured as a MOS capacitor.

[0036] Furthermore, multiple layers for transmitting signals, supplying power, etc., can be formed on the substrate SUB configured as described above. These multiple layers may include multiple metal layers.

[0037] More specifically, multiple layers ML1, ML2, and ML3 can be formed on the substrate SUB as described above. For the purpose of describing the implementation, the multiple layers ML1, ML2, and ML3 are referred to as metal layer ML1, metal layer ML2, and metal layer ML3.

[0038] Metal layers ML1, ML2, and ML3 are stacked sequentially on the substrate SUB. Typically, metal layers ML1, ML2, and ML3 are formed to be isolated from each other by an interlayer dielectric layer (not shown).

[0039] Each of the metal layers ML1, ML2, and ML3 is formed with a specific planar pattern for forming metal lines for transmitting signals or supplying power. Contacts / vias (not shown) formed to penetrate the interlayer dielectric layer can be formed at specific locations in each metal layer. Each of the metal layers ML1, ML2, and ML3 can transmit signals or supply power to an underlying element corresponding to one of the channel circuit 20, data processing circuit 30, and ESD circuit 40 via the contact / via.

[0040] Embodiments of this disclosure are configured to form MIM capacitors in metal layers ML2 and ML3, among metal layers ML1, ML2, and ML3.

[0041] Metal layer ML1 is formed close to substrate SUB. Therefore, if a MIM capacitor is formed in metal layer ML1, the MIM capacitor can affect the operation of the components formed in substrate SUB. Therefore, preferably, the MIM capacitors according to this disclosure are formed at a location isolated from substrate SUB, and at least one metal layer is interposed between them.

[0042] The driver integrated circuit 10 configured according to embodiments of the present disclosure includes a MIM capacitor capable of achieving high capacitance in a smaller area than a capacitor using a MOS transistor.

[0043] MIM capacitors are configured to correspond to each of the channel circuit 20 and the data processing circuit 30. The MIM capacitor corresponding to the channel circuit 20 may generally be referred to as the first MIM capacitor. The MIM capacitor corresponding to the data processing circuit 30 may generally be referred to as the second MIM capacitor.

[0044] Reference Figure 2 MIM capacitor C31, serving as the first MIM capacitor, has a first capacitance for the channel circuit 20 and is formed in the first layer above the substrate SUB, specifically within the first region CH of the metal layer ML3. Furthermore, MIM capacitors C20 and C32, serving as second MIM capacitors, have second capacitances for the data processing circuit 30 and are formed in the second region IP of the second layer above the substrate SUB. In this case, Figure 2 The second layer is shown to include metal layer ML2 and metal layer ML3, i.e., the unit layer.

[0045] The channel circuit 20 drives the first signal using a first voltage level having a maximum value of a drive voltage set to a preset level. The data processing circuit 30 drives the second signal using a second voltage level set to use a half-drive voltage (i.e., the intermediate voltage between the drive voltage and the ground voltage).

[0046] Specifically, it can be understood that the first voltage level lies between the ground voltage and the drive voltage. Furthermore, it can be understood that the second voltage level lies between the ground voltage and the half-drive voltage, or between the half-drive voltage and the drive voltage.

[0047] For example, the data processing circuit 30 drives a signal between the half-drive voltage and the drive voltage based on display data with positive polarity, and drives a second signal between the ground voltage and the half-drive voltage based on display data with negative polarity. Therefore, the data processing circuit 30 limits the maximum value of the voltage level of the second signal to the level of the half-drive voltage. Thus, the power used to drive the second signal can be reduced.

[0048] Furthermore, the channel circuit 20 receives signals from the data processing circuit 30 driven between the ground voltage and the half-drive voltage, or between the half-drive voltage and the drive voltage, and drives and outputs the source signal between the ground voltage and the drive voltage. That is, the channel circuit 20 drives the first signal using a first voltage level having a maximum value set to the drive voltage.

[0049] Therefore, the MIM capacitor C31, configured to correspond to the channel circuit 20, as the first MIM capacitor, needs to be designed to have a first capacitance by taking into account the first voltage level of the first signal. The MIM capacitors C20 and C32, configured to correspond to the data processing circuit 30, as the second MIM capacitors, need to be designed to have a second capacitance by taking into account the second voltage level of the second signal. In this case, it can be understood that the second capacitance is the capacitance formed by the combination of the two MIM capacitors C20 and C32, i.e., the capacitance of the second MIM capacitor.

[0050] Therefore, the first capacitance of the first MIM capacitor needs to be set to be greater than the second capacitance of the second MIM capacitor.

[0051] In this disclosure, each of the first MIM capacitor and the second MIM capacitor may be formed in one or more metal layers. If the first MIM capacitor and the second MIM capacitor are formed in multiple metal layers, each metal layer can be understood as a unit metal layer.

[0052] The first MIM capacitor and the second MIM capacitor can be formed in the same metal layer. In this case, it can be understood that the first MIM capacitor and the second MIM capacitor are formed with reference to MIM capacitors C31 and C32 formed in the metal layer ML3. In this case, MIM capacitors C31 and C32 can be formed to have the same maximum charging voltage and the same charging capacitance per unit area.

[0053] Furthermore, the first MIM capacitor and the second MIM capacitor can be formed in different metal layers. In this case, it can be understood that the first MIM capacitor and the second MIM capacitor are referenced... Figure 2 The MIM capacitor C31 is formed in the metal layer ML3 and the MIM capacitor C20 is formed in the metal layer ML2. In this case, the MIM capacitor C31 and the MIM capacitor C20 can be formed to have different maximum charging voltages and different charging capacitances per unit area.

[0054] refer to Figure 3 Describe the configuration in more detail.

[0055] exist Figure 3 In the MIM capacitor C31, the configuration includes a metal line M31 formed in the metal layer ML3, an insulating layer IN30, and a through-hole contact V30, as well as a metal line M41 in the metal layer ML3. The MIM capacitor C20 is configured to include a metal line M21 formed in the metal layer ML2, an insulating layer IN20, and a through-hole contact V20, as well as a metal line M32 in the metal layer ML3. It can be understood that... Figure 3 The MIM capacitor C31 and MIM capacitor C20 are shown to be formed in different metal layers.

[0056] One of the first MIM capacitor and the second MIM capacitor can be formed in a unit layer comprising two or more layers, and the other can be formed in one or more of the same layers as the unit layer comprising two or more layers. In this case, the first MIM capacitor and the second MIM capacitor can be respectively... Figure 2 The MIM capacitor C31 of the metal layer ML3 is understood as the first MIM capacitor, and the MIM capacitor C20 of the metal layer ML2 and the MIM capacitor C32 of the metal layer ML3 are understood as the second MIM capacitor.

[0057] Furthermore, the first MIM capacitor and the second MIM capacitor configured as described above can be connected in series or in parallel. That is, the first MIM capacitor and the second MIM capacitor can provide capacitance to the channel circuit 20 or the data processing circuit 30, while sharing some capacitance.

[0058] refer to Figure 4 It can be understood that each of the first and second MIM capacitors is configured into multiple layers. Figure 4 In Chinese, omission and Figure 3 Redundant descriptions of components that are identical to those in the original text.

[0059] exist Figure 4 In the implementation method, with Figure 3 In contrast, a layer of MIM capacitor is also disposed below the metal line M31 of the first region CH, i.e., in the metal layer ML2, and a layer of MIM capacitor is also disposed on the metal line M32 of the second region IP, i.e., in the metal layer ML3.

[0060] That is, with Figure 3 Compared to the MIM capacitor C31, the MIM capacitor C33 also includes a metal line M22 disposed in the metal layer ML2, an insulating layer IN21, and a through-hole contact V21.

[0061] In addition, with Figure 3 Compared to the MIM capacitor C20, the MIM capacitor C23 also includes a metal line M42, an insulating layer IN31, and a through-hole contact V31 disposed in the metal layer ML3.

[0062] Figure 4 An example is shown in which each of the first MIM capacitors in the first region CH and the second MIM capacitors in the second region IP is configured in multiple layers. Figure 4 The implementation includes a unit capacitor for each layer and has a structure in which the MIM capacitors are connected in series for each region.

[0063] Furthermore, the first MIM capacitor and the second MIM capacitor can be configured to be connected in series, in parallel, or in both series and parallel. For example, in Figure 2 In this configuration, all of the MIM capacitors C31 and C32 and C20 can be connected in series. The two MIM capacitors C32 and C20 connected in series to MIM capacitor C31 can be connected in parallel, and the two MIM capacitors C32 and C20 can be connected in parallel to MIM capacitor C31.

[0064] Besides the example, the first MIM capacitor and the second MIM capacitor can be configured to have various electrical connections depending on the manufacturer's intentions.

[0065] According to this disclosure, the driver integrated circuit 10 for a display is configured to provide capacitance to the channel circuit 20 and the data processing circuit 30 by using the same type of MIM capacitors overlapping in each region in which the channel circuit 20 and the data processing circuit 30 are formed, as described above.

[0066] Therefore, the channel circuit 20 and the data processing circuit 30 can ensure the necessary capacitance for the drive signal or output source signal by using the upper MIM capacitor. Thus, the driver integrated circuit can reduce the area burden from the capacitor.

[0067] Furthermore, MIM capacitors can achieve high capacitance and a smaller area than capacitors using MOS transistors.

[0068] Therefore, the advantage of driver integrated circuits is that they can limit the increase in chip size from capacitors and have a reduced chip size.

[0069] Although various embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the disclosure described herein should not be limited based on the described embodiments.

Claims

1. A driver integrated circuit for a display, comprising: A first circuit is formed in a first region of a substrate on the chip; A second circuit is formed in a second region of the substrate on the chip; A first MIM capacitor is formed in a first layer above the substrate and has a first capacitance for the first circuit. as well as A second MIM capacitor is formed in a second layer above the substrate and has a second capacitance for the second circuit. The first capacitor is formed to be larger than the second capacitor. in: The first circuit includes a channel circuit configured to drive a first signal using a first voltage level. The second circuit includes a data processing circuit configured to drive a second signal using a second voltage level, and The second voltage level is lower than the first voltage level.

2. The driver integrated circuit according to claim 1, wherein: The first MIM capacitor is formed in the first region, and The second MIM capacitor is formed in the second region.

3. The driver integrated circuit according to claim 1, wherein, The first layer and the second layer are different layers. The first MIM capacitor is formed in the first layer, and the second MIM capacitor is formed in the second layer.

4. The driver integrated circuit according to claim 1, wherein: The first MIM capacitor is formed in the first layer comprising at least two first unit layers, and The second MIM capacitor is formed in the same second layer as one or more of the first cell layers.

5. The driver integrated circuit according to claim 1, wherein: The second MIM capacitor is formed in the second layer, which comprises at least two layers of a second unit layer, and The first MIM capacitor is formed in the same first layer as one or more second cell layers.

6. The driver integrated circuit according to claim 1, wherein: At least one of the first MIM capacitor and the second MIM capacitor includes two or more unit MIM capacitors, and The first MIM capacitor and the second MIM capacitor are connected in series, in parallel, or in both series and parallel.

7. The driver integrated circuit according to claim 6, wherein, The two or more unit MIM capacitors are formed in the same layer.

8. The driver integrated circuit according to claim 6, wherein, The two or more unit MIM capacitors are formed in different layers.

9. The driver integrated circuit according to claim 1, wherein, The first layer and the second layer are formed at locations isolated from the substrate, and at least one metal layer is interposed between the first layer, the second layer, and the substrate.

10. The driver integrated circuit according to claim 1, wherein: The first voltage level has a maximum value of a drive voltage set to a preset level, and The second voltage level has a maximum value set as a half-drive voltage, which is the intermediate voltage between the drive voltage and the ground voltage.

11. The driver integrated circuit of claim 1, further comprising a third circuit formed in a third region of the substrate on the chip. in, The third circuit includes a MOS capacitor for preventing electrostatic discharge (ESD).

12. A driver integrated circuit for a display, comprising: A channel circuit is formed in a first region of a substrate on a chip and configured to drive a first signal using a first voltage level; A data processing circuit is formed in a second region of the substrate on the chip and configured to drive a second signal using a second voltage level; A first MIM capacitor is formed in a first layer above the substrate and located in the first region, and has a first capacitance for the channel circuit; as well as A second MIM capacitor is formed in a second layer above the substrate and located in the second region, and has a second capacitance for the data processing circuit. Wherein, the second voltage level is lower than the first voltage level, and The first capacitor is formed to be larger than the second capacitor.

13. The driver integrated circuit according to claim 12, wherein: The first voltage level has a maximum value of a drive voltage set to a preset level. The second voltage level has a maximum value set as half-drive voltage, which is the midpoint between the drive voltage and the ground voltage. The first MIM capacitor is formed in the first region, and The second MIM capacitor is formed in the second region.

14. The driver integrated circuit according to claim 12, wherein, At least one of the first MIM capacitor and the second MIM capacitor includes a plurality of unit MIM capacitors with different capacitances.

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