Semiconductor device package

Abstract

A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit, and a power module. The first substrate has a first surface and a second surface opposite the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor chip. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor chip, the power element, and the passive element are vertically arranged relative to each other, and the passive element is assembled between the semiconductor chip and the power element.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package, and more particularly to a semiconductor device package having passive components. Background Technology

[0002] For high-performance computing or artificial intelligence (AI) computing, power loss and IR drop are major issues in power routing as current consumption increases with decreasing metal linewidth. Reducing power loss and enhancing heat conduction are crucial for improving the overall efficiency of power delivery systems used in high-performance computing, such as CPUs, GPUs, and TPUs.

[0003] Conventionally, lateral power delivery systems are integrated with high-performance computing semiconductor packages, resulting in long power routing paths. These long power routing paths lead to significant power losses and a substantial drop in electrical resistance (IR) when current consumption is high. This creates a vicious cycle of reduced overall power efficiency (including excessive thermal load and overheat protection leading to reduced current), requiring more voltage regulator modules (VRMs) to meet power demands and thus increasing material costs. New packaging architectures are needed to break this vicious cycle by shortening the power delivery path. Summary of the Invention

[0004] According to some embodiments of this disclosure, a semiconductor device package includes a first substrate, a computing unit, and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor chip. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor chip, the power element, and the passive element is arranged vertically relative to each other, and the passive element is assembled between the semiconductor chip and the power element.

[0005] According to some embodiments of this disclosure, a semiconductor device package includes a substrate, a computing unit, a power module, and passive components. The substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor chip. The power module is adjacent to the second surface. The power module includes a power element and an inductor stacked with the power element. The passive components are located on top of the power module. Each of the semiconductor chip, the power module, and the passive components is arranged vertically relative to each other, and the inductor is assembled between the semiconductor chip and the power element.

[0006] According to some embodiments of this disclosure, a semiconductor device package includes a substrate, a computing unit, a power module, and passive components. The substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor chip and a printed circuit board (PCB) beneath the substrate. The PCB includes a third surface and a fourth surface opposite to the third surface. The power module is adjacent to the fourth surface. The power module includes power elements on the fourth surface and inductors embedded in the PCB. The passive components are located above the power module. Each of the semiconductor chip, the power module, the PCB, and the passive components is arranged vertically relative to each other. Attached Figure Description

[0007] When with attachment Figure 1 When reading the following detailed description, various aspects of this disclosure can be readily understood from it. It should be noted that the various features may not necessarily be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0009] Figure 2 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 3 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0011] Figure 4 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0012] Figure 5 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0013] Figure 6 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0014] Figure 7 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0015] Figure 8 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0016] Figure 9 Impedance profiles of semiconductor device packages and comparative examples according to some embodiments of the present disclosure are shown.

[0017] Throughout the accompanying drawings and detailed description, common reference numerals are used to indicate the same or similar components. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming or placing a first feature on or over a second feature may include embodiments in which the first and second features are formed or placed in direct contact, and may also include embodiments in which an additional feature may be formed or placed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0020] Figure 1 This is a cross-sectional view of a semiconductor device package 10 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device package 10 includes a substrate 101, a computing unit 103, and a power module 104.

[0021] Substrate 101 has a surface 1011 and a surface 1012 opposite to surface 1011. In some embodiments, substrate 101 is formed of, for example, a printed circuit board (PCB) (such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate). Substrate 101 may include a redistribution layer (RDL), traces, and pads for enabling electrical connections between components. In some embodiments, substrate 101 may be replaced by other suitable carriers (such as lead frames). Additionally, dielectric layers may be disposed on surfaces 1011 and 1012 to act as mask layers protecting the traces and pads on substrate 101.

[0022] The computing unit 103 is adjacent to surface 1011. The computing unit 103 may include a semiconductor die 1031, a semiconductor die 1032, and an interposer 1033. Semiconductor dies 1031 and / or 1032 may be mounted on the interposer 1033. In some embodiments, semiconductor dies 1031 and / or 1032 may be mounted on the side of the interposer 1033 away from substrate 101. Semiconductor dies 1031 and 1032 may be integrated circuit (IC) chips. In some embodiments, semiconductor die 1031 may be an application-specific integrated circuit (ASIC) chip. In some embodiments, semiconductor die 1032 may be a memory chip. The number of semiconductor dies 1031 and 1032 may be modified, and this disclosure is not limited thereto.

[0023] Interposer 1033 may be assembled on surface 1011 of substrate 101. Interposer 1033 may include a silicon substrate and a redistribution layer (RDL) therein. Interposer 1033 may be configured to electrically connect substrate 101 to semiconductor chip 1031 and / or 1032 via conductive terminal 1034.

[0024] The conductive terminal 1034 can be disposed on the surface 1011 of the substrate 101. The conductive terminal 1034 can be mounted on the side of the interposer 1033 closest to the substrate 101. The conductive terminal 1034 can be a copper pillar or a solder ball, such as a Sn ball.

[0025] Semiconductor device package 10 may include molding compound 1035. Molding compound 1035 may surround or seal semiconductor chip 1031, semiconductor chip 1032, and interposer 1033. Molding compound 1035 may be configured to protect the above components from damage or contamination. Molding compound 1035 may be or may include, for example, epoxy resin with filler, molding compound (e.g., epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, material having silicone resin dispersed therein, or combinations thereof.

[0026] The power module 104 is adjacent to the surface 1012 of the substrate 101. The power module 104 may include a power element 1041 and a passive element 1042. The power element 1041 may include a power stage that provides power. The power element 1041 may be an integrated power stage (IPS) or a smart power stage (SPS). The IPS or SPS may include a driver and high / low-side metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0027] In some embodiments, passive element 1042 may be mounted below power element 1041. In some embodiments, passive element 1042 may be stacked with power element 1041. In some embodiments, passive element 1042 may include an inductor. Passive element 1042 may be configured to transfer magnetic energy to potential energy and may act as a transformer.

[0028] In some embodiments, each of the semiconductor chip 1031 or 1032, the power element 1041, and the passive element 1042 is arranged vertically with respect to each other. In this embodiment, the power supplied by the power element 1041 is transmitted to the semiconductor chip 1031 or 1032 via a vertical path, thereby shortening the power routing path. Therefore, the semiconductor device package 10 shortens the power routing path between the power element and the semiconductor chip, resulting in less power loss and less IR drop, even at high current consumption. Compared to conventional semiconductor device packages that provide a lateral power routing path between the power element and the semiconductor chip, the semiconductor device package 10 improves overall efficiency by reducing the equivalent series resistance (ESR) and equivalent series inductance (ESL) along the overall power delivery path.

[0029] In some embodiments, the semiconductor device package 10 includes a substrate 102. In some embodiments, the substrate 102 may include a printed circuit board (PCB). The PCB may include a semiconductor substrate and a plurality of ICs and traces therein. The substrate 102 may include a surface 1021 and a surface 1022 opposite to surface 1021. Surface 1021 faces surface 1012. Additionally, a dielectric layer may be applied to surfaces 1021 and 1022. In some embodiments, a power module 104 is adjacent to surface 1022 of the substrate 102.

[0030] In some embodiments, the semiconductor device package 10 includes passive components 1043A, 1043B, 1043C, 1043D, and 1043E. In some embodiments, passive components 1043A, 1043B, 1043C, 1043D, and / or 1043E may comprise various types of capacitors. Passive components 1043A, 1043B, 1043C, 1043D, and / or 1043E may act as, but are not limited to, decoupling capacitors, thereby removing noise and stabilizing voltage.

[0031] In some embodiments, passive element 1043A is assembled on or adjacent to surface 1012 of substrate 101. In some embodiments, passive element 1043A is adjacent to surface 1021 of substrate 102. In some embodiments, passive element 1043A is assembled between substrate 101 and power element 1041. In this embodiment, each of passive element 1043A, passive element 1042, power element 1041, and semiconductor chip 1031 or 1032 is arranged vertically relative to each other. In some embodiments, power element 1041 is electrically connected to computing unit 103 via passive elements 1042 and 1043A. In some embodiments, power element 1041 is electrically connected to computing unit 103 via inductors and capacitors.

[0032] The passive component 1043B can be assembled on the surface 1022 of the substrate 102.

[0033] Passive component 1043C can be mounted on surface 1011 of substrate 101. In some embodiments, passive components 1043A, 1043B, and / or 1043C can comprise micrometer-scale multilayer ceramic capacitors (MLCCs) with large capacitance. Passive components 1043A, 1043B, and / or 1043C can be configured, but not limited to, to filter out low-frequency noise in the power delivery path.

[0034] Passive component 1043D can be assembled adjacent to or partially embedded in the interposer 1033 that connects conductive terminal 1034 to semiconductor chip 1031. Passive component 1043D can be assembled on the side of interposer 1033 facing conductive terminal 1034. In some embodiments, passive component 1043D can be a thin film or deep trench (TF / DT) capacitor manufactured using semiconductor processes. Passive component 1043D can be configured to filter out noise with frequencies higher than those filtered by passive components 1043A, 1043B, and / or 1043C.

[0035] Passive component 1043E can be embedded in the interposer 1033 proximal to the side facing the semiconductor chip 1031. Passive component 1043E integrated in the interposer 1033 can be a deep trench capacitor (DTC) to filter out noise signals with frequencies higher than those filtered by passive components 1043A, 1043B, 1043C and / or 1043D.

[0036] In some embodiments, the semiconductor device package 10 includes a heat sink 1051. The heat sink 1051 may be mounted on the surfaces of semiconductor chips 1031 and 1032. The heat sink 1051 may be coupled to the computing unit 103 via a TIM (Thermal Interface Material). The heat sink 1051 may comprise, but is not limited to, a solid metal block or an electrically insulator coated with a metal film. For example, the heat sink 1051 may comprise copper (Cu), aluminum (Al), and / or other suitable materials. The heat sink 1051 may also comprise a copper-coated alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (SiN) plate.

[0037] In some embodiments, the semiconductor device package 10 may include a frame 1039 surrounding semiconductor chips 1031 and 1032, an interposer 1033, and passive components 1043D and 1043E. The frame 1039 may be positioned to separate a heat sink 1051 from a substrate 101. The frame 1039 may be configured to prevent warping on the semiconductor device package 10 in cases of large package sizes.

[0038] The semiconductor device package 10 includes a conductive terminal 106. The conductive terminal 106 may be disposed between substrate 101 and substrate 102. The conductive terminal 106 may be a solder ball, such as a Sn ball. In some embodiments, the height of the conductive terminal 106 is greater than or exceeds the height of the passive component 1043A.

[0039] In some embodiments of this disclosure, the semiconductor device package 10 includes passive components (such as passive component 1043E or passive component 1042) close to the semiconductor chip, thereby resulting in lower ESR and / or ESL. Therefore, the impedance of power delivery on the semiconductor device package 10 can be increased for better noise filtering.

[0040] Additionally, the semiconductor device package 10 may include a thermal interface material (TIM) 1071 disposed between the heat sink 1051 and the semiconductor chip 1031 and / or 1032 to facilitate heat dissipation from the semiconductor chips 1032 and 1032 to the heat sink 1051.

[0041] Figure 2 This is a cross-sectional view of a semiconductor device package 20 according to some embodiments of the present disclosure. Figure 2 The structure of the semiconductor device package 20 is similar to Figure 1 The structure of the semiconductor device package 10 is shown, but it is cut open in cross-section so that embedded vias 1013 and 1023 connecting the opposing surfaces of substrates 101 and 102 can be observed. Vias 1013 and 1023 are configured to transmit electrical signals from the power element 1041 of the power module 104 to the semiconductor chip 1032 of the computing unit 103. Figure 2 As shown, for example, the current flowing in the power routing path can start from the power element 1041, pass sequentially through the passive element 1042 (e.g., an inductor), the embedded via 1023 in the substrate 102, the conductive terminal 106, the passive element 1043A (e.g., a capacitor), and the embedded via 1013 in the substrate 101, and reach the computing unit 103.

[0042] A via 1013 is formed in the substrate 101 and connects the surface 1011 to the surface 1012. The via 1013 can electrically connect the passive component 1043A to the conductive terminal 1034.

[0043] A via 1023 is formed in the substrate 102 and connects surface 1021 to surface 1022. The via 1023 can electrically connect passive component 1042 to conductive terminal 106. In some embodiments, power component 1041 is electrically connected to semiconductor chip 1031 and / or 1032 through passive component 1042, via 1023, conductive terminal 106, passive component 1043A, via 1013, conductive terminal 1034, and interposer 1033.

[0044] Figure 3 This is a cross-sectional view of a semiconductor device package 30 according to some embodiments of the present disclosure. Figure 3 The structure of the semiconductor device package 30 is similar to Figure 1 The structure of the semiconductor device package 10 is different, and one of the differences is that the passive components 1042 of the semiconductor device package 30 are assembled between the substrates 101 and 102.

[0045] In some embodiments, the semiconductor device package 30 includes a cavity substrate 201. The cavity substrate 201 may be assembled between substrates 101 and 102. The cavity substrate 201 may include a PCB or other suitable substrate. The cavity substrate 201 may include an RDL or traces therein. The cavity substrate 201 may surround a passive component 1043A. The cavity substrate 201 may surround a passive component 1042. In some embodiments, the cavity substrate 201 includes a cavity accommodating passive component 1043A and / or passive component 1042.

[0046] In some embodiments, passive components 1042 and 1043A may be assembled within a cavity in the cavity substrate 201. Passive components 1042 and 1043A may alternatively be arranged in a lateral direction. In some embodiments, passive component 1042 is assembled between the power component 1041 and the semiconductor chip 1031 or 1032. In this embodiment, the passive component 1042 is closer to the semiconductor chip 1031 or 1032 for better noise filtering.

[0047] In some embodiments, the semiconductor device package 30 includes a heat sink 1052. The heat sink 1052 may be mounted on or in contact with the power element 1041 using a TIM (thermal interface material). The material of the heat sink 1052 may be similar to or the same as that of the heat sink 1051, and will not be described further herein. In this embodiment, heat can be dissipated from both sides of the semiconductor device package 30, thereby improving the efficiency of the semiconductor device package 30.

[0048] Additionally, the semiconductor device package 30 may include a TIM 1072 disposed between the heat sink 1052 and the power element 1041.

[0049] Figure 4 This is a cross-sectional view of a semiconductor device package 40 according to some embodiments of the present disclosure. Figure 4 The structure of the semiconductor device package 40 is similar to Figure 3 The semiconductor device package 40 has a different structure, and one difference is that the electrical terminals of the passive element 1042 in the semiconductor device package 40 are in contact with the electrical terminals of the surface 1021 of the substrate 102. For example, the electrical terminals of the passive element 1042 (e.g., an inductor assembled in the cavity substrate 201) are in physical contact with conductive traces on the surface 1021 of the substrate 102. The physical contact between the electrical terminals of the passive element 1042 and the surface 1021 of the substrate 102 effectively shortens the power routing path of the semiconductor device package 40.

[0050] like Figure 4As shown, for example, current flowing in the power routing path can originate from power element 1041, sequentially passing through embedded vias 1023 in substrate 102, passive element 1042 (e.g., an inductor), embedded vias in cavity substrate 201, passive element 1043A (e.g., a capacitor), and embedded vias 1013 in substrate 101, reaching computing unit 103. Figure 2 Compared to the power routing path in a semiconductor device package 20, a vertically stacked architecture that includes physical contact between the inductor and the substrate forms a shorter power routing path.

[0051] In some embodiments, passive component 1042 is electrically connected to power component 1041 through via 1023. In some embodiments, power component 1041 is electrically connected to semiconductor chip 1031 or 1032 through via 1023, passive component 1042, passive component 1043A, via 1013 and conductive terminal 1034.

[0052] Figure 5 This is a cross-sectional view of a semiconductor device package 50 according to some embodiments of the present disclosure. Figure 5 The structure of the semiconductor device package 50 is similar to Figure 4 The semiconductor device package 50 has a different structure, and one difference is that the electrical terminals of the passive element 1042 in the semiconductor device package 50 are in contact with the electrical terminals of the surface 1012 of the substrate 101. For example, the electrical terminals of the passive element 1042 (e.g., an inductor assembled in the cavity substrate 201) are in physical contact with conductive traces on the surface 1012 of the substrate 101. The physical contact between the electrical terminals of the passive element 1042 and the surface 1012 of the substrate 101 effectively shortens the power routing path of the semiconductor device package 50.

[0053] like Figure 5 As shown, for example, current flowing in the power routing path can originate from power element 1041, sequentially passing through embedded vias 1023 in substrate 102, embedded traces in cavity substrate 201, passive element 1043A (e.g., capacitor), passive element 1042 (e.g., inductor), and embedded vias 1013 in substrate 101, reaching computing unit 103. Figure 2 Compared to the power routing path in a semiconductor device package 20, a vertically stacked architecture that includes physical contact between the inductor and the substrate forms a shorter power routing path.

[0054] Figure 6 This is a cross-sectional view of a semiconductor device package 60 according to some embodiments of the present disclosure. Figure 6 The structure of the semiconductor device package 60 is similar to Figure 4The semiconductor device package 60 has a different structure, and one difference is that the electrical terminals of the passive element 1042 in the semiconductor device package 60 are in contact with the electrical terminals of both surfaces 1012 and 1021. For example, the electrical terminals of the passive element 1042 (e.g., an inductor assembled in the cavity substrate 201) are in physical contact with conductive traces on surface 1021 of substrate 102 and conductive traces on surface 1012 of substrate 101. The physical contact between the electrical terminals of the passive element 1042 and surfaces 1021 and 1012 of substrates 102 and 1011 effectively shortens the power routing path of the semiconductor device package 60.

[0055] like Figure 6 As shown, for example, current flowing in the power routing path can originate from power element 1041, sequentially passing through embedded via 1023 in substrate 102, passive element 1042 (e.g., inductor), passive element 1043A (e.g., capacitor), and embedded via 1013 in substrate 101, reaching computing unit 103. Figure 2 Compared to the power routing path in a semiconductor device package 20, a vertically stacked architecture that includes physical contact between the inductor and the substrate forms a shorter power routing path.

[0056] Figure 7 This is a cross-sectional view of a semiconductor device package 70 according to some embodiments of the present disclosure. Figure 7 The structure of the semiconductor device package 70 is similar to Figure 3 The structure of the semiconductor device package 30 is different, and one of the differences is that the semiconductor device package 70 uses a substrate 301 or motherboard instead of a heat sink 1052.

[0057] Substrate 301 may comprise a PCB or other suitable substrate. Substrate 301 may comprise an RDL and / or traces therein. In some embodiments, power element 1041 may be mounted on substrate 301. Substrate 301 or motherboard may also facilitate the dissipation of heat generated by power element 1041 and provide a flat bottom surface to semiconductor device package 70.

[0058] The semiconductor device package 70 may include a socket 302. The socket 302 is mounted on a substrate 301. The socket 302 may be mounted between the substrate 102 and the substrate 301. In some embodiments, the socket 302 includes a cavity for receiving a power element 1041.

[0059] Figure 8 This is a cross-sectional view of a semiconductor device package 80 according to some embodiments of the present disclosure. Figure 8 The structure of the semiconductor device package 80 is similar to Figure 2The structure of the semiconductor device package 20 is different, and one of the differences is that the passive components 1042 of the semiconductor device package 80 are embedded in the substrate 102.

[0060] like Figure 8 As shown, for example, current flowing in the power routing path can originate from power element 1041, sequentially pass through passive element 1042 (e.g., inductor) embedded in substrate 102, passive element 1043A (e.g., capacitor), and embedded via 1013 in substrate 101, to reach computing unit 103. Figure 2 Compared to the power routing path in a semiconductor device package 20, a vertically stacked architecture that includes physical contact between the inductor and the substrate forms a shorter power routing path.

[0061] In some embodiments, the passive element 1043A (e.g., a capacitor) may include electrical terminals. Contact point 401 of the electrical terminal of the passive element 1043A may contact the electrical terminal of the surface 1021 of the substrate 102. Similarly, contact point 402 of the electrical terminal of the passive element 1043A may contact the surface 1012 of the substrate 101. In some embodiments, the height of the conductive terminal 106 is substantially the same as the height of the passive element 1043A.

[0062] In this embodiment, the semiconductor device package 80 can shorten the power routing path between the power element 1041 and the semiconductor chip 1031 or 1032. Therefore, power loss in power delivery can be further reduced.

[0063] Figure 9 This is an impedance curve representing the impedance of power delivery relative to frequency. The X-axis indicates the magnitude of the operating frequency, while the Y-axis indicates the magnitude of the impedance. Line 501 is a simulated curve for a conventional semiconductor device package containing only MLCCs as passive components on substrate 101. Line 502 is a simulated curve for a semiconductor device package (as described herein) containing various types of capacitors (e.g., MLCCs, DTCs, and TF / DT capacitors). Compared to conventional semiconductor device packages, the semiconductor device package described herein provides lower impedance even at high operating frequencies, demonstrating better noise filtering.

[0064] Embodiments of this disclosure provide a semiconductor device package with a shortened power routing path. The lateral power delivery system in a conventional packaging architecture is replaced by a vertical power delivery system that effectively reduces the equivalent series resistance (ESR) and equivalent series inductance (ESL) by 66% and 42.8%, respectively. Power loss and IR drop can be reduced, and overall power efficiency is improved by approximately 2% to 5.5%. For example, the vertical power delivery system integrates the semiconductor chip and power stage along the vertical direction.

[0065] Furthermore, in high-power computing packages, 16-24 chips that generate considerable heat are typically assembled on a PCB. Therefore, the power stage unit of this disclosure is assembled on the side of the PCB furthest from the semiconductor chips and optionally attached to a heat sink.

[0066] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural referents.

[0067] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials generally refer to those materials that offer little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity exceeding approximately 10. 4 S / m, such as at least 10 5 S / m or at least 10 6 Conductive materials with conductivity of S / m. The conductivity of the material may sometimes vary with temperature. Unless otherwise stated, the conductivity of the material is measured at room temperature.

[0068] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0069] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual installations due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor device package comprising: A first substrate, the first substrate having a first surface and a second surface opposite to the first surface; A computing unit is located adjacent to the first surface. The computing unit includes an application-specific integrated circuit (ASIC) chip and a memory, and the ASIC chip and the memory are arranged side by side. A power module, the power module including a power element and a capacitor, the power element and the capacitor being adjacent to the second surface, the power element being an integrated power stage including a driver, a high-side metal-oxide-semiconductor field-effect transistor and a low-side metal-oxide-semiconductor field-effect transistor; Each of the application-specific integrated circuit (ASIC) chip, the power element, and the capacitor is arranged vertically relative to each other, and the capacitor is assembled between the ASIC chip and the power element.

2. The semiconductor device package according to claim 1, further comprising: A second substrate has a third surface and a fourth surface opposite to the third surface, the third surface facing the second surface of the first substrate. The power element is located adjacent to the fourth surface, and the capacitor is located adjacent to the third surface. The power module is configured to provide a power routing path sequentially through the second substrate and the first substrate to the computing unit.

3. The semiconductor device package of claim 2, wherein the capacitor is in contact with one of the second surface and the third surface.

4. The semiconductor device package of claim 3, wherein the capacitor includes a first electrical terminal in contact with the third surface and a second electrical terminal in contact with the second surface.

5. The semiconductor device package of claim 3, further comprising a cavity substrate located between the first substrate and the second substrate, the cavity of the cavity substrate accommodating the capacitor.

6. The semiconductor device package of claim 3, further comprising an inductor located remote from the first substrate relative to the power element.

7. The semiconductor device package of claim 1, further comprising an inductor stacked on the power element and located remotely from the computing unit relative to the power element.

8. The semiconductor device package of claim 7, wherein the power element and the computing unit are configured to provide a power routing path sequentially passing through the power element, the inductor, the capacitor, and the computing unit.

9. The semiconductor device package of claim 1, further comprising a first heat sink coupled to the computing unit.

10. The semiconductor device package of claim 9, further comprising a second heat sink coupled to the power module.

11. A semiconductor device package comprising: A substrate having a first surface and a second surface opposite to the first surface; A computing unit is located adjacent to the first surface, and the computing unit includes an application-specific integrated circuit chip and a memory. A power module, adjacent to the second surface, the power module including a power element and an inductor directly stacked with the power element, the power element being an integrated power stage including a driver, a high-side metal-oxide-semiconductor field-effect transistor and a low-side metal-oxide-semiconductor field-effect transistor; as well as A capacitor, located above the power module, Each of the application-specific integrated circuit chip, the power module, and the capacitor is arranged vertically relative to each other.

12. The semiconductor device package of claim 11, further comprising a printed circuit board located between the capacitor and the power module.

13. The semiconductor device package of claim 12, wherein the printed circuit board includes a third surface and a fourth surface opposite to the third surface, the third surface facing the second surface of the substrate, and the power module is assembled on the fourth surface.

14. The semiconductor device package of claim 11, wherein the inductor is directly stacked on the power element.

15. The semiconductor device package of claim 11, wherein the power element and the computing unit are configured to provide a power routing path sequentially passing through the power element, the inductor, the capacitor, and the computing unit.

16. A semiconductor device package comprising: A printed circuit board having a first surface and a second surface opposite to the first surface; A capacitor disposed adjacent to the first surface; A power element disposed on the second surface, the power element being an integrated power stage comprising a driver, a high-side metal-oxide-semiconductor field-effect transistor, and a low-side metal-oxide-semiconductor field-effect transistor; An application-specific integrated circuit (ASIC) chip, wherein the capacitor is assembled between the ASIC chip and the power element, and each of the ASIC chip, the power element and the capacitor is arranged vertically relative to each other; and Through-holes are embedded in the printed circuit board and disposed between the capacitor and the power components.

17. The semiconductor device package of claim 16, further comprising a substrate, wherein the substrate has a third surface and a fourth surface opposite to the third surface, and the capacitor is disposed on the fourth surface of the substrate.

18. The semiconductor device package of claim 17, further comprising an inductor stacked directly on the power element.

19. The semiconductor device package of claim 18, further comprising a heat sink spaced apart from the power element by the integrated circuit chip.

20. The semiconductor device package of claim 18, wherein the inductor and the capacitor are arranged vertically relative to each other.

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