Non-volatile storage device

Abstract

A nonvolatile storage device is provided. The nonvolatile storage device includes: a conductive plate; a barrier conductive film extending along a surface of the conductive plate; a molded structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film; a channel hole penetrating the molded structure to expose the barrier conductive film; an impurity pattern in contact with the barrier conductive film and formed in the channel hole; and a semiconductor pattern formed in the channel hole, extending along a side surface of the channel hole from the impurity pattern, and intersecting the plurality of gate electrodes.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0033824, filed on March 19, 2020, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a non-volatile storage device and a method for manufacturing the same, and more specifically, to a non-volatile storage device including an impurity region and a method for manufacturing the same. Background Technology

[0004] Semiconductor memory devices can be broadly classified into volatile memory devices and non-volatile memory devices. Non-volatile memory devices retain stored data when the power is off and are typically used for long-term secondary storage.

[0005] Currently, various non-volatile memory devices, such as those based on NAND or NOR flash memory, are widely used. Meanwhile, the integration density of non-volatile memory devices has been increased to meet consumer expectations for high performance and low cost. Incidentally, in the case of two-dimensional or planar memory devices, the integration density is determined by the area occupied by a single memory cell, and may have reached its limit. Therefore, recently, three-dimensional memory devices with vertically placed single memory cells have been developed. Summary of the Invention

[0006] An exemplary embodiment of the present invention provides a non-volatile storage device with enhanced product reliability and performance.

[0007] An exemplary embodiment of the present invention also provides a method for manufacturing a non-volatile memory device, which is capable of manufacturing a non-volatile memory device with enhanced product reliability and performance.

[0008] According to an exemplary embodiment of the present invention, a non-volatile memory device is provided, the non-volatile memory device comprising: a conductive plate; a barrier conductive film extending along a surface of the conductive plate; a molding structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film; a channel hole penetrating the molding structure to expose the barrier conductive film; an impurity pattern contacting the barrier conductive film and formed in the channel hole; and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole and intersecting the plurality of gate electrodes.

[0009] According to an exemplary embodiment of the present invention, a non-volatile memory device is provided, the non-volatile memory device comprising: a molded structure including a first surface and a second surface opposite to each other, the molded structure including a plurality of molded insulating films and a plurality of gate electrodes alternately stacked from the first surface toward the second surface; a first conductive plate extending along the first surface of the molded structure and formed on the first surface of the molded structure; a first barrier conductive film extending along the first surface of the molded structure and interposed between the molded structure and the first conductive plate; a channel hole extending from the second surface toward the first surface and penetrating the molded structure; a first impurity pattern contacting the first barrier conductive film and formed in the channel hole; a semiconductor pattern extending from the first impurity pattern toward the second surface of the molded structure and formed in the channel hole; and a bit line connected to the semiconductor pattern and formed on the second surface of the molded structure.

[0010] According to an exemplary embodiment of the present invention, a non-volatile memory device is provided, the non-volatile memory device comprising: a molding structure including a first surface and a second surface opposite to each other, the molding structure including a plurality of gate electrodes sequentially stacked from the first surface toward the second surface; a source structure extending along the first surface of the molding structure and formed on the first surface of the molding structure; a channel hole extending from the second surface toward the first surface and penetrating the molding structure; an impurity pattern connected to the source structure and formed in the channel hole; and a semiconductor pattern. The semiconductor pattern extends from the impurity pattern toward the second surface of the molded structure and is formed in the channel via; the bit line is connected to the semiconductor pattern and is formed on the second surface of the molded structure; a first inter-wire insulating film covers the bit line and is formed on the second surface of the molded structure; a substrate faces the second surface of the molded structure; a peripheral circuit element is formed on the substrate; and a second inter-wire insulating film covers the peripheral circuit element and is located between the substrate and the first inter-wire insulating film.

[0011] According to an exemplary embodiment of the present invention, a method for manufacturing a non-volatile memory device is provided, the method comprising: providing a first substrate; forming a molding structure including a first surface facing the first substrate and a second surface opposite to the first surface, the molding structure including a plurality of molded insulating films and a plurality of sacrificial films alternately stacked from the first surface toward the second surface; forming a channel hole penetrating the molding structure and recessed into a portion of the first substrate; forming an information storage film extending along the contour of the channel hole in the channel hole; forming an impurity pattern filling a portion of the channel hole on the information storage film; forming a semiconductor pattern extending along a side surface of the information storage film on the impurity pattern; removing at least a portion of the first substrate to expose the impurity pattern; and forming a source structure in contact with the exposed impurity pattern on the first surface of the molding structure. Attached Figure Description

[0012] The above and other aspects and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0013] Figure 1 This is an exemplary circuit diagram illustrating a non-volatile memory device according to an exemplary embodiment of the present invention;

[0014] Figure 2 This is a layout diagram illustrating a non-volatile storage device according to an exemplary embodiment of the present invention;

[0015] Figure 3 It is along Figure 2 A cross-sectional view taken from line AA;

[0016] Figures 4A to 4E yes Figure 3 Various magnified views of part R1;

[0017] Figure 5A and Figure 5B It is used for explanation Figure 3 Various partial perspective views of the first semiconductor pattern and the first impurity region;

[0018] Figure 6 This is a cross-sectional view illustrating a non-volatile storage device according to an exemplary embodiment of the present invention;

[0019] Figure 7A and Figure 7B yes Figure 6 Various magnified views of region R2;

[0020] Figure 8 This is a cross-sectional view illustrating a non-volatile storage device according to an exemplary embodiment of the present invention;

[0021] Figure 9 It is used for explanation Figure 8 A schematic layout diagram of the gaps;

[0022] Figure 10 This is a cross-sectional view illustrating a non-volatile storage device according to an exemplary embodiment of the present invention;

[0023] Figure 11A and Figure 11B yes Figure 10 Various magnified views of region R3;

[0024] Figures 12 to 14 These are various cross-sectional views used to illustrate a non-volatile storage device according to an exemplary embodiment of the present invention;

[0025] Figures 15 to 30 This is an intermediate stage diagram illustrating a method for manufacturing a non-volatile memory device according to an exemplary embodiment of the present invention; and

[0026] Figure 31 This is an intermediate stage diagram illustrating a method for manufacturing a non-volatile storage device according to an exemplary embodiment of the present invention.

[0027] because Figures 1 to 31 The accompanying drawings are for illustrative purposes only, and the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0028] In the following text, reference will be made to Figures 1 to 14 A non-volatile storage device according to an exemplary embodiment of the present invention is described.

[0029] Figure 1 This is an exemplary circuit diagram illustrating a non-volatile memory device according to an exemplary embodiment of the present invention. For example, in an exemplary embodiment of the present invention, Figure 1 An equivalent circuit diagram of a NAND flash memory device with a vertical structure can be shown.

[0030] The memory cell array of a non-volatile memory device according to an exemplary embodiment of the present invention may include a common source line CSL, multiple bit lines BL, and multiple cell strings CSTR.

[0031] Multiple bit lines BL can be arranged in two dimensions. For example, bit lines BL can be spaced apart from each other in a second direction Y and can extend in a first direction X. Multiple cell strings CSTR can be connected in parallel to each bit line BL. Each cell string in the multiple cell strings CSTR can have a vertical structure extending in a third direction Z perpendicular to the plane (XY plane). The cell strings CSTR can be connected together to a common source line CSL. That is, multiple cell strings CSTR can be located between the bit line BL and the common source line CSL.

[0032] The common source line (CSL) can extend in a second direction (Y) intersecting the first direction (X). In an exemplary embodiment of the invention, multiple common source lines (CSLs) can be arranged in two dimensions. For example, multiple common source lines (CSLs) can be spaced apart from each other in the first direction (X) and extend in the second direction (Y). The same voltage can be applied to the common source lines (CSLs), or different voltages can be applied to the common source lines (CSLs), and each common source line (CSL) can be controlled independently.

[0033] Each cell string (CSTR) may include a ground select transistor (GST) connected to the common source line (CSL), a string select transistor (SST) connected to the bit line (BL), and multiple memory cell transistors (MCTs) located between the ground select transistor (GST) and the string select transistor (SST). Each memory cell transistor (MCT) may include a data storage element. The ground select transistor (GST), the memory cell transistors (MCTs), and the string select transistors may be connected in series in the vertical direction (Z direction).

[0034] The common source line CSL can be commonly connected to the source of the ground select transistor GST. Additionally, the ground select line GSL, multiple word lines WL11 to WL1n and WL21 to WL2n, and the string select line SSL can be located between the common source line CSL and the bit line BL. The ground select line GSL can be used as the gate electrode of the ground select transistor GST, the word lines WL11 to WL1n and WL21 to WL2n can be used as the gate electrodes of the memory cell transistors MCT, and the string select line SSL can be used as the gate electrode of the string select transistor SST. For example, in each cell string CSTR, the string select transistor SST can be arranged between the bit line BL and the memory cell transistor MCT, and data transmission between the bit line BL and the memory cell transistor MCT can be controlled by using the string select line SSL, which serves as the gate of the string select transistor SST. In addition, in each cell string CSTR, a ground selection transistor GST can be arranged between the common source line CSL and the memory cell transistor MCT, and data transmission between the common source line CSL and the memory cell transistor MCT can be controlled by using the ground selection line GSL, which serves as the gate of the ground selection transistor GST.

[0035] In an exemplary embodiment of the present invention, the erase control transistor ECT may be located between the common source line CSL and the ground select transistor GST. The common source line CSL may be commonly connected to the source of the erase control transistor ECT. Furthermore, the erase control line ECL may be located between the common source line CSL and the ground select line GSL. The erase control line ECL may be used as the gate electrode of the erase control transistor ECT. The erase control transistor ECT may generate gate-induced drain leakage (GIDL) to perform the erase operation of the memory cell array.

[0036] Figure 2 This is a layout diagram illustrating a non-volatile storage device according to an exemplary embodiment of the present invention. Figure 3 It is along Figure 2 The cross-sectional view taken from line AA. Figures 4A to 4E yes Figure 3 Various magnified views of part R1. Figure 5A and Figure 5B It is used for explanation Figure 3 Various partial perspective views of the first semiconductor pattern and the first impurity region.

[0037] Reference Figures 2 to 5B According to an exemplary embodiment of the present invention, a non-volatile memory device includes a first substrate 10, molded structures MS1 and MS2, a first source structure 190, a plurality of channel holes CH, a first impurity pattern 120, a first semiconductor pattern 130, a plurality of bit lines BL, a first wiring structure PW1, a second substrate 30, and a second wiring structure PW2.

[0038] The first substrate 10 may include, for example, a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. Alternatively, the first substrate 10 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. The first substrate 10 may have a main surface extending in both the first direction X and the second direction Y (XY plane).

[0039] In an exemplary embodiment of the present invention, the first substrate 10 may include impurities. For example, the first substrate 10 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0040] The first substrate 10 may include a cell array region CAR and an extension region EXT.

[0041] The cell array region (CAR) and the extended region (EXT) can be divided by the word line cut region (WLC) to form multiple memory cell blocks. For example, as... Figure 2As shown, the word line cut region (WLC) can extend in the second direction Y to cut the cell array region (CAR) and the extension region (EXT). Each of the multiple memory cell blocks can be formed between two adjacent word line cut regions (WLC).

[0042] A memory cell array comprising multiple memory cells can be formed in a cell array region (CAR). The memory cell array can consist of multiple memory cells, multiple channel vias (CH) electrically connected to the memory cells, multiple word lines (WL11 to WL1n and WL21 to WL2n), multiple bit lines (BL), etc.

[0043] The extended region EXT can be located around the cell array region CAR. The plurality of gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL, which will be described later, can be stacked in a stepped configuration within the extended region EXT. In an exemplary embodiment of the invention, the stepped configuration of the plurality of gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL can be arranged in an upside-down configuration. For example, the steps included in the plurality of gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL can have a length extending in the second direction Y, and these lengths can gradually increase from the lowest length to the highest length. However, the invention is not limited thereto. For example, in an exemplary embodiment of the invention, the steps included in the plurality of gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL can have a length extending in the second direction Y, and these lengths can gradually decrease from the lowest length to the highest length.

[0044] Molded structures MS1 and MS2 may be formed on a first substrate 10. Molded structures MS1 and MS2 may include a first surface MSa and a second surface MSb opposite to each other. For example, the first substrate 10 may be formed on the first surface MSa of molded structures MS1 and MS2. Molded structures MS1 and MS2 may include a plurality of gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL sequentially stacked from the first surface MSa toward the second surface MSb. In an exemplary embodiment of the present invention, molded structures MS1 and MS2 may include a first molded structure MS1 and a second molded structure MS2 stacked on the first substrate 10. Although two molded structures are shown as an example, the present invention is not limited thereto. For example, in an exemplary embodiment of the present invention, three or more molded structures may be stacked on the first substrate 10.

[0045] The first molded structure MS1 can be formed on the first substrate 10 and can include a plurality of first molded insulating films 110 and a plurality of first gate electrodes ECL, GSL and WL11 to WL1n alternately stacked on the first substrate 10. For example, each of the first gate electrodes ECL, GSL and WL11 to WL1n and each first molded insulating film 110 can be a layered structure extending in a first direction X and a second direction Y parallel to the upper surface of the first substrate 10. In addition, the first gate electrodes ECL, GSL and WL11 to WL1n and the first molded insulating films 110 can be alternately stacked along a third direction Z intersecting (e.g., perpendicular to the upper surface of the first substrate 10).

[0046] In an exemplary embodiment of the present invention, the first gate electrodes ECL, GSL, and WL11 to WL1n may include an erase control line ECL, a ground select line GSL, and multiple first word lines WL11 to WL1n sequentially stacked on the first substrate 10. Unlike the illustrated case, in an exemplary embodiment of the present invention, the erase control line ECL may be omitted. Additionally, in an exemplary embodiment of the present invention, the number of ground select transistors GST may be two.

[0047] The second molded structure MS2 can be formed on the first molded structure MS1 and can include a plurality of second molded insulating films 112 and a plurality of second gate electrodes WL21 to WL2n and SSL alternately stacked on the first molded structure MS1. For example, each of the second gate electrodes WL21 to WL2n and SSL and each second molded insulating film 112 can have a layered structure extending in a first direction X and a second direction Y. Furthermore, the second gate electrodes WL21 to WL2n and SSL and the second molded insulating film 112 can be alternately stacked along a third direction Z.

[0048] In an exemplary embodiment of the present invention, the plurality of second gate electrodes WL21 to WL2n and SSL may include a plurality of second word lines WL21 to WL2n and a string select line SSL sequentially stacked on the first molding structure MS1. In an exemplary embodiment of the present invention, the number of string select transistors SST may be two.

[0049] The first gate electrodes ECL, GSL, and WL11 to WL1n, as well as the second gate electrodes WL21 to WL2n and SSL, may all comprise conductive materials. For example, the first gate electrodes ECL, GSL, and WL11 to WL1n, as well as the second gate electrodes WL21 to WL2n and SSL, may comprise, but are not limited to, metals such as tungsten (W), cobalt (Co), and / or nickel (Ni), or semiconductor materials such as silicon (Si).

[0050] The first molded insulating film 110 and the second molded insulating film 112 may include insulating materials. For example, both the first molded insulating film 110 and the second molded insulating film 112 may include, but are not limited to, silicon oxide (SiO2).

[0051] In an exemplary embodiment of the present invention, a first interlayer insulating film 140 may be formed on a first substrate 10 and may cover molded structures MS1 and MS2. For example, the first interlayer insulating film 140 may include, but is not limited to, silicon oxide (SiO2).

[0052] The first source structure 190 can be formed on the first surface MSa of the molded structures MS1 and MS2. For example, the first substrate 10 can be located between the molded structures MS1 and MS2 and the first source structure 190. The first source structure 190 can extend along the first surface MSa of the molded structures MS1 and MS2 and can be provided with a common source line (e.g., Figure 1 (CSL).

[0053] In an exemplary embodiment of the present invention, the first source structure 190 may include a first conductive plate 192a and a first barrier conductive film 194a.

[0054] The first conductive plate 192a may be formed on the first surface MSa of the molded structures MS1 and MS2, and may be a plate-shaped conductive film extending along the first surface MSa of the molded structures MS1 and MS2. The first conductive plate 192a may include, but is not limited to, tungsten (W), aluminum (Al), copper (Cu), or combinations thereof. In an exemplary embodiment of the present invention, the first conductive plate 192a may include tungsten (W) and / or aluminum (Al).

[0055] In an exemplary embodiment of the present invention, the thickness TH21 of the first conductive plate 192a can be approximately To about Within a certain range. Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term "approximately" as used herein includes the listed values ​​and refers to an acceptable deviation from a particular value as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the listed values.

[0056] The first barrier conductive film 194a may be located between the molded structures MS1 and MS2 and the first conductive plate 192a, and may extend along the first surface MSa of the molded structures MS1 and MS2. For example, the first barrier conductive film 194a may extend along the surface of the first conductive plate 192a. For example, the molded structures MS1 and MS2 may include a plurality of gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n and SSL sequentially stacked on the first barrier conductive film 194a.

[0057] The first barrier conductive film 194a can prevent the diffusion of elements contained in the first conductive plate 192a. For example, the first barrier conductive film 194a may include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In an exemplary embodiment of the present invention, the first barrier conductive film 194a may include titanium nitride (TiN).

[0058] In an exemplary embodiment of the present invention, the first substrate 10 may be located between the molded structures MS1 and MS2 and the first barrier conductive film 194a. For example, the lower surface of the first substrate 10 may be in contact with the first molded insulating film 110, and the upper surface of the first substrate 10 may be in contact with the first barrier conductive film 194a.

[0059] In an exemplary embodiment of the present invention, input / output pads 195 may be formed on a first interlayer insulating film 140. For example, a first substrate 10 may be located between the first interlayer insulating film 140 and the input / output pads 195. The input / output pads 195 may extend along the surface of the first interlayer insulating film 140.

[0060] In an exemplary embodiment of the present invention, the input / output pads 195 and the first source structure 190 may be formed at the same level. As used herein, the term "at the same level" means that both are formed using the same manufacturing process. For example, the input / output pads 195 may include: a second conductive plate 197 comprising the same material as the first conductive plate 192a; and a second barrier conductive film 199 comprising the same material as the first barrier conductive film 194a. For example, the lower surface of the first substrate 10 may contact the first interlayer insulating film 140, and the upper surface of the first substrate 10 may contact the second barrier conductive film 199.

[0061] In an exemplary embodiment of the present invention, a first inter-wiring insulating film 50 and a passivation film 60 may be formed on the first surface MSa of the molded structures MS1 and MS2. The first inter-wiring insulating film 50 and the passivation film 60 may be sequentially formed on the first source structure 190. In an exemplary embodiment of the present invention, the first inter-wiring insulating film 50 may completely cover the first source structure 190.

[0062] In an exemplary embodiment of the present invention, the first inter-wiring insulating film 50 and the passivation film 60 may expose at least a portion of the input / output pads 195. For example, the first inter-wiring insulating film 50 and the passivation film 60 may include an opening OP that exposes at least a portion of the input / output pads 195. The input / output pads 195 may be exposed to the outside through the opening OP to form input / output circuitry. For example, the redistribution structure 70 to be described may be connected to the input / output pads 195 through the opening OP.

[0063] Multiple channel holes CH can extend from the second surface MSb toward the first surface MSa and can penetrate the molded structures MS1 and MS2. That is, the channel holes CH can extend in a direction (e.g., the third direction Z) intersecting with the multiple gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n and SSL.

[0064] In an exemplary embodiment of the present invention, the plurality of channel holes CH can be arranged in a zigzag pattern. For example, as Figure 2 As shown, multiple vias CH can be arranged alternately adjacent to each other in the first direction X and the second direction Y. Arranging multiple vias CH in a zigzag pattern can further improve the integration density of non-volatile memory devices.

[0065] In an exemplary embodiment of the present invention, a plurality of dummy vias (DCHs) penetrating through molded structures MS1 and MS2 can be formed. The plurality of dummy vias (DCHs) can be arranged along a second direction Y. The plurality of dummy vias (DCHs) can be formed simultaneously with a plurality of vias (CHs) formed in the memory cell array. The plurality of dummy vias (DCHs) and the plurality of vias (CHs) can have substantially the same structure. Since the dummy vias (DCHs) can have a shape similar to that of the vias (CHs), a detailed description thereof will not be provided below. In an exemplary embodiment of the present invention, the plurality of vias (CHs) and the plurality of dummy vias (DCHs) can be arranged to form a hexagonal array.

[0066] In an exemplary embodiment of the present invention, the width of the channel hole CH penetrating the first molding structure MS1 can decrease from the second surface MSb toward the first surface MSa. Additionally, the width of the channel hole CH penetrating the second molding structure MS2 can decrease from the second surface MSb toward the first surface MSa. This can be attributed to the characteristics of the etching process used to form the channel hole CH.

[0067] In an exemplary embodiment of the present invention, the side surface of the channel hole CH may have a step between the first molding structure MS1 and the second molding structure MS2. This may be because the etching process penetrating the first molding structure MS1 and the etching process penetrating the second molding structure MS2 are performed separately. However, this is merely an example, and the etching process penetrating the first molding structure MS1 and the etching process penetrating the second molding structure MS2 can, of course, be performed simultaneously. In this case, the side surface of the channel hole CH may not have a step between the first molding structure MS1 and the second molding structure MS2.

[0068] The channel via CH can expose at least a portion of the surface of the first source structure 190. For example, the channel via CH can penetrate the molded structures MS1 and MS2 and the first substrate 10 to expose the first barrier conductive film 194a.

[0069] A first impurity pattern 120 may be formed in each channel hole CH and may be connected to the first source structure 190. For example, the upper surface of the first impurity pattern 120 may contact the lower surface of the first barrier conductive film 194a. For example, the first impurity pattern 120 may be formed in the upper part of each channel hole CH.

[0070] The first impurity pattern 120 may be a semiconductor pattern containing impurities. The first impurity pattern 120 may include, for example, but not limited to, semiconductor materials such as single-crystal silicon (Si), polycrystalline silicon (Si), organic semiconductor materials, or carbon (C) nanostructures. In an exemplary embodiment of the present invention, the first impurity pattern 120 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.). In an exemplary embodiment of the present invention, the impurity concentration of the first impurity pattern 120 may be higher than the impurity concentration of the first substrate 10.

[0071] In an exemplary embodiment of the present invention, the first impurity pattern 120 may fill a portion of each channel hole CH. For example, as Figure 4A and Figure 5A As shown, the first impurity pattern 120 may include a filling portion 122 and a tube 124. Figure 5A The channel hole CH is Figure 4AAn inverted view of the channel hole CH. The fill portion 122 may cover the first barrier conductive film 194a exposed by the channel hole CH. Here, the fill portion 122 may cover the first barrier conductive film 194a from below. Throughout the specification, the terms "cover" or "on" may mean covering an object from below or on an object. For example, the fill portion 122 may have a cylindrical shape (e.g., a cylinder) extending from the first barrier conductive film 194a in the third direction Z. A tube 124 may protrude from the fill portion 122 toward the first semiconductor pattern 130. For example, the tube 124 may have a tube shape (e.g., a circular tube shape) extending from the fill portion 122 in the third direction Z.

[0072] In an exemplary embodiment of the present invention, the portion of the first impurity pattern 120 adjacent to the first semiconductor pattern 130 can be formed by diffusing impurities contained in the first impurity pattern 120. For example, impurities can diffuse from the filling portion 122 toward the first semiconductor pattern 130 through the tube 124. Therefore, the impurity concentration of the first impurity pattern 120 can increase as it moves away from the first semiconductor pattern 130. For example, the concentration of n-type impurities in the tube 124 can increase as it moves away from the first semiconductor pattern 130. For example, the portion of the first impurity pattern 120 furthest from the first semiconductor pattern 130 has the highest concentration of n-type impurities.

[0073] In an exemplary embodiment of the present invention, the first impurity pattern 120 may include a recessed first surface 120C1. The first surface 120C1 may be defined by a side surface of a tube 124 protruding from the fill portion 122 in a tubular form. For example, the first surface 120C1 may be formed on a lower surface of the fill portion 122 from which the tube 124 does not protrude. The first surface 120C1 may be attributed to, for example, characteristics of a finishing process used to form the first semiconductor pattern 130. (Refer to...) Figure 21 The finishing process for forming the first semiconductor pattern 130 is described.

[0074] The first semiconductor pattern 130 can be formed in each channel hole CH and can penetrate the molded structures MS1 and MS2 and extend in the third direction Z. Therefore, the first semiconductor pattern 130 can intersect with a plurality of gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n and SSL. Although the first semiconductor pattern 130 is shown as having a cylindrical shape, this is merely an example. For example, the first semiconductor pattern 130 can have a square tube shape or a solid column shape.

[0075] The first semiconductor pattern 130 may contact the first impurity pattern 120. For example, the first semiconductor pattern 130 may extend from the first impurity pattern 120 along the side surface of the channel hole CH.

[0076] Multiple gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL may include an erase control line ECL adjacent to the first barrier conductive film 194a. In an exemplary embodiment of the invention, the interface between the first impurity pattern 120 and the first semiconductor pattern 130 may overlap with the erase control line ECL (e.g., overlap in a direction perpendicular to the extension direction of the channel via). For example, as Figure 4A As shown, the interface between the first impurity pattern 120 and the first semiconductor pattern 130 can be positioned below the upper surface of the erase control line ECL and above the lower surface of the erase control line ECL. Therefore, the erase control line ECL can overlap with at least a portion of the first impurity pattern 120 (e.g., in a direction perpendicular to the extension direction of the channel via), and the erase operation via the gate-induced drain leakage GIDL can be successfully performed.

[0077] In an exemplary embodiment of the present invention, the first semiconductor pattern 130 may extend from the tube 124 of the first impurity pattern 120 along the side surface of the channel hole CH. In an exemplary embodiment of the present invention, the thickness TH11 of the tube 124 of the first impurity pattern 120 may be the same as the thickness TH12 of the first semiconductor pattern 130. Here, "thickness" is measured in a direction parallel to the first surface Msa of the molded structures MS1 and MS2. In this specification, the term "same" means not only identical things, but also minor differences that may occur due to process margins, etc.

[0078] The first semiconductor pattern 130 may include, for example, but not limited to, semiconductor materials such as single-crystal silicon (Si), polycrystalline silicon (Si), organic semiconductor materials, or carbon (C) nanostructures. In an exemplary embodiment of the present invention, the first semiconductor pattern 130 may include undoped polycrystalline silicon (p-Si).

[0079] The information storage film 132 may extend along the side surface of each channel hole CH. For example, the information storage film 132 may be located between the molded structures MS1 and MS2 and the first semiconductor pattern 130, and between the molded structures MS1 and MS2 and the first impurity pattern 120. Therefore, the information storage film 132 may be located between the first semiconductor pattern 130 and the respective gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n and SSL.

[0080] In an exemplary embodiment of the present invention, the information storage film 132 may be in contact with the first barrier conductive film 194a. For example, the first impurity pattern 120 may extend along a portion of the side surface of the information storage film 132, and the first semiconductor pattern 130 may extend along another portion of the side surface of the information storage film 132. In an exemplary embodiment of the present invention, a portion of the information storage film 132 may be located between the first substrate 10 and the first impurity pattern 120.

[0081] The information storage film 132 may include at least one of the following: silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a high dielectric constant material with a dielectric constant higher than that of silicon oxide (SiO2). The high dielectric constant material may include at least one of the following: aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum hafnium oxide (LaHfO), lanthanum aluminum oxide (LaAlO3), dysprosium scandium oxide (DyScO3), or combinations thereof.

[0082] In an exemplary embodiment of the present invention, the information storage film 132 may be formed as multiple films. For example, such as Figure 4A As shown, the information storage film 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a barrier insulating film 132c sequentially stacked on the first impurity pattern 120 and the first semiconductor pattern 130. The barrier insulating film 132c may be formed between the charge storage film 132b and the respective gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL.

[0083] The tunnel insulating film 132a can tunnel charges to the charge storage film 132b via Fowler-Nordheim (FN) tunneling. The tunnel insulating film 132a may comprise, for example, silicon oxide (SiO2) or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)) with a dielectric constant higher than that of silicon oxide (SiO2). The charge storage film 132b may comprise, for example, silicon nitride (Si3N4). The barrier insulating film 132c may comprise, for example, silicon oxide (SiO2) or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)) with a dielectric constant higher than that of silicon oxide (SiO2). In an exemplary embodiment of the invention, the barrier insulating film 132c may comprise a material with a dielectric constant higher than that of the tunnel insulating film 132a. However, the invention is not limited thereto.

[0084] In an exemplary embodiment of the present invention, a gate insulating film 133 may be formed between the gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL and the information storage film 132. The gate insulating film 133 may extend along the lower, side, and upper surfaces of each of the gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL. The gate insulating film 133 may include, for example, but not limited to, aluminum oxide (Al2O3).

[0085] In an exemplary embodiment of the present invention, a filling insulating pattern 134 may be formed within each channel via CH. The filling insulating pattern 134 may be formed to fill the interior of the tubular first semiconductor pattern 130 and the interior of the tube 124 of the first impurity pattern 120. Therefore, the filling insulating pattern 134 may be surrounded by the first semiconductor pattern 130 and the first impurity pattern 120. The filling insulating pattern 134 may include, but is not limited to, silicon oxide (SiO2).

[0086] In an exemplary embodiment of the present invention, the second impurity pattern 136 may be formed on the second surface MSb of the molded structures MS1 and MS2, and may be formed to be connected to the first semiconductor pattern 130. For example, the second impurity pattern 136 may be formed in a second interlayer insulating film 142 covering the first interlayer insulating film 140. The second impurity pattern 136 may include, for example, but not limited to, impurity-doped polycrystalline silicon (p-Si). In an exemplary embodiment of the present invention, the second impurity pattern 136 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0087] Multiple bit lines BL can be spaced apart from each other and extend side by side. For example, each bit line BL can extend in a first direction X. In an exemplary embodiment of the invention, bit lines BL can be formed on the second surface MSb of the molded structures MS1 and MS2. For example, bit lines BL can be formed on a fourth interlayer insulating film 146 covering a third interlayer insulating film 144.

[0088] Each bit line BL can be connected to multiple first semiconductor patterns 130. For example, as Figure 2 and Figure 3 As shown, bit line BL can be connected to a plurality of first semiconductor patterns 130 via first line contact 170. First line contact 170 can penetrate, for example, third interlayer insulating film 144 and fourth interlayer insulating film 146 to electrically connect bit line BL and second impurity pattern 136. First line contact 170 may not be connected to the first semiconductor pattern 130 in the dummy channel via DCH.

[0089] Molded structures MS1 and MS2 can be cut by cutting pattern 150. For example, cutting pattern 150 can extend from the second surface MSb toward the first surface MSa to cut molded structures MS1 and MS2. Cutting pattern 150 can extend in a direction intersecting bit line BL. For example, bit line BL can extend in a first direction X, and cutting pattern 150 can extend in a second direction Y. Cutting pattern 150 can correspond to Figure 2 The letter line cutting area WLC. The cutting pattern 150 may include, but is not limited to, silicon oxide (SiO2).

[0090] In an exemplary embodiment of the present invention, the cut line CL can be formed in the string select line SSL, and the string select line SSL can be cut. For example, as Figure 2 As shown, the cut line CL can extend in the second direction Y to cut the string select line SSL. Arrays of memory cells spaced apart by the cut line CL can be selected individually and controlled by the string select line SSL cut by the cut line CL.

[0091] In an exemplary embodiment of the present invention, the cleaving line CL may span a plurality of dummy vias DCH arranged along the second direction Y. The first semiconductor pattern 130 in the dummy vias DCH may not be connected to the bit line BL.

[0092] Refer again Figure 3 Gate contacts 172, connected to the respective gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL, can be formed in the extended region EXT. For example, gate contacts 172 can penetrate the first to fourth interlayer insulating films 140, 142, 144, and 146, and can be connected to the respective gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL. In an exemplary embodiment of the invention, the width of the gate contact 172 can decrease from the second surface MSb toward the first surface MSa.

[0093] In an exemplary embodiment of the present invention, a source contact 174 connected to the first source structure 190 may be formed in the extended region EXT. For example, the source contact 174 may penetrate the first to fourth interlayer insulating films 140, 142, 144, and 146, and may be connected to the first source structure 190. In an exemplary embodiment of the present invention, the width of the source contact 174 may decrease from the second surface MSb toward the first surface MSa.

[0094] In an exemplary embodiment of the present invention, the input / output contact 176 connected to the input / output pad 195 may be formed in the extended region EXT. For example, the input / output contact 176 may penetrate the first to fourth interlayer insulating films 140, 142, 144, and 146 and may be connected to the input / output pad 195. In an exemplary embodiment of the present invention, the width of the input / output contact 176 may decrease from the second surface MSb toward the first surface MSa. In an exemplary embodiment of the present invention, each of the gate contact 172, the source contact 174, and the input / output contact 176 may have a single-layer structure including a metal layer, a double-layer structure including a metal layer and a metal nitride layer, or a three-layer structure including a metal layer, a metal nitride layer, and a metal silicide layer.

[0095] A first wiring structure PW1 may be formed on the second surface MSb of the molded structures MS1 and MS2. The first wiring structure PW1 may include a first wiring 22 and a first passage 24. For example, a second inter-wiring insulating film 20 covering the bit line BL may be formed. The first wiring 22 and the first passage 24 are formed in the second inter-wiring insulating film 20 and may be electrically connected to each other. In an exemplary embodiment of the invention, at least a portion of the first wiring structure PW1 may be exposed from the surface of the second inter-wiring insulating film 20. In an exemplary embodiment of the invention, the first passage 24 may include a metallic material such as tungsten (W), aluminum (Al), or copper (Cu). The first wiring 22 may include a metallic material such as copper (Cu). However, the invention is not limited thereto.

[0096] The second substrate 30 may face the second surface MSb of the molded structures MS1 and MS2. The second substrate 30 may include, for example, a semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. Alternatively, the second substrate 30 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0097] In an exemplary embodiment of the present invention, the first to fourth peripheral circuit elements PT1, PT2, PT3, and PT4 may be formed on the second substrate 30. The first to fourth peripheral circuit elements PT1, PT2, PT3, and PT4 may form peripheral circuitry (e.g., a page buffer, a row decoder, control logic, etc.) that controls the operation of each memory cell. For example, the first peripheral circuit element PT1 may form a page buffer, and the second peripheral circuit element PT2 may form a row decoder.

[0098] Each of the first to fourth peripheral circuit elements PT1, PT2, PT3, and PT4 may include, for example, but not limited to, transistors. For example, each of the first to fourth peripheral circuit elements PT1, PT2, PT3, and PT4 may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors.

[0099] A second wiring structure PW2 may be formed on a second substrate 30. The second wiring structure PW2 may include a second wiring 42 and a second passage 44. For example, a third inter-wiring insulating film 40 may be formed covering the first to fourth peripheral circuit elements PT1, PT2, PT3, and PT4. The second wiring 42 and the second passage 44 may be formed in the third inter-wiring insulating film 40 and may be electrically connected to each other. In an exemplary embodiment of the invention, at least a portion of the second wiring structure PW2 may be exposed from the surface of the third inter-wiring insulating film 40. In an exemplary embodiment of the invention, the second passage 44 may include a metallic material such as tungsten (W), aluminum (Al), or copper (Cu). The second wiring 42 may include a metallic material such as copper (Cu). However, the invention is not limited thereto.

[0100] In an exemplary embodiment of the present invention, the third inter-wiring insulating film 40 may be attached to the second inter-wiring insulating film 20. For example, the third inter-wiring insulating film 40 may be located between the second inter-wiring insulating film 20 and the second substrate 30.

[0101] A first wiring 22 can be disposed on a second wiring 42, and a second wiring inter-insulation film 20 can be disposed on a third wiring inter-insulation film 40. The first wiring structure PW1 and the second wiring structure PW2 can be electrically connected to each other by attaching the second wiring inter-insulation film 20 and the third wiring inter-insulation film 40. For example, the first wiring 22 exposed from the second wiring inter-insulation film 20 can contact the second wiring 42 exposed from the third wiring inter-insulation film 40. The first wiring 22 and the second wiring 42 can be electrically connected to each other by, for example, but not limited to, copper-copper bonding (Cu-Cu bonding) processes.

[0102] In an exemplary embodiment of the present invention, each bit line BL can be connected to a first peripheral circuit element PT1 formed on the second substrate 30. For example, the bit line BL can be connected to the first peripheral circuit element PT1 through a first wiring structure PW1 and a second wiring structure PW2.

[0103] In an exemplary embodiment of the present invention, each of the gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL can be connected to a second peripheral circuit element PT2 formed on the second substrate 30. For example, a third wiring 182 connected to the gate contact 172 can be formed in the second wiring insulating film 20. The third wiring 182 can be connected to the second peripheral circuit element PT2 through a first wiring structure PW1 and a second wiring structure PW2.

[0104] In an exemplary embodiment of the present invention, the first source structure 190 may be connected to a third peripheral circuit element PT3 formed on the second substrate 30. For example, a fourth wiring 184 connected to the source contact 174 may be formed in the second wiring inter-insulating film 20. The fourth wiring 184 may be connected to the third peripheral circuit element PT3 through a first wiring structure PW1 and a second wiring structure PW2.

[0105] In an exemplary embodiment of the present invention, the input / output pad 195 may be connected to a fourth peripheral circuit element PT4 formed on the second substrate 30. For example, a fifth wiring 186 connected to the input / output pad 195 may be formed in the second inter-wiring insulating film 20. The fifth wiring 186 may be connected to the fourth peripheral circuit element PT4 via a first wiring structure PW1 and a second wiring forming structure PW2.

[0106] Reference Figure 3 and Figure 4B In a non-volatile memory device according to an exemplary embodiment of the present invention, the interface between the first impurity pattern 120 and the first semiconductor pattern 130 may be closer to the first source structure 190 than the erase control line ECL.

[0107] The interface between the first impurity pattern 120 and the first semiconductor pattern 130 can be located at a horizontal height higher than the horizontal height of the upper surface of the erase control line ECL. Therefore, the erase control line ECL can completely overlap with the first semiconductor pattern 130 (e.g., overlap in a direction perpendicular to the extension direction of the channel via).

[0108] In an exemplary embodiment of the present invention, the interface between the first impurity pattern 120 and the first semiconductor pattern 130 may overlap with the first molded insulating film 110 of the first surface MSa closest to the molded structures MS1 and MS2 (e.g., in a direction perpendicular to the extension direction of the channel hole).

[0109] Reference Figure 3 and Figure 4C In a non-volatile storage device according to an exemplary embodiment of the present invention, the first impurity pattern 120 may include a seam 120S.

[0110] The seam 120S may extend in a direction intersecting the surface of the first source structure 190 and may be formed in, for example, the filling portion 122 of the first impurity pattern 120. The seam 120S may be attributed to, for example, the characteristics of the vapor deposition process that forms the first impurity pattern 120.

[0111] In an exemplary embodiment of the present invention, the seam 120S may contact the first source structure 190. In an exemplary embodiment of the present invention, the seam 120S may be spaced apart from the first surface 120C1 of the first impurity pattern 120.

[0112] Figure 4C The interface between the first impurity pattern 120 and the first semiconductor pattern 130 is shown to overlap with the erase control line ECL (e.g., overlapping in a direction perpendicular to the extension direction of the channel via). However, the invention is not limited thereto. For example, in an exemplary embodiment of the invention, the first impurity pattern 120 may include a seam 120S, and the erase control line ECL may completely overlap with the first semiconductor pattern 130 (e.g., overlapping in a direction perpendicular to the extension direction of the channel via).

[0113] Reference Figure 3 and Figure 4D In a non-volatile storage device according to an exemplary embodiment of the present invention, the first impurity pattern 120 may include a protruding second surface 120C2.

[0114] The second surface 120C2 may be defined by the side surface of the tube 124 protruding from the filling portion 122 in a tubular shape. For example, the second surface 120C2 may be formed on the lower surface of the filling portion 122 from which the tube 124 does not protrude. The second surface 120C2 may be attributed to, for example, the characteristics of a finishing process used to form the first semiconductor pattern 130. (Refer to...) Figure 21 The finishing process for forming the first semiconductor pattern 130 is described.

[0115] Figure 4D The interface between the first impurity pattern 120 and the first semiconductor pattern 130 is shown to overlap with the erase control line ECL (e.g., overlapping in a direction perpendicular to the extension direction of the channel via). However, the invention is not limited thereto. For example, in an exemplary embodiment of the invention, the first impurity pattern 120 may include a protruding second surface 120C2, and the erase control line ECL may completely overlap with the first semiconductor pattern 130 (e.g., overlapping in a direction perpendicular to the extension direction of the channel via).

[0116] Reference Figure 3 and Figure 4EIn a non-volatile memory device according to an exemplary embodiment of the present invention, the first semiconductor pattern 130 may extend along the outline of the first impurity pattern 120.

[0117] The first impurity pattern 120 may include a third surface 120C3 facing the first semiconductor pattern 130. For example, the third surface 120C3 may be formed at the interface between the first impurity pattern 120 and the first semiconductor pattern 130. The first semiconductor pattern 130 may extend along the contour of the third surface 120C3.

[0118] In an exemplary embodiment of the present invention, the third surface 120C3 of the first impurity pattern 120 may be concave.

[0119] Reference Figure 3 and Figure 5B In a non-volatile memory device according to an exemplary embodiment of the present invention, the first semiconductor pattern 130 can be crystallized vertically. Figure 5B yes Figure 3 An inverted diagram of a portion of the channel hole CH.

[0120] The first semiconductor pattern 130 may include a plurality of crystal regions 130a to 130f arranged along a plane including a first direction X and a second direction Y. Each crystal region 130a to 130f may be crystallized perpendicularly. That is, the interface of the crystal regions 130a to 130f may extend along a third direction Z. Although in Figure 5B Only six crystal regions 130a to 130f are shown in the illustration, but this is merely an example, and the invention is not limited thereto. For example, the formed crystal regions may be more than six or fewer than six.

[0121] In an exemplary embodiment of the present invention, the crystal regions 130a to 130f of the first semiconductor pattern 130 can be formed by a MIC (metal-induced crystallization) process or a MILC (metal-induced lateral crystallization) process.

[0122] Figure 6 This is a cross-sectional view illustrating a non-volatile storage device according to an exemplary embodiment of the present invention. Figure 7A and Figure 7B yes Figure 6 Various magnified views of region R2 are shown. For ease of description, references will be briefly described or omitted. Figures 1 to 5B The repeated parts of the description.

[0123] Reference Figure 6 and Figure 7A In a non-volatile storage device according to an exemplary embodiment of the present invention, the first source structure 190 further includes a third conductive plate 192b.

[0124] The third conductive plate 192b may be located between the first conductive plate 192a and the first barrier conductive film 194a. The third conductive plate 192b may be a plate-shaped conductive film extending along the first surface MSa of the molded structures MS1 and MS2, and may include, for example, but not limited to, tungsten (W), aluminum (Al), copper (Cu) or combinations thereof.

[0125] The third conductive plate 192b may include a material different from that of the first conductive plate 192a. In an exemplary embodiment of the present invention, the first conductive plate 192a may include aluminum (Al), and the third conductive plate 192b may include tungsten (W). In an exemplary embodiment of the present invention, the thickness of the first conductive plate 192a may be greater than the thickness of the third conductive plate 192b.

[0126] Reference Figure 6 and Figure 7B In a non-volatile storage device according to an exemplary embodiment of the present invention, the first source structure 190 further includes a third barrier conductive film 194b.

[0127] The third barrier conductive film 194b may be located between the first conductive plate 192a and the third conductive plate 192b, and may extend along the first surface MSa of the molded structures MS1 and MS2.

[0128] The third barrier conductive film 194b can prevent the diffusion of elements contained in the first conductive plate 192a and / or the third conductive plate 192b. For example, the third barrier conductive film 194b may include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In an exemplary embodiment of the present invention, the third barrier conductive film 194b may include titanium nitride (TiN). In an exemplary embodiment of the present invention, the first barrier conductive film 194a and the third barrier conductive film 194b may be formed of the same material and have approximately the same thickness. However, the present invention is not limited thereto. For example, the first barrier conductive film 194a and the third barrier conductive film 194b may be formed of different materials and / or have different thicknesses.

[0129] Figure 8 This is a cross-sectional view illustrating a non-volatile storage device according to an exemplary embodiment of the present invention. Figure 9 It is used for explanation Figure 8 A schematic layout diagram of the gaps. For ease of explanation, references will be briefly described or omitted. Figures 1 to 7B The repeated parts of the description.

[0130] Reference Figure 8 and Figure 9 In a non-volatile storage device according to an exemplary embodiment of the present invention, the first source structure 190 includes a gap 190S.

[0131] A slit 190S can be formed in the first conductive plate 192a. The slit 190S can cut a portion of the first conductive plate 192a, and the slit 190S can expose a portion of the third conductive plate 192b. For example, the slit 190S can stop at the top surface of the third conductive plate 192b or can penetrate the top of the third conductive plate 192b. Multiple slits 190S can be formed. The slit 190S can prevent electromigration that may occur in the first conductive plate 192a by cutting a portion of the first conductive plate 192a.

[0132] In an exemplary embodiment of the present invention, each of the plurality of slits 190S may extend in a first direction X. In an exemplary embodiment of the present invention, each slit 190S may be disposed between channel holes CH arranged along a second direction Y.

[0133] Figure 10 This is a cross-sectional view illustrating a non-volatile storage device according to an exemplary embodiment of the present invention. Figure 11A and Figure 11B yes Figure 10 Various magnified views of region R3 are shown. For ease of description, references will be briefly described or omitted. Figures 1 to 5B The repeated parts of the description.

[0134] Reference Figure 10 and Figure 11A In a non-volatile storage device according to an exemplary embodiment of the present invention, the first surface MSa of the molded structures MS1 and MS2 is in contact with the first source structure 190.

[0135] The first molded insulating film 110, which is closest to the first surface MSa of the molded structures MS1 and MS2, can be in contact with the first barrier conductive film 194a. For example, the first substrate 10 may not be located between the first molded insulating film 110 and the first barrier conductive film 194a.

[0136] In an exemplary embodiment of the invention, the first impurity pattern 120 may have a tubular shape extending in the third direction Z. For example, the first impurity pattern 120 may not completely cover the first barrier conductive film 194a exposed by the channel hole CH. In an exemplary embodiment of the invention, the filling insulating pattern 134 may penetrate the first impurity pattern 120 and contact the first barrier conductive film 194a.

[0137] In an exemplary embodiment of the present invention, the thickness TH11 of the first impurity pattern 120 may be the same as the thickness TH12 of the first semiconductor pattern 130.

[0138] Reference Figure 10 and Figure 11BIn a non-volatile storage device according to an exemplary embodiment of the present invention, a first impurity pattern 120 covers a first barrier conductive film 194a exposed by a channel hole CH.

[0139] The first impurity pattern 120 may include a filling portion 122 that completely covers the first barrier conductive film 194a exposed by the channel hole CH. In an exemplary embodiment of the invention, the filling insulating pattern 134 may be spaced apart from the first barrier conductive film 194a.

[0140] Figure 11A and Figure 11B All examples show the interface between the first impurity pattern 120 and the first semiconductor pattern 130 overlapping with the erase control line ECL (e.g., overlapping in a direction perpendicular to the extension direction of the channel via). However, the invention is not limited thereto. For example, in an exemplary embodiment of the invention, the first surface MSa of the molded structures MS1 and MS2 contacts the first source structure 190, and the erase control line ECL may completely overlap with the first semiconductor pattern 130 (e.g., overlapping in a direction perpendicular to the extension direction of the channel via).

[0141] Figures 12 to 14 These are various cross-sectional views used to illustrate a non-volatile storage device according to exemplary embodiments of the present invention. For ease of description, references will be briefly described or omitted. Figures 1 to 5B The repeated parts of the description.

[0142] Reference Figure 12 The non-volatile storage device according to an exemplary embodiment of the present invention further includes a redistribution structure 70.

[0143] The redistribution structure 70 can be formed on the first inter-wire insulating film 50 and the passivation film 60. The redistribution structure 70 can be connected to the input / output pads 195 through the opening OP.

[0144] In an exemplary embodiment of the present invention, the rewiring structure 70 may include a rewiring blocking conductive film 74 and a rewiring 72.

[0145] The redistribution barrier conductive film 74 may extend along the upper surface of the passivation film 60 and the contour of the opening OP, and may be connected to the input / output pads 195. The redistribution barrier conductive film 74 may prevent the diffusion of elements contained in the redistribution 72. For example, the redistribution barrier conductive film 74 may include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0146] The redistribution 72 can be formed on the redistribution barrier conductive film 74. The redistribution 72 may include, for example, but not limited to, tungsten (W), aluminum (Al), copper (Cu), or combinations thereof.

[0147] Reference Figure 13 In a non-volatile memory device according to an exemplary embodiment of the present invention, the gate contact 172 has a step between the first molding structure MS1 and the second molding structure MS2.

[0148] Gate contact 172 may include a first gate contact 172a and a second gate contact 172b. The first gate contact 172a may be connected to each of the first gate electrodes ECL, GSL, and WL11 to WL1n, and the second gate contact 172b may be connected to each of the second gate electrodes WL21 to WL2n and SSL. Each of the second gate electrodes WL21 to WL2n and SSL may also be connected to a third wiring 182. In this case, at the interface between the first gate contact 172a and the second gate contact 172b, the width of the first gate contact 172a may be greater than the width of the second gate contact 172b.

[0149] In an exemplary embodiment of the present invention, the source contact 174 may have a step in the first interlayer insulating film 140. For example, the source contact 174 may include a first source contact 174a and a second source contact 174b. The first source contact 174a may contact the first source structure 190, and the second source contact 174b may contact the fourth wiring 184. In this case, at the interface between the first source contact 174a and the second source contact 174b, the width of the first source contact 174a may be greater than the width of the second source contact 174b.

[0150] In an exemplary embodiment of the present invention, the input / output contact 176 may have a step in the first interlayer insulating film 140. For example, the input / output contact 176 may include a first input / output contact 176a and a second input / output contact 176b. The first input / output contact 176a may contact the input / output pad 195, and the second input / output contact 176b may contact the fifth wiring 186. In this case, at the interface between the first input / output contact 176a and the second input / output contact 176b, the width of the first input / output contact 176a may be greater than the width of the second input / output contact 176b.

[0151] Reference Figure 14 In a non-volatile memory device according to an exemplary embodiment of the present invention, the bit line BL is located between a first molding structure MS1 and a second molding structure MS2.

[0152] The fifth to eighth interlayer insulating films 240, 242, 244 and 246, stacked sequentially from the first molded structure MS1, can be formed between the first molded structure MS1 and the second molded structure MS2. Bit lines BL can be formed on the eighth interlayer insulating film 246.

[0153] In an exemplary embodiment of the present invention, a first channel hole CH1 penetrating the first molding structure MS1 and a second channel hole CH2 penetrating the second molding structure MS2 may be formed. In an exemplary embodiment of the present invention, a first impurity pattern 120 and a first semiconductor pattern 130 may be formed in the first channel hole CH1. In an exemplary embodiment of the present invention, a third impurity pattern 220 and a second semiconductor pattern 230 may be formed in the second channel hole CH2.

[0154] In an exemplary embodiment of the present invention, the first line contact 170 can penetrate the seventh interlayer insulating film 244 and the eighth interlayer insulating film 246, and can be connected to the first semiconductor pattern 130. For example, the first line contact 170 can be connected to the first semiconductor pattern 130 through the second impurity pattern 136. For example, the bit line BL can be connected to the first semiconductor pattern 130 through the first line contact 170.

[0155] In an exemplary embodiment of the present invention, bit line BL can be connected to a second semiconductor pattern 230. For example, bit line BL can be connected to the second semiconductor pattern 230 via a second bit line contact 175. For example, the second bit line contact 175 can be connected to the second semiconductor pattern 230 via a third impurity pattern 220.

[0156] In an exemplary embodiment of the present invention, the second source structure 290 may be formed on the second surface MSb of the molded structures MS1 and MS2. The second source structure 290 may extend along the second surface MSb of the molded structures MS1 and MS2. For example, the second source structure 290 may be formed in the third interlayer insulating film 144.

[0157] The second source structure 290 can be connected to the second semiconductor pattern 230. For example, a fourth impurity pattern 236 connected to the second semiconductor pattern 230 can be formed on the second surface MSb of the molded structures MS1 and MS2. The second source structure 290 can be in contact with the fourth impurity pattern 236 and can be connected to the second semiconductor pattern 230. For example, the fourth impurity pattern 236 can be located between the second source structure 290 and the second semiconductor pattern 230.

[0158] The first source structure 190 can be provided as the common source line of the first molded structure MS1, and the second source structure 290 can be provided as the common source line of the second molded structure MS2.

[0159] In an exemplary embodiment of the present invention, the sixth to eighth wirings 282, 284, and 286 may be formed between the first molding structure MS1 and the second molding structure MS2. The sixth wiring 282 may connect the first gate contact 172a and the second gate contact 172b. The seventh wiring 284 may connect the first source contact 174a and the second source contact 174b. The eighth wiring 286 may connect the first input / output contact 176a and the second input / output contact 176b.

[0160] In the following text, reference will be made to Figures 15 to 31 A method for manufacturing a non-volatile storage device according to an exemplary embodiment of the present invention is described.

[0161] Figures 15 to 30 This is an intermediate stage diagram illustrating a method for manufacturing a non-volatile storage device according to an exemplary embodiment of the present invention. For ease of description, references will be briefly described or omitted. Figures 1 to 14 The repeated parts of the description.

[0162] Reference Figure 15 A first molded structure MS1 is formed on the first substrate 10.

[0163] First, a first substrate 10 may be provided. The first substrate 10 may include a cell array region CAR and an extended region EXT. In an exemplary embodiment of the present invention, the first substrate 10 may include impurities. For example, the first substrate 10 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0164] Next, a first molding structure MS1 can be formed on the first substrate 10. The first molding structure MS1 may include a plurality of first molding insulating films 110 and a plurality of first sacrificial films 310 alternately stacked on the first substrate 10. The first molding insulating films 110 and the first sacrificial films 310 may have etch selectivity relative to each other. For example, good etch selectivity of the first molding insulating film 110 relative to the first sacrificial film 310 can be obtained by using one etchant under one etch condition, while good etch selectivity of the first sacrificial film 310 relative to the first molding insulating film 110 can be obtained by using another different etchant under another different etch condition. For example, although the first molding insulating film 110 may include silicon oxide (SiO2) and the first sacrificial film 310 may include silicon nitride (Si3N4), the present invention is not limited thereto.

[0165] The first molded structure MS1 may include a first channel hole CH1. The first channel hole CH1 may penetrate the first molded structure MS1. In an exemplary embodiment of the present invention, the first channel hole CH1 may be recessed into a portion of the first substrate 10. For example, during the formation of the first channel hole CH1, a portion of the first substrate 10 (e.g., the top) may be etched away. For example, the lower surface of the first channel hole CH1 may be lower than the uppermost surface of the first substrate 10.

[0166] In an exemplary embodiment of the present invention, a first sacrificial pattern 320 may be formed to fill the first channel hole CH1. The first sacrificial pattern 320 may have etch selectivity relative to the first molded insulating film 110 and the first sacrificial film 310. Therefore, the first sacrificial pattern 320 may be selectively etched away without significant film loss of the first molded insulating film 110 and the first sacrificial film 310. For example, the first sacrificial pattern 320 may include, but is not limited to, polysilicon (p-Si).

[0167] Reference Figure 16 A second molding structure MS2 is formed on the first molding structure MS1.

[0168] The second molded structure MS2 may include a plurality of second molded insulating films 112 and a plurality of second sacrificial films 312 alternately stacked on the first molded structure MS1. The second molded insulating films 112 and the second sacrificial films 312 may have etch selectivity relative to each other. For example, good etch selectivity of the second molded insulating film 112 relative to the second sacrificial film 312 can be obtained by using one etchant under one etch condition, while good etch selectivity of the second sacrificial film 312 relative to the second molded insulating film 112 can be obtained by using another different etchant under another different etch condition. For example, although the second molded insulating film 112 may include silicon oxide (SiO2) and the second sacrificial film 312 may include silicon nitride (Si3N4), the invention is not limited thereto.

[0169] The second molding structure MS2 may include a second channel hole CH2. The second channel hole CH2 may penetrate the second molding structure MS2. In an exemplary embodiment of the present invention, the second channel hole CH2 may expose the first sacrificial pattern 320.

[0170] In an exemplary embodiment of the present invention, a second sacrificial pattern 325 may be formed to fill the second channel hole CH2. The second sacrificial pattern 325 may have etch selectivity relative to the second molded insulating film 112 and the second sacrificial film 312. Therefore, the second sacrificial pattern 325 can be selectively etched away without significant film loss of the second molded insulating film 112 and the second sacrificial film 312. For example, the second sacrificial pattern 325 may include, but is not limited to, polysilicon (p-Si).

[0171] Reference Figure 17 Pattern the first molded structure MS1 and the second molded structure MS2 of the extended region EXT.

[0172] The first molded structure MS1 and the second molded structure MS2 of the extended region EXT can be patterned into a stepped shape. For example, the first molded insulating film 110 and the first sacrificial film 310 can be stacked in a stepped manner, and the second molded insulating film 112 and the second sacrificial film 312 can also be stacked in a stepped manner. For example, the steps included in the first molded insulating film 110 and the first sacrificial film 310 can have a length extending in the second direction Y, and these lengths can gradually decrease from their lowest step to their highest step. In addition, the steps included in the second molded insulating film 112 and the second sacrificial film 312 can have a length extending in the second direction Y, and these lengths can gradually decrease from their lowest step to their highest step.

[0173] Next, a first interlayer insulating film 140 can be formed covering the first molded structure MS1 and the second molded structure MS2.

[0174] Reference Figure 18 This forms a channel hole CH that penetrates the first molded structure MS1 and the second molded structure MS2.

[0175] The first sacrificial pattern 320 and the second sacrificial pattern 325 can be removed. This allows the first channel hole CH1 and the second channel hole CH2 to communicate with each other to form the channel hole CH.

[0176] Reference Figures 19 to 20B An information storage film 132 and an impurity film 120L are formed in the channel pore CH. For reference, Figure 20A and Figure 20B yes Figure 19 Various magnified images of part R4.

[0177] The information storage film 132 may extend along the contour of the channel hole CH. In an exemplary embodiment of the present invention, the information storage film 132 may include a barrier insulating film 132c, a charge storage film 132b, and a tunnel insulating film 132a sequentially stacked in the channel hole CH.

[0178] An impurity film 120L can be formed on the information storage film 132 and can extend along the contour of the information storage film 132. A tunnel insulating film 132a can contact the impurity film 120L. The impurity film 120L can be formed, for example, by a vapor deposition process. In an exemplary embodiment of the invention, the impurity film 120L can fill at least a portion of the channel hole CH formed in the first substrate 10.

[0179] The impurity film 120L can be a semiconductor film containing impurities. The impurity film 120L can include, but is not limited to, semiconductor materials such as single-crystal silicon (Si), polycrystalline silicon (Si), organic semiconductor materials, or carbon (C) nanostructures. In an exemplary embodiment of the present invention, the impurity film 120L may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0180] like Figure 20B As shown, in an exemplary embodiment of the present invention, the impurity film 120L may include a seam 120S. The seam 120S may be attributed to, for example, a characteristic of the vapor deposition process that forms the impurity film 120L.

[0181] Reference Figures 21 to 22B This forms the first impurity pattern 120. For reference, Figure 22A and Figure 22B yes Figure 21 Various magnified images of part R5.

[0182] The upper portion of the impurity film 120L can be removed through the channel hole CH. Therefore, a first impurity pattern 120 can be formed filling at least a portion of the channel hole CH formed in the first substrate 10. The first impurity pattern 120 can be formed, for example, by a trimming process. In an exemplary embodiment of the invention, the trimming process can be an isotropic etching process, and can remove the portion of the impurity film 120L formed above the second molded structure MS2 and along the sidewall of the channel hole CH, while retaining the portion of the impurity film 120L formed to fill a portion of the channel hole CH near the bottom.

[0183] like Figure 22A As shown, in an exemplary embodiment of the present invention, the first impurity pattern 120 may include a recessed third surface 120C3. The third surface 120C3 may be attributed to, for example, the characteristics of the finishing process that forms the first impurity pattern 120.

[0184] like Figure 22B As shown, in an exemplary embodiment of the present invention, the first impurity pattern 120 may include a protruding fourth surface 120C4. The fourth surface 120C4 may be attributed to, for example, characteristics of the finishing process used to form the first impurity pattern 120.

[0185] Reference Figure 23 A first semiconductor pattern 130 is formed in the channel hole CH.

[0186] The first semiconductor pattern 130 can be formed on the first impurity pattern 120 and the information storage film 132. For example, the first semiconductor pattern 130 can extend along the upper surface of the first impurity pattern 120 and the side surface of the information storage film 132.

[0187] The first semiconductor pattern 130 may include, but is not limited to, semiconductor materials such as single-crystal silicon (Si), polycrystalline silicon (Si), organic semiconductor materials, or carbon (C) nanostructures.

[0188] In an exemplary embodiment of the present invention, a filling insulating pattern 134 may be formed on the first semiconductor pattern 130. The filling insulating pattern 134 may be formed to fill the interior of the tubular first semiconductor pattern 130 and the interior of the tube 124 of the first impurity pattern 120. The filling insulating pattern 134 may include, for example, but not limited to, silicon oxide (SiO2).

[0189] In an exemplary embodiment of the present invention, a second impurity pattern 136 may be formed on the first semiconductor pattern 130 and the filling insulating pattern 134. The second impurity pattern 136 may be formed to be connected to the first semiconductor pattern 130. For example, the second impurity pattern 136 may be formed in a second interlayer insulating film 142 covering the first interlayer insulating film 140. The second impurity pattern 136 may include, for example, but not limited to, impurity-doped polycrystalline silicon (p-Si).

[0190] Next, a third interlayer insulating film 144 can be formed covering the second impurity pattern 136 and the second interlayer insulating film 142.

[0191] In an exemplary embodiment of the present invention, a MIC (metal-induced crystallization) process or a MILC (metal-induced lateral crystallization) process can be further performed on the first semiconductor pattern 130. In this case, the first semiconductor pattern 130 can form multiple vertically crystallized crystal regions (e.g., Figure 5B (130a to 130f). In an exemplary embodiment of the present invention, in a MIC or MILC process, the first semiconductor pattern 130 may be annealed to transform amorphous silicon (a-Si) into polycrystalline silicon (p-Si).

[0192] Reference Figure 24 Multiple first sacrificial membranes 310 and multiple second sacrificial membranes 312 are removed.

[0193] For example, a word line cutting region WLC is formed that cuts the first molded structure MS1 and the second molded structure MS2. The word line cutting region WLC extends from the second surface MSb toward the first surface MSa and can cut the first molded structure MS1 and the second molded structure MS2.

[0194] Subsequently, the plurality of first sacrificial films 310 and the plurality of second sacrificial films 312 exposed by the word line cut region WLC can be removed. For example, a wet etching process, as an isotropic etching process, can be used to selectively remove the first sacrificial films 310 and 312 relative to the first molded insulating film 110 and the second molded insulating film 112. For example, when the first sacrificial films 310 and 312 are formed of silicon nitride (Si3N4) and the first molded insulating film 110 and 112 are formed of silicon oxide (SiO2), an etchant including phosphoric acid (H3PO4) can be used to perform the etching process.

[0195] Reference Figures 25 to 26B This forms the gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL. For reference, Figure 26A and Figure 26B yes Figure 25 Various magnified images of part R5.

[0196] Gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL are formed in the regions where the plurality of first sacrificial films 310 and the plurality of second sacrificial films 312 are removed. For example, the first sacrificial films 310 may be replaced by the first gate electrodes ECL, GSL, and WL11 to WL1n, and the second sacrificial films 312 may be replaced by the second gate electrodes WL21 to WL2n and SSL. The gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL may all comprise, for example, metals, metal nitrides, doped polysilicon (Si), metal silicides, or combinations thereof.

[0197] In an exemplary embodiment of the present invention, impurities contained in the first impurity pattern 120 can diffuse into the first semiconductor pattern 130. For example, as Figure 26A As shown, the third surface 120C3 of the first impurity pattern 120 can rise to the first surface 120C1 of the first impurity pattern 120. Alternatively, as... Figure 26B As shown, the fourth surface 120C4 of the first impurity pattern 120 can rise to the second surface 120C2 of the first impurity pattern 120.

[0198] In an exemplary embodiment of the present invention, the tube 124 of the first impurity pattern 120 can be formed by transforming the first semiconductor pattern 130 adjacent to the first impurity pattern 120.

[0199] The diffusion of impurities contained in the first impurity pattern 120 can be performed, for example, but not limited to, an annealing process.

[0200] Reference Figure 27Bit lines BL and first wiring structures PW1 are formed on the second surface MSb of the molded structures MS1 and MS2.

[0201] Bit line BL can be formed on a fourth interlayer insulating film 146 covering the third interlayer insulating film 144. In an exemplary embodiment of the present invention, bit line BL can be connected to each of the plurality of first semiconductor patterns 130 via a first bit contact 170.

[0202] In an exemplary embodiment of the present invention, gate contacts 172 and third wiring 182 connected to the respective gate electrodes ECL, GSL, WL11 to WL1n, WL21 to WL2n, and SSL can be formed in the extended region EXT. Additionally, source contacts 174 and fourth wiring 184 connected to the first source structure 190 can be formed in the extended region EXT. Furthermore, input / output contacts 176 and fifth wiring 186 connected to the input / output pads 195 can be formed in the extended region EXT.

[0203] Subsequently, a first wiring structure PW1 can be formed connecting the bit line BL, the third wiring 182, the fourth wiring 184, and the fifth wiring 186. For example, a second inter-wiring insulating film 20 covering the bit line BL, the third wiring 182, the fourth wiring 184, and the fifth wiring 186 can be formed. The first wiring structure PW1 may include a first wiring 22 and a first passage 24 formed in the second inter-wiring insulating film 20 and electrically connected to the bit line BL, the third wiring 182, the fourth wiring 184, and the fifth wiring 186.

[0204] Reference Figure 28 The second wiring compartment insulation film 20 is attached to the third wiring compartment insulation film 40.

[0205] For example, a second substrate 30 may be provided. The second substrate 30 may be provided as a second surface MSb facing the molded structures MS1 and MS2.

[0206] In an exemplary embodiment of the present invention, first to fourth peripheral circuit elements PT1, PT2, PT3 and PT4 may be formed on the second substrate 30. The first to fourth peripheral circuit elements PT1, PT2, PT3 and PT4 may form peripheral circuitry (e.g., page buffer, row decoder, control logic, etc.) that controls the operation of each memory cell.

[0207] Next, a second wiring structure PW2 can be formed on the second substrate 30. For example, a third inter-wiring insulating film 40 covering the first to fourth peripheral circuit elements PT1, PT2, PT3 and PT4 can be formed. The second wiring structure PW2 may include a second wiring 42 and a second channel 44 formed in the third inter-wiring insulating film 40 and electrically connected to the first to fourth peripheral circuit elements PT1, PT2, PT3 and PT4.

[0208] Subsequently, the first wiring 22 can be disposed on the second wiring 42, and the second wiring inter-insulation film 20 can be disposed on the third wiring inter-insulation film 40. The second wiring inter-insulation film 20 and the third wiring inter-insulation film 40 can then be attached. The first wiring structure PW1 and the second wiring structure PW2 can be electrically connected to each other. For example, the first wiring 22 exposed from the second wiring inter-insulation film 20 can contact the second wiring 42 exposed from the third wiring inter-insulation film 40. The first wiring 22 and the second wiring 42 can be electrically connected to each other by, for example but not limited to, copper-copper bonding (Cu-Cu bonding) processes.

[0209] Reference Figure 29 At least a portion of the first substrate 10 is removed to expose the first impurity pattern 120.

[0210] At least a portion of the first substrate 10 can be removed by, for example, a planarization process. The planarization process may include, for example, but is not limited to, a chemical mechanical polishing (CMP) process.

[0211] In an exemplary embodiment of the present invention, as the first impurity pattern 120 is exposed, the information storage film 132 may also be exposed.

[0212] Reference Figure 30 A first source structure 190 is formed on the first surface MSa of the molded structures MS1 and MS2.

[0213] The first source structure 190 may be formed to contact the exposed first impurity pattern 120. For example, the first source structure 190 may extend along the first substrate 10.

[0214] In an exemplary embodiment of the present invention, the first source structure 190 may include a first barrier conductive film 194a and a first conductive plate 192a. The first barrier conductive film 194a may be formed on, for example, a first substrate 10 and in contact with a first impurity pattern 120. The first conductive plate 192a may be formed on the first barrier conductive film 194a.

[0215] In an exemplary embodiment of the present invention, the first barrier conductive film 194a may include titanium nitride (TiN), and the first conductive plate 192a may include tungsten (W) and / or aluminum (Al).

[0216] In an exemplary embodiment of the present invention, the first source structure 190 may be formed to contact the source contact 174.

[0217] In an exemplary embodiment of the present invention, input / output pads 195 may be formed on the first interlayer insulating film 140. For example, the first source structure 190 may extend along the first substrate 10. In an exemplary embodiment of the present invention, the input / output pads 195 and the first source structure 190 may be formed at the same horizontal height. For example, the input / output pads 195 may include: a second barrier conductive film 199 comprising the same material as the first barrier conductive film 194a; and a second conductive plate 197 comprising the same material as the first conductive plate 192a.

[0218] In an exemplary embodiment of the present invention, the input / output pad 195 may be formed to contact the input / output contact 176.

[0219] Subsequently, referring to Figure 3 A first inter-wire insulating film 50 and a passivation film 60 can be formed on the first surface MSa of the molded structures MS1 and MS2. In an exemplary embodiment of the present invention, the first inter-wire insulating film 50 and the passivation film 60 may include openings OP that expose at least a portion of the input / output pads 195.

[0220] Impurity patterns attached to the source structure may require high-temperature (e.g., approximately 400°C or higher) annealing processes to activate the impurities (e.g., phosphorus (P), arsenic (As), etc.). However, annealing processes performed after copper-copper bonding processes may not be feasible at high temperatures due to the heat resistance of copper (Cu).

[0221] In a method for manufacturing a non-volatile storage device according to an exemplary embodiment of the present invention, a copper-copper bonding process (e.g., referred to above) can be used. Figure 28 The first semiconductor pattern 130 can be formed before the steps described above (e.g., referred to above). Figure 23 The steps described above). Therefore, the annealing process of the first semiconductor pattern 130 can be performed before the copper-copper bonding process (e.g., referred to above). Figure 26A and Figure 26B The steps described can effectively activate impurities to provide a non-volatile storage device with enhanced product reliability and performance.

[0222] To enhance the performance of non-volatile memory devices, semiconductor patterning MIC processes or MILC processes can be performed (e.g., as described above). Figure 23(The steps described). However, the MIC process or MILC process has the following problem: byproducts (e.g., nickel silicide (NiSi2)) remain in the lower part of the channel hole (e.g., the channel hole CH adjacent to the first substrate 10).

[0223] In a method for manufacturing a non-volatile memory device according to an exemplary embodiment of the present invention, by removing at least a portion of the first substrate 10 (e.g., as described above), Figure 29 The described steps can remove at least a portion of the first impurity pattern 120 adjacent to the first substrate 10. This can effectively remove byproducts of MIC or MILC processes and can provide a non-volatile memory device with enhanced product reliability and performance.

[0224] Figure 31 This is an intermediate stage diagram illustrating a method for manufacturing a non-volatile memory device according to an exemplary embodiment of the present invention. For reference, Figure 31 It is used for explanation Figure 28 The following steps are illustrated in the diagram.

[0225] Reference Figure 31 The first substrate 10 is completely removed to expose the first impurity pattern 120.

[0226] The first substrate 10 can be removed until the first surface MSa of the molded structures MS1 and MS2 is exposed. Since the removal of the first substrate 10 is similar to that described above... Figure 29 Due to the removal of the description, a detailed description will not be provided below.

[0227] Subsequently, referring to Figure 10 A first inter-wire insulating film 50 and a passivation film 60 can be formed on the first surface MSa of the molded structures MS1 and MS2.

[0228] In summary, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the exemplary embodiments of the invention disclosed herein are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A non-volatile storage device, the non-volatile storage device comprising: A source structure, the source structure comprising a conductive plate and a barrier conductive film, the barrier conductive film extending along the surface of the conductive plate; A molded structure comprising a plurality of gate electrodes sequentially stacked on the barrier conductive film in a first direction; A channel hole that penetrates the molded structure to expose the barrier conductive film; Impurity pattern, the impurity pattern being in contact with the barrier conductive film and formed in the channel hole; and A semiconductor pattern is formed in the channel hole, extends along the side surface of the channel hole from the impurity pattern, and intersects with the plurality of gate electrodes. The plurality of gate electrodes include erase control lines adjacent to the barrier conductive film, and The interface between the impurity pattern and the semiconductor pattern overlaps with the erase control line, wherein the interface between the impurity pattern and the semiconductor pattern is perpendicular to the first direction.

2. The non-volatile storage device according to claim 1, further comprising: An information storage film extends along the side surface of the channel aperture, is located between the molded structure and the impurity pattern, and is located between the molded structure and the semiconductor pattern.

3. The non-volatile storage device according to claim 2, wherein, The impurity pattern extends along a portion of the side surface of the information storage film, and The semiconductor pattern extends along another portion of the side surface of the information storage film.

4. The non-volatile storage device according to claim 2, wherein, The information storage film is in contact with the barrier conductive film.

5. The non-volatile storage device according to claim 1, wherein, As the impurity pattern moves away from the semiconductor pattern, the impurity concentration of the impurity pattern increases.

6. The non-volatile storage device according to claim 1, wherein, The impurity pattern contains n-type impurities.

7. The non-volatile storage device according to claim 1, wherein, The impurity pattern includes: A filling portion, the filling portion covering the barrier conductive film exposed by the channel aperture; and A tube that protrudes from the filled portion toward the semiconductor pattern.

8. The non-volatile storage device according to claim 7, wherein, The thickness of the tube in the impurity pattern is the same as the thickness of the semiconductor pattern.

9. The non-volatile storage device according to claim 1, further comprising: A filling insulating pattern is formed in the channel hole, the filling insulating pattern penetrating the impurity pattern and contacting the barrier conductive film.

10. The non-volatile storage device according to claim 9, wherein, The thickness of the impurity pattern is the same as the thickness of the semiconductor pattern.

11. A non-volatile storage device, the non-volatile storage device comprising: A molded structure comprising a first surface and a second surface opposite to each other in a first direction, the molded structure comprising a plurality of molded insulating films and a plurality of gate electrodes alternately stacked in the first direction from the first surface toward the second surface; A source structure comprising: a first conductive plate extending along a first surface of the molding structure and formed on the first surface of the molding structure; and a first barrier conductive film extending along the first surface of the molding structure and located between the molding structure and the first conductive plate; A channel hole extending from the second surface toward the first surface and penetrating the molded structure; A first impurity pattern is formed in the channel hole, which is in contact with the first barrier conductive film. A semiconductor pattern extending from the first impurity pattern toward the second surface of the molded structure and formed in the channel hole; and Bit lines, which are connected to the semiconductor pattern and formed on the second surface of the molded structure, The plurality of gate electrodes include erase control lines adjacent to the first barrier conductive film, and The interface between the impurity pattern and the semiconductor pattern overlaps with the erase control line, wherein the interface between the impurity pattern and the semiconductor pattern is perpendicular to the first direction.

12. The non-volatile storage device according to claim 11, wherein, The width of the channel hole decreases from the second surface toward the first surface.

13. The non-volatile storage device according to claim 11, further comprising: A second conductive plate extends along the first surface of the molded structure, is located between the first conductive plate and the first barrier conductive film, and comprises a material different from that of the first conductive plate.

14. The non-volatile storage device according to claim 13, further comprising: A second barrier conductive film extends along the first surface of the molded structure and is located between the first conductive plate and the second conductive plate.

15. The non-volatile storage device according to claim 13, further comprising: A gap that exposes the second conductive plate and is formed in the first conductive plate.

16. The non-volatile storage device according to claim 11, further comprising: A substrate, the substrate extending along the first surface of the molded structure and situated between the first barrier conductive film and the molded structure. The first impurity pattern penetrates the substrate and comes into contact with the first barrier conductive film.

17. The non-volatile storage device according to claim 11, wherein, The first surface of the molded structure is in contact with the first barrier conductive film.

18. A non-volatile storage device, the non-volatile storage device comprising: A molded structure comprising a first surface and a second surface opposite to each other, the molded structure comprising a plurality of gate electrodes sequentially stacked from the first surface toward the second surface; A source structure that extends along the first surface of the molding structure and is formed on the first surface of the molding structure; A channel hole extending from the second surface toward the first surface and penetrating the molded structure; Impurity patterns are connected to the source structure and formed in the channel vias; A semiconductor pattern extending from the impurity pattern toward the second surface of the molded structure and formed in the channel hole; Bit lines, which are connected to the semiconductor pattern and formed on the second surface of the molded structure; A first inter-wire insulating film covers the bit line and is formed on the second surface of the molded structure; Substrate, the substrate facing the second surface of the molded structure; Peripheral circuit elements, the peripheral circuit elements being formed on the substrate; and A second inter-wiring insulating film covers the peripheral circuit elements and is located between the substrate and the first inter-wiring insulating film.

19. The non-volatile storage device according to claim 18, wherein, The source structure includes: A conductive plate extending along and formed on the first surface of the molded structure; and A barrier conductive film extends along the first surface of the molded structure and is located between the molded structure and the conductive plate.

Images