Reverse conducting insulated gate bipolar transistor with reduced forward recovery voltage

Abstract

Reverse conducting insulated gate bipolar transistors with reduced forward recovery voltage are disclosed. According to an embodiment of a power semiconductor device, the device includes a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to a first major surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first major surface of the semiconductor substrate. An average lateral spacing between adjacent ones of the second trenches is greater than an average lateral spacing between adjacent ones of the first trenches. Additional embodiments of power semiconductor devices are described as are corresponding methods of production.

Description

Background Technology

[0001] A reverse-conducting insulated-gate bipolar transistor (RC-IGBT) integrates an insulated-gate bipolar transistor (IGBT) and a freewheeling diode onto a single chip (die). Many IGBT applications have a mode in which the freewheeling current flows from the emitter to the collector. For such freewheeling operation, the freewheeling diode is connected in anti-parallel to the IGBT.

[0002] Trench patterning, similar to that used in IGBTs, can be used at the anode of an integrated diode to provide improved diode switching durability. The resulting trench electrode, formed within the diode region, shields the anode of the integrated diode from a high electric field, preventing punch-through and thus providing switching durability. RC-IGBTs with sufficiently high switching durability can be used in applications employing hard switching. In the case of hard switching, voltage and current are applied to the IGBT during the turn-on transition. Therefore, when the IGBT is hard-switched, the collector current and collector-emitter voltage change drastically.

[0003] However, increasing IGBT switching robustness typically results in a higher forward recovery voltage (Vfr) for the integrated diode. When the IGBT is turned on, the diode is blocked. As the IGBT begins to turn off and the IGBT's switching current begins to commutate into the diode, the IGBT's collector-emitter voltage begins to increase, and the diode voltage, in turn, begins to decrease. As current continues to commutate into the diode, a voltage undershoot occurs. This undershoot is commonly referred to as the diode's forward recovery voltage (Vfr). The peak value of the forward recovery voltage Vfr can be significant. For example, for 1200V technology, a Vfr of approximately 300V is not uncommon. Such a Vfr can interfere with the operation of neighboring IGBTs and damage the gate driver circuitry used for the IGBTs.

[0004] The diode of an RC-IGBT can include trench electrodes formed in a semiconductor substrate to enhance switching robustness, as explained above. Eliminating the trench electrode from the diode region of an RC-IGBT device drastically reduces the diode's Vfr. In diodes without trench electrodes, the reduction in anode efficiency—which is a preferred measure for improving diode performance—is limited by the decrease in switching robustness. That is, a highly doped diode anode region provides sufficient switching robustness but is highly efficient and increases switching losses. Therefore, RC-IGBT devices without trench electrodes and with a doped anode region to minimize switching losses can be used in soft-switching applications where anode efficiency may be relatively high. However, in hard-switching applications, trench electrodes are preferred in the diode region due to the required switching robustness.

[0005] Therefore, there is a trade-off between anode efficiency and switching durability. If the anode region is highly doped, a trench electrode is not needed because the highly doped anode provides sufficient switching durability, but at the cost of increased switching losses. A less doped anode region has lower efficiency, which is good for reducing switching losses, but reduces switching durability, which is problematic for applications using hard switches.

[0006] Therefore, there is a need for improved RC-IGBTs with low anode efficiency and high switching durability. Summary of the Invention

[0007] According to an embodiment of a power semiconductor device, the power semiconductor device includes a semiconductor substrate, the semiconductor substrate including an IGBT (Insulated Gate Bipolar Transistor) region and a diode region, the IGBT region including an IGBT, the diode region including a diode, the IGBT region having a first region in a top view and the diode region having a second region in a top view, wherein the IGBT region includes a plurality of first trenches, the plurality of first trenches including first trench electrodes and extending perpendicular to a first main surface of the semiconductor substrate, wherein the diode region includes a plurality of second trenches, the plurality of second trenches having second trench electrodes and extending perpendicular to the first main surface of the semiconductor substrate, wherein the plurality of first trenches provide a first capacitance between the first trench electrodes in the IGBT region and the semiconductor substrate, and the plurality of second trenches provide a second capacitance between the second trench electrodes in the diode region and the semiconductor substrate, wherein the capacitance density of the second capacitance per second region is less than the capacitance density of the first capacitance per first region.

[0008] According to another embodiment of the power semiconductor device, the power semiconductor device includes a semiconductor substrate, the semiconductor substrate including an IGBT region and a diode region, the IGBT region having an IGBT, the diode region having a diode, wherein the IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate, wherein the diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate, wherein the average lateral spacing between adjacent second trenches in the second trenches is greater than the average lateral spacing between adjacent first trenches in the first trenches.

[0009] According to an embodiment of a method for manufacturing a power semiconductor device, the method includes: forming an IGBT in an IGBT region of a semiconductor substrate, the IGBT region having a first region in a top view; and forming a diode in a diode region of the semiconductor substrate, the diode region having a second region in a top view, wherein forming the IGBT includes forming a plurality of first trenches having first trench electrodes and extending perpendicular to a first main surface of the semiconductor substrate in the IGBT region, wherein forming the diode includes forming a plurality of second trenches having second trench electrodes and extending perpendicular to the first main surface of the semiconductor substrate in the diode region, such that the capacitance density of the capacitance provided between the plurality of second trenches and the semiconductor substrate per second region is less than the capacitance density of the capacitance provided between the plurality of first trenches and the semiconductor substrate per first region.

[0010] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0011] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0012] Figure 1 The illustration shows a top view of a power semiconductor device including an RC-IGBT (reverse conduction IGBT).

[0013] Figure 2A The diagram shows a cross-sectional view of a portion of the diode region of an RC-IGBT, the cross-sectional view being along... Figure 1 It was obtained from the line marked II.

[0014] Figure 2B The diagram shows a cross-sectional view of a portion of the IGBT region of an RC-IGBT, which is also along... Figure 1 It was obtained from the line marked II.

[0015] Figure 3 The diagram shows the voltage (V) and current (I) waveforms for the RC-IGBT when the IGBT transitions from the on state to the off state and the diode transitions from the blocking state to the freewheeling (conduction) state.

[0016] Figures 4 to 6 The figures show corresponding cross-sectional views of different contact trench embodiments for the diode region of an RC-IGBT. Detailed Implementation

[0017] This document describes an RC-IGBT with low anode efficiency and high switching durability, along with corresponding manufacturing methods. Several embodiments described herein achieve high switching durability without excessively increasing anode efficiency. To further refine anode efficiency and switching durability, the anode contact region of the integrated diode can be specifically designed, as described herein. It should be understood that, unless otherwise specifically indicated, features of the various embodiments described herein can be combined with each other.

[0018] Figure 1 The figure shows a top view of a power semiconductor device 100. The power semiconductor device 100 includes a semiconductor substrate 102. The semiconductor substrate 102 may include one or more of various semiconductor materials used to form integrated circuit devices, such as, but not limited to, silicon (Si), silicon carbide (SiC), germanium (Ge), silicon-germanium (SiGe), gallium nitride (GaN), and gallium arsenide (GaAs). The semiconductor substrate 102 may be a bulk semiconductor material, or may include one or more epitaxial layers grown on the bulk semiconductor material.

[0019] The power semiconductor device 100 includes a cell region 104 and an outer peripheral region 106. An RC-IGBT is formed in the cell region 104, and the outer peripheral region 106 laterally surrounds the cell region 104 and electrically isolates the RC-IGBT from the edge 108 of the semiconductor substrate 102. Within the cell region 104, the semiconductor substrate 102 includes an IGBT region 110 and a diode region 112. The IGBT region 110 includes an IGBT, and the diode region 112 includes a diode. The IGBT region 110 and the diode region 112 are located within... Figure 1The image is shown as having a strip layout. In this example, IGBT cells and diode cells are staggered relative to each other in a strip-like manner. This arrangement allows for a more uniform distribution of heat generated primarily in the diode region 112 and thus allows for more efficient cooling. Each IGBT strip may include multiple trenches, such as at least two, at least five, or at least ten trenches forming a corresponding IGBT cell. Each IGBT cell includes at least one trench configured to control the IGBT current. In some embodiments, each IGBT cell may include trenches connected to the emitter potential and trenches connected to the gate potential, as will be described in more detail below. In some embodiments, trenches connected to the emitter potential may be staggered with trenches connected to the gate potential. Each diode cell includes multiple trenches, such as at least two, at least five, or at least ten trenches. In one embodiment, the multiple trenches may include trenches connected to the same potential (e.g., emitter potential). However, this is only an example, and other arrangements are possible. In some embodiments, each IGBT strip may include multiple IGBT cells, and each diode strip may include multiple diode cells. Each of the IGBT region 110 and the diode region 112 can have any desired layout. In one embodiment, the diode region is embedded in the IGBT. The IGBT region 110 may be adjacent to an edge-terminating structure formed in the outer peripheral region 106.

[0020] Figure 2A The diagram follows Figure 1 A cross-sectional view of the portion of diode region 112 obtained by the line marked II. Figure 2B The diagram also follows Figure 1 The cross-sectional view of the IGBT region 110 obtained by the line marked II.

[0021] exist Figure 1 In the top view, the IGBT region 110 has a first region, and the diode region 112 has a second region. Based on... Figure 1The strip layout shown in the diagram has a first region occupied by IGBT region 110 that is discontinuous and includes the region of each IGBT strip. The second region occupied by diode region 112 is also discontinuous and similarly includes the region of each diode strip. Therefore, IGBT region 110 can be a combination of multiple discontinuous IGBT sub-regions (e.g., strips) used to form IGBT region 110, and diode region 112 can also be considered as a combination of multiple discontinuous diode sub-regions (e.g., strips) used to form diode region 112. In other words, the first region occupied by IGBT region 110 is the total region of all IGBT sub-regions, and the second region occupied by diode region 112 is the total region of all diode sub-regions. For the first trench 114, which is similarly arranged in strips, the first region can be calculated by adding the top view region of the first trench 114 and the top view region of the mesa portion formed between the first trenches 114. Figure 1 The discontinuous arrangement of the first (IGBT) region and the second (diode) region is due to the interleaving of the IGBT "strips" and the diode "strips". Alternatively, each of the first region occupied by the IGBT region 110 and the second region occupied by the diode region 112 can be continuous. For example, the IGBT region 110 may not be interrupted by the diode region 112 and may be formed in the semiconductor substrate 102 adjacent to the diode region 112.

[0022] The IGBT region 110 includes a first trench 114 having a first trench electrode 116 insulated from the surrounding semiconductor substrate 102 by a first insulating layer 118. The first trench 114 of the IGBT region 110 is perpendicular to (…). Figure 2B The first main surface 103 of the semiconductor substrate 102 extends in the direction 'x'. In some embodiments, the number of first trenches formed in the first region may be 100 or more, 500 or more, or 1000 or more. In some embodiments, the number of second trenches formed in the second region may be 100 or more, 500 or more, or 1000 or more.

[0023] Some of the first trench electrodes 116 are gate (G) electrodes used to control the conductive channel 120 in the body region 122 of the IGBT. The other electrodes in the first trench electrodes 116 are field (F) electrodes used to configure the electric field potential within the semiconductor substrate 102 during operation of the controlled RC-IGBT. The field electrode F can be electrically connected to a different potential than the gate electrode G. For example, the field electrode F can be electrically connected to the emitter potential, ground, or can be electrically floating.

[0024] Body region 122 separates the emitter region 124 of the IGBT from the drift region 126. When the conductive channel 120 is present, the emitter region 124 is electrically connected to the drift region 126. The conductive channel 120 is controlled by the voltage applied to the gate electrode G of the IGBT.

[0025] The IGBT also includes a collector region 128 on the surface 105 of the semiconductor substrate 102 opposite to the emitter region 124. The emitter region 124, drift region 126, and conductive channel 120 are of a first conductivity type, and the body region 122 and collector region 128 are of a second conductivity type opposite to the first conductivity type. For example, in the case of an n-type conductive channel 120, the emitter region 124 and drift region 126 are n-type, and the body region 122 and collector region 128 are p-type. Conversely, in the case of a p-type conductive channel 120, the emitter region 124 and drift region 126 are p-type, and the body region 122 and collector region 128 are n-type. An optional field stop region 130 of the first conductivity type may be formed in the semiconductor substrate 102 between the drift region 126 and the collector region 128. Even if a field stop region 130 is provided in the IGBT region 110, it may be omitted in the diode region 112. In some embodiments, the field stop regions 130 in the diode region 112 and the IGBT region 110 may have different doping concentrations, different doping profiles, or different thicknesses, or combinations thereof.

[0026] The diode region 112 of the power semiconductor device 100 includes a second trench 132, the second trench 132 having a second trench electrode 134 insulated from the surrounding semiconductor substrate 102 by a second insulating layer 136. The second trench 132 of the diode region 112 is perpendicular to ( Figure 2A The first main surface 103 of the semiconductor substrate 102 extends in the direction 'x'. For trenches 132 arranged in a similar stripe pattern, the second region of the diode region 112 can be calculated by adding the top view region of the second trench 132 and the top view region of the mesa portion formed between the second trenches 132.

[0027] The cell structure of diode region 112 can be similar to that of IGBT region 110. However, the emitter region 124 is omitted from diode region 112. Additionally, diode region 112 has a cathode region 138 of a first conductivity type at the second main surface 105 of semiconductor substrate 102 instead of a collector region 128 of a second conductivity type. At the first main surface 103 of semiconductor substrate 102, first metallization 140 can be electrically connected to the body region 122, emitter region 124, and field electrode F in IGBT region 110, and is electrically connected to the second trench electrode 134 and anode region 141 in diode region 112. The gate electrode G of IGBT region 110 is insulated from first metallization 140 by an insulating material 142, such as a dielectric.

[0028] The electrical connection to the first metallization 140 can be formed via a first contact trench 144 and a second contact trench 146, the first contact trench 144 being perpendicular to ( Figure 2B The first main surface 103 of the semiconductor substrate 102 in the IGBT region 110 extends in the direction 'x', and the second contact trench 146 is also perpendicular to ( Figure 2A The first main surface 103 of the semiconductor substrate 102 extends in the diode region 112 (direction 'x'). In the IGBT region 110, the first metallization 140 is electrically connected to the body region 122, emitter region 124, and field electrode F of the IGBT via a first contact trench 144. In the diode region 112, the first metallization 140 is electrically connected to the second trench electrode 134 and anode region 141 of the diode via a second contact trench 146. The semiconductor substrate 102 may include a highly doped region 148 of a second conductivity type, which is adjacent to at least a portion of the bottom and sidewalls of the first contact trench 144 and the second contact trench 146.

[0029] According to one embodiment, the doping concentration of the semiconductor substrate 102 at least in the highly doped region 148 at the sidewalls of the second contact trench 146 is lower than the doping concentration at the bottom of the second contact trench 146 in the diode region 112. This doping variation in the semiconductor substrate 102 can be achieved by correspondingly controlling the doping profile of the highly doped region 148.

[0030] The higher doping concentration at the bottom of the second contact trench 146 in diode region 112 provides good ohmic contact with the first metallization 140, while the lower doping along the sidewalls reduces anode efficiency, which is good for lower switching losses.

[0031] The second metallization 150 contacts the collector region 128 of the IGBT and the cathode region 138 of the diode at the second main surface 105 of the semiconductor substrate 102.

[0032] Figure 3 The diagram illustrates the voltage (V) and current (I) waveforms for the RC-IGBT as the IGBT transitions from the on state to the off state and the diode transitions from the blocking state to the freewheeling (conduction) state. Before time t1, the collector-emitter voltage V of the IGBT is... CE When the voltage is at or near zero volts and the diode is in the blocking state, the diode voltage V during the blocking state is... Diode It is at peak blocking level. As the IGBT begins to turn off at time t1, the collector-emitter voltage V of the IGBT... CE It starts to rise and the diode voltage V Diode It begins to decrease. At time t2, the collector current I of the IGBT... C It begins to decrease, and the diode voltage V Diode The undercurrent begins. This occurs during the IGBT's turn-off period, specifically at the diode voltage V. Diode The overshoot is usually referred to as the forward recovery voltage (V) of a diode. fr The forward recovery voltage V of the diode. fr V reaches its peak at time t3. fr_peak At this point, the undershoot begins to decrease. Ultimately, the diode voltage V... Diode Reaching the forward voltage V of the diode f The diode becomes forward biased. When the diode is forward biased and the IGBT is off, freewheeling current flows through the diode.

[0033] Each trench 114, 132 of the RC-IGBT has a MOS (Metal-Oxide-Semiconductor) interface with a certain capacitance. More specifically, the first trench 114 in the IGBT region 110 provides a first capacitance C1 between the first trench electrode 116 in the IGBT region 110 and the semiconductor substrate 102. Similarly, the second trench 132 in the diode region 112 provides a second capacitance C2 between the second trench electrode 134 in the diode region 112 and the semiconductor substrate 102. As used herein, the capacitance is calculated by C = kεA / d, where k is a constant, ε is the dielectric constant of the corresponding insulating layers 118, 136 that insulate the IGBT trench 114 or the diode trench 132 from the semiconductor substrate 102, respectively, A is the corresponding area of ​​the capacitance, and d is the average thickness of the corresponding insulating layers 118, 136. The area A of the corresponding capacitor can be calculated by the surface area of ​​the corresponding trench 114 / 132 facing the semiconductor substrate 102 on one side and the surface area of ​​the corresponding electrode 116 / 134 in the trench 114 / 132 from the semiconductor substrate 102 on the other side (via the insulating layer 118 / 136).

[0034] To ensure both low anode efficiency and high switching durability of the RC-IGBT, the capacitance density of the second capacitor C2 in the second region of diode region 112 can be less than the capacitance density of the first capacitor C1 in the first region of IGBT region 110. In other words, the ratio of C2 to F2 is less than the ratio of C1 to F1, where C2 is the total capacitance in diode region 112, F2 is the capacitance in the second region of diode region 112, C1 is the total capacitance in IGBT region 110, and F1 is the capacitance in the first region of IGBT region 110. Reducing the capacitance density of diode region 112 relative to the capacitance density of IGBT region 110 allows for a reduction in the forward recovery voltage V of the diode. fr The upper undershoot. However, to support hard-switching applications, diode region 112 is still provided with a second trench electrode 134.

[0035] In one embodiment, the capacitance density of the second capacitor C2 of diode region 112 in the second region is 1 / 10 to 2 / 3 of the capacitance density of the first capacitor C1 of IGBT region 110 in the first region. In another embodiment, the capacitance density of the second capacitor C2 of diode region 112 in the second region is 1 / 4 to 2 / 3 of the capacitance density of the first capacitor C1 of IGBT region 110 in the first region. In some embodiments, the capacitance density of the second capacitor C2 of diode region 112 in the second region is 1 / 3 to 5 / 9 of the capacitance density of the first capacitor C1 of IGBT region 110 in the first region.

[0036] The capacitance density of the second capacitor C2 in the diode region 112, relative to the second region, can be made smaller in the semiconductor substrate 102 by making the second trench 132 in the diode region 112 terminate more shallowly in the second trench 112 compared to the first trench 114 in the IGBT region 110. For example, as in Figure 2A and Figure 2B As shown in the diagram. According to this embodiment, the first trench 114 in the IGBT region 110 extends in the semiconductor substrate 102 to a first depth D1 as measured from the first main surface 103 of the semiconductor substrate 102, and the second trench 132 in the diode region 112 extends in the semiconductor substrate 102 to a second depth D2, the second depth D2 being less than the first depth D1 (i.e., D2). <D1)。

[0037] Individually or additionally, the capacitance density of the second capacitor C2 per unit area in the diode region 112 can be made smaller per unit area than the capacitance density of the first capacitor C1 per unit area in the IGBT region 110 by forming fewer second trenches 132 per unit area compared to the first trenches 114 present per unit area in the IGBT region 110, and / or by spacing the second trenches 132 further apart in the diode region 112 compared to spacing the first trenches 114 in the IGBT region 110, for example, as in Figure 2A and Figure 2B As shown in the diagram. According to this embodiment, the average lateral spacing S between adjacent second trenches in the second trench 132 of the diode region 112 is... L2 The average lateral spacing S between adjacent first trenches in the first trench 114 of the IGBT region 110 is greater than the average lateral spacing S between adjacent first trenches. L1 (i.e. S) L2 >S L1 In one embodiment, the average lateral spacing S between adjacent second trenches in the second trench 132 of the diode region 112 is... L2 The average lateral spacing S between adjacent first trenches in the first trench 114 of the IGBT region 110 is... L1 The average lateral spacing S between adjacent second trenches in the second trench 132 of the diode region 112 is 1.5 to 30 times. In another embodiment, the average lateral spacing S between adjacent second trenches in the second trench 132 of the diode region 112 is... L2 The average lateral spacing S between adjacent first trenches in the first trench 114 of the IGBT region 110 is... L1 1.5 to 10 times. In another embodiment, the average lateral spacing S between adjacent second trenches in the second trench 132 of the diode region 112 is 1.5 to 10 times. L2 The average lateral spacing S between adjacent first trenches in the first trench 114 of the IGBT region 110 is greater than 0.3 μm and less than 20 μm. L1 It is 0.6μm or smaller.

[0038] Alternatively, the capacitance density of the second capacitor C2 of the diode region 112 in the second region can be made smaller than the capacitance density of the first capacitor C1 of the IGBT region 110 in the first region by separating the second trench 132 along the longitudinal extension direction (z-axis) of the trench 132 in the diode region 112. Instead of having a continuous trench 132 extending substantially from one end of the diode region 112 to the other end, each second trench 132 in the diode region 112 can be segmented into a plurality of trench portions formed along the longitudinal extension direction of the second trench 132. Adjacent trench portions of the same second trench 132 in the diode region 112 are separated from each other by a substrate region of the semiconductor substrate 102.

[0039] Alternatively, the capacitance density of the second capacitor C2 of the diode region 112 in the second region can be made smaller than the capacitance density of the first capacitor C1 of the IGBT region 110 in the first region by making the insulating layer 136 in the diode region 112 that separates the second trench electrode 134 from the semiconductor substrate 102 thicker than the insulating layer 118 in the IGBT region 110 that separates the first trench electrode 116 from the semiconductor substrate 102.

[0040] Alternatively, the dielectric constant (ε) of the insulating layer separating the second trench electrode 134 from the semiconductor substrate 102 in diode region 112 can be selected to be less than the dielectric constant of the insulating layer 118 separating the first trench electrode 116 from the semiconductor substrate 102 in IGBT region 110, thereby making the capacitance density of the second capacitor C2 in diode region 112 by the second region less than the capacitance density of the first capacitor C1 in IGBT region 110 by the first region. For example, the insulating layer 136 in diode region 112 that pads the sidewalls and bottom of the second trench 132 can be a low-k dielectric material, such as fluorine-doped silicon dioxide, carbon-doped oxide, porous silicon dioxide, etc., and the insulating layer 118 in IGBT region 110 that pads the sidewalls and bottom of the first trench 114 can be silicon dioxide formed by thermal oxidation.

[0041] In addition to one, some, or all of the embodiments described herein for making the capacitance density of the second capacitor C2 of diode region 112 by the second region less than the capacitance density of the first capacitor C1 of IGBT region 110 by the first region, the average density of the sidewall regions of the second contact trenches 146 between adjacent second trenches 132 in diode region 112 may be greater than the average density of the sidewall regions of the first contact trenches 144 between adjacent first trenches 114 in IGBT region 110. The sidewall region of each contact trench 144, 146 is the surface area occupied by the sidewall of the contact trench 144, 146. Individually or in combination, the average density of the sidewall regions of the second contact trenches 146 of diode region 112 by the second region may be greater than the average density of the sidewall regions of the first contact trenches 114 of IGBT region 110 by the first region.

[0042] By utilizing the additional contact trench 146 to occupy the wider anode region 122 in the diode region 112, the current density at the contact point with the first metallization 140 is reduced. This results in lower anode efficiency but improved switching durability.

[0043] Figure 2A and Figure 2BThe illustration shows an embodiment in which two (two) second contact trenches 146 are deployed between adjacent second trenches 132 in diode region 112 and a single (one) first contact trench 144 is deployed between adjacent first trenches 114 in IGBT region 110. Increasing the number of second contact trenches 146 deployed between adjacent second trenches 132 in diode region 112 provides more paths for carriers to leave the diode and reduces anode efficiency, which in turn reduces switching losses.

[0044] Figure 4 The illustration shows an embodiment in which three (3) second contact trenches 146 are deployed between adjacent second trenches 132 in the diode region 112. A single (1) first contact trench 144 can be deployed between adjacent first trenches 114 in the IGBT region 110, for example, as shown in... Figure 2B As shown in the image.

[0045] Figure 5 The illustration shows an embodiment in which four (4) second contact trenches 146 are deployed between adjacent second trenches 132 in the diode region 112. A single (1) first contact trench 144 can be deployed between adjacent first trenches 114 in the IGBT region 110, for example, as shown in... Figure 2B As shown in the diagram. In yet another embodiment, more than four (>4) second contact trenches 146 may be deployed between adjacent second trenches 132 in the diode region 112.

[0046] In embodiments, corresponding second contact trenches 146 are connected at predetermined locations by one or more intersecting contact trenches extending in a direction perpendicular to the longitudinal extension of the second contact trenches 146. In some embodiments, the intersecting contact trenches may extend at an angle relative to the second contact trenches 146. The formation of intersecting contact trenches can result in a grid-like or mesh-like arrangement of contact trenches in a top view. A grid-like or mesh-like arrangement of contact trenches can maximize the contact area with equal critical dimensions. A grid-like or mesh-like arrangement of contact trenches can also increase the area of ​​the anode region formed by highly doped regions 148 of a second conductivity type adjacent to the bottom and at least part of the sidewalls of the second contact trenches 146. A grid-like or mesh-like arrangement of contact trenches can also increase the length of the perimeter of the second contact trenches 132 and thus increase the sidewall density to obtain improved performance during the on-state.

[0047] Figure 6 The illustration shows an embodiment in which a single (1) second contact trench 146 is deployed between adjacent second trenches 132 in the diode region 112. (As shown in...) Figure 2BAs shown, a single (1) first contact trench 144 can be similarly deployed between adjacent first trenches 114 in the IGBT region 110. According to... Figure 6 In the embodiment illustrated, the second contact trench 146 in diode region 112 has an average width W. DIODE It is greater than the average width of the first contact trench 144 in the IGBT region 110. For example, the average width W of the second contact trench 146 in the diode region 112 is greater than the average width of the first contact trench 144 in the IGBT region 110. DIODE This can be achieved from 100 nm across the entire anode region 141 between adjacent second trenches 132. (As with...) Figure 2A , Figure 4 and Figure 5 Compared to the multi-contact embodiment illustrated in the figure, providing a single (1) but relatively wide contact 146 between adjacent second trenches 132 in diode region 112 provides higher anode efficiency with similar switching durability.

[0048] While this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0049] Example 1. A power semiconductor device comprising: a semiconductor substrate including an IGBT (Insulated Gate Bipolar Transistor) region and a diode region, the IGBT region including an IGBT, the diode region including a diode, the IGBT region having a first region in a top view and the diode region having a second region in a top view, wherein the IGBT region includes a plurality of first trenches, the plurality of first trenches including first trench electrodes and extending perpendicular to a first main surface of the semiconductor substrate, wherein the diode region includes a plurality of second trenches, the plurality of second trenches having second trench electrodes and extending perpendicular to the first main surface of the semiconductor substrate, wherein the plurality of first trenches provide a first capacitance between the first trench electrodes in the IGBT region and the semiconductor substrate, and the plurality of second trenches provide a second capacitance between the second trench electrodes in the diode region and the semiconductor substrate, wherein the capacitance density of the second capacitance per second region is less than the capacitance density of the first capacitance per first region.

[0050] Example 2. The power semiconductor device of Example 1, wherein the capacitance density of the second capacitor in the second region is 1 / 10 to 2 / 3 of the capacitance density of the first capacitor in the first region.

[0051] Example 3. A power semiconductor device of Example 1 or 2, wherein a plurality of first trenches extend in a semiconductor substrate to a first depth, wherein a plurality of second trenches extend in a semiconductor substrate to a second depth, and wherein the second depth is less than the first depth.

[0052] Example 4. A power semiconductor device of any one of Examples 1 to 3, wherein the insulating layer between the second trench electrode and the semiconductor substrate is thicker than the insulating layer between the first trench electrode and the semiconductor substrate.

[0053] Example 5. A power semiconductor device of any one of Examples 1 to 4, wherein the dielectric constant of the insulating layer between the second trench electrode and the semiconductor substrate is less than the dielectric constant of the insulating layer between the first trench electrode and the semiconductor substrate.

[0054] Example 6. A power semiconductor device of any one of Examples 1 to 5, further comprising: a plurality of first contact trenches extending perpendicular to a first main surface of a semiconductor substrate in an IGBT region; and a plurality of second contact trenches extending perpendicular to the first main surface of a semiconductor substrate in a diode region, wherein the average density of the sidewall regions of the second contact trenches between adjacent second trenches in the diode region is greater than the average density of the sidewall regions of the first contact trenches between adjacent first trenches in the IGBT region.

[0055] Example 7. The power semiconductor device of Example 6, wherein at least two second contact trenches are deployed between adjacent second trenches in a diode region, and wherein a single first contact trench is deployed between adjacent first trenches in an IGBT region.

[0056] Example 8. The power semiconductor device of Example 6, wherein at least four contact trenches are deployed between adjacent second trenches in a diode region, and wherein a single first contact trench is deployed between adjacent first trenches in an IGBT region.

[0057] Example 9. A power semiconductor device of any one of Examples 6 to 8, wherein the doping concentration of the semiconductor substrate at the sidewalls of the plurality of second contact trenches is lower than the doping concentration of the semiconductor substrate at the bottom of the plurality of second contact trenches.

[0058] Example 10. A power semiconductor device of any one of Examples 1 to 9, further comprising: a plurality of first contact trenches extending in an IGBT region perpendicular to a first main surface of a semiconductor substrate; and a plurality of second contact trenches extending in a diode region perpendicular to the first main surface of a semiconductor substrate, wherein the average density of the sidewall regions of the second contact trenches per second region is greater than the average density of the sidewall regions of the first contact trenches per first region.

[0059] Example 11. A power semiconductor device of any one of Examples 1 to 10, further comprising: a plurality of first contact trenches extending perpendicular to a first main surface of a semiconductor substrate in an IGBT region; and a plurality of second contact trenches extending perpendicular to the first main surface of a semiconductor substrate in a diode region, wherein a single first contact trench is deployed between adjacent first trenches in the IGBT region, wherein a single second contact trench is deployed between adjacent second trenches in the diode region, wherein the second contact trench has an average width greater than the average width of the first contact trenches.

[0060] Example 12. A power semiconductor device comprising: a semiconductor substrate, the semiconductor substrate including an IGBT region and a diode region, the IGBT region having an IGBT, the diode region having a diode, wherein the IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate, wherein the diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate, wherein the average lateral spacing between adjacent second trenches in the second trenches is greater than the average lateral spacing between adjacent first trenches in the first trenches.

[0061] Example 13. The power semiconductor device of Example 12, wherein the average lateral spacing between adjacent second trenches in the second trench is 1.5 to 30 times the average lateral spacing between adjacent first trenches in the first trench.

[0062] Example 14. A power semiconductor device of Example 12 or 13, wherein the average lateral spacing between adjacent second trenches in the second trench is greater than 0.6 μm and less than 20 μm.

[0063] Example 15. A power semiconductor device of any one of Examples 12 to 14, further comprising: a plurality of first contact trenches extending in an IGBT region into a first main surface of a semiconductor substrate; and a plurality of second contact trenches extending in a diode region into the first main surface of a semiconductor substrate, wherein the average density of the sidewall regions of the second contact trenches between adjacent second trenches is greater than the average density of the sidewall regions of the first contact trenches between adjacent first trenches by a first region.

[0064] Example 16. The power semiconductor device of Example 15, wherein at least two second contact trenches are deployed between adjacent second trenches in a diode region, and wherein a single first contact trench is deployed between adjacent first trenches in an IGBT region.

[0065] Example 17. The power semiconductor device of Example 15, wherein at least four contact trenches are deployed between adjacent second trenches in a diode region, and wherein a single first contact trench is deployed between adjacent first trenches in an IGBT region.

[0066] Example 18. A power semiconductor device of any one of Examples 15 to 17, wherein the doping concentration of the semiconductor substrate at the sidewalls of the plurality of second contact trenches is lower than the doping concentration of the semiconductor substrate at the bottom of the plurality of second contact trenches.

[0067] Example 19. A power semiconductor device of any one of Examples 12 to 18, further comprising: a plurality of first contact trenches extending perpendicular to a first main surface of a semiconductor substrate in an IGBT region; and a plurality of second contact trenches extending perpendicular to the first main surface of a semiconductor substrate in a diode region, wherein a single first contact trench is deployed between adjacent first trenches in the IGBT region, wherein a single second contact trench is deployed between adjacent second trenches in the diode region, wherein the second contact trench has an average width greater than the average width of the first contact trenches.

[0068] Example 20. A power semiconductor device of any one of Examples 12 to 19, wherein each second trench is segmented into trench portions along the longitudinal extension direction of the plurality of second trenches, and wherein adjacent trench portions of the same second trench are separated from each other by a substrate region of a semiconductor substrate.

[0069] Example 21. A power semiconductor device of any one of Examples 12 to 20, further comprising a plurality of contact trenches extending in a diode region into a first main surface of a semiconductor substrate, wherein the contact trenches are connected at a predetermined location by one or more intersecting contact trenches extending in a direction perpendicular to the longitudinal extension of the contact trenches.

[0070] Example 22. A method of manufacturing a power semiconductor device, the method comprising: forming an IGBT in an IGBT region of a semiconductor substrate, the IGBT region having a first region in a top view; and forming a diode in a diode region of the semiconductor substrate, the diode region having a second region in a top view, wherein forming the IGBT includes forming a plurality of first trenches having first trench electrodes and extending perpendicular to a first main surface of the semiconductor substrate in the IGBT region, wherein forming the diode includes forming a plurality of second trenches having second trench electrodes and extending perpendicular to the first main surface of the semiconductor substrate in the diode region, such that the capacitance density of the capacitance provided between the plurality of second trenches and the semiconductor substrate per second region is less than the capacitance density of the capacitance provided between the plurality of first trenches and the semiconductor substrate per first region.

[0071] Example 23. The method of Example 22, wherein forming a plurality of second trenches includes forming fewer second trenches per unit area in the diode region compared to the first trenches present per unit area in the IGBT region.

[0072] Example 24. The method of Example 22 or 23, wherein forming a plurality of second trenches includes terminating the second trenches in a shallower manner in the semiconductor substrate compared to the first trenches.

[0073] Example 25. A method of any of Examples 22 to 24, wherein forming a plurality of second trenches includes spacing the second trenches further apart in the diode region than spacing the first trenches apart in the IGBT region.

[0074] Terms such as "first" and "second" are used to describe various elements, sections, and segments, and are not intended to be restrictive. Throughout the description, the same terms refer to the same elements.

[0075] As used herein, the terms “having,” “containing,” “including,” and “including” are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “one,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0076] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A power semiconductor device, comprising: A semiconductor substrate includes an IGBT (Insulated Gate Bipolar Transistor) region and a diode region. The IGBT region includes an IGBT, and the diode region includes a diode. The IGBT region has a first region in a top view, and the diode region has a second region in a top view. The IGBT region includes multiple first trenches, each first trench including a first trench electrode and extending perpendicularly to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches, each second trench having a second trench electrode and extending perpendicular to a first main surface of the semiconductor substrate. The plurality of first trenches provide a first capacitance between a first trench electrode in the IGBT region and the semiconductor substrate, and the plurality of second trenches provide a second capacitance between a second trench electrode in the diode region and the semiconductor substrate. The capacitance density of the second capacitor in the second region is less than the capacitance density of the first capacitor in the first region.

2. The power semiconductor device according to claim 1, wherein the capacitance density of the second capacitor in the second region is 1 / 10 to 2 / 3 of the capacitance density of the first capacitor in the first region.

3. The power semiconductor device of claim 1, wherein the plurality of first trenches extend to a first depth in the semiconductor substrate, wherein the plurality of second trenches extend to a second depth in the semiconductor substrate, and wherein the second depth is less than the first depth.

4. The power semiconductor device according to claim 1, wherein the insulating layer between the second trench electrode and the semiconductor substrate is thicker than the insulating layer between the first trench electrode and the semiconductor substrate.

5. The power semiconductor device according to claim 1, wherein the dielectric constant of the insulating layer between the second trench electrode and the semiconductor substrate is less than the dielectric constant of the insulating layer between the first trench electrode and the semiconductor substrate.

6. The power semiconductor device according to claim 1, further comprising: Multiple first contact trenches extend perpendicularly to the first main surface of the semiconductor substrate in the IGBT region; as well as Multiple second contact trenches extend perpendicularly to the first main surface of the semiconductor substrate within the diode region. The average density of the sidewall region of the second contact trench between adjacent second trenches in the diode region is greater than the average density of the sidewall region of the first contact trench between adjacent first trenches in the IGBT region.

7. The power semiconductor device of claim 6, wherein at least two second contact trenches are deployed between adjacent second trenches in the diode region, and wherein a single first contact trench is deployed between adjacent first trenches in the IGBT region.

8. The power semiconductor device of claim 6, wherein at least four contact trenches are deployed between adjacent second trenches in the diode region, and wherein a single first contact trench is deployed between adjacent first trenches in the IGBT region.

9. The power semiconductor device of claim 6, wherein the doping concentration of the semiconductor substrate at the sidewalls of the plurality of second contact trenches is lower than the doping concentration of the semiconductor substrate at the bottom of the plurality of second contact trenches.

10. The power semiconductor device according to claim 1, further comprising: Multiple first contact trenches extend perpendicularly to the first main surface of the semiconductor substrate in the IGBT region; as well as Multiple second contact trenches extend perpendicularly to the first main surface of the semiconductor substrate within the diode region. The average density of the sidewall region of the second contact trench, relative to the second region, is greater than the average density of the sidewall region of the first contact trench, relative to the first region.

11. The power semiconductor device according to claim 1, further comprising: Multiple first contact trenches extend perpendicularly to the first main surface of the semiconductor substrate in the IGBT region; as well as Multiple second contact trenches extend perpendicularly to the first main surface of the semiconductor substrate within the diode region. Each first contact trench is deployed between adjacent first trenches in the IGBT region. Each second contact trench is deployed between adjacent second trenches in the diode region. The second contact groove has an average width that is greater than the average width of the first contact groove.

12. A power semiconductor device, comprising: A semiconductor substrate comprising an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to the first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. The average lateral spacing between adjacent second trenches in the second trench is greater than the average lateral spacing between adjacent first trenches in the first trench. The plurality of first trenches provide a first capacitance between a first trench electrode in the IGBT region and the semiconductor substrate, and the plurality of second trenches provide a second capacitance between a second trench electrode in the diode region and the semiconductor substrate. The capacitance density of the second capacitor in the second region is less than the capacitance density of the first capacitor in the first region.

13. The power semiconductor device of claim 12, wherein the average lateral spacing between adjacent second trenches in the second trench is 1.5 to 30 times the average lateral spacing between adjacent first trenches in the first trench.

14. The power semiconductor device of claim 12, wherein the average lateral spacing between adjacent second trenches in the second trench is greater than 0.6 μm and less than 20 μm.

15. The power semiconductor device of claim 12, further comprising: Multiple first contact trenches extend from the IGBT region into the first main surface of the semiconductor substrate; as well as Multiple second contact trenches extend from the diode region into the first main surface of the semiconductor substrate. The average density of the sidewall region of the second contact trench between adjacent second trenches, as per the second region, is greater than the average density of the sidewall region of the first contact trench between adjacent first trenches, as per the first region.

16. The power semiconductor device of claim 15, wherein at least two second contact trenches are deployed between adjacent second trenches in the diode region, and wherein a single first contact trench is deployed between adjacent first trenches in the IGBT region.

17. The power semiconductor device of claim 15, wherein at least four contact trenches are deployed between adjacent second trenches in the diode region, and wherein a single first contact trench is deployed between adjacent first trenches in the IGBT region.

18. The power semiconductor device of claim 15, wherein the doping concentration of the semiconductor substrate at the sidewalls of the plurality of second contact trenches is lower than the doping concentration of the semiconductor substrate at the bottom of the plurality of second contact trenches.

19. The power semiconductor device according to claim 12, further comprising: Multiple first contact trenches extend perpendicularly to the first main surface of the semiconductor substrate in the IGBT region; as well as Multiple second contact trenches extend perpendicularly to the first main surface of the semiconductor substrate within the diode region. Each first contact trench is deployed between adjacent first trenches in the IGBT region. Each second contact trench is deployed between adjacent second trenches in the diode region. The second contact groove has an average width that is greater than the average width of the first contact groove.

20. The power semiconductor device of claim 12, wherein each second trench is segmented into trench portions along the longitudinal extension direction of the plurality of second trenches, and wherein adjacent trench portions of the same second trench are separated from each other by a substrate region of the semiconductor substrate.

21. The power semiconductor device of claim 12, further comprising: Multiple contact trenches extend from the diode region into the first main surface of the semiconductor substrate. The contact grooves are connected at a predetermined location by one or more intersecting contact grooves extending in a direction perpendicular to the longitudinal extension of the contact grooves.

22. A method for producing a power semiconductor device according to any one of claims 1 to 21, the method comprising: An IGBT is formed in the IGBT region of a semiconductor substrate, and the IGBT region has a first region in the top view; as well as A diode is formed in a diode region on a semiconductor substrate, the diode region having a second region in the top view. The formation of an IGBT includes forming a plurality of first trenches in the IGBT region, each having a first trench electrode and extending perpendicularly to a first main surface of the semiconductor substrate. The diode formation includes forming a plurality of second trenches having second trench electrodes extending perpendicular to a first main surface of a semiconductor substrate in a diode region, such that the capacitance density of the capacitance provided between the plurality of second trenches and the semiconductor substrate per second region is less than the capacitance density of the capacitance provided between the plurality of first trenches and the semiconductor substrate per first region.

23. The method of claim 22, wherein forming the plurality of second trenches comprises forming fewer second trenches per unit area in the diode region compared to the number of first trenches present per unit area in the IGBT region.

24. The method of claim 22, wherein forming the plurality of second trenches includes terminating the second trenches in a shallower manner in the semiconductor substrate compared to the first trenches.

25. The method of claim 22, wherein forming the plurality of second trenches includes spacing the second trenches further apart in the diode region than spacing the first trenches apart in the IGBT region.

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