Three-dimensional semiconductor memory device

Abstract

A three-dimensional (3D) semiconductor memory device includes: first cell stacks arranged along a first direction and a second direction; second cell stacks disposed on the first cell stacks and arranged along the first direction and the second direction; first conductive lines extending along the first direction and disposed between a substrate and the first cell stacks; common conductive lines extending along the second direction and disposed between the first cell stacks and the second cell stacks; etch stop patterns extending along the second direction and disposed between top surfaces of the first cell stacks and the common conductive lines; second conductive lines extending along the first direction and disposed on the second cell stacks; and a cover pattern covering sidewalls of the common conductive lines and sidewalls of the etch stop patterns, wherein a second thickness of each of the common conductive lines is greater than a first thickness of each of the first conductive lines.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0041777, filed on April 6, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate to three-dimensional (3D) semiconductor memory devices, and more specifically, to 3D semiconductor memory devices including variable resistance memory cells. Background Technology

[0004] Next-generation memory devices with non-volatile characteristics that eliminate the need for refresh operations have been investigated to provide high-capacity and low-power memory. In dynamic random-access memory (DRAM) chips, memory refresh may involve restoring the charge on capacitors to their original levels. Next-generation memory devices may require the high integration density of DRAM devices, the non-volatile characteristics of flash memory devices, and the high speed of static random-access memory (SRAM) devices.

[0005] Recently, next-generation semiconductor memory devices (such as ferroelectric random access memory (FRAM) devices, magnetic random access memory (MRAM) devices, and phase-change random access memory (PRAM) devices) have been developed to provide high-performance and low-power semiconductor memory devices. The materials of these next-generation semiconductor memory devices can have a resistance value that changes according to the current or voltage applied to them, and can maintain its resistance value even when the current or voltage is interrupted. For example, FRAM can use a ferroelectric layer instead of a dielectric layer to achieve non-volatility, and PRAM memory cells can switch between a low-resistance crystalline state and a high-resistance amorphous state.

[0006] In addition, due to the need to increase the integration density of semiconductor devices, 3D semiconductor memory devices, including memory cells arranged in three dimensions, have been developed. Summary of the Invention

[0007] According to an exemplary embodiment of the present invention, a three-dimensional (3D) semiconductor memory device is provided, comprising: a first cell stack arranged along a first direction and a second direction, the first direction and the second direction being parallel to and intersecting each other with a top surface of a substrate; a second cell stack disposed on the first cell stack and arranged along the first direction and the second direction; a first conductive line extending along the first direction and disposed between the substrate and the first cell stack; a common conductive line extending along the second direction and disposed between the first cell stack and the second cell stack; an etch stop pattern extending along the second direction and disposed between the top surface of the first cell stack and the common conductive line, the etch stop pattern comprising a conductive material; a second conductive line extending along the first direction and disposed on the second cell stack; and a cover pattern covering the sidewalls of the common conductive line and the sidewalls of the etch stop pattern, wherein a second thickness of each of the common conductive lines is greater than a first thickness of each of the first conductive lines.

[0008] According to an exemplary embodiment of the present invention, a 3D semiconductor memory device is provided, comprising: a first conductive line extending along a first direction parallel to the top surface of a substrate; a first cell stack located on the first conductive line; a first fill insulating pattern located between the first cell stacks; a common conductive line extending on each of the first cell stacks along a second direction intersecting the first direction; an etch stop pattern disposed between the common conductive line and each of the first cell stacks and formed of a conductive material; a second cell stack located on the common conductive line; a second fill insulating pattern covering the sidewalls of the common conductive line and the sidewalls of the etch stop pattern; a cover pattern disposed between the sidewalls of the common conductive line and the second fill insulating pattern and between the sidewalls of the etch stop pattern and the second fill insulating pattern; and a second conductive line extending on each of the second cell stacks along the first direction, wherein a second thickness of the common conductive line is greater than a first thickness of the first conductive line.

[0009] According to an exemplary embodiment of the present invention, a 3D semiconductor memory device is provided, comprising: a plurality of first conductive lines extending on a substrate along a first direction; a stacked structure including a plurality of cell array layers vertically stacked on the first conductive lines, wherein each cell array layer includes cell stacks arranged along the first direction and a second direction intersecting the first direction; a plurality of common conductive lines disposed between the cell array layers, wherein the thickness of the common conductive lines is greater than the thickness of the first conductive lines; an etch stop pattern disposed between the bottom surface of each of the common conductive lines and the top surface of the cell stack and formed of a conductive material; and a plurality of second conductive lines extending on the stacked structure along the first direction or the second direction.

[0010] According to an exemplary embodiment of the present invention, a 3D semiconductor memory device is provided, comprising: a first cell array layer, the first cell array layer including a plurality of first cell stacks arranged along a first direction and a second direction parallel to the top surface of a substrate and intersecting each other, and a first fill insulating pattern located between the first cell stacks; a second cell array layer disposed on the first cell array layer, and including a plurality of second cell stacks arranged along the first direction and the second direction, and a second fill insulating pattern located between the second cell stacks; a first conductive line extending along the first direction between the substrate and the first cell array layer and connected to the first cell stacks; a common conductive line extending along the second direction between the first cell array layer and the second cell array layer and connected to the first cell stacks and the second cell stacks; and a second conductive line extending along the first direction on the second cell array layer and connected to the second cell stacks, wherein the first conductive line and the second conductive line comprise a first metal material, and the common conductive line comprises a second metal material with a resistivity less than that of the first metal material.

[0011] According to an exemplary embodiment of the present invention, a 3D semiconductor memory device is provided, comprising: a first cell stack disposed on a substrate; a second cell stack disposed on the first cell stack; a first conductive line disposed between the substrate and the first cell stack; a second conductive line disposed between the first cell stack and the second cell stack; an etch stop pattern disposed between the second conductive line and the first cell stack; a third conductive line disposed on the second cell stack; and an overlay pattern contacting the second conductive line and the etch stop pattern. Attached Figure Description

[0012] Figure 1 This is a view illustrating an exemplary embodiment of a three-dimensional (3D) semiconductor memory device according to a concept of the present invention.

[0013] Figure 2 This is a circuit diagram illustrating a memory cell array of a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0014] Figure 3 This is a perspective view illustrating a memory cell array of a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0015] Figure 4 This is a top view illustrating an exemplary 3D semiconductor memory device according to a concept of the present invention.

[0016] Figure 5A and Figure 5B It is along Figure 4 The cross-sectional views taken along lines I-I' and II-II' illustrate a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0017] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E yes Figure 5A A magnified view of part "A".

[0018] Figure 7 This is a cross-sectional view illustrating an exemplary embodiment of a 3D semiconductor memory device according to the concept of the present invention.

[0019] Figure 8 , Figure 9 , Figure 10 and Figure 11 It is along Figure 4The cross-sectional views taken along lines I-I' and II-II' illustrate a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0020] Figure 12 yes Figure 10 A magnified view of part "B".

[0021] Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 It is along Figure 4 The cross-sectional views taken along lines I-I' and II-II' illustrate a method for manufacturing a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0022] Figure 25 , Figure 26 , Figure 27 , Figure 28 and Figure 29 It is along Figure 4 The cross-sectional views taken along lines I-I' and II-II' illustrate a method for manufacturing a 3D semiconductor memory device according to an exemplary embodiment of the present invention. Detailed Implementation

[0023] In the following, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings.

[0024] Figure 1 This is a view illustrating an exemplary embodiment of a three-dimensional (3D) semiconductor memory device according to a concept of the present invention.

[0025] Reference Figure 1 A 3D semiconductor memory device according to an exemplary embodiment of the present invention may include a plurality of memory cell array layers (MCAs) sequentially stacked on a substrate 100. Each memory cell array layer (MCA) may include a plurality of two-dimensionally arranged variable-resistance memory cells. A 3D semiconductor memory device according to an exemplary embodiment of the present invention may include conductive lines disposed between the memory cell array layers (MCAs) for writing, reading, and erasing memory cells. Figure 1 Five memory cell array layers (MCAs) are shown. However, exemplary embodiments of the inventive concept are not limited thereto. For example, exemplary embodiments of the inventive concept may include more than five memory cell array layers (MCAs) or fewer than five.

[0026] Figure 2 This is a circuit diagram illustrating a memory cell array of a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0027] Reference Figure 2 The first memory cell array layer MCA1, the second memory cell array layer MCA2, the third memory cell array layer MCA3, and the fourth memory cell array layer MCA4 can be stacked along a third direction D3 on a plane extending along intersecting first directions D1 and second directions D2. Each of the first memory cell array layers MCA1 to the fourth memory cell array layer MCA4 can include intersecting conductive lines CL1 and CL2, and multiple memory cells MC respectively disposed at the intersections of conductive lines CL1 and CL2. In each memory cell array layer of the first memory cell array layer MCA1 to the fourth memory cell array layer MCA4, the memory cells MC can be arranged two-dimensionally along the first direction D1 and the second direction D2. Memory cells MC adjacent to each other in the third direction D3 can share conductive lines CL1 or CL2 disposed between them. Figure 2 The diagram illustrates four memory cell array layers MCA1 to MCA4 as an example. However, exemplary embodiments of the present invention are not limited thereto.

[0028] Figure 3 This is a perspective view illustrating a memory cell array of a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0029] Reference Figure 3 The second memory cell array layer MCA2 can be disposed on the first memory cell array layer MCA1. The first memory cell array layer MCA1 can be disposed between the first conductive line CL1 and the common conductive line CCL, and the second memory cell array layer MCA2 can be disposed between the second conductive line CL2 and the common conductive line CCL.

[0030] The first conductive line CL1 and the second conductive line CL2 can extend along the first direction D1, and the common conductive line CCL can extend along the second direction D2 that intersects the first direction D1.

[0031] The first memory cell array layer MCA1 may include first memory cells MC1 respectively disposed at the intersection of the first conductive line CL1 and the common conductive line CCL. The first memory cells MC1 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0032] The second memory cell array layer MCA2 may include second memory cells MC2 respectively disposed at the intersection of the common conductive line CCL and the second conductive line CL2. The second memory cells MC2 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0033] Both the first storage cell MC1 and the second storage cell MC2 may include a switching element SW and a variable resistor VR. The switching element SW and the variable resistor VR may be connected in series with each other between a pair of conductive lines CL1 and CCL (or CCL and CL2).

[0034] In an exemplary embodiment of the present invention, the variable resistor VR of the first storage cell MC1 and the switching element SW of the second storage cell MC2 can be jointly connected to a corresponding common conductive line CCL.

[0035] Figure 4 This is a top view illustrating an exemplary 3D semiconductor memory device according to a concept conceived in this invention. Figure 5A and Figure 5B It is along Figure 4 The cross-sectional views taken along lines I-I' and II-II' illustrate a 3D semiconductor memory device according to an exemplary embodiment of the present invention. Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E yes Figure 5A A magnified view of part "A".

[0036] Reference Figure 4 and Figure 5A A first conductive line CL1 extending along a first direction D1 can be disposed on the substrate 100 and can be spaced apart from each other in a second direction D2. The first direction D1 and the second direction D2 can be parallel to the top surface of the substrate 100 and can intersect each other.

[0037] The common conductive line CCL may be spaced apart from the first conductive line CL1 in a third direction D3 perpendicular to the top surface of the substrate 100. The common conductive lines CCL may extend along a second direction D2 and may be spaced apart from each other in a first direction D1.

[0038] The second conductive line CL2 may be spaced apart from the common conductive line CCL in the third direction D3. The second conductive line CL2 may extend along the first direction D1 and may be spaced apart from each other in the second direction D2.

[0039] The first conductive line CL1, the common conductive line CCL, and the second conductive line CL2 may comprise a metal (e.g., copper, tungsten, or aluminum) and / or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride). For example, the first conductive line CL1, the common conductive line CCL, and the second conductive line CL2 may comprise the same metallic material.

[0040] An interlayer insulating layer 110 may be disposed between the substrate 100 and the first conductive line CL1. For example, the interlayer insulating layer 110 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0041] The lower insulating pattern 115 may fill the space between the first conductive lines CL1. The top surface of the lower insulating pattern 115 may be located at substantially the same horizontal height as the top surface of the first conductive lines CL1. The lower portion of the lower insulating pattern 115 may be disposed within the interlayer insulating layer 110. The bottom surface of the lower insulating pattern 115 may be located at a lower horizontal height than the bottom surface of the first conductive lines CL1. For example, the lower insulating pattern 115 may protrude into the interlayer insulating layer 110. The lower insulating pattern 115 may comprise at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0042] The first unit stack CS1 can be respectively disposed at the intersection of the first conductive line CL1 and the common conductive line CCL. In other words, the first unit stack CS1 can be spaced apart from each other along the first conductive line CL1 in the first direction D1. The top width of each first unit stack CS1 can be smaller than the bottom width of each first unit stack CS1. Alternatively, the top width of each first unit stack CS1 can be substantially equal to the bottom width of each first unit stack CS1.

[0043] Each first unit stack CS1 may include a switch pattern SP disposed between a first conductive line CL1 and a common conductive line CCL, and a variable resistor pattern RP disposed between the switch pattern SP and the common conductive line CCL.

[0044] In an exemplary embodiment of the present invention, each first unit stack CS1 may include a first electrode BE, a switch pattern SP, a second electrode ME, a variable resistance pattern RP, and a third electrode TE stacked sequentially. Hereinafter, the switch pattern SP disposed between the first electrode BE and the second electrode ME, and the variable resistance pattern RP disposed between the second electrode ME and the third electrode TE, will be described as examples. Alternatively, the variable resistance pattern RP may be disposed between the first electrode BE and the second electrode ME, and the switch pattern SP may be disposed between the second electrode ME and the third electrode TE.

[0045] The variable resistor pattern RP of the first unit stack CS1 can have sloping sidewalls, such as... Figure 6AAs shown. Alternatively, the variable resistor pattern RP of the first unit stack CS1 can have circular sidewalls, as shown. Figure 6B As shown. For example, Figure 6B The variable resistance pattern RP of the first unit stack CS1 can be bent.

[0046] The variable resistance pattern RP of the first unit stack CS1 can be formed from at least one of materials having the property of storing data. When the 3D semiconductor memory device according to an exemplary embodiment of the present invention is a phase-change memory device, the variable resistance pattern RP can include a material whose phase can be reversibly changed between a crystalline phase and an amorphous phase by temperature. For example, the phase transition temperature between the crystalline and amorphous phases of the variable resistance pattern RP can be in the range of about 250 degrees Celsius to about 350 degrees Celsius. The variable resistance pattern RP can be formed from a compound including at least one of Te or Se (e.g., chalcogenides) and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, or C. In addition to the compounds, the variable resistance pattern RP may also include a light element. For example, the light element may include at least one of C, N, O, P, Cd, W, Ti, Hf, or Zr. For example, the variable resistance pattern RP may include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, or InSbTe. In exemplary embodiments of the inventive concept, the variable resistance pattern RP may have a superlattice structure in which layers including Ge and layers not including Ge are repeatedly and alternately stacked. For example, the variable resistance pattern RP may have a structure in which GeTe layers and SbTe layers are repeatedly and alternately stacked.

[0047] In exemplary embodiments of the present invention, the variable resistance pattern RP may include at least one of a perovskite compound or a conductive metal oxide. For example, the variable resistance pattern RP may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, (Pr,Ca)MnO3 (PCMO), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, or barium strontium zirconium oxide. When the variable resistance pattern RP includes a transition metal oxide, the dielectric constant of the variable resistance pattern RP may be greater than that of silicon oxide.

[0048] In an exemplary embodiment of the present invention, the variable resistance pattern RP may have a two-layer structure of a conductive metal oxide layer and a tunneling insulating layer, or a three-layer structure of a first conductive metal oxide layer, a tunneling insulating layer, and a second conductive metal oxide layer. The tunneling insulating layer may include aluminum oxide, hafnium oxide, or silicon oxide.

[0049] Each switch pattern SP in the first unit stack CS1 can be a bidirectional threshold switch (OTS) element with bidirectional characteristics. For example, each switch pattern SP can be an element based on a threshold switching phenomenon with a nonlinear IV curve (e.g., an S-shaped IV curve). The switch pattern SP can have a phase transition temperature between a crystalline phase and an amorphous phase, which is higher than the phase transition temperature of the variable resistor pattern RP. For example, the phase transition temperature of the switch pattern SP can be in the range of approximately 350 degrees Celsius to approximately 450 degrees Celsius. Therefore, when operating a 3D semiconductor memory device according to an exemplary embodiment of the present invention, the phase of the variable resistor pattern RP can be reversibly changed between a crystalline phase and an amorphous phase by an operating voltage (e.g., a programming voltage), but even when an operating voltage is applied to it, the switch pattern SP can remain in a substantially amorphous state without a phase transition. In this specification, the term "substantially amorphous" can include amorphous state and can also include cases where grain boundaries or crystalline portions are locally present in a portion of the assembly.

[0050] The switch pattern SP can be formed from a compound comprising at least one of Te or Se (e.g., a chalcogenide) and at least one of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, or P. In addition to the compounds, the switch pattern SP may also include a thermally stabilizing element. The thermally stabilizing element may include at least one of B, C, N, or O. For example, the switch pattern SP may include at least one of AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGe, AsTeGeSe, AsSeGeSi, AsSeGeC, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, AsTeGeSiSeNS, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, or GeAsBiSe.

[0051] The first electrode BE, the second electrode ME, and the third electrode TE may comprise conductive materials. For example, the first electrode BE, the second electrode ME, and the third electrode TE may be carbon electrodes comprising carbon. The first electrode BE, the second electrode ME, and the third electrode TE may comprise metals and / or metal nitrides. The width of each first electrode BE may be substantially equal to or greater than the width of the first conductive line CL1 disposed below it.

[0052] In an exemplary embodiment of the present invention, each first unit stack CS1 may include a first metal pattern MB1 located between the second electrode ME and the variable resistance pattern RP, and a second metal pattern MB2 located between the third electrode TE and the variable resistance pattern RP, as shown below. Figures 6A to 6E As shown. The first metal pattern MB1 and the second metal pattern MB2 can cover the bottom and top surfaces of the variable resistance pattern RP to prevent material diffusion of the variable resistance pattern RP. For example, the first metal pattern MB1 can directly contact the bottom surface of the variable resistance pattern RP, and the second metal pattern MB2 can directly contact the top surface of the variable resistance pattern RP. In addition, the first metal pattern MB1 can be disposed between the variable resistance pattern RP and the second electrode ME to reduce the contact resistance between them. For example, the first metal pattern MB1 and the second metal pattern MB2 can include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, or TaSiN.

[0053] The first filling insulating pattern 134 can fill the space between the first cell stacks CS1. The first filling insulating pattern 134 can extend along a first direction D1 and a second direction D2 to insulate the first cell stacks CS1 from each other in the first direction D1 and the second direction D2. The first filling insulating pattern 134 can include a low-k dielectric layer. For example, the first filling insulating pattern 134 can include at least one of SiN, SiON, SiC, SiCN, SiOC, SiOCH, SiOCN, SiOF, SiO2, or Al2O3.

[0054] The top surface of the first filler insulating pattern 134 between adjacent first cell stacks CS1 along the first direction D1 may be located at a lower horizontal height than the top surface of the first cell stack CS1. In another embodiment, the top surface of the first filler insulating pattern 134 may be located at the same horizontal height as the top surface of one of the first cell stacks CS1. Additionally, the first filler insulating pattern 134 may have a circular top surface between adjacent first cell stacks CS1 along the first direction D1.

[0055] The first cover pattern 132 may be disposed between the sidewall of the first cell stack CS1 and the first filler insulating pattern 134. The first cover pattern 132 may be in direct contact with the sidewall of the variable resistor pattern RP and the switch pattern SP of the first cell stack CS1. The lower portion of the first cover pattern 132 may be disposed between the bottom surface of the first filler insulating pattern 134 and the top surface of the lower insulating pattern 115. Alternatively, the lower portion of the first cover pattern 132 may be disposed between the bottom surface of the first filler insulating pattern 134 and the top surface of the first conductive line CL1. The first cover pattern 132 may cover the sidewall of the first cell stack CS1 and the bottom surface of the first filler insulating pattern 134 with a substantially uniform thickness. The first cover pattern 132 may include an insulating material different from the insulating material of the first filler insulating pattern 134. For example, the first cover pattern 132 may include silicon nitride and / or silicon oxynitride.

[0056] A common conductive line CCL may extend along a second direction D2 on the first unit stack CS1. The common conductive line CCL may comprise the same metallic material as the first conductive line CL1. Each common conductive line CCL may have a second thickness T2, and the second thickness T2 may be at least twice the first thickness T1 of the first conductive line CL1. For example, the second thickness T2 of each common conductive line CCL may be approximately... up to approximately Within a certain range. The top width of the common conductive line CCL can be smaller than the bottom width of the common conductive line CCL. For example, the common conductive line CCL can be gradually narrowed. Since the common conductive line CCL connected to the first cell stack CS1 and the second cell stack CS2 is thicker than the first conductive line CL1 connected to the first cell stack CS1 or the second conductive line CL2 connected to the second cell stack CS2, the resistance of the common conductive line CCL can be reduced. Therefore, the electrical characteristics of the 3D semiconductor memory device in operating mode can be improved.

[0057] An etch stop pattern ES can be disposed between each common conductive line CCL and the first cell stack CS1 arranged along the second direction D2. The etch stop pattern ES can extend parallel to the common conductive line CCL in the second direction D2. The etch stop pattern ES can be formed of a conductive material having etch selectivity relative to the common conductive line CCL. For example, the etch stop pattern ES can include Ti, Ta, TiN, TaN, AlN, or any combination thereof. The thickness t1 of the etch stop pattern ES can be less than the thickness TE of the third electrode of the first cell stack CS1. The etch stop pattern ES can have approximately up to approximately The thickness.

[0058] The top surface of the etch stop pattern ES can contact the bottom surface of the common conductive line CCL, and the bottom surface of the etch stop pattern ES can contact the top surface of the third electrode TE of the first cell stack CS1. The bottom surface of the etch stop pattern ES can contact the entire top surface of the third electrode TE of each first cell stack CS1, such as... Figure 6A As shown. Or, as Figure 6E As shown, a portion of the bottom surface of the etch stop pattern ES can contact a portion of the first cover pattern 132 and a portion of the first fill insulating pattern 134.

[0059] The etch stop pattern ES may contact a portion of the first filler insulating pattern 134 between adjacent first cell stacks CS1 in the second direction D2. The top width of the etch stop pattern ES may be substantially equal to or greater than the bottom width of the common conductive line CCL. The bottom width of the etch stop pattern ES may be substantially equal to or greater than the top width of the first cell stack CS1.

[0060] The second fill insulating pattern 154 can fill the space between the common conductive lines CCL and between the etch stop patterns ES. The bottom surface of the second fill insulating pattern 154 can be located at a lower horizontal height than the bottom surface of the etch stop patterns ES. For example, the bottom surface of the second fill insulating pattern 154 can be disposed between the third electrodes TE of adjacent first cell stacks CS1. The second fill insulating pattern 154 can extend parallel to the common conductive lines CCL in the second direction D2. The second fill insulating pattern 154 can include a low-k dielectric layer. For example, the second fill insulating pattern 154 can include at least one of a SiC layer, a SiCN layer, a SiOCH layer, a SiOC layer, or a SiOF layer.

[0061] The top surface of the second filler insulating pattern 154 may be located at a horizontal height lower than the top surface of the common conductor CCL. Alternatively, the top surface of the second filler insulating pattern 154 may be located at a horizontal height substantially the same as the top surface of the common conductor CCL. The second filler insulating pattern 154 may have a circular top surface located at a horizontal height lower than the top surface of the common conductor CCL.

[0062] A buffer insulation pattern 156 may be disposed on the top surface of the second filling insulation pattern 154. The buffer insulation pattern 156 may be disposed between the upper portions of the common conductive line CCL. The top surface of the buffer insulation pattern 156 may be located at substantially the same horizontal height as the top surface of the common conductive line CCL.

[0063] The second cover pattern 152 may be disposed between the sidewall of the common conductive line CCL and the second fill insulating pattern 154. Additionally, the second cover pattern 152 may be disposed between the sidewall of the etch stop pattern ES and the second fill insulating pattern 154. The second cover pattern 152 may have a substantially uniform thickness and may extend continuously from the sidewall of the common conductive line CCL to the sidewall of the etch stop pattern ES. The thickness of the second cover pattern 152 may be substantially equal to or less than the thickness of the first cover pattern 132. A portion of the second cover pattern 152 may be disposed between the bottom surface of the second fill insulating pattern 154 and the top surface of the first fill insulating pattern 134. For example, this portion of the second cover pattern 152 may contact the first fill insulating pattern 134. The second cover pattern 152 may include an insulating material different from the insulating material of the first fill insulating pattern 134. For example, the second cover pattern 152 may include silicon nitride and / or silicon oxynitride.

[0064] Reference Figure 6A The second cover pattern 152 may contact the top surface of the first cover pattern 132 and the top surface of the first filler insulating pattern 134. The bottom surface of the second cover pattern 152 may be located at the horizontal height between the top and bottom surfaces of the third electrode TE of the first unit stack CS1. The second cover pattern 152 may be spaced apart from the third electrode TE of the first unit stack CS1. Alternatively, as... Figure 6C As shown, a portion of the second covering pattern 152 may contact a portion of the sidewall of the third electrode TE of the first unit stack CS1.

[0065] The second unit stack CS2 can be respectively located at the intersection of the second conductive line CL2 and the common conductive line CCL. In other words, the second unit stack CS2 can be spaced apart from each other along the second direction D2 on each common conductive line CCL.

[0066] The second unit stack CS2 can have a stacking structure that is substantially the same as that of the first unit stack CS1. For example, each second unit stack CS2 may include a first electrode BE, a switch pattern SP, a second electrode ME, a variable resistor pattern RP, and a third electrode TE stacked in sequence.

[0067] The first electrode BE of the second cell stack CS2 can be in contact with the top surface of the corresponding common conductive line CCL. The bottom width of the second cell stack CS2 can be greater than the top width of the common conductive line CCL.

[0068] The third filler insulating pattern 164 can fill the space between the second cell stacks CS2. The third filler insulating pattern 164 can extend along the first direction D1 and the second direction D2 to insulate the second cell stacks CS2 from each other in the first direction D1 and the second direction D2. The third filler insulating pattern 164 can include a low-k dielectric layer. For example, the third filler insulating pattern 164 can include at least one of a SiC layer, a SiCN layer, a SiOCH layer, a SiOC layer, or a SiOF layer.

[0069] The top surface of the third filler insulating pattern 164 between adjacent second unit stacks CS2 along the second direction D2 can be located at a lower horizontal height than the top surface of the second unit stacks CS2. In another embodiment, the top surface of the third filler insulating pattern 164 can be located at the same horizontal height as the top surface of one of the second unit stacks CS2. Additionally, the third filler insulating pattern 164 can have a circular top surface between adjacent second unit stacks CS2 along the second direction D2.

[0070] The third cover pattern 162 can be disposed between the sidewall of the second cell stack CS2 and the third filler insulating pattern 164. The lower part of the third cover pattern 162 can be disposed between the third filler insulating pattern 164 and the second filler insulating pattern 154. In addition, the lower part of the third cover pattern 162 can be disposed between the third filler insulating pattern 164 and the common conductive line CCL. The third cover pattern 162 can cover the sidewall of the second cell stack CS2 and the bottom surface of the third filler insulating pattern 164 with a substantially uniform thickness.

[0071] The buffer insulating pattern 156 can be disposed between the lower part of the third cover pattern 162 and the second fill insulating pattern 154. In other words, the bottom surface of the third cover pattern 162 can be in direct contact with the buffer insulating pattern 156. Or, as... Figure 6D As shown, the bottom surface of the third cover pattern 162 can be in direct contact with the second filler insulating pattern 154.

[0072] The bottom surface of the third overlay pattern 162 can be located at approximately the same horizontal height as the top surface of the common conductive line CCL, such as... Figure 6A As shown. Or, as Figure 6D As shown, the bottom surface of the third overlay pattern 162 can be located at a lower horizontal level than the top surface of the common conductive line CCL. For example, the bottom surface of the third overlay pattern 162 can protrude into the area between adjacent common conductive lines CCL.

[0073] The third overlay pattern 162 may include an insulating material different from the insulating material of the third fill insulating pattern 164. For example, the third overlay pattern 162 may include silicon nitride and / or silicon oxynitride.

[0074] The second conductive line CL2 may extend along the first direction D1 on the second cell stack CS2. The second conductive line CL2 may include the same metallic material as the first conductive line CL1. The second conductive line CL2 may be thinner than the common conductive line CCL. For example, the second conductive line CL2 may have a third thickness T3 that is substantially equal to the first thickness T1 of the first conductive line CL1.

[0075] An upper etch stop pattern (UES) may be disposed between each second conductive line CL2 and the second cell stack CS2. The upper etch stop pattern (UES) may extend parallel to the second conductive line CL2 in a first direction D1. The upper etch stop pattern (UES) may be in direct contact with the top surface of the third electrode TE of the second cell stack CS2 arranged along the first direction D1. The upper etch stop pattern (UES) may be formed of a conductive material having etch selectivity relative to the second conductive line CL2. For example, the upper etch stop pattern (UES) may include Ti, Ta, TiN, TaN, AlN, or any combination thereof. The thickness t1 of the etch stop pattern (UES) may be less than the thickness of the third electrode TE of the first cell stack CS1. The thickness t2 of the upper etch stop pattern (UES) may be less than the thickness t1 of the etch stop pattern (UES). In an exemplary embodiment of the inventive concept, the upper etch stop pattern (UES) may be omitted, and each second conductive line CL2 may be in direct contact with the top surface of the second cell stack CS2 arranged along the first direction D1.

[0076] The hard mask pattern HP can be disposed on each second conductive line CL2. For example, the hard mask pattern HP may include silicon nitride and / or silicon oxynitride.

[0077] The upper capping layer CPL can cover the sidewalls of the hard mask pattern HP, the sidewalls of the second conductive line CL2, and the sidewalls of the upper etch stop pattern UES with a substantially uniform thickness. A portion of the upper capping layer CPL can cover the top surface of the third filler insulating pattern 164 between the second conductive lines CL2.

[0078] according to Figure 5B In an exemplary embodiment of the inventive concept shown, the top surface of the first fill insulating pattern 134 may be located at a lower horizontal height than the top surfaces of the first unit stack CS1 adjacent to each other in the second direction D2. The etch stop pattern ES may extend along the second direction D2 and may conformally cover the top surfaces of the first unit stack CS1 and the first fill insulating pattern 134. In other words, the etch stop pattern ES may have a non-flat top surface. The common conductive line CCL may be disposed on the etch stop pattern ES and may have a flat top surface.

[0079] The top surface of the third filler insulating pattern 164 may be located at a lower horizontal height than the top surface of the second cell stack CS2 adjacent to each other in the first direction D1. The upper etch stop pattern UES may extend along the first direction D1 and may conformally cover the top surface of the second cell stack CS2 and the top surface of the third filler insulating pattern 164. The second conductive line CL2 may be disposed on the upper etch stop pattern UES and may have a flat top surface.

[0080] According to an exemplary embodiment of the present invention, Figures 1 to 6E The 3D semiconductor memory device shown may include: a first cell stack CS1; a second cell stack CS2 disposed on the first cell stack CS1; a first conductive line CL1 disposed between the substrate 100 and the first cell stack CS1; a common conductive line CCL disposed between the first cell stack CS1 and the second cell stack CS2; an etch stop pattern ES disposed between the top surface of the first cell stack CS1 and the common conductive line CCL, the etch stop pattern ES comprising a conductive material; a second conductive line CL2 disposed on the second cell stack CS2; and a cover pattern 152 covering the sidewalls of the common conductive line CCL and the sidewalls of the etch stop pattern ES, wherein the second thickness T2 of each common conductive line CCL is greater than the first thickness T1 of each first conductive line CL1.

[0081] Figure 7 This is a cross-sectional view illustrating an exemplary embodiment of a 3D semiconductor memory device according to the concept of the present invention. In the following, the same components as in the above embodiments may be indicated by the same reference numerals or reference numerals, and their descriptions may be omitted or briefly mentioned for ease of explanation.

[0082] Reference Figure 7 According to an exemplary embodiment of the present invention, a 3D semiconductor memory device may include a peripheral circuit structure PCS and a cell array structure CAS located on the peripheral circuit structure PCS.

[0083] The peripheral circuit structure PCS may include peripheral logic circuit PC integrated on the top surface of substrate 100 and an interlayer insulating layer 110 covering the peripheral logic circuit PC.

[0084] Substrate 100 may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Substrate 100 may include an active region defined by a device isolation layer.

[0085] The peripheral logic circuit PC may include row and column decoders, page buffers, and / or control circuitry. More specifically, the peripheral logic circuit PC may include a gate insulating layer on the substrate 100, a gate electrode on the gate insulating layer, and source / drain regions disposed in the active region on both sides of the gate electrode. For example, the peripheral logic circuit PC may include transistors.

[0086] The peripheral circuit interconnect INC can be electrically connected to the peripheral logic circuit PC via the peripheral contact pin PCT. For example, the peripheral contact pin PCT and the peripheral circuit interconnect INC can be connected to an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor.

[0087] Interlayer insulating layer 110 may be disposed on the entire top surface of substrate 100. In other words, interlayer insulating layer 110 may cover the entire top surface of substrate 100. Interlayer insulating layer 110 may cover peripheral logic circuits PC, peripheral contact pins PCT, and peripheral circuit interconnects INC on substrate 100. Interlayer insulating layer 110 may include multiple stacked insulating layers. For example, interlayer insulating layer 110 may include at least one of silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or low-k dielectric layer.

[0088] The cell array structure CAS can be disposed on the interlayer insulating layer 110. The cell array structure CAS can include the vertically stacked cell array layers described above. In other words, the cell array structure CAS can include the referenced above. Figure 5A and Figure 5B The first conductive line CL1, the first unit stack CS1, the common conductive line CCL, the second unit stack CS2, and the second conductive line CL2 are described.

[0089] Figures 8 to 11 It is along Figure 4 The cross-sectional views taken along lines I-I' and II-II' illustrate a 3D semiconductor memory device according to an exemplary embodiment of the present invention. Figure 12 yes Figure 10 An enlarged view of part "B". In the following text, the same components as in the above embodiments may be indicated by the same reference numerals or reference numerals, and their descriptions may be omitted or briefly mentioned for ease of explanation.

[0090] Reference Figure 8The 3D semiconductor memory device may include a first cell stack CS1, a second cell stack CS2, and a third cell stack CS3 vertically stacked on a substrate 100. The first cell stack CS1 and the second cell stack CS2 may share a first common conductive line CCL1, and the second cell stack CS2 and the third cell stack CS3 may share a second common conductive line CCL2. In other words, the first common conductive line CCL1 is disposed between the first cell stack CS1 and the second cell stack CS2, and the second common conductive line CCL2 is disposed between the second cell stack CS2 and the third cell stack CS3.

[0091] The first common conductive line CCL1 can extend along the second direction D2 to intersect with the first conductive line CL1, and the second common conductive line CCL2 can extend along the first direction D1 to intersect with the first common conductive line CCL1. The second conductive line CL2 can extend along the second direction D2 to intersect with the second common conductive line CCL2.

[0092] The first unit stack CS1 can be disposed at the intersection of the first conductive line CL1 and the first common conductive line CCL1. The first filling insulating pattern 134 can fill the space between the first unit stack CS1. The first covering pattern 132 can cover the sidewalls of the first unit stack CS1 with a substantially uniform thickness, and can be disposed between the bottom surface of the first filling insulating pattern 134 and the first conductive line CL1.

[0093] The second unit stack CS2 can be disposed at the intersection of the first common conductive line CCL1 and the second common conductive line CCL2. The third filling insulating pattern 164 can fill the space between the second unit stack CS2. The third covering pattern 162 can cover the sidewalls of the second unit stack CS2 with a substantially uniform thickness, and can be disposed between the third filling insulating pattern 164 and the first buffer insulating pattern 156.

[0094] The third unit stack CS3 can be disposed at the intersection of the second common conductive line CCL2 and the second conductive line CL2. The fifth fill insulating pattern 194 can fill the space between the third unit stack CS3. The fifth cover pattern 192 can be disposed between the sidewall of the third unit stack CS3 and the fifth fill insulating pattern 194, and between the fifth fill insulating pattern 194 and the second buffer insulating pattern 186. For example, the fifth cover pattern 192 can be in direct contact with the bottom of the fifth fill insulating pattern 194 and the second buffer insulating pattern 186.

[0095] The first unit stack CS1, the second unit stack CS2, and the third unit stack CS3 can each include a first electrode BE, a switch pattern SP, a second electrode ME, a variable resistor pattern RP, and a third electrode TE stacked in the order described above.

[0096] In this embodiment, the first common conductive line CCL1 and the second common conductive line CCL2 may be thicker than the first conductive line CL1. For example, the thickness of the first common conductive line CCL1 and the thickness of the second common conductive line CCL2 may be at least twice the thickness of the first conductive line CL1. Furthermore, the first common conductive line CCL1 and the second common conductive line CCL2 may be thicker than the second conductive line CL2.

[0097] A first etch stop pattern ES1 may be disposed between the top surface of the first cell stack CS1 and each first common conductive line CCL1. The first etch stop pattern ES1 may be formed of a metal material different from the metal material of the first common conductive line CCL1. A second overlay pattern 152 may conformally cover the sidewalls of the first common conductive line CCL1 and the sidewalls of the first etch stop pattern ES1. For example, the second overlay pattern 152 may penetrate the first etch stop pattern ES1. The bottom surface of the second overlay pattern 152 may be located at a lower horizontal level than the bottom surface of the first etch stop pattern ES1.

[0098] A second etch stop pattern ES2 may be disposed between the top surface of the second cell stack CS2 and each second common conductive line CCL2. The second etch stop pattern ES2 may be formed of a metal material different from the metal material of the second common conductive line CCL2. A fourth fill insulating pattern 184 may be disposed between the second common conductive lines CCL2. A fourth cover pattern 182 may conformally cover the sidewalls of the second common conductive line CCL2 and the sidewalls of the second etch stop pattern ES2. For example, the fourth cover pattern 182 may penetrate the second etch stop pattern ES2. The bottom surface of the fourth cover pattern 182 may be located at a lower horizontal level than the bottom surface of the second etch stop pattern ES2.

[0099] Each second conductive line CL2 can be disposed on the third cell stack CS3 arranged along the second direction D2. An upper etch stop pattern UES can be disposed between the top surface of the third cell stack CS3 and each second conductive line CL2.

[0100] according to Figure 9 In the exemplary embodiment of the inventive concept shown, the first unit stack CS1, the second unit stack CS2, the third unit stack CS3, and the fourth unit stack CS4 can be vertically stacked between the first conductive line CL1 and the second conductive line CL2. In the following description, for ease of explanation, references to [the above] may be omitted or briefly mentioned. Figure 8 The same components are described in the embodiments.

[0101] The first unit stack CS1 and the second unit stack CS2 can share the first common conductive line CCL1, and the second unit stack CS2 and the third unit stack CS3 can share the second common conductive line CCL2. The third unit stack CS3 and the fourth unit stack CS4 can share the third common conductive line CCL3.

[0102] The first common conductive line CCL1 can extend along the second direction D2 to intersect with the first conductive line CL1, and the second common conductive line CCL2 can extend along the first direction D1 to intersect with the first common conductive line CCL1. The third common conductive line CCL3 can extend along the second direction D2 to intersect with the second common conductive line CCL2. The second conductive line CL2 can extend along the first direction D1 to intersect with the third common conductive line CCL3.

[0103] A third common conductive line CCL3 may be disposed on a third cell stack CS3, and a third etch stop pattern ES3 may be disposed between the top surface of the third cell stack CS3 and each third common conductive line CCL3. The third common conductive line CCL3 may have substantially the same characteristics as the first common conductive line CCL1 and the second common conductive line CCL2 described above. The third etch stop pattern ES3 may have substantially the same characteristics as the first etch stop pattern ES1 and the second etch stop pattern ES2 described above.

[0104] The sixth fill insulating pattern 214 can be disposed between the third common conductive lines CCL3, and the sixth cover pattern 212 can conformally cover the sidewalls of the third common conductive lines CCL3 and the sidewalls of the third etch stop pattern ES3. The seventh fill insulating pattern 224 can be disposed between the fourth cell stacks CS4, and the seventh cover pattern 222 can be disposed between the seventh fill insulating pattern 224 and the fourth cell stacks CS4.

[0105] The second conductive line CL2 can be disposed on the fourth unit stack CS4, and the upper etch stop pattern UES can be disposed between the top surface of the fourth unit stack CS4 and each second conductive line CL2.

[0106] according to Figure 10 and Figure 11 In an exemplary embodiment of the inventive concept shown, a common conductive line CCL extending along the second direction D2 can be disposed between the first unit stack CS1 and the second unit stack CS2.

[0107] The first conductive line CL1 and the second conductive line CL2 may comprise a first metallic material, while the common conductive line CCL may comprise a second metallic material with a resistivity lower than that of the first metallic material. For example, the first conductive line CL1 and the second conductive line CL2 may be formed from tungsten, aluminum, ruthenium, platinum, or any combination thereof. The first conductive line CL1 and the second conductive line CL2 may also comprise conductive metal nitrides such as TiN, TaN, or WN. The common conductive line CCL may comprise copper or a copper alloy. Here, the copper alloy may be an alloy obtained by mixing copper with very small amounts of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Al, or Zr.

[0108] The common conductive line CCL may have a second thickness T2 that is substantially equal to or less than the first thickness T1 of the first conductive line CL1. The second thickness T2 of the common conductive line CCL may be substantially equal to or less than the thickness of the second conductive line CL2.

[0109] The bottom width of each common conductive line CCL can be smaller than the top width of each common conductive line CCL. (Refer to...) Figure 12 The bottom width of each common conductive line CCL can be smaller than the top width of the first unit stack CS1. For example, Figure 12 The bottom width of the common conductive line CCL can be smaller than the top width of the third electrode TE of the first unit stack CS1. The blocking metal pattern MB can conformally cover the bottom surface and sidewalls of each common conductive line CCL. In other words, the bottom of the blocking metal pattern MB can be disposed between the third electrode TE of the first unit stack CS1 and the common conductive line CCL. The sidewall portions of the blocking metal pattern MB can be disposed between the sidewall of the common conductive line CCL and the molded pattern MLP, and between the sidewall of the common conductive line CCL and the molded etch stop pattern MES. In an exemplary embodiment of the inventive concept, the third electrode TE of the first unit stack CS1 can have a circular top surface.

[0110] Refer again Figure 10 The molded pattern MLP can be disposed between the common conductive lines CCL, and the molded etch stop pattern MES can be disposed between the molded pattern MLP and the first fill insulating pattern 134. Here, the molded pattern MLP may include an insulating material, and the molded etch stop pattern MES may include an insulating material different from the insulating material of the molded pattern MLP. The molded pattern MLP may include a silicon oxide layer or a low-k dielectric layer with a dielectric constant lower than that of silicon oxide. The molded etch stop pattern MES may include a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, a silicon carbonitride layer, or any combination thereof.

[0111] A second conductive line CL2 can be disposed on a second cell stack CS2. Each second conductive line CL2 can contact a third electrode TE of the second cell stack CS2 arranged along the first direction D1.

[0112] according to Figure 11 In an exemplary embodiment of the inventive concept shown, the upper etch stop pattern UES can be disposed between each second conductive line CL2 and the second cell stack CS2. The upper etch stop pattern UES can contact the third electrode TE of the second cell stack CS2 arranged along the first direction D1. Additionally, the top surface of the third fill insulating pattern 164 can be recessed between the second conductive lines CL2. In other words, the bottom surface of the upper cover layer CPL can be located at a lower horizontal level than the bottom surface of the upper etch stop pattern UES.

[0113] Figures 13 to 24 It is along Figure 4 The cross-sectional views taken along lines I-I' and II-II' illustrate a method for manufacturing a 3D semiconductor memory device according to an exemplary embodiment of the present invention.

[0114] Reference Figure 4 and Figure 13 A first conductive line CL1 can be formed on the substrate 100. The first conductive line CL1 can extend along a first direction D1 and can be spaced apart from each other in a second direction D2.

[0115] In an exemplary embodiment of the present invention, a first conductive layer may be deposited on a substrate 100, and then the first conductive layer may be patterned to form a first conductive line CL1. In an exemplary embodiment of the present invention, the first conductive line CL1 may be formed together with a first cell stack CS1 formed on the first conductive line CL1.

[0116] The first conductive line CL1 may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), or a metal semiconductor compound (e.g., a metal silicide).

[0117] An interlayer insulating layer 110 may be formed on the substrate 100 prior to the formation of the first conductive line CL1, and the top surface of the interlayer insulating layer 110 between the first conductive lines CL1 may be recessed during the patterning process for forming the first conductive line CL1. The interlayer insulating layer 110 may be formed of an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride).

[0118] After forming the first conductive lines CL1, a lower insulating pattern 115 may be formed to fill the spaces between the first conductive lines CL1. Forming the lower insulating pattern 115 may include: depositing a lower insulating layer to fill the spaces between the first conductive lines CL1; and planarizing the lower insulating layer to expose the top surface of the first conductive lines CL1. For example, the lower insulating pattern 115 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0119] Reference Figure 14 A first electrode layer 121, a switching layer 123, a second electrode layer 125, a variable resistor layer 127, and a third electrode layer 129 can be sequentially stacked on the first conductive line CL1 and the lower insulating pattern 115. Additionally, metal layers can be formed between the second electrode layer 125 and the variable resistor layer 127, and between the third electrode layer 129 and the variable resistor layer 127, respectively. The third electrode layer 129 can be thicker than the first electrode layer 121 and the second electrode layer 125. Alternatively, the thicknesses of the first electrode layer 121, the second electrode layer 125, and the third electrode layer 129 can be substantially equal to each other.

[0120] The first electrode layer 121, the second electrode layer 125, and the third electrode layer 129 can be formed using chemical vapor deposition (CVD), metal-organic CVD (MOCVD), or plasma-enhanced CVD (PECVD).

[0121] A first mask pattern MP1 can be formed on the third electrode layer 129. The first mask pattern MP1 can be spaced apart from each other on the third electrode layer 129 along a first direction D1 and a second direction D2. The first mask pattern MP1 may include silicon nitride, silicon carbide and / or silicon oxynitride.

[0122] Reference Figure 4 and Figure 15 The third electrode layer 129, the variable resistor layer 127, the second electrode layer 125, the switch layer 123, and the first electrode layer 121 can be sequentially etched using the first mask pattern MP1 as an etching mask. Therefore, a first unit stack CS1 spaced apart from each other can be formed on each first conductive line CL1. Each first unit stack CS1 may include a first electrode BE, a switch pattern SP, a second electrode ME, a variable resistor pattern RP, and a third electrode TE sequentially stacked on each first conductive line CL1. Each first unit stack CS1 may be separated by a lower insulating pattern 115.

[0123] The formation of the first electrode BE, the second electrode ME, the third electrode TE, the variable resistance pattern RP, and the switch pattern SP can be performed using an anisotropic etching process with strong flatness. For example, the anisotropic etching process may include an ion beam etching process and / or a reactive ion etching process. When forming the first cell stack CS1, a spacer layer covering the sidewalls of the variable resistance pattern RP can be formed after the formation of the variable resistance pattern RP and before the formation of the switch pattern SP.

[0124] When forming the first unit stack CS1, the width of the variable resistor pattern RP can be different from the width of the switch pattern SP. For example, the width of the variable resistor pattern RP can be smaller than the width of the switch pattern SP. The variable resistor pattern RP can have sloping sidewalls or circular sidewalls. The top width of the switch pattern SP can be smaller than the bottom width of the switch pattern SP, and the switch pattern SP can have sloping sidewalls. In other words, the switch pattern SP can be gradually narrowing.

[0125] Reference Figure 16 A first capping layer 131 can be formed to cover the first cell stack CS1. The first capping layer 131 can cover the sidewalls of the first cell stack CS1 and can cover the top surface of the lower insulating pattern 115 exposed between the first cell stacks CS1. The first capping layer 131 may comprise silicon nitride and / or silicon oxynitride. The first capping layer 131 can be formed by atomic layer deposition (ALD) and / or CVD methods. The thickness of the first capping layer 131 can be less than half the distance between adjacent first cell stacks CS1. Therefore, after depositing the first capping layer 131, a void space can be formed between the first cell stacks CS1.

[0126] Subsequently, a first filler insulating layer 133 can be formed to fill the empty spaces between the first unit stacks CS1. The first filler insulating layer 133 can be formed of an insulating material different from the insulating material of the first cover layer 131.

[0127] The first filling insulating layer 133 can completely fill the blank space between the first cell stacks CS1 on the first capping layer 131. The first filling insulating layer 133 can be formed using a layer formation method with excellent gap-filling characteristics (e.g., flowable chemical vapor deposition (FCVD) or spin coating). The first filling insulating layer 133 can be formed of a low-k dielectric layer. For example, the first filling insulating layer 133 can include at least one of a SiC layer, a SiCN layer, a SiOCH layer, a SiOC layer, or a SiOF layer.

[0128] Reference Figure 17A planarization process can be performed on the first fill insulating layer 133 and the first capping layer 131 to expose the third electrode TE of the first cell stack CS1. Therefore, a first capping pattern 132 and a first fill insulating pattern 134 can be formed between the first cell stack CS1. A chemical mechanical polishing (CMP) process can be performed as a planarization process. In the planarization process forming the first capping pattern 132 and the first fill insulating pattern 134, the top surfaces of the first capping pattern 132 and the first fill insulating pattern 134 can be recessed from the top surface of the first cell stack CS1.

[0129] Next, an etch stop layer 141 and a common conductive layer 143 can be sequentially stacked on the first cell stack CS1. The etch stop layer 141 can cover the top surface of the first cell stack CS1 and the top surface of the first filled insulating pattern 134. The etch stop layer 141 and the common conductive layer 143 can be formed by ALD and / or CVD methods.

[0130] The etch stop layer 141 may be formed of a material having etch selectivity relative to the third electrode TE of the first unit stack CS1. The etch stop layer 141 may be formed of a conductive material and may include a metallic material. For example, the etch stop layer 141 may be formed of Ti, Ta, TiN, TaN, AlN, or any combination thereof. The etch stop layer 141 may have approximately up to approximately The thickness.

[0131] The common conductive layer 143 can be formed of the same conductive material as the first conductive line CL1. The thickness of the common conductive layer 143 can be equal to or greater than twice the thickness of the first conductive line CL1. The common conductive layer 143 can be formed of copper, tungsten, aluminum, ruthenium, platinum, or any combination thereof. The common conductive layer 143 can have approximately [missing information - likely a number or shape]. up to approximately The thickness.

[0132] Next, a second mask pattern MP2 can be formed on the common conductive layer 143. The second mask pattern MP2 may have a line extending along the second direction D2 on the common conductive layer 143. The second mask pattern MP2 may include silicon nitride, silicon carbide, and / or silicon oxynitride.

[0133] Reference Figure 4 and Figure 18An anisotropic etching process can be performed on the common conductive layer 143 using the second mask pattern MP2 as an etching mask. Therefore, a common conductive line CCL extending along the second direction D2 can be formed on the first cell stack CS1. In the anisotropic etching process of the common conductive layer 143, the common conductive layer 143 can be etched until the etch stop layer 141 is exposed. For example, the common conductive layer 143 can be etched to form a concave shape on top of the etch stop layer 141.

[0134] The etch stop layer 141 prevents the first cell stack CS1 from being exposed during the formation of the common conductive line CCL. Therefore, damage to the first cell stack CS1 can be prevented during the formation of a thick common conductive line CCL. As described above, when the common conductive layer 143 is etched, a portion of the etch stop layer 141 can be etched, and thus the top surface of the etch stop layer 141 can be recessed. The top width of each common conductive line CCL can be smaller than the bottom width of each common conductive line CCL, and each common conductive line CCL can have sloping sidewalls. For example, some common conductive line CCLs can be gradually narrowed.

[0135] The second mask pattern MP2 can be removed during the formation of the common conductive line CCL. Alternatively, the process of removing the second mask pattern MP2 can be performed after the formation of the common conductive line CCL.

[0136] Reference Figure 4 and Figure 19 An etching process can be performed on the etch stop layer 141 to expose the first fill insulating pattern 134. Therefore, an etch stop pattern ES extending along the second direction D2 can be formed on the first cell stack CS1.

[0137] The etching processes for the common conductive layer 143 and the etch stop layer 141 are shown in the accompanying drawings. Alternatively, anisotropic etching processes for the common conductive layer 143 and the etch stop layer 141 can be performed in situ.

[0138] In the etching process used to form the etch stop pattern ES, the top surface of the first fill insulating pattern 134 and / or the top surface of the first cover pattern 132 can be recessed by over-etching. After forming the common conductive line CCL and the etch stop pattern ES, the first fill insulating pattern 134 and the first cover pattern 132 may have circular top surfaces. In an exemplary embodiment of the inventive concept, a portion of the first cover pattern 132 may be exposed when forming the etch stop pattern ES. Additionally, a portion of the first fill insulating pattern 134 may be exposed when forming the etch stop pattern ES. In an exemplary embodiment of the inventive concept, a portion of the sidewall of the third electrode TE of the first cell stack CS1 may be exposed when forming the etch stop pattern ES.

[0139] Reference Figure 20 A second capping layer 151 can be formed to conformally cover the sidewalls of the etch stop pattern ES and the common conductive line CCL. The second capping layer 151 can cover the top surface of the first capping pattern 132 exposed between the common conductive lines CCL and the top surface of the first fill insulating pattern 134. The second capping layer 151 can be formed by an ALD method and / or a CVD method. The second capping layer 151 may include silicon nitride and / or silicon oxynitride.

[0140] The thickness of the second capping layer 151 can be less than half the distance between adjacent common conductive lines CCL. Therefore, after depositing the second capping layer 151, a blank space can be formed between the common conductive lines CCL.

[0141] Subsequently, a second filler insulating layer 153 can be formed on the second cover layer 151 to fill the empty spaces between the common conductive lines CCL. The second filler insulating layer 153 can be formed of an insulating material different from the insulating material of the second cover layer 151.

[0142] The second filling insulating layer 153 can be formed using a layer forming method with excellent gap-filling properties (e.g., flowable chemical vapor deposition (FCVD) or spin coating).

[0143] The second filling insulating layer 153 may be formed of an oxide-based material doped with impurities. For example, the oxide-based material doped with impurities may include fluorine-doped oxides (or fluorosilicone glass (FSG)), carbon-doped oxides (e.g., SiOC), silicon oxide, hydrosilicates (SiO:H, HSQ), methylsilicates (SiO:CH3, MSQ), or a-SiOC (SiOC:H).

[0144] Reference Figure 21 A planarization process can be performed on the second filler insulating layer 153 and the second cover layer 151 to expose the top surface of the common conductive line CCL. Therefore, a second cover pattern 152 and a second filler insulating pattern 154 can be formed between the common conductive lines CCL. A chemical mechanical polishing (CMP) process can be performed as the planarization process. In the planarization process, the top surface of the second filler insulating pattern 154 can be recessed between the common conductive lines CCL. Therefore, the top surface of the second filler insulating pattern 154 can be lower than the top surface of the common conductive lines CCL. The second filler insulating pattern 154 can have a circular top surface. In other words, a recessed region can be formed between the common conductive lines CCL.

[0145] Reference Figure 22A buffer insulation pattern 156 can be formed to fill the recessed area of ​​the second fill insulation pattern 154. Forming the buffer insulation pattern 156 may include: forming a buffer insulation layer that fills the recessed area of ​​the second fill insulation pattern 154 and covers the common conductive line CCL; and planarizing the buffer insulation layer to expose the top surface of the common conductive line CCL. The buffer insulation pattern 156 may be formed of an insulating material different from the insulating material of the second cover pattern 152 and the second fill insulation pattern 154.

[0146] Next, refer to Figure 4 and Figure 22 A second unit stack CS2 can be formed on each common conductive line CCL. Similar to the first unit stack CS1, the second unit stack CS2 can be spaced apart from each other in a first direction D1 and a second direction D2. The method of forming the second unit stack CS2 can be substantially similar to the method of forming the first unit stack CS1. The formation of the second unit stack CS2 may include: sequentially stacking a first electrode layer, a switch layer, a second electrode layer, a variable resistor layer, and a third electrode layer on the common conductive line CCL; forming a third mask pattern MP3 on the third electrode layer; and anisotropically etching the third electrode layer, the variable resistor layer, the second electrode layer, the switch layer, and the first electrode layer using the third mask pattern MP3 as an etching mask. Therefore, each second unit stack CS2 may include a first electrode BE, a switch pattern SP, a second electrode ME, a variable resistor pattern RP, and a third electrode TE sequentially stacked on each common conductive line CCL.

[0147] The second unit stack CS2 can be formed using an anisotropic etching process with strong flatness, and in the anisotropic etching process, the buffer insulation pattern 156 between the common conductive lines CCL can be used as an etching stop layer.

[0148] Reference Figure 23 Similar to the formation of the first cover pattern 132 and the first fill insulation pattern 134, a third cover pattern 162 and a third fill insulation pattern 164 can be formed between the second unit stacks CS2. The third cover pattern 162 and the third fill insulation pattern 164 can be formed of different insulating materials. The third cover pattern 162 can contact either the buffer insulation pattern 156 or the second fill insulation pattern 154.

[0149] The formation of the third cover pattern 162 and the third fill insulating pattern 164 may include: sequentially depositing a third cover layer and a third fill insulating layer covering the second cell stack CS2, and performing a planarization process on the third fill insulating layer and the third cover layer to expose the third electrode TE of the second cell stack CS2. In the planarization process for forming the third cover pattern 162 and the third fill insulating pattern 164, the top surfaces of the third cover pattern 162 and the third fill insulating pattern 164 may be recessed from the top surface of the second cell stack CS2.

[0150] Subsequently, referring to Figure 4 and Figure 23 An etch stop layer 171, an upper conductive layer 173, and a hard mask layer HM can be sequentially stacked on the second unit stack CS2. The upper etch stop layer 171 can cover the third electrode TE, the third overlay pattern 162, and the third fill insulating pattern 164 of the second unit stack CS2.

[0151] The upper etch stop layer 171 may be formed of a material having etch selectivity relative to the third electrode TE of the second cell stack CS2. For example, the upper etch stop layer 171 may directly contact the third electrode TE and the upper portion of the third overlay pattern 162 and the upper portion of the third fill insulating pattern 164. The upper etch stop layer 171 may be formed of a conductive material and may include a metallic material. The upper etch stop layer 171 may be thinner than the etch stop pattern ES.

[0152] The upper conductive layer 173 may be thinner than the common conductive line CCL and may have substantially the same thickness as the first conductive line CL1. The upper conductive layer 173 may be formed of the same conductive material as the first conductive line CL1. The hard mask layer HM may be formed of an insulating material that has etch selectivity relative to the upper conductive layer 173.

[0153] Next, a fourth mask pattern MP4 can be formed on the hard mask layer HM. The fourth mask pattern MP4 can have a line extending along the first direction D1 on the hard mask layer HM. In other words, gaps can be formed between the fourth mask patterns MP4. The fourth mask pattern MP4 can include silicon nitride, silicon carbide, and / or silicon oxynitride.

[0154] Reference Figure 4 and Figure 24An anisotropic etching process can be performed on the hard mask layer HM and the upper conductive layer 173 by using the fourth mask pattern MP4 as an etching mask. In the anisotropic etching process of the upper conductive layer 173, the upper etch stop layer 171 can be used as an etch stop layer, and the upper etch stop layer 171 can be etched by over-etching. Therefore, a hard mask pattern HP extending along the first direction D1, a second conductive line CL2, and an upper etch stop pattern UES can be formed on the second cell stack CS2. The fourth mask pattern MP4 can be removed after the second conductive line CL2 and the upper etch stop pattern UES are formed.

[0155] When forming the second conductive line CL2 and the upper etch stop pattern UES, the top surface of the third overlay pattern 162 and the top surface of the third fill insulating pattern 164 can be recessed between the second conductive line CL2. The recessed areas of the third overlay pattern 162 and the third fill insulating pattern 164 are located in the region between the fourth mask pattern MP4.

[0156] Next, refer to Figure 5A and Figure 5B An upper capping layer CPL can be formed to conformally cover the sidewalls of the second conductive line CL2. The upper capping layer CPL can cover the top surface and sidewalls of the hard mask pattern HP, and can cover the third capping pattern 162 and the third filler insulating pattern 164 exposed between the second conductive lines CL2. The upper capping layer CPL may include silicon nitride and / or silicon oxynitride. The upper capping layer CPL can be formed by ALD and / or CVD methods.

[0157] Figures 25 to 29 It is along Figure 4 The cross-sectional views taken along lines I-I' and II-II' illustrate a method for manufacturing a 3D semiconductor memory device according to an exemplary embodiment of the present invention. In the following text, references to [reference numerals] may be omitted for ease of explanation. Figures 4 to 24 Descriptions of the same features mentioned.

[0158] Reference Figure 25 You can refer to the above. Figures 13 to 16 The first conductive line CL1, the first unit stack CS1, the first cover pattern 132 and the first fill insulating pattern 134 are formed as described.

[0159] After forming the first cover pattern 132 and the first fill insulating pattern 134, a molding etch stop layer ESL and a molding layer ML can be formed on the first cell stack CS1. Here, the molding etch stop layer ESL can be formed of an insulating material that has etch selectivity relative to the molding layer ML. For example, the molding etch stop layer ESL can be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, a silicon carbonitride layer, or any combination thereof. The molding layer ML can be formed of silicon oxide or a low-k dielectric material with a dielectric constant lower than that of silicon oxide.

[0160] After forming the molding layer ML, a molding mask pattern MP having a line extending along the second direction D2 can be formed on the molding layer ML.

[0161] Reference Figure 26 A molding mask pattern MP can be used as an etch mask to anisotropically etch the molding layer ML, thereby forming a molding pattern MLP. During the formation of the molding pattern MLP, the molding etch stop layer ESL can be etched by over-etching to form a molding etch stop pattern MES. In other words, trenches can be formed. For example, trenches can be formed between adjacent stacks of the molding pattern MLP and the molding etch stop pattern MES. Each trench can expose the third electrode TE of the first cell stack CS1 arranged along the second direction D2. The top surface of the third electrode TE of the first cell stack CS1 exposed through the trench can be partially recessed during the formation of the molding pattern MLP. The molding mask pattern MP can be removed after the trenches are formed.

[0162] Reference Figure 27 A common conductive line (CCL) can be formed in a trench. The formation of the common conductive line CCL may include: forming a barrier metal layer that conformally covers the inner surface of the trench; forming a metal layer that completely fills the trench having the barrier metal layer; and planarizing the metal layer and the barrier metal layer to expose the top surface of the molded pattern MLP. Therefore, each common conductive line CCL may include a barrier metal pattern and a metal pattern.

[0163] Here, the common conductive line CCL may include a metallic material different from that of the first conductive line CL1. The resistivity of the metallic material in the common conductive line CCL may be less than that of the metallic material in the first conductive line CL1. For example, the common conductive line CCL may include copper or a copper alloy. Here, the copper alloy may be an alloy obtained by mixing copper with very small amounts of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Al, or Zr. The barrier metal layer may include conductive metal nitrides such as titanium nitride, tantalum nitride, and / or tungsten nitride.

[0164] Reference Figure 28 You can refer to the above. Figure 22 As described, a second unit stack CS2 is formed on the common conductive line CCL. Next, it can be referred to above... Figure 23 As described, a third cover pattern 162 and a third filler insulating pattern 164 are formed between the second unit stack CS2. Here, the third cover pattern 162 may contact the molded pattern MLP.

[0165] Reference Figure 29 You can refer to the above. Figure 23 and Figure 24 As described, a second conductive line CL2 extending along the first direction D1 is formed on the second cell stack CS2. In other words, when forming the second conductive line CL2, an upper etch stop pattern UES can be formed between the second conductive line CL2 and the second cell stack CS2. Here, the upper etch stop pattern UES can be formed of a conductive material.

[0166] According to an exemplary embodiment of the present invention, the resistance of the common conductive line shared by the first memory cell and the second memory cell can be reduced, thereby improving the electrical characteristics of the 3D semiconductor memory device.

[0167] In addition, etch stop patterns can be used in the formation of common conductive lines, thus preventing damage to the cell stack below the common conductive lines.

[0168] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A three-dimensional semiconductor memory device, comprising: A first unit stack is arranged along a first direction and a second direction, the first direction and the second direction being parallel to the top surface of the substrate and intersecting each other; A second unit stack is disposed on the first unit stack and arranged along the first direction and the second direction; A first conductive line extends along the first direction and is disposed between the substrate and the first cell stack; A common conductive line extends along the second direction and is disposed between the first unit stack and the second unit stack; An etch stop pattern extending along the second direction and disposed between the top surface of the first unit stack and the common conductive line, the etch stop pattern comprising a conductive material; A second conductive line extends along the first direction and is disposed on the second unit stack; as well as A cover pattern, penetrating the etch stop pattern, extends continuously from the sidewall of the common conductive line to the sidewall of the etch stop pattern, and covers both the sidewall of the common conductive line and the sidewall of the etch stop pattern. The second thickness of each of the common conductive lines is greater than the first thickness of each of the first conductive lines.

2. The three-dimensional semiconductor memory device according to claim 1, wherein, The bottom width of one of the etch stop patterns is greater than the top width of one of the first cell stacks.

3. The three-dimensional semiconductor memory device according to claim 1, wherein, The top width of one of the common conductive lines is smaller than the bottom width of one of the second unit stacks.

4. The three-dimensional semiconductor memory device according to claim 1, wherein, The second thickness is at least twice the first thickness.

5. The three-dimensional semiconductor memory device according to claim 1, further comprising: An insulating pattern is filled between the common conductive lines. The bottom surface of the filling insulating pattern is located at a lower horizontal height than the bottom surface of one of the etching stop patterns.

6. The three-dimensional semiconductor memory device according to claim 5, further comprising: An underfill insulating pattern is disposed between the first unit stacks. The covering pattern includes a bottom portion disposed between the filling insulation pattern and the lower filling insulation pattern.

7. The three-dimensional semiconductor memory device according to claim 6, wherein, Both the first cell stack and the second cell stack include: The first, second, and third electrodes are stacked sequentially. The switching pattern located between the first electrode and the second electrode; and A variable resistance pattern located between the second electrode and the third electrode. The bottom of the overlay pattern is located between the top and bottom surfaces of the third electrode in each of the first unit stacks.

8. The three-dimensional semiconductor memory device according to claim 5, further comprising: An insulating pattern is filled in the upper part of the unit, which is disposed between the stacks of the second units. as well as An upper cover pattern is disposed between the sidewall of the second unit stack and the upper fill insulation pattern, and between the upper fill insulation pattern and the fill insulation pattern. The bottom surface of the upper covering pattern is located at approximately the same horizontal height as the top surface of the common conductive line.

9. The three-dimensional semiconductor memory device according to claim 8, further comprising: A buffer insulation pattern is disposed on the fill insulation pattern between the common conductive lines. The upper covering pattern is in contact with the top surface of the buffer insulation pattern.

10. The three-dimensional semiconductor memory device according to claim 1, further comprising: An upper etch stop pattern is formed between the top surface of the second unit stack and each of the second conductive lines, and is made of a conductive material. Wherein, the second thickness of the common conductive wire is greater than the third thickness of the second conductive wire, and The upper etch stop pattern is thinner than the etch stop pattern.

11. A three-dimensional semiconductor memory device, comprising: A first conductive line extends along a first direction parallel to the top surface of the substrate; The first unit stack is located on the first conductive line; A first filler insulating pattern is located between the first cell stacks; A common conductive line extends on each of the first unit stacks along a second direction intersecting the first direction; An etch stop pattern is disposed between the common conductive line and each of the first unit stacks and is formed of a conductive material; A second unit stack is located on the common conductive line; A second filling insulating pattern covers the sidewalls of the common conductive line and the sidewalls of the etch stop pattern; A cover pattern that penetrates the etch stop pattern, extends continuously from the sidewall of the common conductive line to the sidewall of the etch stop pattern, and is disposed between the sidewall of the common conductive line and the second fill insulating pattern and between the sidewall of the etch stop pattern and the second fill insulating pattern; as well as The second conductive line extends along the first direction on each of the second unit stacks. The second thickness of the common conductive line is greater than the first thickness of the first conductive line.

12. The three-dimensional semiconductor memory device according to claim 11, wherein, The bottom surface of the second insulating pattern is located below the top surface of the first unit stack.

13. The three-dimensional semiconductor memory device according to claim 11, wherein, Each of the first cell stack and the second cell stack includes: First electrode, second electrode, and third electrode; A switch pattern located between the first electrode and the second electrode; and A variable resistance pattern, wherein the variable resistance pattern is located between the second electrode and the third electrode. The cover pattern includes a bottom located between the first filling insulating pattern and the second filling insulating pattern, and the bottom of the cover pattern is located between the top and bottom surfaces of the third electrode of the first unit stack.

14. The three-dimensional semiconductor memory device according to claim 11, wherein, The bottom width of the etch stop pattern is greater than the top width of the first unit stack.

15. The three-dimensional semiconductor memory device according to claim 11, wherein, The top width of the common conductive line is smaller than the bottom width of the second unit stack.

16. A three-dimensional semiconductor memory device, comprising: Multiple first conductive lines, the multiple first conductive lines extending along a first direction on the substrate; A stacked structure comprising a plurality of cell array layers vertically stacked on the first conductive line, wherein each cell array layer comprises a stack of cells arranged along the first direction and a second direction intersecting the first direction; Multiple common conductive lines are disposed between the unit array layers, wherein the thickness of the common conductive lines is greater than the thickness of the first conductive line; An etch stop pattern is disposed between the bottom surface of each of the common conductive lines and the top surface of the unit stack, and is formed of a conductive material; A cover pattern, penetrating the etch stop pattern, extending continuously from the sidewall of the common conductive line to the sidewall of the etch stop pattern, and covering both the sidewall of the common conductive line and the sidewall of the etch stop pattern; and Multiple second conductive lines extend along the first direction or the second direction on the stacked structure.

17. The three-dimensional semiconductor memory device according to claim 16, wherein, The thickness of one of the common conductive lines is greater than the thickness of one of the second conductive lines.

18. The three-dimensional semiconductor memory device of claim 16, further comprising a filling insulating pattern disposed between the common conductive lines; and in, The overlay pattern is disposed between the sidewall of the common conductive line and the fill insulating pattern, and between the sidewall of the etch stop pattern and the fill insulating pattern.

19. The three-dimensional semiconductor memory device according to claim 18, wherein, The bottom surface of the filling insulating pattern is located below the bottom surface of the etching stop pattern.

20. The three-dimensional semiconductor memory device according to claim 18, wherein, At least one of the cell stacks includes: The first, second, and third electrodes are stacked sequentially. The switching pattern located between the first electrode and the second electrode; and A variable resistance pattern located between the second electrode and the third electrode. The etch stop pattern contacts the top surface of the third electrode of the unit stack, and The bottom surface of the covering pattern is located at a horizontal height between the top and bottom surfaces of the third electrode.

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