Display device with transmissive regions and method of manufacturing a display device

Abstract

A display device and a method of manufacturing a display device are provided. The display device includes a substrate including a first display area and a second display area, the second display area including a transmissive area; a plurality of first pairs of electrodes and a plurality of second pairs of electrodes, each corresponding to the first display area; and a plurality of third pairs of electrodes and a plurality of fourth pairs of electrodes, each corresponding to the second display area and surrounding at least a portion of the transmissive area. A shape of each of the plurality of first pairs of electrodes is identical to a shape of each of the plurality of third pairs of electrodes.

Description

[0001] This application claims the benefit and priority of Korean Patent Application No. 10-2020-0040480, filed on April 2, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more specifically, to a display device having a transmissive region and a method for manufacturing the display device. Background Technology

[0003] Display devices are now used more widely than ever before. Furthermore, they have become thinner and lighter, allowing them to be used in a wide variety of devices.

[0004] Because display devices are used in various ways, there are various methods available for designing their shapes, allowing for the efficient production of displays in different shapes. Furthermore, a wide variety of functional devices are integrated into display devices, making modern display devices more capable than ever before. Summary of the Invention

[0005] The display device includes: a substrate including a first display area and a second display area, the second display area including a transmissive area; a plurality of first pairs of electrodes and a plurality of second pairs of electrodes, each corresponding to the first display area; and a plurality of third pairs of electrodes and a plurality of fourth pairs of electrodes, each corresponding to the second display area and surrounding at least a portion of the transmissive area. The shapes of the plurality of first pairs of electrodes are the same as the shapes of the plurality of third pairs of electrodes.

[0006] The shapes of the plurality of second pairs of electrodes can be the same as the shapes of the plurality of fourth pairs of electrodes.

[0007] The area of ​​each of the plurality of third pairs of electrodes may be different from the area of ​​each of the plurality of fourth pairs of electrodes.

[0008] Each of the plurality of first pairs of electrodes to the plurality of fourth pairs of electrodes may correspond to two pixels.

[0009] Each of the plurality of first pairs of electrodes may have a first quadrilateral shape with a long side in a first direction, and the first pairs of electrodes that are adjacent to each other in the first direction may overlap each other at the edges of the first quadrilateral.

[0010] The plurality of first pairs of electrodes may be spaced apart from each other in a second direction intersecting the first direction, and some of the plurality of second pairs of electrodes may be arranged in the space between the plurality of first pairs of electrodes.

[0011] Each of the plurality of third pairs of electrodes may have a third quadrilateral shape with a long side in a first direction, and the transmission region may be arranged between the third pairs of electrodes that are adjacent to each other in the first direction.

[0012] The plurality of first pairs of electrodes may be at least partially superimposed on the plurality of third pairs of electrodes at the boundary between the first display area and the second display area.

[0013] The plurality of second pairs of electrodes may be at least partially superimposed on the plurality of fourth pairs of electrodes at the boundary between the first display area and the second display area.

[0014] The display device may also include a region in which two of the plurality of first pairs of electrodes can overlap with one of the plurality of second pairs of electrodes.

[0015] A method of manufacturing a display device, the display device including a first display area and a second display area, the second display area including a transmissive area, the method comprising: aligning a first mask to correspond to a substrate; firstly depositing a portion of a counter electrode on the substrate using the first mask; secondly depositing a portion of the counter electrode by moving the first mask along a +x direction and a +y direction intersecting the +x direction; aligning a second mask to correspond to the substrate; thirdly depositing a portion of the counter electrode on the substrate using the second mask; and fourthly depositing the remaining portion of the counter electrode by moving the second mask along a -x direction and a +y direction.

[0016] The first mask may include a first mask opening and a third mask opening. The first mask opening may have the same shape and the same size as the third mask opening. The separation distance of the first mask opening may be different from the separation distance of the third mask opening.

[0017] The second mask may include a second mask opening and a fourth mask opening. The second mask opening may have the same shape and the same size as the fourth mask opening. The separation distance of the second mask opening may be different from the separation distance of the fourth mask opening. The size of the second mask opening may be different from the size of the first mask opening.

[0018] The first mask opening and the second mask opening can have a rectangular shape, the rectangular shape having a long side in a direction of -45° relative to the x direction.

[0019] The display device includes: a substrate including a first display area, a second display area, and a non-display area, the second display area including a transmissive area, and the non-display area located outside the first and second display areas; counter electrodes corresponding to the first and second display areas; and power lines disposed in the non-display area. Some of the counter electrodes are superimposed on the power lines, and some of the outer patterns of the outermost portion of the counter electrodes are spaced apart from each other.

[0020] The counter electrodes may include a plurality of first pairs of electrodes arranged in a first display area and a plurality of third pairs of electrodes arranged in a second display area. The plurality of first pairs of electrodes may have the same shape and the same size as the plurality of third pairs of electrodes.

[0021] The display device may further include: a planarization layer disposed on the power lines and including contact holes that expose a portion of the power lines; and connecting wires disposed on the planarization layer and connected to the power lines through the contact holes. Some of the counter electrodes may contact the connecting wires.

[0022] No separation space may be provided between the external patterns arranged outside the first display area.

[0023] The display device includes: a substrate including a first display area and a second display area, the second display area including a transmissive area; a plurality of first pairs of electrodes and a plurality of second pairs of electrodes, each corresponding to the first display area; and a plurality of third pairs of electrodes and a plurality of fourth pairs of electrodes, each corresponding to the second display area and surrounding at least a portion of the transmissive area. The shapes of the plurality of first pairs of electrodes are the same as the shapes of the plurality of second pairs of electrodes. The shapes of the plurality of third pairs of electrodes are different from the shapes of the plurality of fourth pairs of electrodes.

[0024] The edges of the plurality of first pairs of electrodes can be configured as rounded rhombuses (e.g., rhombuses with rounded corners), and the edges of the plurality of third pairs of electrodes can be configured as rounded rectangles (e.g., rectangles with rounded corners).

[0025] The size of the plurality of third pairs of electrodes may be larger than the size of the plurality of fourth pairs of electrodes.

[0026] Each of the plurality of third pairs of electrodes may correspond to six pixels, and each of the plurality of fourth pairs of electrodes may correspond to two pixels.

[0027] Each of the multiple first electrode pairs can correspond to four pixels.

[0028] The display device includes: a first display area and a second display area, the first display area including first pixels with a first pixel density, the second display area including second pixels with a second pixel density less than the first pixel density; and a sensor disposed within a transmissive area of ​​the second display area. The counter electrode of the second pixel at least partially surrounds the transmissive area.

[0029] The shape and size of the counter electrode of the second pixel can be the same as those of the counter electrode of the first pixel. The sensor can be configured to emit or receive light or sound. Attached Figure Description

[0030] The above and other aspects, features, and elements of certain embodiments disclosed will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 This is a perspective view showing a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 2 This is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 3 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 4A This is an equivalent circuit diagram illustrating active matrix driven pixels arranged in a display area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 4B This is an equivalent circuit diagram illustrating active matrix driven pixels arranged in a display area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0036] Figure 5 This is a diagram illustrating the arrangement structure of a plurality of pixels applicable to exemplary embodiments of the present disclosure;

[0037] Figure 6 It is shown Figure 3 The diagram shows a plan view of region B, a portion of the boundary between the first and second display areas;

[0038] Figure 7 It is along Figure 6 A sectional view taken from lines I-I' and II-II';

[0039] Figure 8 It is along Figure 6 A sectional view taken from line III-III';

[0040] Figure 9This is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0041] Figure 10A and Figure 10B This is a diagram illustrating an example of a mask for forming an electrode according to an exemplary embodiment of the present disclosure;

[0042] Figures 11A to 11D It shows the use Figure 10A and Figure 10B A diagram illustrating the mask manufacturing method;

[0043] Figure 12 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0044] Figure 13A and Figure 13B It is shown Figure 12 A magnified view of region C;

[0045] Figure 14 It is along Figure 13A A sectional view taken by line IV-IV';

[0046] Figure 15 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure, showing a portion of the boundary between a first display area and a second display area;

[0047] Figure 16A and Figure 16B It shows the basis for forming Figure 15 A diagram illustrating an example of the arrangement of the electrode masks; and

[0048] Figure 17A and Figure 17B It shows the use Figure 16A and Figure 16B A diagram illustrating the mask manufacturing method. Detailed Implementation

[0049] Referring now to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Throughout the drawings and specification, the same reference numerals may refer to the same elements. In this respect, the invention may take different forms and should not necessarily be construed as limited to the description set forth herein. Therefore, several exemplary embodiments of the present disclosure are described below with reference to the figures to explain aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0050] Because this disclosure allows for various modifications and numerous embodiments, exemplary embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as methods of implementing them, will become apparent and more readily understood from the following description of embodiments and the accompanying drawings. However, the invention is not necessarily limited to the exemplary embodiments given below, and the invention can be implemented in various other forms.

[0051] In the following description, embodiments are described in detail with reference to the accompanying drawings. When describing with reference to the drawings, the same reference numerals may be given to the same or corresponding elements, and in respect of omitting repeated descriptions, it may be assumed that elements not given in description are at least similar to corresponding elements described elsewhere in the specification.

[0052] It will be understood that although the terms “first,” “second,” etc., may be used here to describe various components, these components should not necessarily be limited by these terms. These components may only be used to distinguish one component from another.

[0053] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0054] It will also be understood that the term “including / comprises” and its variations, as used herein, indicate the presence of the stated feature or component, but do not exclude the presence or addition of one or more other features or components. Conversely, the term “consisting of” is intended to exclude the presence or addition of one or more other features or components.

[0055] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, that layer, region, or component may be formed directly or indirectly on said other layer, region, or component. For example, there may be, for instance, intermediate layers, regions, or components.

[0056] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are shown for ease of explanation, the following embodiments are not necessarily limited thereto.

[0057] When an embodiment can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in a sequence opposite to the described sequence or other different sequences.

[0058] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, that layer, region, or component may be "directly connected" to said other layer, region, or component, and / or may be "indirectly connected" to said other layer, region, or component with other layers, regions, or components between them. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, that layer, region, or component may be "directly electrically connected" to said other layer, region, or component, and / or may be "indirectly electrically connected" to said other layer, region, or component with other layers, regions, or components between them.

[0059] Reference Figure 1 The display device 1 includes a first display area DA1, a second display area DA2, and a non-display area NDA. The first display area DA1 and the second display area DA2 display images, while the non-display area NDA does not display images. The display device 1 can display a main image by utilizing light emitted from a plurality of main pixels Pm arranged in the first display area DA1.

[0060] Display device 1 includes a second display area DA2. The second display area DA2 may include an area in which components are arranged, including sensors or cameras (or image sensors) using infrared light, visible light, and / or sound. The second display area DA2 may include a transmission area TA through which light and / or sound emitted from the components to the outside or traveling from the outside toward the components can pass. In an exemplary embodiment of this disclosure, when infrared light or visible light passes through the second display area DA2, the transmittance of the second display area DA2 may be 30% or greater, 50% or greater, 75% or greater, 80% or greater, 85% or greater, or 90% or greater.

[0061] Multiple auxiliary pixels Pa can be arranged in a second display area DA2, and the display device 1 can display a predetermined image by using light emitted from the multiple auxiliary pixels Pa. The image displayed in the second display area DA2 is an auxiliary image and may have a lower resolution (e.g., the number of pixels per unit area) than the image displayed in the first display area DA1. For example, because the second display area DA2 includes a transmissive area TA through which light and / or sound can pass, the number of auxiliary pixels Pa arranged per unit area of ​​the second display area DA2 may be less than the number of main pixels Pm arranged per unit area of ​​the first display area DA1. Optionally, the area of ​​the auxiliary pixels Pa per unit area may be less than the area of ​​the main pixels Pm per unit area.

[0062] The second display area DA2 can be arranged on one side of the first display area DA1. In an exemplary embodiment of this disclosure, in Figure 1The diagram shows that the second display area DA2 is arranged on the top side of the first display area DA1, so the second display area DA2 can be arranged between the non-display area NDA and the first display area DA1.

[0063] In the following description, although an organic light-emitting display device is used as an example to illustrate display device 1, the display device of the present invention is not limited thereto. For example, various display devices, such as inorganic light-emitting display devices and quantum dot light-emitting display devices, can be used.

[0064] Despite Figure 1 The illustration shows a second display area DA2 positioned on the top side of the first display area DA1, but the invention is not limited thereto. The shape of the second display area DA2 may include a circle, an ellipse, or a polygon such as a triangle or a pentagon. The position of the second display area DA2 and the number of second display areas DA2 may vary.

[0065] Figure 2 It is along Figure 1 A cross-sectional view of a display device 1 according to an exemplary embodiment of the present disclosure, taken by line A-A'.

[0066] Reference Figure 2 The display device 1 may include a display panel 10 and a component 20. The display panel 10 includes display elements, and the component 20 corresponds to a second display area DA2.

[0067] The display panel 10 may include a substrate 100, a display element layer 200, and a thin-film encapsulation layer 300. The display element layer 200 may be disposed on the substrate 100. The thin-film encapsulation layer 300 may serve as a sealing member for sealing the display element layer 200. In addition, the display panel 10 may also include a bottom protective film 175 and a bottom cover layer 185 disposed under the substrate 100.

[0068] Substrate 100 may comprise glass or a polymeric resin. The polymeric resin may comprise polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide, polyarylate, polyimide (PI), polycarbonate, and / or cellulose acetate propionate (CAP). Substrate 100 comprising a polymeric resin may be flexible, rollable, or bendable. For example, substrate 100 comprising a polymeric resin may be bent, rolled, or folded to a non-negligible degree without cracking or otherwise breaking. Substrate 100 may have a multilayer structure comprising a layer containing a polymeric resin and an inorganic layer.

[0069] The display element layer 200 may include a circuit layer, organic light-emitting diodes (OLEDs) and OLED', and insulating layers IL and IL'. The circuit layer may include thin-film transistors (TFTs) and TFT'.

[0070] The main pixel Pm can be arranged in the first display area DA1, and the auxiliary pixel Pa can be arranged in the second display area DA2. The main pixel Pm includes a main thin-film transistor TFT and a main organic light-emitting diode OLED connected to the main thin-film transistor TFT, and the auxiliary pixel Pa includes an auxiliary thin-film transistor TFT' and an auxiliary organic light-emitting diode OLED' connected to the auxiliary thin-film transistor TFT'.

[0071] Additionally, the transmissive region TA can be arranged within the second display region DA2. The auxiliary thin-film transistor TFT' and the display element do not need to be arranged within the transmissive region TA. The transmissive region TA can be the area through which light / signal emitted from component 20 or incident on component 20 passes (e.g., where most of the light / signal is not absorbed or reflected).

[0072] Component 20 can be arranged in the second display area DA2. Component 20 may include electronic components that use light or sound. For example, component 20 may include sensors such as infrared sensors that emit and / or receive light, sensors that output and sense light or sound to measure distance or identify fingerprints, small lamps that output light, speakers that output sound, and image sensors that capture images. When using electronic components that use light, various wavelengths of light, such as visible light, infrared light, and ultraviolet light, can be used. Multiple components 20 can be arranged in the second display area DA2. For example, a light emitter and a light receiver, which are components 20, can be arranged together in one second display area DA2. Optionally, a light emitter and a light receiver can be arranged simultaneously in one component 20.

[0073] A bottom metal layer BSM can be disposed in the second display area DA2. The bottom metal layer BSM can correspond to the auxiliary thin-film transistor TFT'. The bottom metal layer BSM can correspond to the second display area DA2 other than the transmissive area TA. The bottom metal layer BSM can block external light from reaching the auxiliary pixel Pa, including the auxiliary thin-film transistor TFT', etc. Optionally, the bottom metal layer BSM can prevent light emitted from component 20 from being diffracted by slits formed by wiring disposed in the second display area DA2.

[0074] In an exemplary embodiment of this disclosure, because a constant voltage or signal can be applied to the bottom metal layer BSM, damage to the pixel circuitry due to electrostatic discharge can be prevented.

[0075] The thin-film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Regarding this, Figure 2 A first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 disposed therebetween are shown.

[0076] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may comprise a polymeric material. The polymeric material may comprise an acrylic resin, an epoxy resin, polyimide, and / or polyethylene.

[0077] The bottom protective film 175 may be attached to the bottom portion of the substrate 100 to support and protect the substrate 100. The bottom protective film 175 may include a material with high light transmittance. For example, the bottom protective film 175 may include PET and / or PI.

[0078] A bottom cover layer 185 may be disposed below the bottom protective film 175. The bottom cover layer 185 may include an opening 185OP corresponding to the second display area DA2. Because the bottom cover layer 185 includes the opening 185OP, the light transmittance of the second display area DA2 can be increased. The bottom cover layer 185 may include a light-blocking material. Therefore, the bottom cover layer 185 can block external light that can pass through the bottom surface of the substrate 100.

[0079] The area of ​​the second display area DA2 can be larger than the area of ​​the area where the component 20 is arranged. Therefore, the area of ​​the opening 185OP of the bottom cover layer 185 can be different from the area of ​​the second display area DA2. For example, the area of ​​the opening 185OP can be smaller than the area of ​​the second display area DA2.

[0080] In addition, multiple components 20 can be arranged in the second display area DA2. The multiple components 20 can have different functions.

[0081] Elements such as input sensing components, anti-reflective components, and transparent windows can be further arranged on the display panel 10. The input sensing components can be configured to sense touch input. The anti-reflective components may include polarizers, delayers, color filters, and / or black matrices.

[0082] Although the thin-film encapsulation layer 300 can be used as an encapsulation component for sealing the display element layer 200, the present invention is not limited thereto. For example, as a component for sealing the display element layer 200, a sealing substrate can be used that is attached to the substrate 100 by using a sealant or frit.

[0083] Figure 3 This is a plan view of a display panel 10 according to an exemplary embodiment of the present disclosure.

[0084] Reference Figure 3The display panel 10 includes a plurality of main pixels Pm arranged in a first display area DA1. Each of the main pixels Pm may include a display element such as an organic light-emitting diode (OLED). Each main pixel Pm may emit, for example, red, green, blue, or white light through the organic light-emitting diode. In this specification, as described above, the main pixel Pm can be understood as a sub-pixel that emits red, green, blue, or white light. The first display area DA1 is referred to above. Figure 2 The described encapsulation component covers the area, thus protecting it from external air or moisture.

[0085] The second display area DA2 can be arranged on one side of the first display area DA1. A plurality of auxiliary pixels Pa can be arranged in the second display area DA2. Each of the auxiliary pixels Pa can include a display element such as an organic light-emitting diode (OLED). Each auxiliary pixel Pa can emit, for example, red, green, blue, or white light through the OLED. In this specification, as described above, the auxiliary pixel Pa can be understood as a sub-pixel that emits red, green, blue, or white light. A transmissive region TA can be provided in the second display area DA2, and the transmissive region TA is arranged between the auxiliary pixels Pa. At least one component 20 can be arranged in the second display area DA2 of the display panel 10.

[0086] In exemplary embodiments of this disclosure, the pixel circuitry of a main pixel Pm may be the same as that of an auxiliary pixel Pa. However, the invention is not limited thereto. The pixel circuitry of the main pixel Pm may be different from that of the auxiliary pixel Pa.

[0087] Because the second display area DA2 includes the transmission area TA, the resolution of the second display area DA2 can be less than the resolution of the first display area DA1. For example, the resolution of the second display area DA2 per unit area can be about half the resolution of the first display area DA1. In an exemplary embodiment of this disclosure, the resolution of the first display area DA1 can be 400 ppi (pixels per inch) or greater, and the resolution of the second display area DA2 can be 200 ppi or greater. Figure 3 Region B represents a portion of the boundary between the first display region DA1 and the second display region DA2, as described in detail below.

[0088] Pixels (e.g., primary pixel Pm and auxiliary pixel Pa) can be electrically connected to external circuitry arranged in the non-display area NDA. A first scan drive circuit 110, a second scan drive circuit 120, a terminal 140, a first power line 160, and a second power line 170 can be arranged in the non-display area NDA.

[0089] The first scan driving circuit 110 can provide scan signals to pixels (e.g., main pixel Pm and auxiliary pixel Pa) via scan lines SL. The first scan driving circuit 110 can also provide transmission control signals to each pixel via transmission control lines EL. The second scan driving circuit 120 can be arranged parallel to the first scan driving circuit 110, and a first display area DA1 is disposed between the first scan driving circuit 110 and the second scan driving circuit 120. Some pixels (e.g., main pixel Pm and auxiliary pixel Pa) can be electrically connected to the first scan driving circuit 110, and the remaining pixels (e.g., main pixel Pm and auxiliary pixel Pa) can be electrically connected to the second scan driving circuit 120. In exemplary embodiments of this disclosure, the second scan driving circuit 120 may be omitted.

[0090] Terminal 140 may be disposed on one side of substrate 100. Terminal 140 may be exposed and electrically connected to printed circuit board (PCB) without being covered by an insulating layer. Terminal PCB-P of printed circuit board PCB may be electrically connected to terminal 140 of display panel 10. Printed circuit board PCB transmits signals or power from controller to display panel 10. Control signals generated by controller may be transmitted through printed circuit board PCB to first scan drive circuit 110 and second scan drive circuit 120. Controller may provide first power voltage ELVDD and second power voltage ELVSS (see [reference]) to first power line 160 and second power line 170 respectively via first connection line 161 and second connection line 171. Figure 4A and Figure 4B (And the corresponding explanation below). A first power voltage ELVDD (also known as a drive voltage) can be provided to the pixels (e.g., main pixel Pm and auxiliary pixel Pa) through the drive voltage line PL connected to the first power line 160, and a second power voltage ELVSS (also known as a common voltage) can be provided to the counter electrode of the pixels (e.g., main pixel Pm and auxiliary pixel Pa) connected to the second power line 170.

[0091] Data drive circuit 150 is electrically connected to data line DL. Data signals from data drive circuit 150 can be provided to pixels (e.g., primary pixel Pm and auxiliary pixel Pa) via connection line 151 and data line DL. Connection line 151 is connected to terminal 140, and data line DL is connected to connection line 151. Although in Figure 3 The diagram shows the data driver circuit 150 arranged on a printed circuit board (PCB), but the data driver circuit 150 may optionally be arranged on the substrate 100. For example, the data driver circuit 150 may be arranged between terminal 140 and the first power line 160.

[0092] The first power line 160 may include a first sub-line 162 and a second sub-line 163, which extend parallel to each other in the x-direction. A first display area DA1 is disposed between the first sub-line 162 and the second sub-line 163. The second power line 170 may have an annular shape with an open side and may partially surround the first display area DA1.

[0093] Figure 4A and Figure 4B This is an equivalent circuit diagram of a main pixel Pm and / or an auxiliary pixel Pa that may be included in a display panel 10 according to an exemplary embodiment of the present disclosure.

[0094] Reference Figure 4A Each of the pixels (e.g., main pixel Pm and auxiliary pixel Pa) includes a pixel circuit PC and a main organic light-emitting diode OLED. The pixel circuit PC is connected to the scan line SL and the data line DL, and the main organic light-emitting diode OLED is connected to the pixel circuit PC.

[0095] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 can be connected to the scan line SL and the data line DL, and can transmit the data signal Dm input from the data line DL to the driving thin-film transistor T1 based on the scan signal Sn input from the scan line SL.

[0096] The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store the voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor T2 and the first power voltage ELVDD supplied to the drive voltage line PL.

[0097] The driving thin-film transistor T1 can be connected between the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the main organic light-emitting diode (OLED) in response to the voltage stored in the storage capacitor Cst. The main organic light-emitting diode (OLED) can emit light with a predetermined brightness according to the driving current.

[0098] although Figure 4A The invention describes a pixel circuit PC comprising two thin-film transistors and a storage capacitor, but the invention is not limited thereto. Figure 4B As shown, the pixel circuit PC may include seven thin-film transistors and a storage capacitor.

[0099] Reference Figure 4BEach pixel (e.g., a main pixel Pm and an auxiliary pixel Pa) includes a pixel circuit PC and a main organic light-emitting diode (OLED), the OLED being connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor and multiple thin-film transistors. The thin-film transistors and storage capacitors may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL.

[0100] Despite Figure 4B The diagram illustrates each of the pixels (e.g., primary pixel Pm and auxiliary pixel Pa) connected to signal lines SL, SL-1, EL, and DL, initialization voltage line VL, and drive voltage line PL; however, the invention is not limited thereto. In exemplary embodiments of this disclosure, at least one of the signal lines SL, SL-1, EL, and DL, initialization voltage line VL, and drive voltage line PL may be shared by adjacent pixels.

[0101] The multiple thin-film transistors may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0102] Signal lines SL, SL-1, EL, and DL may include a scan line SL, a previous scan line SL-1, an emit control line EL, and a data line DL. The scan line SL transmits the scan signal Sn. The previous scan line SL-1 transmits the previous scan signal Sn-1 to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7. The emit control line EL transmits the emit control signal En to the operation control thin-film transistor T5 and the emit control thin-film transistor T6. The data line DL intersects with the scan line SL and transmits the data signal Dm. The drive voltage line PL transmits the drive voltage ELVDD to the drive thin-film transistor T1. The initialization voltage line VL transmits the initialization voltage Vint that initializes the drive thin-film transistor T1 and the pixel electrode.

[0103] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 is connected to the driving voltage line PL through the operation control thin-film transistor T5. The driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the main organic light-emitting diode (OLED) through the emission control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2 and drives the driving current I. OLED Supply to the main organic light-emitting diode (OLED).

[0104] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL, the switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1, and the operating control thin-film transistor T5 is simultaneously connected to the driving voltage line PL. The switching thin-film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL, and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin-film transistor T1.

[0105] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1, and is simultaneously connected to the pixel electrode of the main organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and the driving thin-film transistor T1 is diode-connected by electrically connecting the driving gate electrode G1 of the driving thin-film transistor T1 to the driving drain electrode D1 of the driving thin-film transistor T1.

[0106] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin-film transistor T4 is connected to the second initialization drain electrode D7 and the initialization voltage line VL of the second initialization thin-film transistor T7. The first initialization drain electrode D4 of the first initialization thin-film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and performs an initialization operation to initialize the voltage of the driving gate electrode G1 of the driving thin-film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin-film transistor T1.

[0107] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emitter control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the drive source electrode S1 of the driving thin film transistor T1 and the switch drain electrode D2 of the switching thin film transistor T2.

[0108] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. The emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the main organic light-emitting diode OLED.

[0109] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL. The driving voltage ELVDD is transmitted to the main organic light-emitting diode OLED, and the driving current I... OLED It flows through the main organic light-emitting diode (OLED).

[0110] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization thin-film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin-film transistor T6 and the pixel electrode of the main organic light-emitting diode (OLED). The second initialization drain electrode D7 of the second initialization thin-film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin-film transistor T4 and the initialization voltage line VL. The second initialization thin-film transistor T7 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, thereby initializing the pixel electrode of the main organic light-emitting diode (OLED).

[0111] Despite Figure 4B The diagram shows a first initialization thin-film transistor T4 and a second initialization thin-film transistor T7 connected to the previous scan line SL-1, but the invention is not limited thereto. For example, the first initialization thin-film transistor T4 may be connected to the previous scan line SL-1 and driven according to the previous scan signal Sn-1, and the second initialization thin-film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and driven according to the signal transmitted through that separate signal line.

[0112] The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the main organic light-emitting diode (OLED) is connected to the second power supply line 170. The common voltage ELVSS is transmitted through the second power supply line 170. Therefore, the main organic light-emitting diode (OLED) can receive the driving current I from the driving thin-film transistor T1. OLED It emits light to display the image.

[0113] Despite Figure 4BThe diagram shows that both the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 include dual gate electrodes, but both the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may include a single gate electrode.

[0114] The pixel circuit PC of the main pixel Pm can be the same as the pixel circuit PC of the auxiliary pixel Pa. However, the present invention is not limited thereto. The pixel circuit PC of the main pixel Pm can be different from the pixel circuit PC of the auxiliary pixel Pa. For example, the main pixel Pm can use... Figure 4B The pixel circuit, while the auxiliary pixel Pa can be adopted Figure 4A The pixel circuitry can be modified in various ways.

[0115] Figure 5 This is a diagram illustrating an example of an arrangement structure of multiple pixels applicable to exemplary embodiments of this disclosure. For example, Figure 5 The arrangement of the emission regions of multiple pixels R, G, and B is shown. In this case, the emission region of a pixel can be defined by an opening in the pixel-defining layer, as described below.

[0116] like Figure 5 As shown, multiple green pixels G are spaced apart from each other at predetermined intervals in the first row 1N; multiple red pixels R and multiple blue pixels B are arranged alternately in the adjacent second row 2N; multiple green pixels G are spaced apart from each other at predetermined intervals in the third row 3N; and multiple blue pixels B and multiple red pixels R are arranged alternately in the adjacent fourth row 4N. This pixel arrangement is repeated until the Nth row. In this case, the blue pixels B and red pixels R can be larger than the green pixels G.

[0117] In this configuration, multiple green pixels G in the first row 1N are arranged alternately with multiple red pixels R and multiple blue pixels B in the second row 2N. Therefore, red pixels R and blue pixels B are arranged alternately in the first column 1M, multiple green pixels G are spaced apart from each other at predetermined intervals in the adjacent second column 2M, blue pixels B and red pixels R are arranged alternately in the adjacent third column 3M, and green pixels G are spaced apart from each other at predetermined intervals in the adjacent fourth column 4M. This pixel arrangement is repeated until the Mth column.

[0118] The pixel arrangement can be described as follows: red pixels R are arranged at the first and third vertices facing each other among the vertices of the virtual quadrilateral VS, and blue pixels B are arranged at the second and fourth vertices, which are the remaining vertices. The virtual quadrilateral VS is centered on the green pixel G. In this case, the virtual quadrilateral VS can be modified into rectangles, rhombuses, squares, etc.

[0119] The pixel arrangement structure according to exemplary embodiments of this disclosure is not necessarily limited thereto. For example, in Figure 5 In the virtual quadrilateral VS, the blue pixel B, instead of the green pixel G, can be placed at the center of the virtual quadrilateral VS. The red pixel R can be placed at the first and third vertices facing each other among the vertices of the virtual quadrilateral VS. The green pixel G can be placed at the second and fourth vertices, which are the remaining vertices.

[0120] This pixel arrangement structure is called a pentile matrix. Pentile matrices can achieve high resolution with a small number of pixels by employing a rendering driver that expresses color by sharing adjacent pixels.

[0121] Figure 6 yes Figure 3 The plan view of region B shows a portion of the boundary between the first display region DA1 and the second display region DA2. Figure 7 It is along Figure 6 The sectional view taken from lines I-I' and II-II'. Figure 8 It is along Figure 6 The sectional view taken from line III-III'.

[0122] First, refer to Figure 6 According to an exemplary embodiment of the present disclosure, a display device 1 includes a first display area DA1, a second display area DA2, and a plurality of counter electrodes 223. The second display area DA2 includes a transmissive area TA. The counter electrodes 223 include a plurality of first counter electrodes 223A, a plurality of second counter electrodes 223B, a plurality of third counter electrodes 223C, and a plurality of fourth counter electrodes 223D. The plurality of first counter electrodes 223A and the plurality of second counter electrodes 223B correspond to the first display area DA1, and the plurality of third counter electrodes 223C and the plurality of fourth counter electrodes 223D correspond to the second display area DA2. The shapes of the plurality of first counter electrodes 223A and the plurality of third counter electrodes 223C are the same. Furthermore, the shapes of the plurality of second counter electrodes 223B and the plurality of fourth counter electrodes 223D are the same. The counter electrodes 223 can be connected to each other, and the counter electrodes 223 can be thicker at the connection portions.

[0123] Each of the first to fourth pairs of electrodes 223A, 223B, 223C, and 223D can be arranged to correspond to the same number of pixels. For example, as Figure 6 As shown, each of the first to fourth pairs of electrodes 223A, 223B, 223C and 223D can be arranged to correspond to two pixels.

[0124] In an exemplary embodiment of this disclosure, a first pair of electrodes 223A may be arranged to correspond to a blue pixel B and a green pixel G.

[0125] In an exemplary embodiment of this disclosure, a second pair of electrodes 223B may be arranged to correspond to a red pixel R and a green pixel G.

[0126] In an exemplary embodiment of this disclosure, a third pair of electrodes 223C may be arranged to correspond to a blue pixel B and a green pixel G. In an exemplary embodiment of this disclosure, a fourth pair of electrodes 223D may be arranged to correspond to a red pixel R and a green pixel G.

[0127] Furthermore, the first to fourth pairs of electrodes 223A, 223B, 223C, and 223D can be configured as rectangular shapes with long sides extending at -45° relative to the x-direction. The edges of the first to fourth pairs of electrodes 223A, 223B, 223C, and 223D can be rounded (rounded).

[0128] The area of ​​a first pair of electrodes 223A can be the same as the area of ​​a third pair of electrodes 223C. Furthermore, the area of ​​a second pair of electrodes 223B can be the same as the area of ​​a fourth pair of electrodes 223D.

[0129] Conversely, because the size of the blue pixel B corresponding to the first pair of electrodes 223A is larger than the size of the red pixel R corresponding to the second pair of electrodes 223B, the area of ​​one pair of first electrodes 223A can be larger than the area of ​​one pair of second electrodes 223B. Furthermore, this allows the edges of the first pair of electrodes 223A and the edges of the second pair of electrodes 223B to overlap.

[0130] Similarly, because the size of the blue pixel B corresponding to the third electrode pair 223C is larger than the size of the red pixel R corresponding to the fourth electrode pair 223D, the area of ​​one third electrode pair 223C can be larger than the area of ​​one fourth electrode pair 223D. Furthermore, this allows the edges of the third electrode pair 223C and the edges of the fourth electrode pair 223D to overlap.

[0131] The third pair of electrodes 223C may have a first length L1 in the a direction and a first width W1 in the b direction. The fourth pair of electrodes 223D may have a second length L2 in the a direction and a second width W2 in the b direction. In this case, the first length L1 may be equal to the second length L2, and the first width W1 may be greater than the second width W2 (e.g., W1>W2).

[0132] Multiple first pairs of electrodes 223A may be arranged side-by-side in the a direction within the first display area DA1. The first pairs of electrodes 223A may be arranged to at least partially overlap with adjacent first pairs of electrodes 223A. The multiple first pairs of electrodes 223A may be spaced apart from each other in the b direction, extending at +45° relative to the x direction.

[0133] The second pair of electrodes 223B can be arranged between a plurality of first pairs of electrodes 223A. In this case, the edges of the second pair of electrodes 223B can at least partially overlap with the edges of the first pair of electrodes 223A.

[0134] Multiple second pairs of electrodes 223B can be arranged side-by-side in direction a. The second pairs of electrodes 223B can be arranged to at least partially overlap with adjacent pairs of electrodes 223B. The multiple pairs of electrodes 223B can be spaced apart from each other in direction b, extending at +45° relative to the x-direction. A first pair of electrodes 223A can be arranged between the multiple pairs of second electrodes 223B.

[0135] For example, within the first display area DA1, the first pair of electrodes 223A can be arranged in a line in direction a, or the second pair of electrodes 223B can be arranged in a line in direction a. The first pair of electrodes 223A and the second pair of electrodes 223B can be arranged alternately in direction b.

[0136] Because the transmission region TA is arranged in the second display region DA2, the arrangement of the counter electrode in the second display region DA2 can be different from the arrangement of the counter electrode in the first display region DA1.

[0137] The transmissive region TA is the area in which no display element is disposed, and therefore has high light transmittance. Multiple transmissive regions TA can be configured in the second display area DA2. Transmissive regions TA and pixel groups Pg can be arranged alternately, with pixel group Pg including auxiliary pixels Pa. Pixel group Pg can include eight pixels. Optionally, auxiliary pixels Pa can surround the transmissive region TA. The transmissive region TA includes the area in which the third pair of electrodes 223C and the fourth pair of electrodes 223D are not disposed, and can represent the area of ​​the second display area DA2 corresponding to the opening 223OP of the electrode 223. In an exemplary embodiment of this disclosure, the transmissive regions TA can be connected to each other in the a direction.

[0138] Multiple third pairs of electrodes 223C may be spaced apart from each other in the a and b directions within the second display area DA2. For example, the third pairs of electrodes 223C may not overlap each other.

[0139] Multiple fourth pairs of electrodes 223D can be arranged side-by-side in direction a. The fourth pairs of electrodes 223D can be at least partially superimposed on adjacent fourth pairs of electrodes 223D. The multiple fourth pairs of electrodes 223D can be spaced apart from each other in direction b. For example, the fourth pairs of electrodes 223D in the second display area DA2 can be arranged in a line in direction a.

[0140] The distance d4 between the plurality of fourth pairs of electrodes 223D in the b direction can be greater than the distance d2 between the plurality of second pairs of electrodes 223B in the b direction (e.g., d4>d2).

[0141] In the second display area DA2, two third pairs of electrodes 223C and two fourth pairs of electrodes 223D can be arranged to correspond to a pixel group Pg. The two third pairs of electrodes 223C can be arranged with a separation space between them, and the two fourth pairs of electrodes 223D can be arranged side by side in the separation space in the a direction.

[0142] The first to fourth pairs of electrodes 223A, 223B, 223C, and 223D can be electrically connected to each other. As described above, the first pair of electrodes 223A and the second pair of electrodes 223B can overlap and contact each other through their edges, and the third pair of electrodes 223C and the fourth pair of electrodes 223D can overlap and contact each other through their edges. Furthermore, within the boundary between the first display area DA1 and the second display area DA2, the first to fourth pairs of electrodes 223A, 223B, 223C, and 223D can overlap and contact each other through their edges.

[0143] The first to fourth pairs of electrodes 223A, 223B, 223C, and 223D can also be arranged in the non-display area NDA and can be electrically connected to the second power line 170 of the non-display area NDA (see...). Figure 3 ).

[0144] In the following text, refer to Figure 7 and Figure 8 The stacking structure of the display device 1 according to an exemplary embodiment of the present disclosure is described. Figure 7 It is along Figure 6 The cross-sectional views are taken by lines I-I' and II-II', and a partial cross-section of the first display area DA1 is shown. Figure 8 It is along Figure 6 The section cut by line III-III' shows a partial cross-section of the second display area DA2 (or sensor area).

[0145] Reference Figure 7 and Figure 8 The display device 1 according to an exemplary embodiment of the present disclosure includes a first display area DA1 and a second display area DA2. A main pixel Pm is disposed in the first display area DA1, and auxiliary pixels Pa and a transmissive area TA are disposed in the sensor area.

[0146] The main pixel Pm may include a main thin-film transistor (TFT), a main storage capacitor Cst, and a main organic light-emitting diode (OLED). The auxiliary pixel Pa may include an auxiliary thin-film transistor (TFT'), an auxiliary storage capacitor Cst', and an auxiliary organic light-emitting diode (OLED'). The transmission region TA may include a transmission aperture TAH corresponding to the transmission region TA.

[0147] Hereinafter, a structure in which elements of a display device 1 according to an exemplary embodiment of the present disclosure are stacked is described.

[0148] The substrate 100 may comprise glass or a polymeric resin. The polymeric resin may comprise polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide, polyarylate, polyimide (PI), polycarbonate, and / or cellulose acetate propionate (CAP). The substrate 100 comprising the polymeric resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure comprising a layer containing the polymeric resin and an inorganic layer.

[0149] A buffer layer 111 may be disposed on a substrate 100 to reduce or prevent the penetration of foreign substances, moisture, or outside air from beneath the substrate 100 and to provide a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials, organic materials, or organic / inorganic composite materials such as oxides or nitrides, and has a single-layer or multi-layer structure comprising inorganic and organic materials. A barrier layer may also be disposed between the substrate 100 and the buffer layer 111, blocking the penetration of outside air. In exemplary embodiments of this disclosure, the buffer layer 111 may comprise silicon oxide (SiO2) or silicon nitride (SiN). x The buffer layer 111 may include a stacked first buffer layer 111a and a second buffer layer 111b.

[0150] The bottom metal layer BSM can be disposed in the second display area DA2 between the first buffer layer 111a and the second buffer layer 111b. In an exemplary embodiment of this disclosure, the bottom metal layer BSM can be disposed between the substrate 100 and the first buffer layer 111a. The bottom metal layer BSM can be disposed below the auxiliary thin-film transistor TFT' to prevent the characteristics of the auxiliary thin-film transistor TFT' from being degraded by light emitted from the component 20, etc.

[0151] Additionally, the bottom metal layer (BSM) can be connected to the wiring GCL arranged on different layers. The bottom metal layer (BSM) can receive a constant voltage or signal from the wiring GCL. For example, the bottom metal layer (BSM) can receive a drive voltage ELVDD or a scan signal. Because the bottom metal layer (BSM) receives a constant voltage or signal, the probability of electrostatic discharge (ESD) can be reduced. The bottom metal layer (BSM) can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), and / or copper (Cu). The bottom metal layer (BSM) can include a single layer or multiple layers containing the above materials.

[0152] The main thin-film transistor (TFT) and the auxiliary thin-film transistor (TFT') can be disposed on the buffer layer 111. The main thin-film transistor (TFT) includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The auxiliary thin-film transistor (TFT') includes a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin-film transistor (TFT) can be connected to the main organic light-emitting diode (OLED) in the first display area DA1 to drive the main OLED. The auxiliary thin-film transistor (TFT') can be connected to the auxiliary organic light-emitting diode (OLED') in the second display area DA2 to drive the auxiliary OLED.

[0153] The first semiconductor layer A1 and the second semiconductor layer A2 may be disposed on the buffer layer 111 and may include polycrystalline silicon. In an exemplary embodiment of this disclosure, the first semiconductor layer A1 and the second semiconductor layer A2 may include amorphous silicon. In an exemplary embodiment of this disclosure, the first semiconductor layer A1 and the second semiconductor layer A2 may include oxides of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). Each of the first semiconductor layer A1 and the second semiconductor layer A2 may include a channel region, a source region, and a drain region, wherein the source region and the drain region are doped with impurities.

[0154] The second semiconductor layer A2 can be stacked with the bottom metal layer BSM, and the second buffer layer 111b is located between the second semiconductor layer A2 and the bottom metal layer BSM. In an exemplary embodiment of this disclosure, the width of the second semiconductor layer A2 can be smaller than the width of the bottom metal layer BSM. Therefore, when projected in a direction perpendicular to the substrate 100, the second semiconductor layer A2 can be completely stacked with the bottom metal layer BSM.

[0155] The first gate insulating layer 112 may cover the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x The inorganic insulating layer 112 may comprise a single layer or multiple layers containing the aforementioned inorganic insulating materials, such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0156] The first gate electrode G1 and the second gate electrode G2 are disposed on the first gate insulating layer 112 and are stacked with the first semiconductor layer A1 and the second semiconductor layer A2, respectively. The first gate electrode G1 and the second gate electrode G2 may comprise molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may comprise a single layer or multiple layers. For example, each of the first gate electrode G1 and the second gate electrode G2 may comprise a single Mo layer.

[0157] The second gate insulating layer 113 may cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x The inorganic insulating layer 113 may comprise a single layer or multiple layers containing the aforementioned inorganic insulating materials, such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0158] The first top electrode CE2 of the main storage capacitor Cst and the second top electrode CE2' of the auxiliary storage capacitor Cst' can be arranged on the second gate insulating layer 113.

[0159] In the first display area DA1, the first top electrode CE2 can be stacked with the first gate electrode G1 below it. The first gate electrode G1 and the first top electrode CE2, which are stacked together and with the second gate insulating layer 113 located therebetween, can constitute the main storage capacitor Cst. For example, the first gate electrode G1 can be used as the first bottom electrode CE1 of the main storage capacitor Cst.

[0160] In the second display area DA2, the second top electrode CE2' can be stacked with the second gate electrode G2 below it. The second gate electrode G2 and the second top electrode CE2', which are stacked together and with the second gate insulating layer 113 located therebetween, can constitute an auxiliary storage capacitor Cst'. The second gate electrode G2 can be used as the second bottom electrode CE1' of the auxiliary storage capacitor Cst'.

[0161] The first top electrode CE2 and the second top electrode CE2' may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers containing the above materials.

[0162] The interlayer insulating layer 115 may cover the first top electrode CE2 and the second top electrode CE2'. The interlayer insulating layer 115 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2).

[0163] The first source electrode S1, the second source electrode S2, and the first drain electrode D1 and the second drain electrode D2 can be disposed on the interlayer insulating layer 115. The first source electrode S1, the second source electrode S2, and the first drain electrode D1 and the second drain electrode D2 can comprise a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and can comprise a single layer or multiple layers comprising the aforementioned materials. For example, the first source electrode S1, the second source electrode S2, and the first drain electrode D1 and the second drain electrode D2 can have a Ti / Al / Ti multilayer structure. In exemplary embodiments of this disclosure, at least one of the first source electrode S1, the second source electrode S2, and the first drain electrode D1 and the second drain electrode D2 can be omitted. In this case, the source region and the drain region on two opposite sides of the channel region of the first semiconductor layer A1 and the second semiconductor layer A2 can be used as the source electrode and the drain electrode, respectively.

[0164] The planarization layer 117 may cover the first source electrode S1 and the second source electrode S2, as well as the first drain electrode D1 and the second drain electrode D2. The planarization layer 117 may have a flat top surface, such that the first pixel electrode 221 and the second pixel electrode 221' disposed on the planarization layer 117 are formed flat.

[0165] The planarization layer 117 may comprise a single layer or multiple layers containing organic or inorganic materials. The planarization layer 117 may comprise general-purpose polymers (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate, or polystyrene), polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof. xThe materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). After forming the planarization layer 117, chemical mechanical polishing can be performed to provide a flat upper surface.

[0166] The planarization layer 117 includes an opening that exposes one of the first source electrode S1 and the first drain electrode D1 of the main thin-film transistor TFT. The first pixel electrode 221 can be electrically connected to the main thin-film transistor TFT by contacting the first source electrode S1 or the first drain electrode D1 through the opening.

[0167] Additionally, the planarization layer 117 includes an opening that exposes one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin-film transistor TFT'. The second pixel electrode 221' can be electrically connected to the auxiliary thin-film transistor TFT' by contacting the second source electrode S2 or the second drain electrode D2 through the opening.

[0168] The first pixel electrode 221 and the second pixel electrode 221' may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In an exemplary embodiment of this disclosure, the first pixel electrode 221 and the second pixel electrode 221' may include a reflective layer, which includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a composite thereof. In an exemplary embodiment of this disclosure, the first pixel electrode 221 and the second pixel electrode 221' may also include a layer containing ITO, IZO, ZnO, or In2O3 located on / below the reflective layer. In an exemplary embodiment of this disclosure, the first pixel electrode 221 and the second pixel electrode 221' may have a stacked ITO / Ag / ITO structure.

[0169] The pixel defining layer 119 may cover the edges of each of the first pixel electrode 221 and the second pixel electrode 221'. The pixel defining layer 119 is stacked with each of the first pixel electrode 221 and the second pixel electrode 221', and includes a first opening OP1 and a second opening OP2 that respectively define the emission region of a pixel. The pixel defining layer 119 can prevent arcing or the like at the edges of the first pixel electrode 221 and the second pixel electrode 221' by increasing the distance between the edges of the first pixel electrode 221 and the second pixel electrode 221' and the counter electrode 223 above the first pixel electrode 221 and the second pixel electrode 221'. The pixel defining layer 119 can be formed by spin coating or the like using an organic insulating material (such as polyimide, polyamide, acrylic resin, BCB, and HMDSO).

[0170] The first functional layer 222a may be disposed on the portions of the first pixel electrode 221 and the second pixel electrode 221' exposed through openings OP1 and OP2. The first functional layer 222a may extend to the top surface of the pixel defining layer 119. The first functional layer 222a may include a single layer or multiple layers. The first functional layer 222a may include a hole transport layer (HTL) having a single-layer structure. Optionally, the first functional layer 222a may include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 222a may be formed integrally to correspond to the main pixel Pm and the auxiliary pixel Pa respectively included in the first display area DA1 and the second display area DA2.

[0171] The first emitting layer 222b and the second emitting layer 222b' can be disposed on the first functional layer 222a, and the first emitting layer 222b and the second emitting layer 222b' correspond to the first pixel electrode 221 and the second pixel electrode 221', respectively. The first emitting layer 222b and the second emitting layer 222b' can include polymer materials or low molecular weight materials, and emit red light, green light, blue light or white light.

[0172] The second functional layer 222c may be formed on the first emission layer 222b and the second emission layer 222b'. The second functional layer 222c may include a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 222c may be formed integrally to correspond to the main pixel Pm and the auxiliary pixel Pa respectively included in the first display area DA1 and the second display area DA2. The first functional layer 222a and / or the second functional layer 222c may be omitted.

[0173] Counter electrode 223 is disposed on the second functional layer 222c. Counter electrode 223 may comprise a conductive material having a low work function. As used herein, "low work function" is intended to mean any material having a work function equal to or lower than any of the materials listed below as examples of low work function materials. For example, counter electrode 223 may comprise a transparent or translucent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, counter electrode 223 may also comprise a layer on top of a (translucent) transparent layer comprising the aforementioned materials, the layer comprising ITO, IZO, ZnO, or In2O3.

[0174] As described above, the counter electrode 223 includes a first pair of electrodes 223A and a second pair of electrodes 223B disposed in the first display area DA1. Additionally, the counter electrode 223 includes a third pair of electrodes 223C and a fourth pair of electrodes 223D disposed in the second display area DA2 (see...). Figure 6 ).

[0175] The first pair of electrodes 223A that are adjacent to each other can overlap and contact each other through their edges. The overlapping portion can be formed between the main pixels Pm. Figure 7 Region R1). One edge of the first pair of electrodes 223A can overlap with the second pair of electrodes 223B, and regions in which two of the first pair of electrodes 223A overlap with one of the second pair of electrodes 223B can be set ( Figure 7 Region R2).

[0176] The thickness of the counter electrode 223 in the stacked region is greater than the thickness of the central region of each first pair of electrodes 223A.

[0177] For example, when the first pair of electrodes 223A has a first thickness t1, the thickness of the pair of electrodes 223 in region R1 can be a second thickness t2 greater than the first thickness t1, where region R1 is the region in which the first pair of electrodes 223A overlaps with adjacent first pair of electrodes 223A. The second thickness t2 can be approximately twice the first thickness t1.

[0178] Furthermore, the thickness of the counter electrode 223 in region R2 can be a third thickness t3 greater than the second thickness t2. Region R2 is the area where two first counter electrodes 223A and one second counter electrode 223B are stacked. The third thickness t3 can be approximately three times the first thickness t1.

[0179] Some of the third pair of electrodes 223C may be spaced apart from each other in the second display area DA2, with the transmission area TA located between the third pair of electrodes 223C. In this case, the separation space between the third pair of electrodes 223C can be understood as an opening 223OP of the electrode 223. The opening 223OP may be included in the transmission aperture TAH through which light passes. The transmission aperture TAH may also include a first aperture H1 and / or a second aperture H2, the first aperture H1 being defined in the pixel defining layer 119 and the second aperture H2 being defined in the planarization layer 117.

[0180] The pixel defining layer 119 may include a first aperture H1 corresponding to the transmission region TA. The first aperture H1 may overlap with the opening 223OP of the counter electrode 223. Although the bottom width of the opening 223OP is shown in the figures to be greater than the bottom width of the first aperture H1, the invention is not limited thereto. For example, because the counter electrode 223 may extend to the inner wall of the transmission aperture TAH, the width of the opening 223OP may be smaller than the width of the first aperture H1.

[0181] The planarization layer 117 may include a second aperture H2 corresponding to the transmission region TA. The second aperture H2 may be stacked with the opening 223OP of the counter electrode 223. Although the bottom width of the first aperture H1 is shown to be greater than the bottom width of the second aperture H2 in the figures, the invention is not limited thereto. For example, because the pixel defining layer 119 may cover the edge of the second aperture H2 of the planarization layer 117, the width of the first aperture H1 may be smaller than the width of the second aperture H2.

[0182] Because a first aperture H1 and / or a second aperture H2 are formed, the transmittance of the transmission region TA can be further increased. Although both a first aperture H1 and a second aperture H2 are shown in the figures, the invention is not limited thereto. For example, only one of the first aperture H1 and the second aperture H2, each corresponding to the transmission region TA, can be provided. Various modifications can be made. The first functional layer 222a and the second functional layer 222c can be arranged inside the transmission aperture TAH.

[0183] The width Wt of the transmission aperture TAH can be greater than the width Wa of the emission region defined by the second opening OP2 of the pixel defining layer 119. When the transmission aperture TAH is formed, this means that components such as the counter electrode 223 corresponding to the transmission region TA are removed. Therefore, the transmittance of the transmission region TA can be significantly increased.

[0184] A capping layer can be formed on the counter electrode 223, which protects the counter electrode 223 while increasing light extraction efficiency. The capping layer may include lithium fluoride (LiF). Optionally, the capping layer may include an inorganic insulating material such as silicon nitride and / or an organic insulating material. In exemplary embodiments of this disclosure, the capping layer may be omitted.

[0185] Figure 9 This is a cross-sectional view showing a display device 1 according to an exemplary embodiment of the present disclosure. Figure 9 It can be along Figure 6 A cross-sectional view of display device 1 taken by line III-III'. Figure 9 Since detailed descriptions of certain components have already been omitted, it can be assumed that these components are at least similar to... Figure 8 The corresponding components.

[0186] Reference Figure 9The transmission aperture TAH may also include a third aperture H3 corresponding to the transmission region TA.

[0187] Assuming the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may include a third aperture H3 corresponding to the transmission region TA. The third aperture H3 can expose the top surface of the buffer layer 111 or the substrate 100. The third aperture H3 may include a first opening of the first gate insulating layer 112, a second opening of the second gate insulating layer 113, and a third opening of the interlayer insulating layer 115 stacked on top of each other. The first opening to the third opening can be formed separately by a separate process or simultaneously by the same process. Optionally, the first opening and the second opening can be formed simultaneously, and the third opening can be formed separately. Various modifications can be made. In the case where the first opening to the third opening is formed by a separate process, a step difference can be formed on the side surface of the third aperture H3.

[0188] The inorganic insulating layer IL may include a recess instead of a third hole H3 that exposes the buffer layer 111. For example, the first gate insulating layer 112 of the inorganic insulating layer IL may be continuously arranged to correspond to the transmission region TA. The second gate insulating layer 113 and the interlayer insulating layer 115 may each include a second opening and a third opening, both corresponding to the transmission region TA.

[0189] Optionally, the first gate insulating layer 112 and the second gate insulating layer 113 can be continuously formed to correspond to the transmission region TA. The interlayer insulating layer 115 may include a third opening corresponding to the transmission region TA. Various modifications can be made.

[0190] Because the inorganic insulating layer IL, planarization layer 117, and pixel defining layer 119 can have a transmittance of component 20 based on its transmitted / received light, it is not necessary to provide an aperture corresponding to the transmission region TA. However, if the inorganic insulating layer IL, planarization layer 117, and pixel defining layer 119 include an aperture corresponding to the transmission region TA, the transmittance can be further increased.

[0191] Figure 10A and Figure 10B This is a diagram illustrating an example of a mask for forming counter electrode 223 according to an exemplary embodiment of the present disclosure. Figures 11A to 11D This is a diagram illustrating a manufacturing method using a mask.

[0192] Reference Figure 10A According to an exemplary embodiment of the present disclosure, the first mask M1 includes a first mask opening 510A and a third mask opening 510C having the same shape.

[0193] The first mask opening 510A can be configured as a quadrilateral shape having a first mask width MW1 in the b direction and a first mask length ML1 in the a direction. The third mask opening 510C can be configured as a quadrilateral shape having a first mask width MW1 in the b direction and a first mask length ML1 in the a direction. The first mask length ML1 can be at least twice the first mask width MW1.

[0194] The first mask openings 510A can be spaced apart from each other in the first region 1A of the first mask M1 and arranged regularly in the x and y directions (e.g., at regular intervals). The third mask openings 510C can be spaced apart from each other in the second region 2A of the first mask M1 and arranged regularly in the x and y directions (e.g., at regular intervals).

[0195] In this case, the distance cd1 between the centers of adjacent first mask openings 510A in the x direction can be less than the distance cd3 between the centers of adjacent third mask openings 510C in the x direction.

[0196] In an exemplary embodiment of this disclosure, the first mask opening 510A may be designed for depositing the first pair of electrodes 223A corresponding to the blue pixel B and the green pixel G arranged in the first display area DA1 (see Figure 6 Furthermore, the third mask opening 510C can be designed for depositing the third pair of electrodes 223C corresponding to the blue pixel B and green pixel G arranged in the second display area DA2 (see...). Figure 6 ).

[0197] The first mask M1 may include a method for depositing counter electrode 233 (see...). Figure 6 A mask, and may include a fine metal mask (FMM). An FMM can be manufactured by forming holes in a metal sheet and pulling and stretching (tensioning) the metal sheet. When the shapes and areas of the first mask opening 510A and the third mask opening 510C are designed to be different from each other, it becomes difficult to manufacture the first mask opening 510A and the third mask opening 510C to the designed dimensions during the process of tensioning the first mask.

[0198] Conversely, because the first mask opening 510A and the third mask opening 510C of the first mask M1 have the same shape and the same area, process errors during the tensioning process can be reduced.

[0199] Reference Figure 10B According to an exemplary embodiment of the present disclosure, the second mask M2 includes a second mask opening 510B and a fourth mask opening 510D having the same shape.

[0200] The second mask opening 510B can be configured as a quadrilateral shape having a second mask width MW2 in the b direction and a second mask length ML2 in the a direction. The fourth mask opening 510D can be configured as a quadrilateral shape having a second mask width MW2 in the b direction and a second mask length ML2 in the a direction. The second mask length ML2 can be at least twice the second mask width MW2.

[0201] The second mask openings 510B can be spaced apart from each other in the first region 1A of the second mask M2 and arranged regularly in the x and y directions (e.g., at regular intervals). The fourth mask openings 510D can be spaced apart from each other in the second region 2A of the second mask M2 and arranged regularly in the x and y directions (e.g., at regular intervals).

[0202] In this case, the distance cd2 between the centers of adjacent second mask openings 510B in the x direction can be less than the distance cd4 between the centers of adjacent fourth mask openings 510D in the x direction.

[0203] In an exemplary embodiment of this disclosure, the second mask opening 510B can be designed for depositing a second pair of electrodes 223B corresponding to the red pixel R and green pixel G arranged in the first display area DA1 (see Figure 6 Furthermore, the fourth mask opening 510D can be designed for depositing the fourth pair of electrodes 223D corresponding to the red pixel R and green pixel G arranged in the second display area DA2 (see...). Figure 6 ).

[0204] Because the second mask opening 510B and the fourth mask opening 510D of the second mask M2 have the same shape and the same area, the process error during the tensioning process can be reduced.

[0205] The shapes and / or sizes of the first mask opening 510A of the first mask M1 and the second mask opening 510B of the second mask M2 may be different from each other. In an exemplary embodiment of this disclosure, the area of ​​the first mask opening 510A may be larger than the area of ​​the second mask opening 510B of the second mask M2. In an exemplary embodiment of this disclosure, the first mask width MW1 may be larger than the second mask width MW2.

[0206] The counter electrode 223 can be formed by a four-step deposition process using a first mask M1 and a second mask M2. Figures 11A to 11D A method for depositing counter electrode 223 by using a first mask M1 and a second mask M2 is shown.

[0207] Reference Figure 11A A second functional layer 222c is formed on the substrate 100 (see...) Figure 7 Then, a first mask M1 is arranged such that the first mask opening 510A of the first mask M1 corresponds to the blue pixel B and the green pixel G in the first display area DA1, and the third mask opening 510C corresponds to the blue pixel B and the green pixel G in the second display area DA2.

[0208] Next, by emitting the deposition material to be formed as the counter electrode from the deposition source, a portion of the counter electrode 223 is initially deposited on the second functional layer 222c. In this case, according to the arrangement of the first mask opening 510A and the third mask opening 510C of the first mask M1, only portions of the first counter electrode 223A and the third counter electrode 223C are formed.

[0209] Next, as Figure 11B As shown, by moving the position of the first mask M1 in the x and y directions, the first mask M1 is arranged such that the first mask opening 510A of the first mask M1 corresponds to the blue pixel B and the green pixel G in the first display area DA1, and the third mask opening 510C corresponds to the blue pixel B and the green pixel G in the second display area DA2. For example, after the initial deposition of the counter electrode 223, a second deposition of the counter electrode 223 can be performed by moving the arrangement of the first mask M1 in the upper right direction. Alternatively, after the initial deposition of the counter electrode 223, a second deposition of the counter electrode 223 can be performed by moving the arrangement of the first mask M1 in the lower left direction. Assuming that the substrate 100 has a width in the x direction and a length in the y direction in the plan view, it can be understood that the first mask M1 is moved and arranged along the diagonal direction of the substrate 100 before performing the second deposition.

[0210] Next, a portion of the electrode 223 is deposited a second time using a deposition source. In this case, the first pair of electrodes 223A formed during the second deposition in the first display area DA1 can overlap and contact the first pair of electrodes 223A formed during the initial deposition through their edges. The third pair of electrodes 223C formed during the second deposition in the second display area DA2 can be spaced apart from the third pair of electrodes 223C formed during the initial deposition.

[0211] Next, as Figure 11C As shown, a second mask M2 is arranged such that the second mask opening 510B of the second mask M2 corresponds to the red pixel R and the green pixel G in the first display area DA1, and the fourth mask opening 510D corresponds to the red pixel R and the green pixel G in the second display area DA2.

[0212] Next, a portion of electrode 223 is deposited for the third time using a deposition source. In this case, based on the arrangement of the second mask opening 510B and the fourth mask opening 510D of the second mask M2, only portions of the second pair of electrodes 223B and the fourth pair of electrodes 223D are formed. The edges of the second pair of electrodes 223B formed during the third deposition can overlap and contact the edges of the first pair of electrodes 223A in the first display area DA1. The edges of the fourth pair of electrodes 223D formed during the third deposition can overlap and contact the edges of the third pair of electrodes 223C in the second display area DA2.

[0213] Next, as Figure 11D As shown, by moving the position of the second mask M2 along the -x and y directions, the second mask M2 is arranged such that the second mask opening 510B of the second mask M2 corresponds to the red pixel R and the green pixel G in the first display area DA1, and the fourth mask opening 510D corresponds to the red pixel R and the green pixel G in the second display area DA2. For example, after the third deposition of the counter electrode 223, the fourth deposition of the counter electrode 223 can be performed by moving the second mask M2 along the upper left direction. Alternatively, after the third deposition of the counter electrode 223, the fourth deposition of the counter electrode 223 can be performed by moving the second mask M2 along the lower right direction. It is understood that the second mask M2 is moved and arranged along the diagonal direction of the substrate 100 before performing the fourth deposition.

[0214] As described above, when using the first mask M1 and the second mask M2 according to exemplary embodiments of the present disclosure, the process time and process cost can be reduced compared to a process that uses four masks because the counter electrode 223 is deposited twice by using one mask M1 (or M2).

[0215] In the display device 1 employing the deposition method described above according to an exemplary embodiment of the present disclosure, the counter electrode formed in the non-display area NDA can be obtained by means of... Figure 12 The connecting wire CM shown is electrically connected to the second power line 170.

[0216] Figure 13A and Figure 13B yes Figure 12 A magnified view of region C. Figure 14 It is along Figure 13A A sectional view taken along line IV-IV'. Figures 13A to 14 Since detailed descriptions of the components have been omitted, it can be assumed that these components are at least similar to their counterparts described elsewhere in this specification.

[0217] Reference Figure 13AThe counter electrode 223 can extend into the non-display area NDA. Since the counter electrode 223 includes a first pair of electrodes 223A, a second pair of electrodes 223B, a third pair of electrodes 223C, and a fourth pair of electrodes 223D, the first pair of electrodes 223A, the second pair of electrodes 223B, the third pair of electrodes 223C, and the fourth pair of electrodes 223D can be arranged in the non-display area NDA.

[0218] The first pair of electrodes 223A and the second pair of electrodes 223B can be arranged in the non-display area NDA outside the first display area DA1. Because the first pair of electrodes 223A and the second pair of electrodes 223B can be stacked and in contact with each other, the same voltage can be applied to the first pair of electrodes 223A and the second pair of electrodes 223B.

[0219] The third pair of electrodes 223C and the fourth pair of electrodes 223D can be arranged in the non-display area NDA outside the second display area DA2, and a transmission area corresponding to the separation space of the third pair of electrodes 223C and the fourth pair of electrodes 223D can be provided. In addition, some of the third pair of electrodes 223C and the fourth pair of electrodes 223D arranged in the non-display area NDA can be arranged in an island shape without being connected to the first pair of electrodes 223A and the second pair of electrodes 223B.

[0220] Near the first display area DA1, the outer patterns 223E1, 223E2, 223E3, and 223E4 arranged along the x-direction in the outermost region can be superimposed and connected to each other. Near the second display area DA2, some of the outer patterns 223E1, 223E2, 223E3, and 223E4 can be superimposed on each other, and some can be spaced apart from each other. Therefore, one side of the counter electrode 223 can have an irregular sawtooth shape. Optionally, in the plan view, one side of the counter electrode 223 may not have a straight shape.

[0221] The counter electrode 223 can be electrically connected to the second power supply line 170 to receive the second power voltage ELVSS. In an exemplary embodiment of this disclosure, a connecting line CM is arranged between the counter electrode 223 and the second power supply line 170. The counter electrode 223 can be electrically connected to the second power supply line 170 via the connecting line CM.

[0222] Reference Figure 14 The thin-film transistor T' can be arranged between the display area DA and the second power line 170, and the thin-film transistor T' is included in the second scan drive circuit 120 (see...). Figure 3 Because the planarization layer 117 and the pixel definition layer 119 are arranged on the thin-film transistor T', the counter electrode 223 can be spaced apart from the thin-film transistor T'.

[0223] The second power line 170 may include the same material as the source or drain electrode of the thin-film transistor T' and is disposed on the same layer as the thin-film transistor T'. A planarization layer 117 is disposed on the second power line 170. The planarization layer 117 may include an opening OP' that exposes a portion of the second power line 170. As shown in FIG13, in a plan view, the opening OP' may include a straight portion formed along one side of the first display region DA1 and / or the second display region DA2. In an exemplary embodiment of the present disclosure, the opening OP' may surround the first display region DA1 along the edge of the first display region DA1. Therefore, the planarization layer 117 may be divided into an inner planarization layer 117a and an outer planarization layer 117b by the opening OP'. In an exemplary embodiment of the present disclosure, the opening OP' may include a plurality of contact holes separated from each other.

[0224] The connecting line CM can be disposed on the planarization layer 117, and the connecting line CM includes connections to the first pixel electrode 221 and / or the second pixel electrode 221' (see...). Figure 7 and / or Figure 8 The same material is used and disposed on the same layer as the first pixel electrode 221 and / or the second pixel electrode 221'. The connecting line CM can contact the second power line 170 through the opening OP'.

[0225] The pixel defining layer 119 can be disposed on the connecting line CM and can include a connecting opening CH that exposes a portion of the connecting line CM. A portion of the counter electrode 223 can be disposed in the connecting opening CH and connected to the connecting line CM.

[0226] The counter electrode 223 may include a first pair of electrodes 223A, a second pair of electrodes 223B, a third pair of electrodes 223C, and a fourth pair of electrodes 223D. There exists a region in which the first pair of electrodes 223A, the second pair of electrodes 223B, the third pair of electrodes 223C, and the fourth pair of electrodes 223D overlap each other. The thickness of the overlapping region may be greater than the thickness of the non-overlapping region.

[0227] The outer pattern 223E arranged in the outermost portion of the counter electrode 223 may at least partially overlap with the second power line 170. Additionally, a portion of the counter electrode 223 may correspond to the opening OP'.

[0228] Despite Figure 13A and Figure 14 The diagram shows the second power line 170 superimposed on the outer pattern 223E arranged in the outermost portion of the counter electrode 223, but the invention is not limited thereto. Figure 13B As shown, the outer pattern 223E arranged in the outermost portion of the counter electrode 223 may overlap only with the connecting line CM and may not overlap with the second power line 170.

[0229] Figure 15 This is a plan view of a display device 1 according to an exemplary embodiment of the present disclosure, showing a portion of the boundary between a first display area DA1 and a second display area DA2. For the purposes of omitting detailed descriptions of the elements, it can be assumed that these elements are at least similar to corresponding elements already described elsewhere in this specification.

[0230] Reference Figure 15 According to an exemplary embodiment of the present disclosure, a display device 1 includes a first display area DA1, a second display area DA2, and a plurality of counter electrodes 224. The second display area DA2 includes a transmissive area TA. The counter electrodes 224 may include a plurality of first counter electrodes 224A, a plurality of second counter electrodes 224B, a plurality of third counter electrodes 224C, and a plurality of fourth counter electrodes 224D. The plurality of first counter electrodes 224A and the plurality of second counter electrodes 224B all correspond to the first display area DA1, and the plurality of third counter electrodes 224C and the plurality of fourth counter electrodes 224D all correspond to the second display area DA2. The shapes of the first counter electrodes 224A and the second counter electrodes 224B are the same, while the shapes of the third counter electrodes 224C and the fourth counter electrodes 224D are different. The counter electrodes 224 may be connected to each other, and the counter electrodes 224 may be thicker at the connection portions.

[0231] Each of the first pair of electrodes 224A and the second pair of electrodes 224B can be arranged to correspond to the same number of pixels. For example, as Figure 15 As shown, each of the first pair of electrodes 224A and the second pair of electrodes 224B can be arranged to correspond to four main pixels Pm. In an exemplary embodiment of this disclosure, each of the first pair of electrodes 224A and the second pair of electrodes 224B can be arranged to correspond to one red pixel R, one blue pixel B, and two green pixels G.

[0232] Each of the third pair of electrodes 224C and the fourth pair of electrodes 224D can be arranged to correspond to a different number of pixels. For example, as Figure 15 As shown, the third pair of electrodes 224C can be arranged to correspond to six auxiliary pixels Pa, and the fourth pair of electrodes 224D can be arranged to correspond to two auxiliary pixels Pa. In an exemplary embodiment of this disclosure, the third pair of electrodes 224C can be arranged to correspond to one red pixel R, two blue pixels B, and three green pixels G. In an exemplary embodiment of this disclosure, the fourth pair of electrodes 224D can be arranged to correspond to one red pixel R and one green pixel G.

[0233] The first pair of electrodes 224A and the second pair of electrodes 224B may include a rhomboid shape with rounded (rounded) edges. The third pair of electrodes 224C may include a rectangular shape with a long side in the b direction. The fourth pair of electrodes 224D may include a rectangular shape with a long side in the a direction.

[0234] In the first display area DA1, a first pair of electrodes 224A and a second pair of electrodes 224B are arranged alternately, and the edges of the first pair of electrodes 224A overlap with the edges of the second pair of electrodes 224B. In the overlapping portion, the thickness of the electrodes 224 can be the sum of the thickness of the first pair of electrodes 224A and the thickness of the second pair of electrodes 224B.

[0235] In the second display area DA2, the third pair of electrodes 224C and the fourth pair of electrodes 224D can be arranged alternately in the a direction. In this case, the edge of the third pair of electrodes 224C can overlap with the edge of the fourth pair of electrodes 224D.

[0236] In the second display area DA2, a transmissive region TA is arranged. The transmissive region TA and pixel group Pg can be arranged alternately, and pixel group Pg includes auxiliary pixels Pa. Pixel group Pg can include eight pixels. Optionally, the auxiliary pixels Pa can at least partially surround the transmissive region TA. The transmissive region TA is the area in which the third pair of electrodes 224C and the fourth pair of electrodes 224D are not arranged, and can represent the area corresponding to the opening 224OP of the electrode 224. In an exemplary embodiment of this disclosure, the transmissive regions TA can be connected to each other in the a direction.

[0237] In the second display area DA2, a plurality of third pairs of electrodes 224C and a plurality of fourth pairs of electrodes 224D may be spaced apart from each other in the a direction and the b direction. For example, the third pairs of electrodes 224C may not overlap each other. In addition, the fourth pairs of electrodes 224D may not overlap each other.

[0238] The first to fourth pairs of electrodes 224A, 224B, 224C, and 224D can be electrically connected to each other. As described above, the first pair of electrodes 224A and the second pair of electrodes 224B can overlap and contact each other through their edges, and the third pair of electrodes 224C and the fourth pair of electrodes 224D can overlap and contact each other through their edges. Furthermore, at the boundary between the first display area DA1 and the second display area DA2, the first to fourth pairs of electrodes 224A, 224B, 224C, and 224D can overlap and contact each other through their edges.

[0239] The first to fourth pairs of electrodes 224A, 224B, 224C, and 224D can be arranged up to the non-display area NDA, and are electrically connected to the second power line 170 in the non-display area NDA (see...). Figure 3 ).

[0240] Figure 16A and Figure 16B It is used to form a basis Figure 15 A diagram showing an example of the mask for the counter electrode 224 in an embodiment. Figure 17A and Figure 17B It shows the use Figure 16A and Figure 16B A diagram illustrating the mask manufacturing method.

[0241] Reference Figure 16A According to an exemplary embodiment of the present disclosure, the first mask M1' includes a first mask opening 610A and a third mask opening 610C with different shapes.

[0242] The edge of the first mask opening 610A may have a rounded rhombus shape (e.g., a rhombus shape with rounded corners). The third mask opening 610C may have a long side in the b direction and an edge with a rounded rectangular shape (e.g., a rectangular shape with rounded corners). The area of ​​the third mask opening 610C may be larger than the area of ​​the first mask opening 610A.

[0243] The first mask openings 610A may be spaced apart from each other in the first region 1A of the first mask M1' and arranged regularly in the x and y directions (e.g., at regular intervals). The third mask openings 610C may be spaced apart from each other in the second region 2A of the first mask M1' and arranged regularly in the x and y directions (e.g., at regular intervals).

[0244] In this case, the distance ccd1 between the centers of adjacent first mask openings 610A in the x direction can be less than the distance ccd3 between the centers of adjacent third mask openings 610C in the x direction.

[0245] Reference Figure 16B The second mask M2' according to an exemplary embodiment of the present disclosure includes a second mask opening 610B and a fourth mask opening 610D with different shapes.

[0246] The edge of the second mask opening 610B can have a rounded rhombus shape (e.g., a rhombus shape with rounded corners). The fourth mask opening 610D can have a rectangular shape with a long side in the a direction. The area of ​​the fourth mask opening 610D can be smaller than the area of ​​the second mask opening 610B.

[0247] The second mask openings 610B can be spaced apart from each other in the first region 1A of the second mask M2' and arranged regularly in the x and y directions (e.g., at regular intervals). The fourth mask openings 610D can be spaced apart from each other in the second region 2A of the second mask M2' and arranged regularly in the x and y directions (e.g., at regular intervals).

[0248] In this case, the distance ccd2 between the centers of adjacent second mask openings 610B in the x direction can be less than the distance ccd4 between the centers of adjacent fourth mask openings 610D in the x direction.

[0249] The shape and / or size of the first mask opening 610A of the first mask M1' and the second mask opening 610B of the second mask M2' can be substantially the same.

[0250] The counter electrode 224 can be formed by a two-step deposition using a first mask M1' and a second mask M2'. Figure 17A and Figure 17B This is a diagram illustrating a method for depositing the counter electrode 224 using a first mask M1' and a second mask M2'.

[0251] Reference Figure 17A A second functional layer 222c is formed on the substrate 100 (see...) Figure 7 Then, a first mask M1' is arranged such that a first mask opening 610A of the first mask M1' corresponds to one red pixel R, one blue pixel B, and two green pixels G arranged in the first display area DA1. Additionally, the first mask M1' is arranged such that a third mask opening 610C of the first mask M1' corresponds to one red pixel R, two blue pixels B, and three green pixels G arranged in the second display area DA2.

[0252] Next, by emitting the deposition material to be formed as the counter electrode from the deposition source, a portion of the counter electrode 224 is initially deposited on the second functional layer 222c. In this case, the first counter electrode 224A and the third counter electrode 224C are formed according to the arrangement of the first mask opening 610A and the third mask opening 610C of the first mask M1'.

[0253] Next, as Figure 17BAs shown, a second pair of electrodes 224B and a fourth pair of electrodes 224D are formed by aligning a second mask M2' on the substrate 100. For example, the second mask M2' is arranged such that the second mask opening 610B of the second mask M2' corresponds to a red pixel R, a blue pixel B, and two green pixels G arranged in the first display area DA1. Additionally, the second mask M2' is arranged such that the fourth mask opening 610D of the second mask M2' corresponds to a red pixel R and a green pixel G arranged in the second display area DA2.

[0254] Next, the remaining portion of the counter electrode 224 is deposited a second time on the second functional layer 222c by emitting the deposition material to be formed as the counter electrode from the deposition source. In this case, the second counter electrode 224B and the fourth counter electrode 224D can be formed according to the arrangement of the second mask opening 610B and the fourth mask opening 610D of the second mask M2'.

[0255] The second pair of electrodes 224B and the fourth pair of electrodes 224D are superimposed on the already deposited first pair of electrodes 224A and the third pair of electrodes 224C through their edges, and are therefore electrically connected to the first pair of electrodes 224A and the third pair of electrodes 224C.

[0256] Because the counter electrode 224 can be formed in the display device 1 through a 2-step deposition process, it can save process cost and process time compared with a 4-step deposition process.

[0257] Because the counter electrode 224 can be formed only in the desired area by depositing the first to fourth pairs of electrodes 224A, 224B, 224C, and 224D respectively, a display device 1 with high reliability can be provided. Furthermore, because the counter electrode 224 is not deposited in the transmissive region TA, excellent light transmittance can be ensured.

[0258] In a display device according to an exemplary embodiment of the present disclosure, pixel portions and transmissive regions therein with increased light transmittance are arranged in a second display region corresponding to components such as sensors, cameras, etc. Therefore, an environment can be provided under which the components can operate, while simultaneously allowing images to be displayed in the region superimposed on the components.

[0259] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to figures, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A display device, the display device comprising: The substrate includes a first display area and a second display area; A transmissive area is disposed within the second display area; Multiple first pairs of electrodes and multiple second pairs of electrodes all correspond to the first display area; as well as Multiple third pairs of electrodes and multiple fourth pairs of electrodes, each corresponding to the second display area and surrounding at least a portion of the transmission area, Wherein, the shape of each of the plurality of first pairs of electrodes is the same as the shape of each of the plurality of third pairs of electrodes, and The distance between the first pair of electrodes is less than the distance between the third pair of electrodes.

2. The display device according to claim 1, wherein, The shape of each of the plurality of second pairs of electrodes is the same as the shape of each of the plurality of fourth pairs of electrodes.

3. The display device according to claim 1, wherein, The area of ​​each of the plurality of third pairs of electrodes is different from the area of ​​each of the plurality of fourth pairs of electrodes.

4. The display device according to claim 1, wherein, Each of the plurality of first to fourth pairs of electrodes corresponds to two pixels of the display device.

5. The display device according to claim 1, wherein, Each of the plurality of first pairs of electrodes has a first quadrilateral shape, the first quadrilateral shape having a long side extending in a first direction, and the first pairs of electrodes that are adjacent to each other in the first direction overlap each other at the edge of the first quadrilateral shape.

6. The display device according to claim 5, wherein, The plurality of first pairs of electrodes are spaced apart from each other by a separation space in a second direction intersecting the first direction, and some of the plurality of second pairs of electrodes are arranged within the separation space.

7. The display device according to claim 1, wherein, Each of the plurality of third pairs of electrodes has a third quadrilateral shape, the third quadrilateral shape having a long side extending in a first direction, and the transmission region is arranged between the third pairs of electrodes that are adjacent to each other in the first direction.

8. The display device according to claim 1, wherein, The plurality of first pairs of electrodes are at least partially overlapped with the plurality of third pairs of electrodes at the boundary between the first display area and the second display area.

9. The display device according to claim 1, wherein, The plurality of second pairs of electrodes are at least partially overlapped with the plurality of fourth pairs of electrodes at the boundary between the first display area and the second display area.

10. The display device according to claim 1, further comprising a region in which two of the plurality of first pairs of electrodes overlap with one of the plurality of second pairs of electrodes.

11. A method of manufacturing a display device, the display device comprising a first display area and a second display area, the second display area comprising a transmissive area, the method comprising: Align the first mask to correspond to a base having a width in the x-direction and a length in the y-direction; A first portion of the electrode is deposited on the substrate using the first mask; After depositing the first portion, the second portion of the counter electrode is deposited by moving the first mask along the diagonal direction of the substrate; Align the second mask to correspond to the substrate; After depositing the second portion, the third portion of the counter electrode is deposited on the substrate using the second mask; as well as After depositing the third portion, the remaining portion of the counter electrode is deposited by moving the second mask along the diagonal direction of the substrate. The first mask includes a first mask opening and a third mask opening, and The first mask opening has the same shape and size as the third mask opening, and the separation distance of the first mask opening is smaller than the separation distance of the third mask opening.

12. The method according to claim 11, further comprising: The first mask is moved along the +x and +y directions to perform the deposition of the second portion; as well as The second mask is moved along the -x direction and the +y direction to perform the deposition of the remaining portion of the counter electrode.

13. The method according to claim 11, wherein, The second mask includes a second mask opening and a fourth mask opening. The second mask opening has the same shape and size as the fourth mask opening, the separation distance of the second mask opening is different from that of the fourth mask opening, and the size of the second mask opening is different from that of the first mask opening.

14. The method according to claim 13, wherein, The first mask opening and the second mask opening have rectangular shapes, the rectangular shapes having a long side in a -45° direction relative to the x direction.

15. A display device, the display device comprising: The substrate includes a first display area, a second display area, and a non-display area, wherein the second display area includes a transmissive area, and the non-display area is disposed outside the first display area and the second display area; The counter electrode corresponds to both the first display area and the second display area; The power cord is located in the non-display area; A planarization layer is disposed on the power line and includes an opening that exposes at least a portion of the power line; and A connecting wire is arranged on the planarization layer and connected to the power line through the opening. Some of the counter electrodes are stacked with the power line. Some of the counter electrodes are in contact with the connecting wire. The separation space is located between some of the outer patterns in the outermost portion of the counter electrode. The electrode assembly includes a plurality of first pairs of electrodes arranged in the first display area and a plurality of third pairs of electrodes arranged in the second display area, wherein the plurality of first pairs of electrodes have the same shape and the same size as the plurality of third pairs of electrodes. The distance between the first pair of electrodes is less than the distance between the third pair of electrodes.

16. The display device according to claim 15, wherein, The opening includes a straight section formed along one side of the first display area.

17. The display device according to claim 15, wherein, The planarization layer is divided into an inner planarization layer and an outer planarization layer by the opening.

18. The display device according to claim 15, wherein, The separation space is not arranged between the external patterns arranged outside the first display area.

19. A display device, the display device comprising: The substrate includes a first display area and a second display area, wherein the second display area includes a transmissive area; Multiple first pairs of electrodes and multiple second pairs of electrodes all correspond to the first display area; as well as Multiple third pairs of electrodes and multiple fourth pairs of electrodes, each corresponding to the second display area and surrounding at least a portion of the transmission area, Wherein, the shape of each of the plurality of first pairs of electrodes is the same as the shape of each of the plurality of second pairs of electrodes. Wherein, the shape of each of the plurality of third pairs of electrodes is different from the shape of each of the plurality of fourth pairs of electrodes, and The distance between the first pair of electrodes is less than the distance between the third pair of electrodes.

20. The display device according to claim 19, wherein, The edges of the plurality of first pairs of electrodes have a rhomboid shape with rounded corners, and The edges of the plurality of third pairs of electrodes have a rectangular shape with rounded corners.

21. The display device according to claim 19, wherein, The size of each of the plurality of third pairs of electrodes is larger than the size of each of the plurality of fourth pairs of electrodes.

22. The display device according to claim 21, wherein, Each of the plurality of third pairs of electrodes corresponds to six pixels of the display device, and each of the plurality of fourth pairs of electrodes corresponds to two pixels of the display device.

23. The display device according to claim 19, wherein, Each of the plurality of first pairs of electrodes corresponds to four pixels of the display device.

24. A display device, the display device comprising: The first display area includes first pixels of a first pixel density; The second display area includes a second pixel with a second pixel density, wherein the second pixel density is less than the first pixel density; as well as The sensor is positioned within the transmission area of ​​the second display area. In this embodiment, the counter electrode of the second pixel at least partially surrounds the transmission region. Wherein, the shape and size of the counter electrode of the second pixel are the same as the shape and size of the counter electrode of the first pixel, and Wherein, the distance between the counter electrodes of the first pixel is less than the distance between the counter electrodes of the second pixel.

25. The display device according to claim 24, wherein, The sensor is configured to emit or receive light or sound.

Images