Switched mode power supply controller and method of operating a switched mode power supply controller

Abstract

Embodiments of a SMPS controller and a method for operating a switch mode power supply (SMPS) controller are described. In embodiments, a SMPS controller includes a gate driver circuit configured to generate a drive signal for a switch of a SMPS and a current sense electrical terminal configured to receive a sense current corresponding to the switch and to conduct a driver discharge current from the gate driver circuit.

Description

Technical Field

[0001] This invention relates to a switch-mode power controller and a method for operating the switch-mode power controller. Background Technology

[0002] Embodiments of the present invention generally relate to circuits and methods, and more specifically, to power controllers and methods for operating power controllers.

[0003] Switch-mode power supplies (SMPS) use switching power stages to convert input voltage and / or current into desired output voltage and / or current. For SMPS controllers with integrated drivers, it is advantageous to provide a ground connection for the integrated driver to isolate driver noise from analog / signal ground. However, if the number of electrical terminals or pins in a packaged SMPS controller integrated circuit (IC) chip is limited, for example for cost reasons, additional ground terminals or pins may not be desirable. Therefore, SMPS controllers with a limited number of electrical terminals or pins are needed, which may have a ground connection to isolate driver noise from analog / signal ground. Summary of the Invention

[0004] An embodiment of an SMPS controller and a method for using the SMPS controller is described. In one embodiment, an SMPS controller includes: a gate driver circuit configured to generate a drive signal for a switch of the SMPS; and a current sensing terminal configured to receive a sensed current corresponding to the switch and to conduct a driver discharge current from the gate driver circuit. Other embodiments are also described.

[0005] In one embodiment, the SMPS controller further includes a current comparator configured to compare the sensed current with a reference current.

[0006] In this embodiment, the gate driver circuit, the current comparator, and the current sensing terminal are electrically connected to an electrical connection point.

[0007] In one embodiment, the current comparator includes an input terminal configured to receive the sensed current, wherein the input terminal of the current comparator, the gate driver circuit, and the current sensing terminal are electrically connected to the electrical connection point.

[0008] In one embodiment, the SMPS controller further includes a current source configured to generate the reference current.

[0009] In one embodiment, the SMPS controller further includes an error amplifier configured to generate an output signal based on the difference between an input voltage corresponding to the output voltage of the SMPS and a reference voltage.

[0010] In one embodiment, the SMPS controller further includes a pulse width modulation (PWM) controller configured to generate a PWM signal in response to the output signal of the error amplifier to control the gate driver circuit.

[0011] In one embodiment, the SMPS controller further includes a voltage source configured to generate the reference voltage.

[0012] In one embodiment, the SMPS controller further includes a second electrical terminal configured to transmit the drive signal to the gate terminal of the switch.

[0013] In one embodiment, the SMPS controller further includes a third electrical terminal configured to receive a power supply voltage for the gate driver circuitry.

[0014] In this embodiment, the SMPS controller is a packaged IC device.

[0015] In one embodiment, the SMPS controller further includes a ground connection terminal, and the driver discharge current from the gate driver circuit is not conducted to electrical ground through the ground connection terminal.

[0016] In one embodiment, an SMPS controller includes: a first gate driver circuit configured to generate a first drive signal for a first switch of the SMPS; a second gate driver circuit configured to generate a second drive signal for a second switch of the SMPS; a current sensing terminal configured to receive sensing currents corresponding to the first switch and the second switch, and to conduct a first driver discharge current and a second driver discharge current from the first gate driver circuit and the second gate driver circuit; and a ground connection terminal, wherein the first driver discharge current and the second driver discharge current are not conducted to electrical ground through the ground connection terminal.

[0017] In one embodiment, the SMPS controller further includes a current comparator configured to compare the sensed current with a reference current, wherein the first gate driver circuit and the second gate driver circuit, the current comparator, and the current sensing terminal are electrically connected to an electrical connection point.

[0018] In one embodiment, the SMPS controller further includes an error amplifier configured to generate an output signal based on the difference between an input voltage corresponding to the output voltage of the SMPS and a reference voltage.

[0019] In one embodiment, the SMPS controller further includes a PWM controller configured to generate a first PWM signal and a second PWM signal in response to the output signal of the error amplifier to control the first gate driver circuit and the second gate driver circuit.

[0020] In one embodiment, the SMPS controller further includes a third electrical terminal configured to transmit the first drive signal to the gate terminal of the first switch; and a fourth electrical terminal configured to transmit the second drive signal to the gate terminal of the second switch.

[0021] In one embodiment, the SMPS controller further includes a fifth electrical terminal configured to receive power supply voltages for the first gate driver circuit and the second gate driver circuit.

[0022] In this embodiment, the SMPS controller is a packaged IC device.

[0023] In one embodiment, a method for operating an SMPS controller involves: generating a drive signal for a switch of the SMPS using a gate driver circuit of the SMPS controller; and conducting a driver discharge current from the gate driver circuit via a current sensing terminal, wherein a sensed current corresponding to the switch is received at the current sensing terminal.

[0024] Other aspects of the invention will become apparent from the following detailed description, illustrated by way of examples of the principles of the invention and taken in conjunction with the accompanying drawings. Attached Figure Description

[0025] Figure 1 This is a schematic block diagram of SMPS according to an embodiment of the present invention.

[0026] Figure 2 Depicting Figure 1 The discharge path of the gate driver circuit of the SMPS controller in the SMPS.

[0027] Figure 3 For corresponding Figure 1 The signal timing diagram of the SMPS is depicted.

[0028] Figure 4 Depicting Figure 1This is embodied in the SMPS controller of a packaged IC device.

[0029] Figure 5 This is a schematic block diagram of an SMPS having an SMPS controller including two gate driver circuits according to an embodiment of the present invention.

[0030] Figure 6 Depicting Figure 5 The SMPS in the circuit, and the two discharge paths of the two gate driver circuits.

[0031] Figure 7 This is a flowchart illustrating a method for operating an SMPS controller according to an embodiment of the present invention.

[0032] Throughout the description, similar reference numerals may be used to identify similar elements. Detailed Implementation

[0033] It will be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the more detailed descriptions of the various embodiments illustrated below are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0034] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments are to be regarded in all respects as illustrative rather than restrictive. Therefore, the scope of the invention is indicated by the appended claims rather than by the specific embodiments described herein. All changes falling within the equivalent meaning and scope of the claims are covered by the claims.

[0035] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable through the invention should be included in or in any single embodiment of the invention. In fact, language relating to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, discussions of features and advantages, as well as similar language throughout this specification, may, but do not necessarily, refer to the same embodiment.

[0036] Furthermore, the features, advantages, and characteristics described in this invention can be combined in one or more embodiments in any suitable manner. Those skilled in the art will recognize that, in view of the description herein, this invention can be practiced without one or more specific features or advantages in a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention can be identified in certain embodiments.

[0037] Throughout this specification, references to "an embodiment," "embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with a specified embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may (but not necessarily) all refer to the same embodiment.

[0038] Figure 1 This is a schematic block diagram of an SMPS 100 according to an embodiment of the present invention. The SMPS converts input power into desired output power (e.g., converts an input voltage level into a stable output voltage level for a load current within an acceptable range). For example, the SMPS delivers power available at its input to a load in a controllable manner. In some embodiments, the input power received at the SMPS is alternating current (AC) power, and the output power is an output voltage, such as direct current (DC) voltage. The SMPS can be used in a variety of applications, such as automotive, communications, industrial, medical, computer, and / or consumer or appliance applications. For example, the SMPS may be included in computing devices such as smartphones, tablets, and laptops. In some embodiments, the flyback converter is a buck-boost converter.

[0039] exist Figure 1 In the depicted embodiments, the SMPS 100 includes: input terminals 102-1, 102-2, bridge rectifier diodes “D1”, “D2”, “D3”, and “D4”, an input capacitor “C1”, an SMPS controller 104, a switch “S1” implemented as, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a resistor “R1”, an inductor “L1”, a diode “D5”, an output capacitor “C2”, and two resistors “R2” and “R3” serving as a voltage divider 106. In some embodiments, the inductor L1 is electrically connected to the drain terminal “D” of the MOSFET switch S1, the SMPS controller is electrically connected to the gate terminal “G” of the MOSFET S1, and the resistor R1 is electrically connected to the source terminal “S” of the MOSFET switch S1. In some embodiments, the SMPS controller is implemented on a substrate, such as a semiconductor wafer or a printed circuit board (PCB). In embodiments, the SMPS controller is packaged as a separate semiconductor integrated circuit (IC) chip. Although the SMPS is in Figure 1 The diagram shows some circuit elements, but in other embodiments, the SMPS may include one or more additional / different circuit elements. For example, although the SMPS is shown in... Figure 1 The diagram shows a MOSFET switch S1, but in other embodiments, the SMPS may include other types of switches.

[0040] exist Figure 1 In the depicted embodiment, the input terminals 102-1 and 102-2 of the SMPS 100 are connected to an AC power supply, which supplies AC power to the input capacitor C1 via bridge rectifier diodes D1, D2, D3, and D4. The received energy is delivered to the output capacitor C2 via inductor L1 and diode D5. The output voltage "Vout" of the SMPS is controlled by two resistors R2 and R3, which act as a voltage divider 106.

[0041] exist Figure 1 In the depicted embodiment, the SMPS controller 104 includes: an error amplifier (AMP) 110, a pulse width modulation (PWM) controller 112, an overcurrent comparator (OCP) 114, a gate driver circuit "drv" 116 configured to generate a drive signal for the MOSFET S1, a voltage source 118 generating a reference voltage "Vref" for the error amplifier 110, and a current source 120 generating a reference current "Iref" for the OCP 114. In some embodiments, the SMPS controller is implemented in a substrate and packaged as a separate semiconductor IC device or chip. Figure 1 In the depicted embodiment, SMPS 100 is a power factor correction (PFC) circuit, and the SMPS controller uses a PWM signal to drive MOSFET S1 via gate driver circuit 116 to generate PFC functionality. However, in other embodiments, the SMPS can be a flyback SMPS, including a transformer or inductor-inductor-capacitor (LLC) resonant converter with an auxiliary winding, a primary winding, and / or a secondary winding.

[0042] exist Figure 1In the depicted embodiment, the input voltage Vsense is generated by a voltage divider 106 formed by resistors R2 and R3 and input to the error amplifier 110 of the SMPS controller 104 via electrical terminal or pin 122. The error amplifier is configured to generate an output signal to the PWM controller 112 based on the voltage difference between the input voltage Vsense and the reference voltage Vref. The PWM controller 112 is configured to generate a PWM signal in response to the output signal of the error amplifier to control the gate driver circuitry. OCP 114 is configured to compare a reference current Iref with a sensed current received from the MOSFET S1 via the current sensing input terminal or pin sense_gnd of the SMPS controller. In some embodiments, the output of OCP is blanked to prevent accidental triggering of the overcurrent protection circuitry. The gate driver circuitry 116 is configured to generate a driver signal applied to the gate terminal of the MOSFET S1 via electrical terminal or pin 124 of the SMPS controller. The gate driver circuitry can operate in response to a supply voltage Vcc received via electrical terminal or pin 126 of the SMPS controller.

[0043] exist Figure 1 In the depicted embodiment, the output voltage Vout of the SMPS 100 is regulated via the input voltage Vsense by the error amplifier 110 of the SMPS controller 104. The output voltage Vout is measured via a resistor divider formed by resistors R2 and R3. The PWM controller 112 uses the error signal from the error amplifier 110 to control the output voltage Vout such that Vout = Vref*(Rs2 + Rs3) / Rs3, where Rs2 represents the resistance of resistor R2 and Rs3 represents the resistance of resistor R3. The output voltage Vout can be greater than the peak value of the AC power input voltage. The ground terminal or pin ic_gnd of the SMPS controller is typically positioned at a distance from the reference ground terminal or pin 150 of the SMPS 100, which may be located on the printed circuit board (PCB) of the SMPS. The IC ground pin ic_gnd can be connected to the reference ground via a PCB trace having a typical inductance of approximately 1 nH / mm. In a typical SMPS PCB layout, the length of this PCB trace can be several centimeters, resulting in parasitic inductances of tens of nanohenries. Figure 1 The middle label is "Lpar1".

[0044] In the SMPS controller of the gate driver circuit 116, the discharge / absorption current flows through the parasitic inductance Lpar1. The di / dt of this current generates a voltage across the parasitic inductance, Lpar1: Unoise = Lpar1 * di / dt. Because switch-mode power supplies typically switch at frequencies of 50kHz or higher, and for higher power, the gate capacitance of MOSFET S1 is large, di / dt can be quite large (e.g., a value of 50A / μsec). For example, if the PCB trace is 2 cm, the parasitic inductance is 20 nH, and di / dt is 50 A / μsec, the resulting voltage is 20 nH * 50 A / μsec. μ sec = 1V. Therefore, in the SMPS controller where the discharge / sink current of the gate driver circuit 116 flows through the parasitic inductance Lparl, the ground voltage at pin ic_gnd may be disturbed by the driver discharge current. Additionally, analog circuitry involving the ground voltage at pin ic_gnd and the reference ground terminal of SMPS 100 or pin 150 is also disturbed by this noise, which may cause timing signal deviations and unexpectedly trigger protection. Furthermore, when the ground voltage at pin ic_gnd is disturbed, the reference voltage Vref is also disturbed, which may cause the SMPS output voltage Vout to be disturbed. To overcome this ground noise when MOSFET S1 is disconnected, an additional power supply ground connection separated from the ground connection via pin ic_gnd can be used to connect the gate driver circuit 116 to ground through the reference ground pin 150 of the SMPS. Therefore, the discharge / sink current of the gate driver circuit 116 does not flow through the IC ground connection, and the ground voltage at pin ic_gnd remains clean / undisturbed. However, the additional power supply ground connection requires an additional pin in the SMPS controller 104. Due to cost considerations (extra pins typically require larger IC packages), the number of IC pins for the SMPS controller 104 needs to be kept as low as possible.

[0045] exist Figure 1 In the depicted embodiment, the current sensing input pin sense_gnd of the SMPS controller 104 is configured to receive the sensed current corresponding to MOSFET S1 and conduct the driver discharge current from the gate driver circuit 116. The ground connection of the gate driver circuit 116 is electrically connected to the current sensing input pin sense_gnd of the SMPS controller 104 at electrical connection point 130. Figure 1As depicted, the positive input terminal 132 of the OCP 114 is configured to receive sensed current, and the positive input terminal of the OCP, the gate driver circuit, and the current sensing input pin sense_gnd are electrically connected to the electrical connection point 130. Therefore, the discharge / sinking current of the gate driver circuit discharges through the current sensing input pin sense_gnd. Consequently, the discharge / sinking current of the gate driver circuit does not conduct through or flow through the pin ic_gnd and the parasitic inductance Lpar1, and the ground voltage at the pin ic_gnd remains clear and unaffected by the discharge / sinking current of the gate driver circuit. Furthermore, because the discharge / sinking current of the gate driver circuit discharges through the current sensing input pin sense_gnd, the gate driver circuit does not require a dedicated ground connection to the reference ground pin 150 of the SMPS. Figure 1 As depicted, there is no direct ground connection from the gate driver circuitry to the SMPS reference ground pin. Furthermore, the SMPS controller 104 has one less pin compared to the SMPS controller in which an additional power ground connection, separated from the ground connection via the ic_gnd pin, is connected to the gate driver circuitry.

[0046] Figure 2 Depicting Figure 1 The discharge path 240 of the gate driver circuit 116 of the SMPS 100 and the SMPS controller 104. Figure 2 As depicted, the discharge path runs from the gate terminal G of MOSFET S1 to the gate driver circuit 116, and then to the source terminal S of MOSFET S1, without passing through the IC ground pin ic_gnd of the SMPS controller. Therefore, the ground voltage at the ic_gnd pin of the SMPS controller remains unaffected by the discharge / absorption current of the gate driver circuit 116.

[0047] Figure 3 It shows the corresponding Figure 1 The signal timing diagram of SMPS 100. Figure 3 The signals shown include: gate voltage V, drain voltage V, current sensing voltage V, IC ground voltage V (ic_gnd) at the IC ground pin ic_gnd of the SMPS controller 104, and sensing ground voltage V (sense_ground) at the current sensing input pin sense_gnd of the SMPS controller. Figure 3In the depicted signal timing diagram, the IC ground voltage V(ic_gnd) at the IC ground pin ic_gnd is undisturbed and substantially equal to the reference ground. The sense ground voltage V(sense_gnd) shows the voltage spike when the gate driver circuit 116 turns off MOSFET S1 due to the parasitic inductance Lpar3 between the current sensing input pin sense_gnd and MOSFET S1. However, this voltage spike does not impair the functionality of the current sensing circuit. Specifically, since the IC ground is undisturbed, the overcurrent protection circuit reference current Iref is undisturbed. Furthermore, the sense ground voltage V(sense_gnd) is not disturbed as long as MOSFET S1 is on. If an overcurrent occurs when MOSFET S1 is on, the PWM controller 112 can turn off MOSFET S1 via the gate driver circuit 116. Noise on at the current sensing input pin sense_gnd only occurs after an overcurrent is detected and MOSFET S1 is turned off. Therefore, this noise on at the current sensing input pin sense_gnd does not affect the proper behavior of OCP 114.

[0048] Figure 4 Depicting Figure 1 This is embodied in the SMPS controller 104 of the packaged IC device 404. For example... Figure 4 As shown, the packaged IC device includes 5 pins / terminals: Vsense (pin 1, connected to error amplifier 110); IC_GND (pin 2, ground); VCC (pin 3, power supply voltage); Drive (pin 4, connected to gate driver circuit 116); and SENSE_GND (pin 5, connected to OCP 114 and gate driver circuit). Figure 4 The packaged IC device described in the text is Figure 1 One possible packaged IC device for the SMPS controller described herein. However, Figure 1 The packaged IC device of the SMPS controller described herein is not limited to Figure 4 The illustrated embodiment. For example, although the pins are... Figure 4 The pins are shown as being located outside the packaged IC device, but in other embodiments, some or all of the pins may be located inside / within the packaged IC device.

[0049] In some embodiments, the SMPS controller 104 integrates more than one gate driver circuit. Figure 5This is a schematic block diagram of an SMPS 500 having an SMPS controller 504 including two gate driver circuits 516-1, 516-2 according to an embodiment of the present invention. The SMPS converts input power into desired output power (e.g., converts the input voltage level into a stable output voltage level within an acceptable range of load current). Figure 5 The SMPS 500 described and Figure 1 The differences between the SMPS100s described are that Figure 5 The SMPS controller 504 of the depicted SMPS 500 includes two gate driver circuits 516-1 and 516-2. Gate driver circuit 516-1 is configured to drive MOSFET S1 electrically connected between inductor L1 and diode D5, while gate driver circuit 516-2 is configured to drive MOSFET S2 electrically connected between inductor L2 and diode D6. Figure 5 In the depicted embodiment, the SMPS 500 is an interleaved power factor correction circuit, wherein the two gate driver circuits 516-1 and 516-2 use the same current sensing input pin sense_gnd for power supply grounding.

[0050] exist Figure 5 In the depicted embodiments, the SMPS 500 includes: input terminals 102-1, 102-2, bridge rectifier diodes D1, D2, D3, and D4, input capacitor C1, SMPS controller 504, two MOSFETs S1 and S2, resistor R1, two inductors L1 and L2, diodes D5 and D6, output capacitor C2, and two resistors R2 and R3 serving as a voltage divider 506. In some embodiments, inductor L1 is connected to the drain terminal D of MOSFET switch S1, the SMPS controller is connected to the gate terminal G of MOSFET switch S1, and resistor R1 is connected to the source terminal S of MOSFET switch S1. In these embodiments, inductor L2 is connected to the drain terminal D of MOSFET switch S2, the SMPS controller is connected to the gate terminal G of MOSFET switch S2, and resistor R1 is connected to the source terminal S of MOSFET switch S2. In some embodiments, the SMPS controller is implemented on a substrate, such as a semiconductor wafer or PCB. In embodiments, the SMPS controller is packaged as a separate semiconductor IC chip. Although SMPS in Figure 5 The diagram shows some circuit elements, but in other embodiments, the SMPS may include one or more additional / different circuit elements. For example, although the SMPS is shown in... Figure 5 The diagram shows MOSFET switches S1 and S2, but in other embodiments, the SMPS may include other types of switches.

[0051] exist Figure 5 In the depicted embodiment, the SMPS controller 504 includes: an error amplifier 510; a PWM controller 512 configured to generate a PWM signal in response to the output signal of the error amplifier to control gate driver circuits 516-1, 516-2; an overcurrent comparator (OCP) 514; gate driver circuits 516-1, 516-2; a voltage source 518 generating a reference voltage “Vref” for the error amplifier 510; and a current source 520 generating a reference current “Iref” for the OCP 514. The error amplifier is configured to generate an output signal to the PWM controller 512 based on the voltage difference between the input voltage Vsense and the reference voltage Vref. The OCP 514 is configured to compare the reference current Iref with a sensed current received from the current sensing input terminal or pin sense_gnd of the SMPS controller. In some embodiments, the output of the OCP is blanked to prevent accidental triggering of overcurrent protection circuitry. Gate driver circuit 516-1 is configured to generate a driver signal applied to the gate terminal G of MOSFET S1 via an electrical terminal or pin 524 of the SMPS controller. Gate driver circuit 516-2 is configured to generate a driver signal applied to the gate terminal G of MOSFET S2 via an electrical terminal or pin 528 of the SMPS controller. The gate driver circuits can operate in response to a power supply voltage Vcc received via an electrical terminal or pin 526 of the SMPS controller. In some embodiments, the SMPS controller is implemented in a substrate and packaged as a separate semiconductor IC device or chip. Figure 5 In the depicted embodiment, the SMPS 500 is an interleaved PFC circuit, and the SMPS controller uses PWM signals to drive MOSFET switches S1 and S2 via gate driver circuits 516-1 and 516-2 to generate PFC functionality. However, in other embodiments, the SMPS can be a flyback SMPS, including a transformer or LLC resonant converter with auxiliary windings, primary windings, and / or secondary windings.

[0052] exist Figure 5 In the depicted embodiment, the output voltage Vout of the SMPS 500 is regulated via the input voltage Vsense by the error amplifier 510 of the SMPS controller 504. The output voltage Vout is measured via a resistor divider formed by resistors R2 and R3. The PWM controller 512 uses the error signal from the error amplifier to control the output voltage Vout such that Vout = Vref*(Rs2 + Rs3) / Rs3, where Rs2 represents the resistance of resistor R2 and Rs3 represents the resistance of resistor R3. The output voltage Vout can be greater than the peak value of the AC power input voltage.

[0053] exist Figure 5 In the depicted embodiment, the ground connection of the gate driver circuits 516-1, 516-2 is electrically connected at electrical connection point 530 to the current sensing input pin sense_gnd of the SMPS controller 504. Figure 5 As depicted, the positive input terminal 532 of the OCP 514 is configured to receive sensed current, and the positive input terminal of the OCP, gate driver circuits 516-1, 516-2, and the current sensing input pin sense_gnd are electrically connected to electrical connection point 530. Therefore, the discharge / absorption current of the gate driver circuits 516-1, 516-2 discharges through the current sensing input pin sense_gnd. Consequently, the discharge / absorption current of the gate driver circuits 516-1, 516-2 is not conducted through or flows through the reference ground terminal or pin ic_gnd and parasitic inductance Lpar1 of the SMPS 500, which are electrically connected to the pin ic_gnd, and the ground voltage at pin ic_gnd remains clear / unaffected by the discharge / absorption current of the gate driver circuits 516-1, 516-2. Additionally, the SMPS controller 504 has one less pin compared to an SMPS controller with an additional power ground connection to the gate driver circuits separated from the ground connection via pin ic_gnd.

[0054] Figure 6 Depicting Figure 5 The SMPS 500 and the two discharge paths 640-1 and 640-2 of the gate driver circuits 516-1 and 516-2 of the SMPS controller 504. Figure 6 As depicted, discharge paths 640-1 and 640-2 run from the gate terminals G of MOSFETs S1 and S2 to the gate driver circuits 516-1 and 516-2, and then to the source terminals S of MOSFETs S1 and S2, without passing through the IC ground pin ic_gnd of the SMPS controller. Therefore, the ground voltage at the ic_gnd pin of the SMPS controller remains unaffected by the discharge / absorption currents of the gate driver circuits 516-1 and 516-2. As is typical in interleaved PFC, gate driver circuits 516-1 and 516-2 are not simultaneously turned off. In addition to leading-edge blanking for each conducting gate driver circuit, the output of the OCP 514 can be blanked for up to 200 nanoseconds (nsec) when one of the gate driver circuits 516-1 and 516-2 is turned off.

[0055] Figure 7This is a flowchart illustrating a method for operating an SMPS controller according to an embodiment of the present invention. In block 702, a drive signal for a switch of the SMPS is generated using the gate driver circuitry of the SMPS controller. In block 704, a driver discharge current is conducted from the gate driver circuitry via a current sensing terminal, at which a sensed current corresponding to the switch is received. The SMPS controller can be coupled with… Figure 1 The SMPS controller 104 and / or described Figure 5 The SMPS controller 504 described is the same as or similar to it.

[0056] Specific details of various embodiments have been provided in the foregoing description. However, some embodiments may be practiced without all of these specific details. In other instances, for the sake of brevity and clarity, certain methods, steps, components, structures, and / or functions are not described in detail except for those methods, steps, components, structures, and / or functions that enable the implementation of the various embodiments of the invention.

[0057] Although the operations of the methods are shown and described herein in a specific order, the order of operations for each method may be changed such that some operations may be performed in reverse order or that some operations may be performed at least partially concurrently with other operations. In another embodiment, instructions or sub-operations of different operations may be implemented in an intermittent and / or alternating manner.

[0058] It should also be noted that at least some of the operations of the methods described herein can be implemented using software instructions stored on a computer-usable storage medium for execution by a computer. As an example, embodiments of a computer program product include a computer-usable storage medium for storing a computer-readable program.

[0059] The computer-usable or computer-readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or apparatus). Examples of non-transitory computer-usable and computer-readable storage media include semiconductor or solid-state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), rigid disks, and optical discs. Current examples of optical discs include high-density disks with read-only memory (CD-ROM), high-density disks with read / write capability (CD-R / W), and digital video optical discs (DVDs).

[0060] Alternatively, embodiments of the present invention can be implemented entirely in hardware or in implementations that include both hardware and software elements. In software-based embodiments, the software may include, but is not limited to, firmware, resident software, microcode, etc.

[0061] While specific embodiments of the invention have been described and illustrated, the invention is not limited to the specific form or arrangement of the portions thus described and illustrated. The scope of the invention will be defined by the appended claims and their equivalents.

Claims

1. A switch-mode power supply (SMPS) controller, characterized in that, The SMPS controller includes: A gate driver circuit configured to generate a drive signal for switching on the SMPS; and A current sensing terminal is configured to receive a sensing current corresponding to the switch and conduct a driver discharge current from the gate driver circuit. A grounding connection terminal, which is different from the current sensing terminal; The driver discharge current from the gate driver circuit is conducted through the current sensing terminal and not through the ground connection terminal to the ground.

2. The SMPS controller according to claim 1, characterized in that, The SMPS controller further includes a current comparator configured to compare the sensed current with a reference current.

3. The SMPS controller according to claim 2, characterized in that, The gate driver circuit, the current comparator, and the current sensing terminal are electrically connected to the electrical connection point.

4. The SMPS controller according to claim 3, characterized in that, The current comparator includes an input terminal configured to receive the sensed current, wherein the input terminal of the current comparator, the gate driver circuit, and the current sensing terminal are electrically connected to the electrical connection point.

5. The SMPS controller according to claim 2, characterized in that, The SMPS controller further includes a current source configured to generate the reference current.

6. The SMPS controller according to claim 1, characterized in that, The SMPS controller further includes an error amplifier configured to generate an output signal based on the difference between an input voltage corresponding to the output voltage of the SMPS and a reference voltage.

7. The SMPS controller according to claim 6, characterized in that, The SMPS controller further includes a pulse width modulation (PWM) controller configured to generate a PWM signal in response to the output signal of the error amplifier to control the gate driver circuit.

8. The SMPS controller according to claim 1, characterized in that, The SMPS controller further includes a second electrical terminal configured to transmit the drive signal to the gate terminal of the switch.

9. A switch-mode power supply (SMPS) controller, characterized in that, The SMPS controller includes: A first gate driver circuit, configured to generate a first drive signal for a first switch of the SMPS; A second gate driver circuit, configured to generate a second drive signal for the second switch of the SMPS; A current sensing terminal, configured to receive sensing currents corresponding to the first switch and the second switch, and to conduct a first driver discharge current and a second driver discharge current from the first gate driver circuit and the second gate driver circuit; and A ground connection terminal, which is different from the current sensing terminal, wherein the first gate driver circuit, the second gate driver circuit, and the current sensing terminal are electrically connected to the same electrical connection point, and The discharge current of the first driver and the discharge current of the second driver are not conducted to the electrical ground through the grounding connection terminal.

10. A method for operating a switch-mode power supply (SMPS) controller, characterized in that, The method includes: The gate driver circuit of the SMPS controller is used to generate drive signals for the switching of the SMPS; and The driver discharge current is conducted from the gate driver circuit through the current sensing terminal, and the sensed current corresponding to the switch is received at the current sensing terminal; and The discharge current of the driver is prevented from being conducted to the electrical ground through the ground connection terminal of the SMPS controller, wherein the ground connection terminal is different from the current sensing terminal.

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