Charge pump converter and control method

Abstract

Embodiments of the present disclosure relate to charge pump converters and control methods. An apparatus comprising: first and second switching devices connected in series between a first node and a second node; first and second voltage blocking devices connected in series between the first node and a third node; a flying capacitor connected between a common node of the first and second switching devices and a common node of the first and second voltage blocking devices; and a controller configured to regulate power loss in the first and second switching devices by controlling a charging process and a discharging process of the flying capacitor.

Description

Technical Field

[0001] This invention relates generally to a charge pump converter and a control method thereon. Background Technology

[0002] Switch-mode power converters are common in many electronic applications, from computers to automobiles. Typically, the voltage within a switch-mode power converter is generated by operating switches coupled to an inductor or transformer. Various conversion topologies can exist. Based on these topology differences, switch-mode power converters can be classified into two categories: isolated power converters and non-isolated power converters.

[0003] In implementing switch-mode circuitry, a gate driver is used to efficiently drive one or more power transistors. The gate driver can be configured to accept a low-power signal from a controller and generate switching signals at appropriate speeds and voltage levels. These voltage levels can be established, for example, using an external power supply, voltage regulator, level shifter, charge pump converter, or any combination thereof, to ensure the power transistors are turned on and off. The power transistors can be insulated-gate bipolar transistors (“IGBTs”) or power metal-oxide-semiconductor field-effect transistors (“MOSFETs”). The gate driver can have a single output for driving a single gate node of the power transistors. Alternatively, the gate driver can have two outputs for driving the high-side power transistor and the low-side power transistor, respectively.

[0004] In a gate driver used to drive a high-voltage-side power transistor, a charge pump converter can be employed to provide bias power for switching the high-side power transistor. More specifically, the charge pump converter is connected between the power supply and the bias input terminal of the gate driver. The charge pump converter is configured to convert the output voltage of the power supply to a higher voltage, which is used to drive the high-side power transistor.

[0005] During operation, power losses may not be evenly distributed among the different switches of a charge pump converter. A simple and reliable control method is desired to distribute power losses evenly among the different switches of the charge pump converter, thereby improving the performance of the charge pump converter. Summary of the Invention

[0006] According to an embodiment, an apparatus includes: a first switching device and a second switching device connected in series between a first node and a second node; a first voltage blocking device and a second voltage blocking device connected in series between a first node and a third node; a flying capacitor connected between a common node of the first switching device and the second switching device and a common node of the first voltage blocking device and the second voltage blocking device; and a controller configured to regulate power loss in the first switching device and the second switching device by controlling the charging and discharging processes of the flying capacitor.

[0007] According to another embodiment, a method includes: configuring a charge pump converter to operate in a charging mode and a discharging mode, wherein in the charging mode a power source is configured to charge a flying capacitor of the charge pump converter, and in the discharging mode the charge pump converter transfers energy from the flying capacitor to a load connected to the charge pump converter; detecting the terminal voltage of the flying capacitor; detecting at least one of an input voltage and an output voltage of the charge pump converter; and applying either the charging mode or the discharging mode to the flying capacitor based on a comparison between the terminal voltage of the flying capacitor and at least one of the input voltage and the output voltage of the charge pump converter.

[0008] According to yet another embodiment, a method includes: configuring a charge pump converter to convert an input voltage from a power source to a higher voltage, wherein the charge pump converter includes: a first switch, a second switch, a third switch, and a fourth switch connected in series between two terminals of the power source; a first voltage blocking device and a second voltage blocking device connected in series between the input terminal and the output terminal of the charge pump converter; and a flying capacitor connected between a common node of the second and third switches and a common node of the first and second voltage blocking devices.

[0009] The method further includes: detecting a first voltage at the common node of the second and third switches, and applying either the charging or discharging process to the flying capacitor based on a comparison between the first voltage at the common node of the second and third switches and the input / output voltage of the charge pump converter.

[0010] The features and technical advantages of this disclosure have been outlined quite extensively above in order to provide a better understanding of the following detailed description of this disclosure. Additional features and advantages of this disclosure that form the subject matter of the claims will be described below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as the basis for modifying or designing other structures or processes for achieving the same purpose as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure as set forth in the appended claims. Attached Figure Description

[0011] To gain a more complete understanding of this disclosure and its advantages, it will now be described with reference to the following description taken in conjunction with the accompanying drawings, wherein:

[0012] Figure 1 A schematic diagram of a charge pump converter according to various embodiments of the present disclosure is shown;

[0013] Figure 2 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram of the charge pump converter is shown.

[0014] Figure 3 The power loss distribution under different control mechanisms according to various embodiments of the present disclosure is illustrated;

[0015] Figure 4 Various embodiments of the present application for control are illustrated. Figure 1 The flowchart shown illustrates the method for a charge pump converter;

[0016] Figure 5 Various embodiments according to this disclosure are shown. Figure 1 A schematic diagram of a first implementation of the feedback circuit of the charge pump converter shown;

[0017] Figure 6 Various embodiments according to this disclosure are shown. Figure 1 A schematic diagram of a second implementation of the feedback circuit of the charge pump converter shown;

[0018] Figure 7 Various embodiments of the present disclosure are illustrated for controlling Figure 1 The flowchart shown illustrates the method for a charge pump converter;

[0019] Figure 8 A schematic diagram of another charge pump converter according to various embodiments of the present disclosure is shown;

[0020] Figure 9 A system diagram of a gate driver according to various embodiments of the present disclosure is shown;

[0021] Figure 10 A schematic diagram of another charge pump converter according to various embodiments of the present disclosure is shown;

[0022] Figure 11 Various embodiments according to this disclosure are shown. Figure 1 Another timing diagram of the charge pump converter is shown;

[0023] Figure 12 A schematic diagram of yet another charge pump converter according to various embodiments of the present disclosure is shown;

[0024] Figure 13 Various embodiments according to this disclosure are shown. Figure 12 The timing diagram of the charge pump converter is shown; and

[0025] Figure 14 A block diagram of a processing system according to various embodiments of the present disclosure is shown.

[0026] Unless otherwise stated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0027] The manufacture and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of particular ways of manufacturing and using this disclosure and do not limit the scope of this disclosure.

[0028] This disclosure will be described in the context of a preferred embodiment, namely a method for controlling power losses in two power switches of a charge pump converter. However, this disclosure can also be applied to various power converters. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0029] Figure 1 A schematic diagram of a charge pump converter according to various embodiments of the present disclosure is shown. The charge pump converter 100 includes a first switch MBP, a second switch MP, a third switch MN, a fourth switch MBN, and a capacitor C. fly First diode D1, second diode D2, and output capacitor C tank The input of the charge pump converter 100 is connected to a power source. In some embodiments, the power source is implemented as a battery. Figure 1 As shown, the battery's output voltage is expressed as V. BAT The input voltage bus of the charge pump converter 100 is connected to the power supply. Output capacitor C tank It is connected between the output voltage bus of the charge pump converter 100 and ground. In some embodiments, the output voltage bus is connected to a load (such as a gate driver). Figure 1 As shown, the voltage on the output voltage bus is represented as V. CP .

[0030] like Figure 1As shown, the first switch MBP, the second switch MP, the third switch MN, and the fourth switch MBN are connected in series between the input voltage bus of the charge pump converter 100 and ground. Throughout the description, the input voltage bus of the charge pump converter 100 and ground can be alternatively referred to as the first node and the second node, respectively. The output voltage bus of the charge pump converter 100 can be alternatively referred to as the third node. Figure 1 As shown, the first node is connected to the positive terminal of the battery. The second node is connected to the negative terminal of the battery.

[0031] like Figure 1 As shown, the common node of the second switch MP and the third switch MN is denoted as CPL. Throughout the description, the voltage at the first node can alternatively be referred to as the first voltage potential. The voltage at CPL can alternatively be referred to as the second voltage potential. The first diode D1 and the second diode D2 are connected in series between the input voltage bus and the output voltage bus of the charge pump converter 100. More specifically, the anode of the first diode D1 is connected to the input voltage bus. The cathode of the first diode D1 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the output voltage bus. The common node of the first diode D1 and the second diode D2 is denoted as CPH. Throughout the description, the first diode D1 and the second diode D2 are alternatively referred to as the first blocking device and the second blocking device, respectively.

[0032] like Figure 1 As shown, capacitor C fly It is connected between CPH and CPL. In some embodiments, capacitor C fly Used as a charge pump capacitor. Charge pump capacitors are often referred to as flying-cross capacitors. Throughout the description, capacitor C... fly It is alternatively referred to as a flying capacitor. In steady-state operation mode, this is achieved by applying either a charging or discharging mode to the flying capacitor C. fly Capable of adjusting flying capacitor C fly The voltage at both ends.

[0033] During operation, when the third switch MN and the fourth switch MBN are turned on, and the first switch MBP and the second switch MP are turned off, the charge pump converter 100 is configured to operate in charging mode. Power from the battery is supplied to the flying capacitor C through a first conductive path formed by the first diode D1, the third switch MN, and the fourth switch MBN. fly Charging. During charging mode, the second diode D2 is reverse biased. The fourth switch MBN acts as a current limiting device and is configured to limit the power loss in the third switch MN. The power loss in the third switch MN during charging mode can be expressed as:

[0034] Plass_MN =V CPL ×I in (1)

[0035] Among them I in It is the current flowing from the battery to the charge pump converter 100, and V CPL It is the voltage at node CPL.

[0036] During operation, when the first switch MBP and the second switch MP are turned on and the third switch MN and the fourth switch MBN are turned off, the charge pump converter 100 is configured to operate in discharge mode. (Battery and flying capacitor C) fly They are combined to provide power to the load through a second conductive path formed by the first switch MBP, the second switch MP, and the second diode D2. During discharge mode, the first diode D1 is reverse biased. The first switch MBP acts as a current limiting device and is configured to limit power loss in the second switch MP. During discharge mode, the power loss in the second switch MP can be expressed as:

[0037] P ioss_MP -(V BAT -V CPL )×I in (2)

[0038] Equations (1) and (2) above show the power loss in the second switch MP and the third switch MN in relation to the voltage (V) at node CPL. CPL This is related to the power loss in the third switch MN. Specifically, the power loss in the third switch MN is related to V. CPL Proportional. On the other hand, the power loss in the second switch MP is proportional to that in V. BAT With V CPL The difference between (V) BAT -V CPL Proportional. To balance the power loss distribution between the second switch MP and the third switch MN, V is proportional during charging and discharging modes. CPL Adjust to a predetermined voltage. In some embodiments, V CPL Adjusted to battery voltage V BAT Approximately half of the voltage.

[0039] According to one embodiment, in Figure 1The switches shown (e.g., switches MBP, MP, MN, and MBN) can be metal-oxide-semiconductor field-effect transistor (MOSFET) devices. Alternatively, the switching element can be any controllable switch, such as an insulated-gate bipolar transistor (IGBT) device, an integrated gate-commutated thyristor (IGCT) device, a gate-turn-off thyristor (GTO) device, a silicon-controlled rectifier (SCR) device, a junction-gate field-effect transistor (JFET) device, a MOS-controlled thyristor (MCT) device, a gallium nitride (GaN)-based power device, a silicon carbide (SiC)-based power device, etc.

[0040] It should be noted that, although Figure 1 The diagram shows switches MBP and MP implemented as p-type transistors, and switches MBN and MN implemented as n-type transistors; however, those skilled in the art will recognize that many variations, modifications, and substitutions are possible. For example, depending on different application and design requirements, switches MBP and MP can be implemented as n-type transistors. Furthermore, Figure 1 Each switch shown can be implemented as multiple switches connected in parallel. Furthermore, a capacitor can be connected in parallel with one switch to implement a zero-voltage switch (ZVS) / zero-current switch (ZCS).

[0041] Figure 1 Controller 102 and comparator 104 are further illustrated. Controller 102 can be implemented as any suitable controller, such as a microprocessor, digital signal processor (DSP), analog controller, or any combination thereof. Controller 102 detects various operating parameters (e.g., input voltage, output voltage, voltage across a flying capacitor, load current, or any combination thereof). Figure 1 As shown, based on the detected operating parameters, the controller 102 determines the gate drive signals GAP and GAN for switches MP and MN. In some embodiments, the first switch MBP and the second switch MP are simultaneously turned on / off. The duty cycle of the gate drive signal of the first switch MBP is the same as the duty cycle of the gate drive signal of the second switch MP. Similarly, the third switch MN and the fourth switch MBN are simultaneously turned on / off. The duty cycle of the gate drive signal of the fourth switch MBN is the same as the duty cycle of the gate drive signal of the third switch MN.

[0042] In some embodiments, the first input of comparator 104 is configured to detect the voltage (V) at the common node of the second switch MP and the third switch MN. CPL The second input of comparator 104 is configured to receive a predetermined reference V. ref The comparison result generated by comparator 104 is fed to controller 102. Controller 102 generates gate drive signals GAP and GAN based on the comparison result and clock signal CLK.

[0043] During operation, the second switch MP and the third switch MN are alternately turned on and off to pump power from the battery to the capacitor C. tank The charge pump converter 100 helps to establish a higher voltage (greater than V) at the output of the charge pump converter 100. BAT The first switch MBP and the fourth switch MBN are used to limit the current flowing through the second switch MP and the third switch MN, respectively. Specifically, the first switch MBP is configured as a first current limiting circuit to control the first current flowing through the second switch MP during the discharge process of the flying capacitor. The fourth switch MBN is configured as a second current limiting circuit to control the second current flowing through the third switch MN during the charging process applied to the flying capacitor.

[0044] In some embodiments, the first switch MBP is configured as a first current source to limit a first current flowing through the second switch MP. Similarly, the fourth switch MBN is configured as a second current source to limit a second current flowing through the third switch MN.

[0045] In some embodiments, the current flowing through the first switch MBP and the fourth switch MBN can be controlled by two current mirrors coupled to the first switch MBP and the fourth switch MBN, respectively. The use of current mirrors to control the current flowing through power switches is well known in the art and will not be discussed further herein.

[0046] The charge pump converter 100 can regulate the voltage V through a control circuit formed by comparator 104 and controller 102. CPL During operation, when the voltage V CPL Less than the predetermined reference V ref At that time, controller 102 turns on the second switch MP and applies the discharge mode to the flying capacitor C. fly As a result of the applied discharge mode, in the flying capacitor C fly The voltage across the terminals decreases, thus increasing the voltage V. CPL On the other hand, when the voltage V CPL Greater than the predetermined reference V ref At that time, controller 102 turns on the third switch MN and applies the charging mode to the flying capacitor C. fly As a result of the applied charging mode, in the flying capacitor C fly The voltage across the terminals increases, thus decreasing the voltage V. CPL .

[0047] Depending on the operating conditions, the charge pump converter 100 can operate in either charging or discharging mode. Through the aforementioned control mechanism, the voltage V... CPL It can be adjusted to approximately equal to V. refThe voltage level. In some embodiments, V ref Equal to battery voltage V BAT Half of it. Throughout the description, this control mechanism (which will V) CPL Adjusting to a predetermined voltage level is alternatively referred to as an adaptive duty cycle control mechanism.

[0048] Figure 2 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram of the charge pump converter is shown. Figure 2 The horizontal axis represents the time interval. There are five vertical axes. The first vertical axis Y1 represents the clock signal CLK fed to the controller 102. The second vertical axis Y2 represents the output voltage V of the charge pump converter 100. CP The third vertical axis Y3 represents the voltage at node CPL. The fourth vertical axis Y4 represents the gate drive signal GAP of the second switch MP. The fifth vertical axis Y5 represents the gate drive signal GAN ​​of the third switch MN.

[0049] Before the first moment t1, the clock signal CLK was not applied to the controller 102. For example... Figure 2 As shown, the output voltage V CP The voltage at node CPL is approximately 48V. The gate drive signal GAP is in a logic high state. Because the second switch MP is a p-type transistor and GAP is in a logic high state, the second switch MP is turned off. The gate drive signal GAN ​​is in a logic low state. Because the third switch MN is an n-type transistor and GAN is in a logic low state, the third switch MN is turned off.

[0050] From time t1 to time t2, the clock signal CLK is applied to controller 102. In response to the clock signal CLK, the gate drive signal GAN ​​is in a logic high state. As a result, the third switch MN (n-type transistor) is turned on. The turn on of the third switch MN provides the power for the flying capacitor C. fly The charging path. For example... Figure 2 As shown, in the flying capacitor C fly After being charged, the voltage at node CPL decreases linearly from t1 to t2. From t1 to t2, the output voltage VCP remains the same.

[0051] Starting from the second moment t2, the controller 102 applies charging and discharging modes alternately to the flying capacitor C. flyFrom time t2 to time t3, the gate drive signal GAP is in a logic low state. As a result, the second switch MP (p-type transistor) is turned on. The gate drive signal GAN ​​is in a logic low state. As a result, the third switch MN (n-type transistor) is turned off. The turning on of the second switch MP provides the power for the flying capacitor C. fly The discharge path. More specifically, the flying capacitor C fly The battery is connected in series to provide power to the output capacitor C via the second diode D2. tank The power. For example... Figure 2 As shown, from t2 to t3, the output voltage V CP Accordingly, the voltage across the flying capacitor decreases during the discharge mode (from t2 to t3). For example... Figure 2 As shown, the voltage at node CPL increases.

[0052] From time t3 to time t4, the gate drive signal GAP is in a logic high state. As a result, the second switch MP (p-type transistor) is turned off. The gate drive signal GAN ​​is in a logic high state. As a result, the third switch MN (n-type transistor) is turned on. The turning on of the third switch MN provides the power for the flying capacitor C. fly The charging path. More specifically, the battery charges the flying capacitor C through the first diode D1, the third switch MN, and the fourth switch MBN. fly Charging. The second diode D2 is reverse biased. (Example:) Figure 2 As shown, from t3 to t4, the output voltage V CP Keep it the same. During the charging mode (from t3 to t4), the flying capacitor C fly The voltage across the terminals increases. For example... Figure 2 As shown, the voltage at node CPL decreases.

[0053] From time t4 to time t5, the discharge mode is applied to the charge pump converter 100 again. The electrical characteristics during t4 to t5 are similar to those during t2 to t3, and therefore will not be discussed here.

[0054] Starting from time t5, charging and discharging modes are applied alternately to the flying capacitor C. fly Output voltage V CP The voltage level reaches approximately 53V. The voltage at the node CPL is approximately 24V. It should be noted that the voltage (24V) mentioned above is only an example. The voltage at the node CPL can vary depending on different applications and design requirements.

[0055] It should be noted that Figure 2The output voltage VCP shown is merely an example. Depending on the application and design requirements, the output voltage VCP can be reduced by controlling the second switch MP and the third switch MN. For example, when the output voltage VCP is above a predetermined voltage threshold, it can be reduced by turning off both the second switch MP and the third switch MN. By applying this control scheme, the output voltage VCP can be regulated to the predetermined voltage threshold.

[0056] Refer again Figure 1 In some embodiments, the input voltage is approximately 48V. The voltage at node CPL can be controlled under different control mechanisms. Under a first control mechanism, the voltage at node CPL is not regulated. Power loss is not uniformly distributed between the second switch MP and the third switch MN. In some embodiments, the power loss in the third switch MN is much greater than the power loss in the second switch MP. Under a second control mechanism, the voltage at node CPL is regulated to approximately 32V. Power loss is not uniformly distributed between the second switch MP and the third switch MN. In some embodiments, the power loss in the third switch MN is greater than the power loss in the second switch MP. Under a third control mechanism, the voltage at node CPL is regulated to approximately 24V. Power loss is substantially uniformly distributed between the second switch MP and the third switch MN. In some embodiments, the power loss in the third switch MN is approximately equal to the power loss in the second switch MP. Reference will be made below. Figure 3 This paper discusses the detailed power loss allocation under different control mechanisms.

[0057] It should be noted that the implementation of MPP and MP as p-type transistors and MN and MBN as n-type transistors in the previous examples is for illustrative purposes only and is not intended to limit the various embodiments of this disclosure to any particular transistor type or configuration. For example, if a negative power supply is used to power the charge pump converter, MPP and MP can be implemented as n-type transistors and MN and MBN can be implemented as p-type transistors.

[0058] Figure 3 The power loss distribution under different control mechanisms according to various embodiments of the present disclosure is illustrated. Figure 3 The horizontal axis represents the time interval. The vertical axis represents the energy loss in the second switch MP and the third switch MN. It should be noted that the energy loss is equal to the power loss in the switches multiplied by the specified time interval.

[0059] Line 301 represents the energy loss in the third switch MN when the voltage at node CPL is not regulated. Line 302 represents the energy loss in the second switch MP when the voltage at node CPL is not regulated. Figure 3As shown, the energy loss in the third switch MN is as high as 3.2 millijoules (mJ). In contrast, the energy loss in the second switch MP is approximately 0.1 mJ.

[0060] Line 303 indicates the energy loss in the third switch MN when the voltage at node CPL is regulated to approximately 32V. Line 304 indicates the energy loss in the second switch MP when the voltage at node CPL is regulated to 32V. For example... Figure 3 As shown, the energy loss in the third switch MN is as high as 2.3 mJ. In contrast, the energy loss in the second switch MP is approximately 0.9 mJ.

[0061] Line 305 (fifth line) indicates the energy loss in the third switch MN when the voltage at node CPL is regulated to 24V. Line 306 (sixth line) indicates the energy loss in the second switch MP when the voltage at node CPL is regulated to 24V. For example... Figure 3 As shown, the energy loss in the third switch MN is as high as 1.7 mJ. In contrast, the energy loss in the second switch MP is approximately 1.5 mJ.

[0062] An advantageous feature of regulating the voltage at node CPL to approximately 24V is that energy loss is evenly distributed between the second switch MP and the third switch MN.

[0063] It should be noted that energy losses in the second switch MP and the third switch MN may not be evenly distributed. For example, in some applications, the die size of the second switch MP can be much larger than that of the third switch MN. Due to its larger die size, the second switch MP can dissipate more heat. Thus, power losses can be unevenly distributed between the second switch MP and the third switch MN.

[0064] Figure 4 Various embodiments of the present application for control are illustrated. Figure 1 The flowchart shows a method for a charge pump converter. Figure 4 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 4 The steps shown.

[0065] Refer again Figure 3 The energy losses in the second switch MP and the third switch MN are not evenly distributed, as shown in lines 301-304. Regulating the voltage at node CPL to a predetermined voltage (e.g., 24V) helps to distribute the energy losses more evenly, thereby improving the reliability of the charge pump converter. Figure 4A control method 400 is shown to regulate the voltage at node CPL to a predetermined voltage in order to achieve a balanced power loss distribution between the second switch MP and the third switch MN.

[0066] Before the control method 400 begins at step 402, the clock signal CLK is fed to Figure 1 In the controller 102 shown, in response to the clock signal, switches MBP, MP, MN, and MBN begin to switch. Figure 2 As shown, the voltage at node CPL responds to the voltage applied to the flying capacitor C. fly The charging and discharging modes vary. Additionally, a first counter (counter_MN) and a second counter (counter_MP) are used to detect whether a fault has occurred in the charge pump converter 100. Initially, both the first and second counters are set to zero. For the first counter, a predetermined maximum number of consecutive MN on-cycles can be selected. This maximum number is equal to T. max_MN (Maximum continuous MN on-time) multiplied by the switching frequency of the clock signal CLK (f clk A predetermined maximum number of consecutive MN on-cycles is used to determine if a fault has occurred. max_MN Given by the following equation:

[0067] T MAX_MN =(V BAT -V ref )×C fly / I MN (3)

[0068] Among them I MN It is the current limit of the third switch MN.

[0069] For the second counter, a predetermined maximum number of consecutive MP on-cycles is used to determine whether a fault has occurred. The predetermined maximum number of consecutive MP on-cycles is equal to 3. During operation, at V... CPL Once the desired voltage level has been reached, the second switch MP is immediately switched on. The duty cycle of the second switch MP is determined by I. MN / (I MN +I MP Confirmed. MN It is the maximum current flowing through the third switch MN. MPThis is the maximum current flowing through the second switch MP. In some embodiments, the duty cycle of the second switch MP is approximately 50%. Due to variations in operating parameters, the duty cycle of the second switch MP can vary to levels exceeding 50%. The maximum duty cycle of the second switch MP is approximately 60%. Thus, the second switch MP cannot be turned on for three consecutive cycles. If the second switch MP is turned on for three consecutive cycles, a fault occurs (e.g., node CPL is short-circuited to ground).

[0070] At step 402, the voltage at node CPL is detected and compared to a predetermined reference. Throughout the description, the predetermined reference may alternatively be referred to as a predetermined threshold. In some embodiments, the predetermined reference is equal to k times the battery voltage, where k is a predetermined parameter. In some embodiments, k equals 0.5. Also at step 402, if the detected voltage (V CPL If the value is greater than the predetermined reference, then method 400 continues to step 404. Otherwise, method 400 continues to step 406.

[0071] At step 404, the consecutive MN on-times are checked. If the consecutive MN on-times are equal to or greater than T... max_MN If the fault is reported and the charge pump converter 100 is shut down, then method 400 continues to step 410, where a fault is reported and the charge pump converter 100 is shut down. Similarly, at step 404, if the continuous MN on-time is less than T... max_MN Then method 400 continues to step 408.

[0072] An advantageous feature of steps 404 and 410 is that a first counter is used to count the continuous charging time of the flying capacitor, and a fault is reported when the continuous charging time of the flying capacitor is detected to be greater than a predetermined maximum charging time.

[0073] At step 408, the third switch MN is turned on. Due to the activation of the third switch MN, a charging mode is applied to the flying capacitor C. fly The voltage at node CPL decreases accordingly. Also at step 408, the first counter (counter_MN) is incremented by 1. The second counter (counter_MP) is reset to zero. After executing step 408, control method 400 returns to step 402.

[0074] At step 406, the consecutive MP on-times are checked. If the consecutive MP on-times are equal to or greater than T... max_MP If the fault is reported and the charge pump converter 100 is shut down, then method 400 continues to step 410, where a fault is reported and the charge pump converter 100 is shut down. Similarly, at step 406, if the continuous MP on-time is less than T... max_MPThen method 400 continues to step 412.

[0075] An advantageous feature of steps 406 and 410 is the use of a second counter to count the continuous discharge time of the flying capacitor and to report a fault when the continuous discharge time of the flying capacitor is detected to be greater than a predetermined maximum discharge time.

[0076] At step 412, the second switch MP is turned on. Due to the turning on of the second switch MP, a discharge mode is applied to the flying capacitor C. fly The voltage at node CPL increases accordingly. Also at step 412, the second counter (counter_MP) is incremented by 1. The first counter (counter_MN) is reset to zero. After executing step 412, control method 400 returns to step 402.

[0077] Figure 5 Various embodiments according to this disclosure are shown. Figure 1 The diagram shows a first implementation of the feedback circuit for the charge pump converter. In addition to two resistive voltage dividers used to detect the battery voltage and the voltage at node CPL, Figure 5 The charge pump converter 500 shown is similar to Figure 1 The charge pump converter 100 is shown.

[0078] like Figure 5 As shown, the first resistor divider includes resistors R1 and R2 connected in series between node CPL and ground. The common node of resistors R1 and R2 is connected to the first input of comparator 104. The second resistor divider includes resistors R3 and R4 connected in series between the input voltage bus of charge pump converter 500 and ground. The common node of resistors R3 and R4 is connected to the second input of comparator 104. The first resistor divider is used to proportionally reduce the voltage at node CPL to a suitable voltage level (V) fed to the first input of comparator 104. CPL_L Voltage V CPL_L It can be represented as:

[0079] V CPL_L =k1×V CPL (4)

[0080] Where k1 is a predetermined parameter. In some embodiments, k1 is equal to 1 / 20.

[0081] A second resistor divider is used to proportionally reduce the voltage on the input voltage bus of the charge pump converter 50 to a suitable voltage level (V) fed to the second input of the comparator 104. BAT_L The voltage VBAT_L can be expressed as:

[0082] V BAT_L =k2×V BAT (5)

[0083] Where k2 is a predetermined parameter. In some embodiments, k2 is equal to 1 / 40.

[0084] It should be noted that Figure 4 The k shown is equal to k2 / k1. In some embodiments, k2 equals 1 / 40 and k1 equals 1 / 20. Therefore, k equals 0.5. Alternatively, other ratios may be used, depending on the specific application and design requirements.

[0085] The detected battery voltage (V) is compared at comparator 104. BAT_L ) and detected CPL voltage (V CPL_L As mentioned above... Figure 4 The comparison results discussed were used to determine which mode (charging mode or discharging mode) should be applied to the flying capacitor C. fly .

[0086] Figure 6 Various embodiments according to this disclosure are shown. Figure 1 The diagram shows a second implementation of the feedback circuit for the charge pump converter. Except that a second resistor divider is connected between the output voltage bus of the charge pump converter 600 and ground, Figure 6 The charge pump converter 600 shown is similar to Figure 5 The charge pump converter 500 is shown. In other words, as referenced above... Figure 4 The output voltage of the charge pump converter 600, as discussed, is used to determine which mode (charging mode or discharging mode) is applied to the flying capacitor C. fly Reference.

[0087] Figure 7 Various embodiments of the present disclosure are illustrated for controlling Figure 1 The flowchart shows a method for a charge pump converter. Figure 7 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 7 The steps shown.

[0088] At step 702, the charge pump converter is configured to operate alternately in charging and discharging modes. During charging mode, the power supply charges the flying capacitor of the charge pump converter. During discharging mode, the energy stored in the flying capacitor is transferred to the load connected to the charge pump converter.

[0089] At step 704, a suitable voltage sensing circuit is configured to detect at least one of the terminal voltage of the flying capacitor and the input and output voltages of the charge pump converter. (See again...) Figure 1 A flying capacitor is connected between the common node of D1 and D2 and node CPL. In some embodiments, the voltage at node CPL and the input voltage of the charge pump converter are detected. In an alternative embodiment, the voltage at node CPL and the output voltage of the charge pump converter are detected.

[0090] At step 706, the detected CPL voltage is compared at a suitable device (such as a comparator) with at least one of the input and output voltages of the charge pump converter. Based on the comparison result, a charging mode or a discharging mode is applied to the flying capacitor.

[0091] Figure 8 A schematic diagram of another charge pump converter according to various embodiments of the present disclosure is shown. Except that the charge pump converter 800 does not include current limiting devices MBP and MBN, the charge pump converter 800 is similar to... Figure 1 The charge pump converter 100 is shown. The charge pump converter 800 operates on a similar principle to the charge pump converter 100, and therefore will not be discussed further here.

[0092] Figure 9 A system diagram of a gate driver according to various embodiments of the present disclosure is shown. Figure 9 As shown, the gate driver 902 includes a charge pump converter 980, a gate drive block 918, a diagnostic block 916, a power management unit (PMU) 914, a logic block 912, and an input / output (I / O) interface 930. The gate driver 902 is configured to generate a gate drive signal applied to the switch Q1.

[0093] like Figure 9 As shown, switch Q1 is connected between the battery and load 940. Switch Q1 functions as a load switch. Figure 9 As shown, switch Q1 is implemented as an n-type MOSFET. The drain of switch Q1 is connected to the positive terminal of the battery. The source of switch Q1 is connected to the load 940. The gate of switch Q1 is connected to the gate drive block 918.

[0094] It should be noted that implementing Q1 as an n-type MOSFET is merely an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art. For example, Q1 can be implemented as an IGBT.

[0095] like Figure 9As shown, the microcontroller 920 is configured to generate multiple control signals based on various operating parameters. These control signals are fed into an I / O interface 930. The I / O interface 930 converts the control signals into appropriate logic signals. These logic signals are then fed into a logic block 912. Based on a predetermined control mechanism, the logic block 912 generates multiple signals to drive the gate driver block 918 and the charge pump converter 980. Furthermore, the logic block 912 exchanges control and protection information with the PMU 914 and the diagnostic block 916.

[0096] Gate driver block 918 includes components connected in series on voltage bus V CP The p-type transistor QP and the n-type transistor QN are connected to the source of switch Q1. The gates of the p-type transistor QP and the n-type transistor QN are controlled by the output signal of logic block 912. It should be noted that under abnormal operating conditions, the outputs of diagnostic block 916 and PMU 914 can affect the operation of gate drive block 918. For example, under short-circuit conditions, diagnostic block 916 and PMU 914 can shut down gate drive block 918 to protect switch Q1.

[0097] Besides the output capacitor C tank Connected to V BAT Between the output of the charge pump converter 980 and the output of the charge pump converter 980, the charge pump converter 980 is similar to Figure 8 The charge pump converter 800 is shown. In other words, it utilizes a reference battery voltage V. BAT Establish output voltage V CP The charge pump converter 980 is configured to provide an output voltage higher than the battery voltage. The output voltage V of the charge pump converter 800 is... CP To provide bias power for the gate drive block 918.

[0098] Figure 9 The bias power of the gate drive block 918 provided by the charge pump converter 980 is shown. This is merely an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art. For example, in this disclosure, the charge pump converter 980 can be any charge pump converter (e.g., Figure 1 The charge pump converter 100 shown is used instead.

[0099] Figure 10 A schematic diagram of yet another charge pump converter according to various embodiments of the present disclosure is shown. Except that diodes D1 and D2 are replaced by switches QD1 and QD2 respectively, the charge pump converter 1000 is similar to... Figure 1 The charge pump converter 100 is shown. (As shown...) Figure 10As shown, both QD1 and QD2 are n-type MOSFETs configured as diodes. The operating principle of charge pump converter 1000 is similar to that of charge pump converter 100, and therefore will not be discussed further here.

[0100] It should be noted that other control mechanisms can be applied to QD1 and QD2. For example, the gates of QD1 and QD2 can be controlled by controller 102 or other suitable control units. In particular, the gates of QD1 and QD2 can be controlled to operate in diode emulation mode. In other words, QD1 and QD2 are controlled to emulate diodes.

[0101] Figure 11 Various embodiments according to this disclosure are shown. Figure 1 Another timing diagram of the charge pump converter is shown. Figure 11 The horizontal axis represents the time interval. There are five vertical axes. The first vertical axis Y1 represents the control signal CLK fed to the controller 102. The second vertical axis Y2 represents the output voltage V of the charge pump converter 100. CP The third vertical axis Y3 represents the voltage at node CPL. The fourth vertical axis Y4 represents the gate drive signal GAP of the second switch MP. The fifth vertical axis Y5 represents the gate drive signal GAN ​​of the third switch MN.

[0102] Before the first moment t1, the clock signal CLK was not applied to the controller 102. For example... Figure 11 As shown, the output voltage V CP The voltage at node CPL is approximately 48V. The gate drive signal GAP is in a logic high state. Because the second switch MP is a p-type transistor and GAP is in a logic high state, the second switch MP is turned off. The gate drive signal GAN ​​is in a logic low state. Because the third switch MN is an n-type transistor and GAN is in a logic low state, the third switch MN is turned off.

[0103] From time t1 to time t2, the clock signal CLK is applied to controller 102. In response to the clock signal CLK, the gate drive signal GAN ​​is in a logic high state. As a result, the third switch MN (n-type transistor) is turned on. The turn on of the third switch MN provides the power for the flying capacitor C. fly The charging path. For example... Figure 2 As shown, in the flying capacitor C fly After being charged, the voltage at node CPL decreases linearly from t1 to t2. From t1 to t2, the output voltage VCP remains the same.

[0104] Starting from the second moment t2, controller 102 applies charging and discharging modes to the flying capacitor C. flyFrom time t2 to time t3, the gate drive signal GAP is in a logic low state. As a result, the second switch MP (p-type transistor) is turned on. The gate drive signal GAN ​​is in a logic low state. As a result, the third switch MN (n-type transistor) is turned off. The turning on of the second switch MP provides the power for the flying capacitor C. fly The discharge path. More specifically, the flying capacitor C fly It is connected in series with the battery to provide power to the output capacitor C via the second diode D2. tank The power. For example... Figure 11 As shown, from t2 to t3, the output voltage V CP Accordingly, the voltage across the flying capacitor decreases during the discharge mode (from t2 to t3). For example... Figure 11 As shown, the voltage on node CPL increases.

[0105] From time t3 to time t4, the gate drive signal GAP is in a logic high state. As a result, the second switch MP (p-type transistor) is turned off. The gate drive signal GAN ​​is in a logic high state. As a result, the third switch MN (n-type transistor) is turned on. The turning on of the third switch MN provides the power for the flying capacitor C. fly The charging path. More specifically, the battery charges the flying capacitor C through the first diode D1, the third switch MN, and the fourth switch MBN. fly Charging. The second diode D2 is reverse biased. (Example:) Figure 11 As shown, from t3 to t4, the output voltage V CP Keep it the same. During the charging mode (from t3 to t4), the flying capacitor C fly The voltage across the terminals increases. For example... Figure 11 As shown, the voltage on node CPL decreases.

[0106] From time t4 to time t5, only the discharge mode is applied to the flying capacitor C. fly In other words, as indicated in the time period from t2 to t4, the discharge and charge modes are not applied to the flying capacitor C in a 50:50 arrangement. fly Specifically, after the voltage at node CPL has reached the desired voltage, the discharge and charge modes are not applied to the flying capacitor C in a 50:50 arrangement. fly For example, such as Figure 11 As shown, the charging mode may not be applied to the flying capacitor C in each clock cycle. fly Depending on design requirements, a discharge mode can be applied to the flying capacitor C during consecutive clock cycles. fly . Figure 11 The timing diagram shown is merely an example. A charging mode is applied to the flying capacitor C.fly The exact number of clock cycles is determined by the feedback loop. Control applies the discharge mode to the flying capacitor C. fly The duration of the time allows the voltage on node CPL to be adjusted to a predetermined level.

[0107] Figure 12 A schematic diagram of yet another charge pump converter according to various embodiments of the present disclosure is shown. In addition to employing a hysteresis control scheme to further improve the performance of the charge pump converter 1200, Figure 12 The charge pump converter 1200 shown is similar to Figure 5 The charge pump converter 500 is shown.

[0108] like Figure 12 As shown, the charge pump converter 1200 includes a first resistive voltage divider and a second resistive voltage divider. The first resistive voltage divider is connected between node CPL and ground, and the second resistive voltage divider is connected to V... BAT Between and ground. The first resistor divider includes resistors R1 and R2 connected in series. The first resistor divider is used to detect the voltage at node CPL. The common node of R1 and R2 is connected to the first input of comparator 104. The second resistor divider includes resistors R3, R4, and R5 connected in series. The second resistor divider is used to generate a first voltage threshold V. BAT_H Second voltage threshold V BAT_L First voltage threshold V BAT_H Greater than the second voltage threshold V BAT_L .

[0109] The charge pump converter 1200 further includes a first control switch S1 and a second control switch S2. A first voltage threshold V BAT_H Second voltage threshold V BAT_L The voltage V is fed to the second input of comparator 104 via the first control switch S1 and the second control switch S2, respectively. In other words, when the first control switch S1 is turned on and the second control switch S2 is turned off, the detected voltage V is fed to the second input of comparator 104. CPL_L With the first voltage threshold V BAT_H A comparison is made, and the comparison result is used to determine the gate drive signals for GAP and GAN. In other words, when the second control switch S2 is turned on and the first control switch S1 is turned off, the detected voltage V will be... CPL_L With the second voltage threshold V BAT_L A comparison was made, and the result was used to determine the gate drive signals for GAP and GAN. The following will refer to... Figure 13 This describes the detailed operating principle of the charge pump converter 1200.

[0110] Figure 13 Various embodiments according to this disclosure are shown. Figure 12 The timing diagram of the charge pump converter is shown. GAP is the gate drive signal for the second switch MP. GAN is the gate drive signal for the third switch MN. The detected voltage V... CPL_L With the first voltage threshold V BAT_H Second voltage threshold V BAT_L A comparison is made. At the first time t1, the detected voltage V... CPL_L Equal to the first voltage threshold V BAT_H The second switch MP is turned off and the third switch MN is turned on. In response to the turning on of the third switch MN, the flying capacitor C... fly The device is charged, and the voltage at node CPL decreases accordingly. From t1 to t2, the detected voltage V... CPL_L It decreases linearly. At the second time t2, the detected voltage V CPL_L Equal to the second voltage threshold V BAT_L The third switch MN is turned off and the second switch MP is turned on. In response to the turning on of the second switch MP, the flying capacitor C... fly The discharge occurs and the voltage at node CPL increases accordingly. From t2 to t3, the detected voltage V... CPL_L It increases in a linear fashion.

[0111] It should be noted that the comparison results (e.g., V) CPL_L With V BAT_H Comparison between or V CPL_L With V BAT_L The duty cycle of the gate drive signal (e.g., GAP and GAN) is determined by comparing the two signals.

[0112] Further attention should be paid to, Figures 12-13 The hysteresis control scheme shown is merely an example. Those skilled in the art will recognize that many alternatives, modifications, and variations exist.

[0113] Figure 14 Block diagrams of processing systems according to various embodiments of the present disclosure are shown. Processing system 1100 depicts a general platform, as well as general components and functions that can be used to implement portions of the charge pump converter of the embodiments and / or external computers or processing devices that interface with the charge pump converter of the embodiments. For example, processing system 1100 can be used to implement... Figure 1 , Figures 5-6 , Figure 8 and Figure 10 The controller 102 shown is a portion thereof. In some embodiments, the processing system 1100 may be used to determine and evaluate the operating parameters of the embodiment, and to determine the gate drive signal of the charge pump converter based on the operating parameters.

[0114] For example, the processing system 1100 may include a central processing unit (CPU) 1102 and a memory 1104 connected to a bus 1108, and may be configured to perform the processes described above. If desired or required, the processing system 1100 may further include: a display adapter 1110 to provide connectivity to a local display 1112; and an input-output (I / O) adapter 1114 to provide input / output interfaces for one or more input / output devices 1116 (such as a mouse, keyboard, flash drive, etc.).

[0115] Processing system 1100 may also include a network interface 1118, which may be implemented using a network adapter configured to couple to a wired link (such as a network cable, USB interface, etc.) and / or a wireless / cellular link for communicating with network 1120. Network interface 1118 may also include suitable receivers and transmitters for wireless communication. It should be noted that processing system 1100 may include other components. For example, if implemented externally, processing system 1100 may include hardware components such as power supplies, cables, motherboards, removable storage media, housings, etc. Although not shown, these other components are considered part of processing system 1100. In some embodiments, processing system 1100 may be implemented on a single monolithic semiconductor integrated circuit and / or on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0116] Embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire specification and claims herein.

[0117] Example 1. An apparatus comprising: a first switching device and a second switching device connected in series between a first node and a second node; a first voltage blocking device and a second voltage blocking device connected in series between a first node and a third node; a flying capacitor connected between a common node of the first switching device and the second switching device and a common node of the first voltage blocking device and the second voltage blocking device; and a controller configured to adjust power losses in the first switching device and the second switching device by controlling the charging and discharging process of the flying capacitor.

[0118] Example 2. The apparatus according to Example 1 further includes: a first current limiting device connected between the first node and the first switching device; and a second current limiting device connected between the second switching device and the second node, wherein the first current limiting device and the first switching device are p-type transistors, the second switching device and the second current limiting device are n-type transistors, and the first voltage blocking device and the second voltage blocking device are diodes.

[0119] Example 3. The apparatus according to Example 1 further includes: a first current limiting device connected between the first node and the first switching device; and a second current limiting device connected between the second switching device and the second node, wherein the first current limiting device and the first switching device are p-type transistors, the second switching device and the second current limiting device are n-type transistors, and the first voltage blocking device and the second voltage blocking device are transistors.

[0120] Example 4. An apparatus according to any one of Examples 1 to 3, wherein the controller is configured to detect a first voltage potential at a common node of the first switching device and the second switching device and a second voltage potential at the first node, and to apply either a charging process or a discharging process to the flying capacitor based on a comparison between the first voltage potential and the second voltage potential.

[0121] Example 5. An apparatus according to any one of Examples 1 to 4, wherein the controller is configured to detect a first voltage potential at a common node of the first and second switching devices via a first resistive voltage divider, and to detect a second voltage potential via a second resistive voltage divider.

[0122] Example 6. An apparatus according to any one of Examples 1 to 4, wherein a comparison between a first voltage potential and a second voltage potential is performed by a comparator.

[0123] Example 7. An apparatus according to any one of Examples 1 to 3, wherein the controller is configured to detect a first voltage potential at a common node of the first switching device and the second switching device and a third voltage potential at a third node, and to apply a charging or discharging process to the flying capacitor based on a comparison between the first voltage potential and the third voltage potential.

[0124] Example 8. An apparatus according to any one of Examples 1 to 7, wherein the controller is configured to detect a first voltage potential at a common node of the first switching device and the second switching device, and to apply a discharge mode to the flying capacitor in successive cycles to regulate the first voltage potential at the common node of the first switching device and the second switching device.

[0125] Example 9. A method comprising: configuring a charge pump converter to operate in a charging mode, wherein a power source is configured to charge a flying capacitor of the charge pump converter, and to operate in a discharging mode to transfer energy from the flying capacitor to a load connected to the charge pump converter; detecting a terminal voltage of the flying capacitor; detecting at least one of an input voltage and an output voltage of the charge pump converter; and applying a charging mode or a discharging mode to the flying capacitor based on a comparison between the terminal voltage of the flying capacitor and at least one of the input voltage and the output voltage of the charge pump converter.

[0126] Example 10. According to the method of Example 9, the charge pump converter includes: a first switch, a second switch, a third switch and a fourth switch, connected in series between two terminals of a power supply; a first voltage blocking device and a second voltage blocking device, connected in series between the input terminal and the output terminal of the charge pump converter; and a flying capacitor, connected between the common node of the second and third switches and the common node of the first and second voltage blocking devices.

[0127] Example 11. The method according to Example 9 further includes: configuring a first switch as a first current source to limit a first current flowing through a second switch, and configuring a fourth switch as a second current source to limit a second current flowing through a third switch.

[0128] Example 12. The method according to any one of Examples 9 to 13 further includes: adjusting the output voltage of the charge pump converter by dissipating power losses in the second and third switches.

[0129] Example 13. The method according to any one of Examples 9 to 13 further includes: dynamically adjusting the voltage at the common node of the second and third switches by continuously applying a charging mode or a discharging mode to the flying capacitor.

[0130] Example 14. The method according to any one of Examples 9 to 13 further includes: detecting the voltage at the common node of the second switch and the third switch and the input voltage of the charge pump converter; charging the flying capacitor when the voltage at the common node of the second switch and the third switch is detected to be greater than a predetermined threshold; and discharging the flying capacitor when the predetermined threshold is detected to be greater than the voltage at the common node of the second switch and the third switch.

[0131] Example 15. A method comprising: configuring a charge pump converter to convert an input voltage from a power source to a higher voltage, wherein the charge pump converter includes: a first switch, a second switch, a third switch, and a fourth switch connected in series between two terminals of the power source; a first voltage blocking device and a second voltage blocking device connected in series between an input terminal and an output terminal of the charge pump converter; and a flying capacitor connected between a common node of the second and third switches and a common node of the first and second voltage blocking devices; detecting a first voltage at the common node of the second and third switches; and applying a charging or discharging process to the flying capacitor based on a comparison between the first voltage at the common node of the second and third switches and an input / output voltage of the charge pump converter.

[0132] Example 16. The method according to Example 15 further includes: applying a charging process to a flying capacitor when it is detected that the ratio of a first voltage at the common node of the second and third switches to the input voltage of the charge pump converter is greater than a predetermined threshold; and applying a discharging process to the flying capacitor when it is detected that the ratio of the first voltage at the common node of the second and third switches to the input voltage of the charge pump converter is less than a threshold voltage.

[0133] Example 17. The method according to any one of Example 15 or Example 16 further includes: configuring a first counter to count the consecutive charging time of the flying capacitor, and reporting a first fault when it is detected that the consecutive charging time of the flying capacitor is greater than a predetermined maximum charging time.

[0134] Example 18. The method according to any one of Example 15 or Example 16 further includes: configuring a second counter to count the continuous discharge time of the flying capacitor, and reporting a second fault when it is detected that the continuous discharge time of the flying capacitor is greater than a predetermined maximum discharge time.

[0135] Example 19. The method according to any one of Examples 15 to 18 further includes: applying a charging process to a flying capacitor when it is detected that the ratio of a first voltage at the common node of the second and third switches to the output voltage of the charge pump converter is greater than a predetermined threshold; and applying a discharging process to the flying capacitor when it is detected that the ratio of the first voltage at the common node of the second and third switches to the output voltage of the charge pump converter is less than a predetermined threshold.

[0136] Example 20. The method according to any one of Examples 15 to 19 further includes: configuring a first switch as a first current limiting circuit to control a first current flowing through a second switch during a discharge process applied to a flying capacitor; and configuring a fourth switch as a second current limiting circuit to control a second current flowing through a third switch during a charging process applied to a flying capacitor.

[0137] Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0138] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. As will be readily understood by those skilled in the art from the disclosure of this publication, processes, machines, manufactures, compositions of matter, means, methods, or steps that are currently existing or to be developed in the future can be utilized to perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. An electronic device comprising: The first switching device and the second switching device are connected in series between the first node and the second node; The first voltage blocking device and the second voltage blocking device are connected in series between the first node and the third node; A flying capacitor is connected between the common node of the first switching device and the second switching device and the common node of the first voltage blocking device and the second voltage blocking device; as well as The controller is configured to control a third voltage potential on the third node by switching the first switching device and the second switching device, and to adjust the power loss in the first switching device and the second switching device by adjusting the duty cycle of the first switching device and the second switching device to adjust the first voltage potential on the common node of the first switching device and the second switching device to a predetermined voltage.

2. The electronic device according to claim 1, further comprising: A first current limiting device is connected between the first node and the first switching device; as well as A second current limiting device is connected between the second switching device and the second node, wherein: The first current limiting device and the first switching device are p-type transistors; The second switching device and the second current limiting device are n-type transistors; and The first voltage blocking device and the second voltage blocking device are diodes.

3. The electronic device according to claim 1, further comprising: A first current limiting device is connected between the first node and the first switching device; as well as A second current limiting device is connected between the second switching device and the second node, wherein: The first current limiting device and the first switching device are p-type transistors; The second switching device and the second current limiting device are n-type transistors; and The first voltage blocking device and the second voltage blocking device are transistors.

4. The electronic device according to claim 1, wherein: The controller is configured to detect a first voltage potential at the common node of the first and second switching devices, and a second voltage potential at the first node, and to apply either a charging or discharging process to the flying capacitor based on a comparison between the first and second voltage potentials.

5. The electronic device according to claim 4, wherein: The controller is configured to detect the first voltage potential at the common node of the first switching device and the second switching device via a first resistor divider, and to detect the second voltage potential via a second resistor divider.

6. The electronic device according to claim 4, wherein: The comparison between the first voltage potential and the second voltage potential is performed by a comparator.

7. The electronic device according to claim 1, wherein: The controller is configured to detect the first voltage potential at the common node of the first and second switching devices, and the third voltage potential at the third node, and to apply either a charging or discharging process to the flying capacitor based on a comparison between the first voltage potential and the third voltage potential.

8. The electronic device according to claim 1, wherein: The controller is configured to detect the first voltage potential at the common node of the first switching device and the second switching device, and to apply a discharge process to the flying capacitor in consecutive cycles to regulate the first voltage potential at the common node of the first switching device and the second switching device.

9. A method for controlling an electronic device, comprising: The charge pump converter is configured to operate in a charging mode, wherein a power source is configured to charge the flying capacitor of the charge pump converter, and to operate in a discharging mode to transfer energy from the flying capacitor to a load connected to the charge pump converter. Detect the terminal voltage of the flying capacitor; Detect at least one of the input voltage and output voltage of the charge pump converter; as well as The charging mode or the discharging mode is applied to the flying capacitor based on a comparison between the terminal voltage of the flying capacitor and at least one of the input voltage and output voltage of the charge pump converter.

10. The method of claim 9, wherein the charge pump converter comprises: The first switch, the second switch, the third switch, and the fourth switch are connected in series between the two terminals of the power supply. A first voltage blocking device and a second voltage blocking device are connected in series between the input and output terminals of the charge pump converter; and The flying capacitor is connected between the common node of the second switch and the third switch and the common node of the first voltage blocking device and the second voltage blocking device.

11. The method of claim 10, further comprising: Configure the first switch as a first current source to limit the first current flowing through the second switch; as well as The fourth switch is configured as a second current source to limit the second current flowing through the third switch.

12. The method of claim 10, further comprising: The output voltage of the charge pump converter is adjusted by dissipating power losses in the second and third switches.

13. The method of claim 10, further comprising: The voltage at the common node of the second and third switches is dynamically adjusted by continuously applying either the charging mode or the discharging mode to the flying capacitor.

14. The method of claim 13, further comprising: The voltage at the common node of the second switch and the third switch, and the input voltage of the charge pump converter are detected; When the voltage at the common node of the second switch and the third switch is detected to be greater than a predetermined threshold, the flying capacitor is charged; as well as The flying capacitor is discharged when the predetermined threshold is detected to be greater than the voltage at the common node of the second and third switches.

15. A method for controlling an electronic device, comprising: Configure a charge pump converter to convert an input voltage from a power source to a higher voltage, wherein the charge pump converter includes: The first switch, the second switch, the third switch, and the fourth switch are connected in series between the two terminals of the power supply. A first voltage blocking device and a second voltage blocking device are connected in series between the input and output terminals of the charge pump converter; and A flying capacitor is connected between the common node of the second switch and the third switch and the common node of the first voltage blocking device and the second voltage blocking device; Detecting a first voltage at the common node of the second switch and the third switch; and The charging or discharging process is applied to the flying capacitor based on a comparison between the first voltage at the common node of the second and third switches and the input / output voltage of the charge pump converter.

16. The method of claim 15, further comprising: When the ratio of the first voltage at the common node of the second and third switches to the input voltage of the charge pump converter is detected to be greater than a predetermined threshold, the charging process is applied to the flying capacitor. as well as When the ratio of the first voltage at the common node of the second and third switches to the input voltage of the charge pump converter is less than the predetermined threshold, the discharge process is applied to the flying capacitor.

17. The method of claim 16, further comprising: Configure a first counter to count the continuous charging time of the flying capacitor; as well as A first fault is reported when the continuous charging time of the flying capacitor is detected to be greater than a predetermined maximum charging time.

18. The method of claim 16, further comprising: Configure a second counter to count the continuous discharge time of the flying capacitor; as well as A second fault is reported when the continuous discharge time of the flying capacitor is detected to be greater than the predetermined maximum discharge time.

19. The method of claim 15, further comprising: When the ratio of the first voltage at the common node of the second switch and the third switch to the output voltage of the charge pump converter is detected to be greater than a predetermined threshold, the charging process is applied to the flying capacitor. as well as When the ratio of the first voltage at the common node of the second and third switches to the output voltage of the charge pump converter is less than the predetermined threshold, the discharge process is applied to the flying capacitor.

20. The method of claim 15, further comprising: The first switch is configured as a first current limiting circuit to control the first current flowing through the second switch during the discharge process applied to the flying capacitor; as well as The fourth switch is configured as a second current limiting circuit to control the second current flowing through the third switch during the charging process applied to the flying capacitor.

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