Display device and method of manufacturing the same

Abstract

A method for manufacturing a display device includes: forming a first substrate on a support substrate; forming a first barrier layer on the first substrate; and forming a conductive layer by implanting n-type or p-type impurities into at least a portion of the first substrate and the first barrier layer. The display device includes a conductive layer disposed on the substrate and a first barrier layer disposed on the conductive layer. When the first barrier layer is doped with an n-type impurity, the conductive layer is also doped with an n-type impurity, and when the first barrier layer is doped with a p-type impurity, the conductive layer is also doped with a p-type impurity.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0043605, filed on April 9, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the same, and to a display device and a method of manufacturing the same with improved reliability. Background Technology

[0004] Recently, the applications of display devices have diversified. As display devices have become increasingly thinner and lighter, their range of uses has gradually expanded. Among display devices, portable, thin, flat, flexible displays have attracted much attention. Flexible displays are typically lightweight and shock-resistant, and can be folded or rolled up for storage purposes. Therefore, flexible displays offer excellent portability.

[0005] However, when a substrate comprising a polymer resin is used in a display device according to the related technology, the polymer resin exhibits polarization, and an afterimage can be observed.

[0006] It should be understood that this background section is partly intended to provide a useful context for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not known or understood by a person skilled in the art prior to the relevant valid application date of the subject matter disclosed herein. Summary of the Invention

[0007] One or more embodiments include a display device and a method of manufacturing the same, in which a conductive layer is disposed between a substrate comprising a polymer resin and a barrier layer, thereby preventing the observation of afterimages and simultaneously improving reliability. However, it should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to limit this disclosure.

[0008] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0009] According to one or more embodiments, the display device may include a first substrate; a conductive layer disposed on the first substrate and doped with n-type impurities or p-type impurities; and a first barrier layer disposed on the conductive layer and doped with n-type impurities or p-type impurities, wherein when the first barrier layer is doped with n-type impurities, the conductive layer may be doped with n-type impurities, and when the first barrier layer is doped with p-type impurities, the conductive layer may be doped with p-type impurities.

[0010] n-type impurities may include, for example, phosphorus.

[0011] p-type impurities may include, for example, boron.

[0012] The first barrier layer may have a distance of approximately [missing information] from the top surface of the conductive layer. to approximately The first thickness within the range.

[0013] The first barrier layer may include amorphous silicon.

[0014] The display device may further include: a second substrate disposed below the first substrate; and a second barrier layer disposed between the second substrate and the first substrate.

[0015] The first substrate and the second substrate may be made of the same material.

[0016] The display device may further include: a pixel circuit disposed above a first substrate and including a thin-film transistor and a storage capacitor; and an organic light-emitting diode electrically connected to the pixel circuit.

[0017] The display device may further include a third barrier layer disposed on the first barrier layer.

[0018] The first barrier layer may have a second thickness from the top surface of the conductive layer, and the third barrier layer may have a third thickness from the top surface of the first barrier layer, the third thickness being greater than the second thickness.

[0019] The second thickness can be approximately to approximately Within the range, and the third thickness can be approximately to approximately Within the range.

[0020] According to one or more embodiments, a method of manufacturing a display device may include: forming a first substrate on a support substrate; forming a first barrier layer on the first substrate; and forming a conductive layer by implanting n-type or p-type impurities into at least a portion of the first substrate and the first barrier layer.

[0021] The formation of the conductive layer may include doping at least a portion of the first substrate with an n-type impurity or a p-type impurity.

[0022] The doping of at least a portion of the first substrate may include: when the first barrier layer is doped with an n-type impurity, doping at least a portion of the first substrate with an n-type impurity, and when the first barrier layer is doped with a p-type impurity, doping at least a portion of the first substrate with a p-type impurity.

[0023] The formation of the conductive layer may include implanting n-type or p-type impurities into at least a portion of the first substrate and the first barrier layer by means of ion implantation or plasma treatment.

[0024] The formation of the conductive layer may include implanting n-type or p-type impurities into at least a portion of the first substrate and the first barrier layer under an accelerating voltage in the range of about 70 keV to about 80 keV.

[0025] The method may further include: after the formation of the conductive layer, heat-treating the first barrier layer and the conductive layer.

[0026] The formation of the first barrier layer may include: forming a layer extending from the top surface of the first substrate at approximately [missing information]. to approximately The first barrier layer of the first thickness within the range.

[0027] The method may further include: forming a second substrate on the support substrate prior to the formation of a first substrate on the support substrate; and forming a second barrier layer on the second substrate.

[0028] The method may further include forming a third barrier layer on the first barrier layer after the formation of the conductive layer.

[0029] The formation of the first barrier layer may include: forming a layer extending from the top surface of the first substrate at approximately [missing information]. to approximately The first barrier layer with a second thickness within the range.

[0030] The formation of the third barrier layer may include: forming a layer extending from the top surface of the first barrier layer at approximately... to approximately The third barrier layer with a third thickness within the range.

[0031] The formation of the conductive layer may include: doping at least a portion of the first substrate with n-type or p-type impurities, and implanting n-type or p-type impurities into at least a portion of the first substrate and the first barrier layer at an accelerating voltage of about 30 keV or less.

[0032] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments, the accompanying drawings, and the claims. Attached Figure Description

[0033] The above and other aspects, features and advantages of embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0034] Figure 1 This is a perspective view of a display device according to an embodiment;

[0035] Figure 2 This is a plan view of the display device according to the embodiment;

[0036] Figure 3 and Figure 4 This is an equivalent circuit diagram of pixels that may be included in a display device according to an embodiment;

[0037] Figure 5 This is a schematic cross-sectional view of a display device according to an embodiment;

[0038] Figure 6 This is a schematic cross-sectional view of a display device according to an embodiment;

[0039] Figure 7 This is a schematic cross-sectional view of a display device according to an embodiment;

[0040] Figures 8 to 11B This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment; and

[0041] Figures 12A to 12C This is a schematic cross-sectional view used to explain the method of manufacturing a display device according to an embodiment. Detailed Implementation

[0042] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals throughout refer to the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below with reference to the drawings only to explain various aspects of the description.

[0043] As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0044] The terms “and” and “or” can be used in a connecting or separating sense and are to be understood as equivalent to “and / or”. In the specification and claims, the phrase “at least one” is intended to include the meaning of “at least one selected from the group consisting of” for purposes of its meaning and interpretation. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0045] Because this disclosure allows for various modifications and numerous implementations, the embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure and the methods of carrying it out will become apparent and more readily understood from the following description of the embodiments and the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be implemented in various forms.

[0046] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various components, these components should not be limited by these terms. These components are used only to distinguish one component from another.

[0047] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] It will be further understood that the terms “comprises” and / or “comprising”, “have” and / or “having”, “includes” and / or “including” as used herein indicate the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0049] When a layer, film, region, substrate, area, or element is referred to as being "on" another layer, film, region, substrate, area, or element, it may be directly on the other layer, film, region, substrate, area, or element, or there may be intermediate layers, films, regions, substrates, areas, or elements between them. Conversely, when a layer, film, region, substrate, or area, element is referred to as being "directly" on another layer, film, region, substrate, area, or element, there may be no intermediate layers, films, regions, substrates, areas, or elements between them. Furthermore, when a layer, film, region, substrate, or area, element is referred to as being "below" another layer, film, region, substrate, or area, element, it may be directly below the other layer, film, region, substrate, or area, element, or there may be intermediate layers, films, regions, substrates, areas, or elements between them. Conversely, when a layer, film, region, substrate, or area, element is referred to as being "directly" below another layer, film, region, substrate, area, or element, there may be no intermediate layers, films, regions, substrates, areas, or elements between them. In addition, "above" or "on" can refer to being above or below an object, and does not necessarily mean a direction based on gravity.

[0050] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” or “up,” etc., may be used herein to describe the relationship between one element or component and another element or component as illustrated in the accompanying drawings. It will be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the drawings. For example, in the case where the device illustrated in the drawings is flipped, a device located “below” or “under” another device may be placed “above” another device. Therefore, the illustrative term “below” may include both lower and upper positions. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0051] For ease of explanation, the dimensions of the components in the accompanying drawings may be enlarged or reduced. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are arbitrarily depicted for ease of explanation, the following embodiments are not limited thereto.

[0052] In the specification, "A and / or B" means A or B, or A and B. In the specification, "at least one of A and B" means A or B, or A and B.

[0053] As used in this article, when wiring is referred to as “extending in a first or second direction”, it means that the wiring extends not only in a straight line in the first or second direction, but also in a zigzag or curved shape.

[0054] As used herein, "in a plan view" means viewing an object from above, and "in a schematic cross-sectional view" means viewing a vertical cross-section of an object from the side. As used herein, "overlap" includes overlapping both "in a plan view" and "in a schematic cross-sectional view".

[0055] Additionally, the term "overlap" means that the first object may be above, below, or to the side of the second object, and vice versa. Furthermore, the term "overlap" may include layering, stacking, facing, extending above, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The term "facing" means that the first element may be directly or indirectly opposite the second element. In the case where a third element is located between the first and second elements, the first and second elements may be understood as being indirectly opposite each other, although still facing each other. When an element is described as "not overlapping" with another element, this may include the elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0056] It will be understood that when a layer, area, or component is referred to as "connected" or "linked" to another layer, area, or component, it may be "directly connected" or "directly linked" to another layer, area, or component, and / or may be "indirectly connected" or "indirectly linked" to another layer, area, or component, with other layers, areas, or components inserted between them. For example, it will be understood that when a layer, area, or component is referred to as "electrically connected" to another layer, area, or component, it may be "directly electrically connected" to another layer, area, or component, and / or may be "indirectly electrically connected" to another layer, area, or component, with other layers, areas, or components inserted between them.

[0057] Furthermore, when a component is referred to as being "in contact" or "in contact" with another component, the component may be in "electrical contact" or "physical contact" with the other component; or in "indirect contact" or "direct contact" with the other component.

[0058] As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation from the particular value, determined by a person skilled in the art taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%.

[0059] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0060] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Furthermore, it will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0061] In the following description, embodiments are described in detail with reference to the accompanying drawings. When described with reference to the drawings, the same reference numerals denote the same or corresponding elements.

[0062] Figure 1 This is a perspective view of the display device 1 according to the embodiment.

[0063] refer to Figure 1 The display device 1 may include a display area DA and a non-display area NDA, with the non-display area NDA located outside the display area DA. The non-display area NDA may surround or be adjacent to the display area DA. The display device 1 can display an image by using light emitted from pixels P arranged or disposed in the display area DA. The non-display area NDA may be an area on which no image is displayed.

[0064] In the following description, although the organic light-emitting display device is described as display device 1 as an example, the display device 1 according to the embodiments is not limited thereto. In the embodiments, the display device 1 according to the embodiments may include inorganic light-emitting display devices and quantum dot light-emitting display devices. For example, the emitting layer of the display element of the display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0065] Despite Figure 1 The illustration shows that the display device 1 may include a flat display surface, but the embodiments are not limited thereto. In some embodiments, the display device 1 may include a three-dimensional display surface or a curved display surface.

[0066] Where the display device 1 may include a three-dimensional display surface, the display device 1 may include display areas indicating different directions, for example, it may include a generally polygonal columnar display surface. In embodiments where the display device 1 may include a curved display surface, the display device 1 may be implemented as various types, such as flexible, foldable, and rollable display devices.

[0067] Figure 1 A display device 1 suitable for a mobile terminal is shown. Although not shown, electronic modules, camera modules, or power modules, etc., mounted or disposed on the motherboard, can be arranged together with the display device 1 or disposed in a bracket / housing to construct or form a mobile terminal. As an example, the display device 1 according to the embodiment is applicable not only to large electronic devices such as televisions and monitors, but also to small and medium-sized electronic devices such as desktop personal computers, vehicle navigation devices, game consoles, and smartwatches.

[0068] although Figure 1 The illustration shows a case where the display area DA of the display device 1 is approximately quadrilateral; however, the shape of the display area DA is not limited to this and can be circular, elliptical, or polygonal (such as triangular or pentagonal).

[0069] Figure 2 This is a plan view of the display device 1 according to the embodiment.

[0070] refer to Figure 2 The display device 1 may include pixels P arranged or disposed in the display area DA. Each pixel P may include a display element, such as an organic light-emitting diode (OLED). Each pixel P may emit, for example, red, green, blue, or white light via the OLED. In the specification, as described above, pixel P may be understood as a pixel that emits red, green, blue, or white light.

[0071] Each pixel P can be electrically connected to external circuitry arranged or disposed in the non-display area NDA. The first scan drive circuit 110, the first transmit drive circuit 115, the second scan drive circuit 120, the terminal 140, the data drive circuit 150, the first power line 160, and the second power line 170 can be arranged or disposed in the non-display area NDA.

[0072] The first scan driving circuit 110 provides a scan signal to each pixel P via the scan line SL. The first transmit driving circuit 115 provides a transmit control signal to each pixel P via the transmit control line EL. The second scan driving circuit 120 may be arranged or disposed parallel to the first scan driving circuit 110, with a display area DA between them. Some or a predetermined number of pixels P arranged or disposed in the display area DA may be electrically connected to the first scan driving circuit 110, and the remaining pixels P may be electrically connected to the second scan driving circuit 120. In an embodiment, the second scan driving circuit 120 may be omitted.

[0073] The first transmission drive circuit 115 may be spaced apart from the first scan drive circuit 110 in the x-direction and arranged or disposed in the non-display area NDA. The first transmission drive circuit 115 may be arranged or disposed alternately with the first scan drive circuit 110 in the y-direction.

[0074] Terminal 140 may be arranged or disposed on one side or one side of the second substrate 100. Terminal 140 may be exposed without being covered or overlapped by an insulating layer and electrically connected to a printed circuit board (PCB). Terminal PCB-P of the printed circuit board (PCB) may be electrically connected to terminal 140 of the display device 1. The printed circuit board (PCB) may transmit signals or power from a controller (not shown) to the display device 1. Control signals generated by the controller may be transmitted via the printed circuit board (PCB) to the first scan drive circuit 110, the first transmit drive circuit 115, and the second scan drive circuit 120. The controller may provide a first power supply voltage ELVDD (see [reference]) to the first power supply line 160 and the second power supply line 170 via the first connection line 161 and the second connection line 171, respectively. Figure 3 ) and the second power supply voltage ELVSS (see Figure 3 The first power supply voltage ELVDD can be provided to pixel P through the drive voltage line PL electrically connected to the first power supply line 160, and the second power supply voltage ELVSS can be provided to the opposite electrode of pixel P electrically connected to the second power supply line 170.

[0075] The data driving circuit 150 can be electrically connected to the data line DL. The data signal of the data driving circuit 150 can be provided to each pixel P through the connection line 151 and the data line DL, the connection line 151 being electrically connected to the terminal 140, and the data line DL being electrically connected to the connection line 151.

[0076] Despite Figure 2 The diagram shows that the data driving circuit 150 can be arranged or disposed on a printed circuit board (PCB), but in an embodiment, the data driving circuit 150 can be arranged or disposed on a second substrate 100. For example, the data driving circuit 150 can be arranged or disposed between terminal 140 and the first power line 160.

[0077] The first power line 160 may include a first sub-line 162 and a second sub-line 163, which extend parallel to each other in the x-direction and have a display area DA between them. The second power line 170 may have a ring shape (having an open side or one open side) and may partially surround or be adjacent to the display area DA.

[0078] Figure 3 and Figure 4 This is an equivalent circuit diagram of pixels that may be included in the display device 1 according to the embodiment.

[0079] refer to Figure 3 The pixel circuit PC can be electrically connected to an organic light-emitting diode (OLED) to implement light emission from the pixel. The pixel circuit PC may include a driving thin-film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 can be electrically connected to the scan line SL and the data line DL, and can transmit the data signal Dm input from the data line DL to the driving TFT T1 based on the scan signal Sn input from the scan line SL.

[0080] The storage capacitor Cst can be electrically connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store the voltage corresponding to the difference between the voltage delivered from the switching thin-film transistor T2 and the first power supply voltage ELVDD supplied to the drive voltage line PL.

[0081] The driving thin-film transistor T1 can be electrically connected between the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) in response to the voltage stored in the storage capacitor Cst. The OLED can emit light with a predetermined brightness by using the driving current.

[0082] although Figure 3 The illustration describes a scenario where the pixel circuit PC may include two thin-film transistors and a storage capacitor, but the implementation is not limited to this.

[0083] refer to Figure 4 The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, a second initialization thin-film transistor T7, and a storage capacitor Cst.

[0084] Despite Figure 4The diagram shows that each pixel circuit PC may include signal lines SL, SL-1, SL+1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL; however, the implementation is not limited thereto. In an implementation, at least one of the signal lines SL, SL-1, SL+1, EL, and DL, and / or the initialization voltage line VL, may be shared by adjacent pixel circuits.

[0085] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. The driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin-film transistor T2, and can supply driving current to the OLED.

[0086] The gate electrode of the switching thin-film transistor T2 can be electrically connected to the scan line SL, and the source electrode of the switching thin-film transistor T2 can be electrically connected to the data line DL. The drain electrode of the switching thin-film transistor T2 can be electrically connected to the source electrode of the driving thin-film transistor T1, and can simultaneously be electrically connected to the driving voltage line PL by operating the control thin-film transistor T5.

[0087] The switching thin-film transistor T2 can be turned on in response to the scan signal Sn transmitted through the scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode of the driving thin-film transistor T1.

[0088] The gate electrode of the compensation thin-film transistor T3 can be electrically connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 can be electrically connected to the drain electrode of the driving thin-film transistor T1, and can also be electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be simultaneously electrically connected to one of the electrodes of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 can be turned on in response to the scan signal Sn transmitted via the scan line SL, and the driving thin-film transistor T1 can be diode-connected by electrically connecting its gate electrode to its drain electrode.

[0089] The gate electrode of the first initialization thin-film transistor T4 can be electrically connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be electrically connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be simultaneously electrically connected to one of the electrodes of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and the initialization operation of the gate electrode of the driving thin-film transistor T1 can be performed by transmitting the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1.

[0090] The gate electrode of the operating control thin-film transistor T5 can be electrically connected to the emitter control line EL. The source electrode of the operating control thin-film transistor T5 can be electrically connected to the drive voltage line PL. The drain electrode of the operating control thin-film transistor T5 can be electrically connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0091] The gate electrode of the emission control thin-film transistor T6 can be electrically connected to the emission control line EL. The source electrode of the emission control thin-film transistor T6 can be electrically connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emission control thin-film transistor T6 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The operation control thin-film transistor T5 and the emission control thin-film transistor T6 can be simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL, the first power supply voltage ELVDD can be transmitted to the OLED, and the driving current can flow through the OLED.

[0092] The gate electrode of the second initialization thin-film transistor T7 can be electrically connected to the next scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The drain electrode of the second initialization thin-film transistor T7 can be electrically connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on in response to the next scan signal Sn+1 transmitted through the next scan line SL+1 to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0093] Despite Figure 4 The diagram shows that the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be electrically connected to the previous scan line SL-1 and the next scan line SL+1, respectively, but the implementation is not limited to this. In the embodiment, both the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be electrically connected to the previous scan line SL-1 and are therefore driven in response to the previous scan signal Sn-1.

[0094] The other electrode of the storage capacitor Cst can be electrically connected to the drive voltage line PL. The other electrode of the storage capacitor Cst can also be electrically connected simultaneously to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0095] The opposite electrode (e.g., the cathode) of an organic light-emitting diode (OLED) can receive a second power supply voltage, ELVSS. An OLED can emit light by receiving a driving current from a driving thin-film transistor T1.

[0096] Pixel circuit PC is not limited to reference Figure 4 The number of thin-film transistors, the number of storage capacitors, and the circuit design described are subject to various changes without departing from the spirit and scope of this disclosure.

[0097] Figure 5 This is a schematic cross-sectional view of the display device 1 according to an embodiment. For example, Figure 5 It is according to the implementation method along Figure 1 A schematic cross-sectional view of a portion of display device 1 taken by line I-I'.

[0098] refer to Figure 5 The display element may be arranged or disposed above the first substrate 102. The display element may include thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs).

[0099] The first substrate 102 may include a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The first substrate 102 including the polymer resin may be flexible, rollable, or bendable. For example, the first substrate 102 may include polyimide.

[0100] A first barrier layer 103 may be disposed or formed above a first substrate 102. The first barrier layer 103 may be disposed or formed above the first substrate 102 and doped with n-type or p-type impurities. In an embodiment, the first barrier layer 103 may be doped with n-type or p-type impurities by ion implantation or plasma treatment. n-type impurities may include, for example, phosphorus, and p-type impurities may include, for example, boron.

[0101] The first barrier layer 103 may include inorganic materials (such as oxides or nitrides), organic materials, or organic / inorganic composite materials, and may have a single-layer structure or a multi-layer structure comprising inorganic and organic materials. For example, the first barrier layer 103 may include amorphous silicon.

[0102] The conductive layer 104 may be disposed or located between the first substrate 102 and the first barrier layer 103. The conductive layer 104 may be disposed or located between the first substrate 102 and the first barrier layer 103 and may be doped with n-type or p-type impurities. The conductive layer 104 may also be disposed directly on the first substrate 102.

[0103] In this embodiment, the conductive layer 104 may be doped with n-type or p-type impurities by means of ion implantation or plasma treatment. n-type impurities may include, for example, phosphorus, and p-type impurities may include, for example, boron.

[0104] The conductive layer 104 may be a portion formed by doping at least a portion of the first substrate 102. As an example, the conductive layer 104 may be a portion formed by doping at least a portion of the first substrate 102 and the first barrier layer 103 after the first barrier layer 103 may be formed on the first substrate 102. Therefore, if the first barrier layer 103 is doped with an n-type impurity, the conductive layer 104 may also be doped with an n-type impurity, and if the first barrier layer 103 is doped with a p-type impurity, the conductive layer 104 may also be doped with a p-type impurity. For example, the first barrier layer 103 and the conductive layer 104 may be doped with the same or similar impurities.

[0105] The first barrier layer 103 may have a first thickness t1 extending from the top surface of the conductive layer 104, and may be disposed or disposed on the conductive layer 104. In an embodiment, the first thickness t1 may be approximately [missing information]. to approximately Within the range.

[0106] The second substrate 100 may be disposed or located below the first substrate 102. The second barrier layer 101 may be disposed or located between the first substrate 102 and the second substrate 100. In one embodiment, the second substrate 100 may comprise a material that is the same as or similar to the material of the first substrate 102. In another embodiment, the second substrate 100 may comprise a material that is different from the material of the first substrate 102.

[0107] The second barrier layer 101 may be disposed or formed on the second substrate 100. The second barrier layer 101 may comprise inorganic materials (such as oxides or nitrides), organic materials, or organic / inorganic composite materials, and may have a single-layer or multi-layer structure comprising both inorganic and organic materials. In some embodiments, the second barrier layer 101 may comprise a material that is the same as or similar to the material of the first barrier layer 103. In other embodiments, the second barrier layer 101 may comprise a material that is different from the material of the first barrier layer 103.

[0108] A buffer layer 107 may be disposed or provided on the first barrier layer 103. The buffer layer 107 may be disposed or provided above the first substrate 102 and the second substrate 100 to reduce or block foreign matter, moisture, or external air or other impurities from below the first substrate 102 and the second substrate 100, and to provide a flat surface on the first substrate 102 and the second substrate 100. The buffer layer 107 may include inorganic materials (such as oxides or nitrides), organic materials, or organic / inorganic composite materials, and may have a single-layer structure or a multi-layer structure comprising inorganic and organic materials.

[0109] The thin-film transistor (TFT) can be disposed or located on the buffer layer 107. The TFT may include a semiconductor layer 134, a gate electrode 136, and a connection electrode, wherein the gate electrode 136 overlaps with the semiconductor layer 134, and the connection electrode is electrically connected to the semiconductor layer 134. The TFT can be electrically connected to an organic light-emitting diode (OLED) to drive the OLED.

[0110] Semiconductor layer 134 may include a channel region 131, a source region 132, and a drain region 133. Channel region 131 is disposed on or on buffer layer 107 and overlaps with gate electrode 136. Source region 132 and drain region 133 are located on opposite sides of channel region 131 and are doped with impurities having a higher concentration than the impurities in channel region 131. Here, the impurities may include n-type or p-type impurities. Source region 132 and drain region 133 may be electrically connected to a connection electrode.

[0111] Semiconductor layer 134 may comprise oxide semiconductors and / or silicon semiconductors. Where semiconductor layer 134 may comprise oxide semiconductors, it may comprise, for example, an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, semiconductor layer 134 may comprise ITZO (InSnZnO) and IGZO (InGaZnO). Where semiconductor layer 134 may comprise silicon semiconductors, it may comprise amorphous silicon (a-Si) or low-temperature polycrystalline silicon (LTPS).

[0112] The first insulating layer 109 may be disposed or disposed on the semiconductor layer 134. The first insulating layer 109 may include silicon oxide (SiO2) or silicon nitride (SiN). x The first insulating layer 109 may comprise at least one inorganic insulating material selected from silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0113] The gate electrode 136 may be disposed or disposed on the first insulating layer 109. The gate electrode 136 may comprise a single layer or multiple layers, which may comprise at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode 136 may be electrically connected to a gate line to which an electrical signal can be applied.

[0114] The second insulating layer 111 may be disposed on or located on the gate electrode 136. The second insulating layer 111 may include silicon oxide (SiO2) or silicon nitride (SiN). x The second insulating layer 111 may comprise at least one inorganic insulating material selected from silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0115] The storage capacitor Cst may be disposed or disposed on the first insulating layer 109. The storage capacitor Cst may include a bottom electrode 144 and a top electrode 146, the top electrode 146 overlapping the bottom electrode 144. The bottom electrode 144 may overlap the top electrode 146 of the storage capacitor Cst, with a second insulating layer 111 between them.

[0116] The bottom electrode 144 of the storage capacitor Cst may overlap with the gate electrode 136 of the thin-film transistor TFT, and is provided as an integral part of the gate electrode 136 of the thin-film transistor TFT.

[0117] The top electrode 146 of the storage capacitor Cst may comprise a single layer or multiple layers comprising at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0118] The third insulating layer 113 may be disposed or disposed on the top electrode 146 of the storage capacitor Cst. The third insulating layer 113 may include silicon oxide (SiO2) or silicon nitride (SiN). x The third insulating layer 113 may comprise a single layer or multiple layers containing the aforementioned inorganic insulating materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0119] The source electrode 137 and drain electrode 138 may be disposed or disposed on the third insulating layer 113, and the source electrode 137 and drain electrode 138 are connection electrodes. The source electrode 137 and drain electrode 138 may include a conductive material comprising Mo, Al, Cu and / or Ti, and may include a single layer or multiple layers comprising the above materials. The source electrode 137 and drain electrode 138 may have a Ti / Al / Ti multilayer structure.

[0120] A first planarization layer 117 may be disposed or disposed on the source electrode 137 and the drain electrode 138. The first planarization layer 117 may comprise a single layer or multiple layers containing organic or inorganic materials. In embodiments, the first planarization layer 117 may comprise a general polymer (such as benzocyclobutene (BCB), polyimide (PI), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof. The first planarization layer 117 may comprise silicon oxide (SiO2), silicon nitride (SiN2), etc. x The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). After forming the first planarization layer 117, chemical mechanical polishing can be performed to provide a flat top surface.

[0121] The contact metal CM may be disposed or set on the first planarization layer 117. The contact metal CM may include at least one of Al, Cu, and Ti, and may include a single layer or multiple layers. The contact metal CM may have a Ti / Al / Ti multilayer structure.

[0122] A second planarization layer 119 may be disposed or formed on the contact metal CM. The second planarization layer 119 may comprise a single layer or multiple layers containing organic or inorganic materials. In one embodiment, the second planarization layer 119 may comprise a material that is the same as or similar to the material of the first planarization layer 117. In another embodiment, the second planarization layer 119 may comprise a material different from the material of the first planarization layer 117. After forming the second planarization layer 119, chemical mechanical polishing may be performed to provide a flat top surface. In another embodiment, the second planarization layer 119 may be omitted.

[0123] An organic light-emitting diode (OLED) can be disposed or disposed on a second planarization layer 119. The OLED includes a pixel electrode 210, an intermediate layer 220, and a counter electrode 230. The pixel electrode 210 can be electrically connected to a contact metal CM through contact holes passing through the second planarization layer 119. The contact metal CM can be electrically connected to a source electrode 137 or a drain electrode 138 (which can be a connection electrode of a thin-film transistor TFT) through contact holes passing through a first planarization layer 117. Therefore, the OLED can be electrically connected to a thin-film transistor TFT.

[0124] Pixel electrode 210 may be disposed or disposed on the second planarization layer 119. Pixel electrode 210 may include a (semi-)transparent electrode or a reflective electrode. Pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer. The reflective layer includes at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and compounds thereof. The transparent or semi-transparent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). Pixel electrode 210 may have an ITO / Ag / ITO stacked structure.

[0125] The pixel defining layer 180 may be disposed or formed on the second planarization layer 119 and may include an opening that exposes at least a portion of the pixel electrode 210 of the organic light-emitting diode (OLED). The area exposed by the opening of the pixel defining layer 180 may be defined as an emission region EA. The area surrounding the emission region EA may be a non-emission region NEA. The non-emission region NEA may surround or be adjacent to the emission region EA. For example, the display region DA may include the emission region EA and the non-emission region NEA surrounding or adjacent to the emission region EA. The pixel defining layer 180 may prevent, for example, arcing at the edge of the pixel electrode 210 by increasing the distance between the pixel electrode 210 and the opposing electrode 230 above the pixel electrode 210. The pixel defining layer 180 may include an organic insulating material comprising, for example, polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO, and phenolic resin, and may be formed, for example, by spin coating within the spirit and scope of this disclosure.

[0126] Intermediate layer 220 may be disposed or located on a portion of pixel electrode 210 that may be exposed by pixel defining layer 180. Intermediate layer 220 may include emission layer 220b, and may include a first functional layer 220a and a second functional layer 220c below or on emission layer 220b.

[0127] In one embodiment, the intermediate layer 220 may be arranged or disposed on the portion of the pixel electrode 210 that is exposed to the pixel defining layer 180. As an example, the emitting layer 220b of the intermediate layer 220 may be arranged or disposed on the portion of the pixel electrode 210 that is exposed to the pixel defining layer 180.

[0128] The first functional layer 220a may be arranged or disposed below or beneath the emission layer 220b, and the second functional layer 220c may be arranged or disposed on the emission layer 220b. The first functional layer 220a and the second functional layer 220c arranged or disposed below or beneath or on the emission layer 220b may be collectively referred to as organic functional layers.

[0129] Although not shown, the first functional layer 220a may include a hole injection layer (HIL) and / or a hole transport layer (HTL). Although not shown, the second functional layer 220c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0130] The emitting layer 220b may include organic materials, including fluorescent or phosphorescent materials that emit red, green, blue, or white light. The emitting layer 220b may include low molecular weight organic materials or polymeric organic materials.

[0131] In cases where the emitter layer 220b may comprise a low molecular weight organic material, the emitter layer 220b may have a structure in which the hole injection layer (HIL), hole transport layer (HTL), emitter layer (EML), electron transport layer (ETL), and electron injection layer (EIL) may be stacked, for example, in a single or composite configuration. The emitter layer 220b may comprise various organic materials as low molecular weight organic materials, such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), and tri-8-hydroxyquinoline aluminum (Alq3). These layers may be formed by vacuum deposition.

[0132] Where the emitter layer 220b may comprise a polymeric organic material, the intermediate layer 220 may have a structure that typically includes a hole transport layer and the emitter layer 220b. In this case, the hole transport layer may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the emitter layer 220b may comprise a polymeric organic material, such as polyphenylenevinyl chloride (PPV) or polyfluorene. For example, within the spirit and scope of this disclosure, the emitter layer 220b may be formed using screen printing, inkjet printing, or laser-induced thermal imaging (LITI).

[0133] The opposing electrode 230 may be arranged or disposed on the intermediate layer 220. The opposing electrode 230 may be arranged or disposed on the intermediate layer 220 and may completely cover or overlap the intermediate layer 220. The opposing electrode 230 may be arranged or disposed above the display area DA and may completely cover or overlap the display area DA. For example, the opposing electrode 230 may be formed integrally by using an open mask to cover or overlap the pixels P arranged or disposed in the display area DA over the entire display area DA.

[0134] The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 230 may include a layer on the (semi-)transparent layer comprising the above-described material, the layer comprising ITO, IZO, ZnO, or In2O3.

[0135] In one embodiment, the organic light-emitting diode (OLED) may be covered or overlapped by a thin-film encapsulation layer. The thin-film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In another embodiment, the OLED may be covered or overlapped by an encapsulation substrate.

[0136] Figure 6 This is a schematic cross-sectional view of the display device 1 according to the embodiment. Figure 6 Implementation methods and Figure 5 The difference in the implementation may be that the bottom electrode 144 may be provided as a separate element from the gate electrode 136. The differences will be mainly described below. Other configurations may be similar to those described in the above embodiments.

[0137] refer to Figure 6 The display device 1 according to the embodiment may include a storage capacitor Cst. The storage capacitor Cst may not overlap with the thin-film transistor TFT.

[0138] The storage capacitor Cst may include a bottom electrode 144 and a top electrode 146 above the bottom electrode 144. Unlike the embodiments described above, the bottom electrode 144 of the storage capacitor Cst may not overlap with the gate electrode 136 of the thin-film transistor TFT, and may be arranged as a separate independent element or disposed on the first insulating layer 109.

[0139] Figure 7 This is a schematic cross-sectional view of the display device 1 according to the embodiment. Figure 7 Implementation methods and Figure 5The implementation may differ in the thickness of the first barrier layer 103, and the third barrier layer 105 may be arranged or disposed on the first barrier layer 103. The differences are described below. Other configurations may be the same as or similar to those of the embodiments described above.

[0140] refer to Figure 7 The first barrier layer 103 may be arranged or disposed above the first substrate 102, the third barrier layer 105 may be arranged or disposed on the first barrier layer 103, and the conductive layer 104 may be arranged or disposed between the first substrate 102 and the first barrier layer 103.

[0141] The first barrier layer 103 may be disposed or disposed above the first substrate 102. The first barrier layer 103 may be disposed or disposed above the first substrate 102 and doped with n-type impurities or p-type impurities. In an embodiment, the first barrier layer 103 may be doped with n-type impurities or p-type impurities by using ion implantation or plasma treatment.

[0142] The conductive layer 104 may be disposed or located between the first substrate 102 and the first barrier layer 103. The conductive layer 104 may be disposed or located between the first substrate 102 and the first barrier layer 103, and may be doped with n-type or p-type impurities. The conductive layer 104 may also be disposed directly on the first substrate 102.

[0143] The conductive layer 104 may be formed by doping at least a portion of the first substrate 102. As an example, the conductive layer 104 may be formed by doping at least a portion of the first substrate 102, where at least a portion of the first substrate 102 and the first barrier layer 103 are doped after the first barrier layer 103 is formed or disposed on the first substrate 102. Therefore, if the first barrier layer 103 is doped with an n-type impurity, the conductive layer 104 may also be doped with an n-type impurity. If the first barrier layer 103 is doped with a p-type impurity, the conductive layer 104 may also be doped with a p-type impurity. For example, the first barrier layer 103 and the conductive layer 104 may be doped with the same or similar impurities.

[0144] The first barrier layer 103 may be disposed or provided on the conductive layer 104, and may have a second thickness t2 from the top surface of the conductive layer 104. In an embodiment, the second thickness t2 may be approximately to approximately Within the range.

[0145] When the first barrier layer 103 is provided thinly, the inside of the chamber can be contaminated by gases generated from the inside of the substrate during the process. When the first barrier layer 103 is provided thickly, a high accelerating voltage may be required to dope at least a portion of the first substrate 102. Therefore, the second thickness t2 can be approximately to approximately Within the range.

[0146] A third barrier layer 105 may be arranged or disposed on the first barrier layer 103. The third barrier layer 105 may have a third thickness t3 extending from the top surface of the first barrier layer 103, and may be arranged or disposed on the first barrier layer 103. In an embodiment, the third thickness t3 may be approximately... to approximately Within the range.

[0147] If the third barrier layer 105 is provided thinly, the inside of the chamber can be contaminated by gases generated from the inside of the substrate during the process. If the third barrier layer 105 is provided thickly, material costs can increase. Therefore, the third thickness t3 can be approximately... to approximately Within the range.

[0148] The third barrier layer 105 may include inorganic materials (such as oxides or nitrides), organic materials, or organic / inorganic composite materials, and may have a single-layer structure or a multi-layer structure of inorganic and organic materials. For example, the first barrier layer 103 may be doped with n-type or p-type impurities, but the third barrier layer 105 may be arranged or disposed on the first barrier layer 103 without being doped with n-type or p-type impurities.

[0149] Figures 8 to 11B A schematic cross-sectional view showing a method for manufacturing a display device according to an embodiment.

[0150] See below for reference. Figures 8 to 11B The methods for manufacturing display devices are described in sequence.

[0151] A method for manufacturing a display device according to an embodiment may include: forming a first substrate 102 over a support substrate 5, forming a first barrier layer 103 on the first substrate 102, and forming a conductive layer 104 by implanting n-type impurities or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103.

[0152] The method of manufacturing a display device according to the embodiment may include forming a second substrate 100 on the support substrate 5 before forming a first substrate 102 on the support substrate 5, and forming a second barrier layer 101 on the second substrate 100.

[0153] First, refer to Figure 8 The step of forming a second substrate 100 on the support substrate 5 can be performed. The second substrate 100 may include a polymer resin. The second substrate 100 including the polymer resin may be flexible, rollable, or bendable. For example, the second substrate 100 may include polyimide.

[0154] refer to Figure 9 After the second substrate 100 is formed on the support substrate 5, the step of forming a second barrier layer 101 on the second substrate 100 can be performed. The second barrier layer 101 may include inorganic materials (such as oxides or nitrides), organic materials or organic / inorganic composite materials, and may have a single-layer structure or a multi-layer structure of inorganic and organic materials.

[0155] refer to Figure 10 After forming the second barrier layer 101 on the second substrate 100, the step of forming the first substrate 102 on the second barrier layer 101 can be performed. In one embodiment, the first substrate 102 may include a material that is the same as or similar to the material of the second substrate 100. In another embodiment, the first substrate 102 may include a material that is different from the material of the second substrate 100.

[0156] refer to Figure 11A After the first substrate 102 is formed on the second barrier layer 101, the step of forming the first barrier layer 103 on the first substrate 102 can be performed. As an example, after the first substrate 102 is formed on the second barrier layer 101, the step of forming the first barrier layer 103 having a first thickness t1 from the top surface of the first substrate 102 on the first substrate 102 can be performed.

[0157] The first barrier layer 103 may have a first thickness t1 extending from the top surface of the first substrate 102. In an embodiment, the first thickness t1 may be approximately [missing information]. to approximately Within the range.

[0158] The first barrier layer 103 may comprise inorganic materials (such as oxides or nitrides), organic materials, or organic / inorganic composite materials, and may have a single-layer or multi-layer structure of inorganic and organic materials. For example, the first barrier layer 103 may comprise amorphous silicon. In some embodiments, the first barrier layer 103 may comprise the same or similar material as the second barrier layer 101. In other embodiments, the first barrier layer 103 may comprise a material different from the material of the second barrier layer 101.

[0159] refer to Figure 11B After forming the first barrier layer 103 over the first substrate 102, the step of forming the conductive layer 104 by implanting n-type or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103 can be performed.

[0160] In cases where the substrate may comprise a polymer resin, the polymer resin is polarized by a bias of wiring arranged or disposed on the substrate. The threshold voltage offset may change according to the bias caused by the charge resulting from the polarization, and thus the element characteristics may become different, and brightness differences may occur between pixels.

[0161] Crosstalk can occur when amorphous silicon doped with n-type impurities is deposited on a substrate using chemical vapor deposition (CVD) to prevent polarization of the polymer resin due to bias in the wiring on the substrate. When polysilicon is formed on the substrate and then a conductive layer is formed, the process cycle time can increase, and crosstalk can also occur. When at least a portion of the substrate is directly doped using ion implantation, the inside of the chamber can be contaminated by gases generated by the polymer resin of the substrate.

[0162] To address the aforementioned issues, embodiments can prevent polarization of the polymer resin by biasing the wiring on the substrate, and simultaneously prevent residual images from being observed by forming a barrier layer on the substrate comprising the polymer resin and doping at least a portion of the substrate by ion implantation to form a conductive layer.

[0163] During the formation of the conductive layer 104 by implanting n-type or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103, at least a portion of the first substrate 102 and the first barrier layer 103 can be doped by implanting n-type or p-type impurities into the top surface of the first barrier layer 103 via ion implantation. For example, the first barrier layer 103 can be doped to approximately to approximately The thickness within the range is formed on the first substrate 102. The conductive layer 104 may be a portion formed by doping at least a portion of the first substrate 102 with n-type or p-type impurities.

[0164] In which the first barrier layer 103 is in approximately to approximately When an n-type impurity or p-type impurity is formed or disposed on the first substrate 102 within a thickness range of about 70 keV to about 80 keV, an n-type impurity or p-type impurity can be implanted into at least a portion of the first substrate 102 and the first barrier layer 103 under an accelerating voltage in the range of about 70 keV to about 80 keV. The n-type impurity or p-type impurity implanted in the top surface of the first barrier layer 103 can penetrate the first barrier layer 103 and dope at least a portion of the first substrate 102. When an n-type impurity or p-type impurity is implanted in the top surface of the first barrier layer 103 at about 70 keV, about 1.5% to about 2.5% of the total impurities can be implanted in the first substrate 102 below or beneath the first barrier layer 103 to dope at least a portion of the first substrate 102. When an n-type impurity or p-type impurity is implanted in the top surface of the first barrier layer 103 at about 80 keV, about 8% to about 12% of the total impurities can be implanted in the first substrate 102 below or beneath the first barrier layer 103 to dope at least a portion of the first substrate 102. For example, when n-type or p-type impurities are implanted into at least a portion of the first substrate 102 and the first barrier layer 103 at an accelerating voltage of approximately 80 keV, the total amount of implanted impurities can be approximately 1 × 10⁻⁶. 23 ions / cm 3 In this case, the impurities implanted in the first substrate 102 can be approximately 1 × 10⁻⁶. 21 ions / cm 3 To approximately 1×10 22 ions / cm 3 Within the range.

[0165] n-type impurities may include, for example, phosphorus, and p-type impurities may include, for example, boron.

[0166] Since at least a portion of the first substrate 102 may be doped with n-type or p-type impurities, and thus a conductive layer 104 may be formed, polarization of the polymer resin due to the bias of wiring on the substrate can be prevented. Therefore, the reliability of the device can be improved, and at the same time, afterimages can be prevented from being observed.

[0167] After forming the conductive layer 104 by implanting n-type or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103, heat treatment of the first barrier layer 103 and the conductive layer 104 may be performed. The impurities implanted in the first barrier layer 103 and the conductive layer 104 can be activated by performing heat treatment of the first barrier layer 103 and the conductive layer 104. Alternatively, the heat treatment of the first barrier layer 103 and the conductive layer 104 may be omitted because a subsequent heat treatment process of the semiconductor layer is performed.

[0168] After heat treatment of the first barrier layer 103 and the conductive layer 104, a step of forming a display element on the first barrier layer 103 can be performed, the display element including a thin film transistor and an organic light-emitting diode.

[0169] Figures 12A to 12C This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment. Figures 12A to 12C The implementation method can be Figure 11A and Figure 11B The modified implementation differs from the above implementation in that the first barrier layer 103 may be arranged or disposed thinner, and the third barrier layer 105 may be formed or disposed on the first barrier layer 103. The differences are described below. Other configurations may be the same as or similar to those of the above implementation.

[0170] refer to Figure 12A After the first substrate 102 is formed on the second barrier layer 101, the step of forming the first barrier layer 103 on the first substrate 102 can be performed. As an example, after the first substrate 102 is formed on the second barrier layer 101, the step of forming the first barrier layer 103 on the first substrate 102 can be performed, and the first barrier layer 103 has a second thickness t2 from the top surface of the first substrate 102.

[0171] The first barrier layer 103 may have a second thickness t2 extending from the top surface of the first substrate 102. In an embodiment, the second thickness t2 may be approximately [missing information]. to approximately Within the range.

[0172] The first barrier layer 103 may include inorganic materials (such as oxides or nitrides), organic materials, or organic / inorganic composite materials, and may have a single-layer structure or a multi-layer structure of inorganic and organic materials. For example, the first barrier layer 103 may include amorphous silicon.

[0173] refer to Figure 12B After forming a first barrier layer 103 on the first substrate 102, a step can be performed to form a conductive layer 104 by implanting n-type or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103. As an example, a conductive layer 104 is formed on the first substrate 102 having approximately... to approximately After the first barrier layer 103 of a thickness within the range is formed, the step of forming a conductive layer 104 by implanting n-type or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103 can be performed.

[0174] During the formation of the conductive layer 104 by implanting n-type or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103, at least a portion of the first substrate 102 and the first barrier layer 103 can be doped by implanting n-type or p-type impurities into the top surface of the first barrier layer 103 via ion implantation. For example, the first barrier layer 103 can be doped to approximately to approximately The thickness within the range is formed on the first substrate 102. The conductive layer 104 may be a portion formed by doping at least a portion of the first substrate 102 with n-type or p-type impurities.

[0175] In which the first barrier layer 103 can be in approximately to approximately When the thickness of the first barrier layer 103 is formed or disposed on the first substrate 102 within the range of [specific thickness range], the first barrier layer 103 can be [specific thickness range] at approximately [specific thickness range]. to approximately Compared to the case where the thickness is formed on the first substrate 102 within a certain range, n-type or p-type impurities can be implanted in at least a portion of the first substrate 102 and the first barrier layer 103 at a lower accelerating voltage. For example, in which the first barrier layer 103 is formed at approximately to approximately When a thickness within the range of [value missing] is formed on the first substrate 102, n-type or p-type impurities can be implanted into at least a portion of the first substrate 102 and the first barrier layer 103 at an accelerating voltage of about 30 keV or less. The n-type or p-type impurities implanted in the top surface of the first barrier layer 103 can penetrate the first barrier layer 103 and dope at least a portion of the first substrate 102. For example, at an accelerating voltage of about 30 keV or less, [value missing]... When n-type or p-type impurities are implanted into the top surface of the first barrier layer 103 of a certain thickness, approximately 60% to approximately 80% of the total impurities can be implanted into the first substrate 102 below or beneath the first barrier layer 103 to dope at least a portion of the first substrate 102. At approximately 30 keV or less, in a substrate having approximately When n-type or p-type impurities are implanted into the top surface of the first barrier layer 103 of a certain thickness, approximately 5% to approximately 15% of the total impurities can be implanted into the first substrate 102 below or beneath the first barrier layer 103 to dope at least a portion of the first substrate 102. Therefore, the first barrier layer 103 can be implanted with approximately... to approximately When the thickness of the first barrier layer 103 is formed or disposed on the first substrate 102 within the range of [specific range], it is achieved by using a lower accelerating voltage (e.g., 30 keV or less) where the first barrier layer 103 is approximately [specific value]. to approximately Under the accelerating voltage used in the case where the thickness is formed on the first substrate 102 within the range of the first substrate 102, n-type impurities or p-type impurities are implanted into at least a portion of the first substrate 102 below or under the first barrier layer 103, and at least a portion of the first substrate 102 is doped to form a conductive layer 104.

[0176] refer to Figure 12CAfter forming a conductive layer 104 by implanting n-type or p-type impurities into at least a portion of the first substrate 102 and the first barrier layer 103, a third barrier layer 105 may be further formed on the first barrier layer 103.

[0177] refer to Figure 11B and Figure 12B When the first barrier layer 103 is provided thin, impurities can be implanted into the substrate at a low accelerating voltage. However, when the barrier layer formed or disposed on the substrate comprising a polymer resin is provided thin, the barrier layer may be insufficient to protect the substrate and components. Therefore, a third barrier layer 105 may be formed or disposed on the second barrier layer 103, such as... Figure 12C As shown in the image.

[0178] The third barrier layer 105 may have a third thickness t3 extending from the top surface of the first barrier layer 103, the third thickness t3 being greater than the second thickness t2. In an embodiment, the third thickness t3 may be approximately [missing information]. to approximately Within the range.

[0179] Since the process of injecting n-type or p-type impurities into the third barrier layer 105 is not performed, the third barrier layer 105 can be formed or disposed on the first barrier layer 103 without being doped with n-type or p-type impurities.

[0180] Since the third barrier layer 105 is formed or disposed on the first barrier layer 103, the conductive layer 104 can be protected even when the conductive layer 104 is formed by injecting impurities into at least a portion of the substrate at a low accelerating voltage.

[0181] According to embodiments, since the conductive layer can be arranged or disposed between the substrate and the barrier layer, afterimages can be prevented from being observed, and simultaneously, a display device and a method of manufacturing thereof can be implemented to improve the reliability of the product. However, the scope of this disclosure is not limited to these effects.

[0182] It should be understood that the embodiments described herein are for descriptive purposes only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: The first substrate includes polyimide; A conductive layer directly disposed on the first substrate and implanted with boron; and A first barrier layer, directly disposed on the conductive layer and infused with boron, The conductive layer is obtained by implanting boron into a portion of the first substrate comprising polyimide and the first barrier layer, and The first barrier layer has a first thickness ranging from 4,000 Å to 6,000 Å from the top surface of the conductive layer.

2. The display device as claimed in claim 1, further comprising: A second substrate disposed below the first substrate; and A second barrier layer disposed between the second substrate and the first substrate.

3. The display device of claim 2, wherein the first substrate and the second substrate comprise the same material.

4. The display device as claimed in claim 1, further comprising: A pixel circuit disposed above the first substrate and including a thin-film transistor and a storage capacitor; and An organic light-emitting diode electrically connected to the pixel circuit.

5. A method for manufacturing a display device, the method comprising: A first substrate comprising polyimide is formed on a support substrate; A first barrier layer is formed on the first substrate; and A conductive layer is formed by implanting boron into at least a portion of the first substrate and the first barrier layer, wherein The formation of the first barrier layer includes: forming a first barrier layer having a first thickness in the range of 4,000 Å to 6,000 Å from the top surface of the first substrate. The formation of the conductive layer includes: implanting boron into at least a portion of the first substrate and the first barrier layer using ion implantation or plasma treatment, and The formation of the conductive layer includes implanting boron into at least a portion of the first substrate and the first barrier layer at an accelerating voltage in the range of 70 keV to 80 keV.

6. The method of claim 5, further comprising: After the formation of the conductive layer, the first barrier layer and the conductive layer are heat-treated.

7. The method of claim 5, further comprising: Before the formation of the first substrate on the support substrate, a second substrate is formed on the support substrate; as well as A second barrier layer is formed on the second substrate.

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