Semiconductor device including delay compensation circuit

Abstract

A semiconductor device including a delay compensation circuit is provided. The semiconductor device includes: an internal clock generation circuit configured to generate an internal clock; a plurality of cell circuits configured to have a first cell circuit and a second cell circuit, the first cell circuit and the second cell circuit operating in synchronization with the internal clock; a plurality of transfer circuits including a first transfer circuit and a second transfer circuit, the first transfer path configured to provide a first transfer path having a first delay time, the second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to: compare a first clock input to the first cell circuit through the first transfer path with a second clock input to the second cell circuit through the second transfer path, and adjust the second delay time so that the adjusted second delay time matches the first delay time.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0044008, filed on April 10, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments disclosed herein relate to a semiconductor device. Background Technology

[0003] Semiconductor devices may include circuitry that operates based on a clock signal, and two or more circuits may operate by receiving the same clock signal. To allow the same clock signal to be input to two or more circuits, a clock tree, providing a path for the clock signal, may be included in the semiconductor device. The clock tree may be symmetrically configured to reduce clock skew between clock signals input to the circuits; however, when such a clock tree is configured symmetrically, the number of devices included in the clock tree may increase, potentially degrading the integration density of the semiconductor device. Summary of the Invention

[0004] Example embodiments of this disclosure will provide a semiconductor device that can effectively compensate for deviations between clock signals, reduce the number of devices included in the clock tree, and reduce clock signal fluctuations.

[0005] According to an example embodiment of this disclosure, a semiconductor device includes: an internal clock generation circuit configured to receive an external clock and generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit, the first unit circuit and the second unit circuit operating in synchronization with the internal clock; a plurality of transmission circuits, including a first transmission circuit and a second transmission circuit, the first transmission circuit being configured to provide a first transmission path having a first delay time and connected between the first unit circuit and the internal clock generation circuit, the second transmission circuit being configured to provide a second transmission path having a second delay time and connected between the second unit circuit and the internal clock generation circuit, the second delay time being different from the first delay time; and a delay compensation circuit configured to: compare a first operating clock input to the first unit circuit via the first transmission path with a second operating clock input to the second unit circuit via the second transmission path, and adjust the second delay time such that the adjusted second delay time matches the first delay time. The first delay time may be the longest delay time among the delay times between the internal clock generation circuit and different unit circuits among the plurality of unit circuits.

[0006] According to an example embodiment of this disclosure, a semiconductor device includes: an input / output circuit configured to input and output a data signal based on a clock signal; a delay-locked loop circuit configured to generate a clock signal; a plurality of repeaters connected between the delay-locked loop circuit and the input / output circuit, and configured to send the clock signal to the input / output circuit; a comparator connected between a first input / output circuit and a second input / output circuit in the input / output circuit, and configured to compare a first clock signal input to the first input / output circuit with a second clock signal input to the second input / output circuit; and a delay chain configured to adjust the phase of the second clock signal based on the output of the comparator such that the first clock signal and the second clock signal have the same phase.

[0007] According to an example embodiment of this disclosure, a semiconductor device includes: a clock generating circuit configured to generate a clock signal; a first delay circuit configured to delay the clock signal by a first delay time and input the clock signal delayed by the first delay time into a first unit circuit; a second delay circuit configured to delay the clock signal by a second delay time shorter than the first delay time and input the clock signal delayed by the second delay time into a second unit circuit different from the first unit circuit; and a delay compensation circuit configured to compare the first delay time with the second delay time and increase the second delay time to obtain an increased second delay time that matches the first delay time. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0010] Figure 2 This is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0011] Figure 3 and Figure 4 This is a diagram illustrating the operation of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0012] Figure 5 This is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0013] Figure 6 This is a block diagram illustrating a delay compensation circuit included in a semiconductor device according to an exemplary embodiment of the present disclosure;

[0014] Figure 7 and Figure 8 This is a diagram illustrating the operation of a delay compensation circuit according to an exemplary embodiment of the present disclosure;

[0015] Figure 9 This is a diagram illustrating the operation of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0016] Figures 10 to 12 This is a diagram illustrating the operation of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0017] Figures 13 to 16 This is a diagram illustrating the operation of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0018] Figures 17 to 20 This is a diagram illustrating the operation of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0019] Figure 21 and Figure 22 This is a diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; and

[0020] Figure 23 This is a block diagram illustrating an electronic device including a semiconductor device according to an example embodiment of the present disclosure. Detailed Implementation

[0021] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the description and drawings, unless otherwise clearly indicated, the same or similar reference numerals denote the same or similar elements / assemblies.

[0022] Figure 1 This is a block diagram illustrating a semiconductor device according to an example embodiment.

[0023] Reference Figure 1 In an example embodiment, the semiconductor device 1 may include a clock generation circuit 10, a clock tree 20, and a plurality of unit circuits 31 to 34 (30). The clock generation circuit 10 may use an external clock received by the semiconductor device 1 from an external device (e.g., a memory controller) to generate an internal clock for the operation of the semiconductor device 1. In one example embodiment, the clock generation circuit 10 may include a delay-locked loop (DLL) circuit.

[0024] Clock tree 20 may be a circuit that provides a transmission path for transmitting the internal clock generated by clock generation circuit 10 to unit circuit 30. Clock tree 20 may include multiple repeaters for transmitting the internal clock. As an example, each repeater may include at least one buffer. Therefore, signal delay may occur when the internal clock is transmitted to unit circuit 30 through the repeaters. To synchronize the internal clocks transmitted to each of the unit circuits 30, various methods for compensating for differences in delay times of the transmission paths connected to unit circuit 30 may be applied to clock tree 20.

[0025] Unit circuit 30 may be a circuit that operates using an internal clock. As an example, unit circuit 30 may be an input and output circuit for sending signals to and receiving signals from an external device (e.g., a memory controller). The input and output circuits may be synchronized with an internal clock and may be used to send or receive signals. The input and output circuits described herein are also described as input / output circuits, each configured to input and output data signals or data strobe signals. In the example embodiment, unit circuits 31 to 34 may have the same operation and structure. For example, unit circuits 31 to 34 may be input / output circuits (e.g., identical input / output circuits). In the example embodiment, at least a portion of unit circuits 31 to 34 may have different operations and structures. For example, unit circuits 31 and 32 may be input / output circuits, unit circuit 33 may be a data strobe buffer configured to output a data strobe signal DQS or DQSB, and unit circuit 34 may be a data inversion buffer configured to output a data masking signal (DM or DMI) to provide data bus inversion (DBI) functionality.

[0026] When there are differences in delay times between the transmission paths of the clock tree 20 used to transmit the internal clock, the operating timing of the unit circuit 30 may differ, and the reliability of the semiconductor device 1 may deteriorate. To address this issue, the clock tree 20 can be designed so that the transmission paths of the clock tree 20 have the same delay time. However, when the clock tree 20 is designed so that the transmission paths have the same delay time, the number of devices used to implement the transmission paths may increase, potentially degrading the integration density of the semiconductor device 1. Furthermore, the shielding space provided between the transmission paths to reduce parasitic capacitance, etc., may not be adequately provided. Therefore, when the internal clock frequency is high, jitter may occur, potentially reducing eye margin or causing other problems.

[0027] In one example embodiment, the internal clock transmitted via the transmission path with the longest delay time in clock tree 20 can be selected as the reference clock, and the delay times of other transmission paths can be adjusted with reference to the delay time of the reference clock. Therefore, the number of devices included in clock tree 20 can be reduced, thereby improving the integration density of semiconductor device 1, and sufficient shielding space can be provided between transmission paths, enabling stable high-speed operation.

[0028] Figure 2 This is a block diagram illustrating a semiconductor device according to an example embodiment.

[0029] Reference Figure 2 The semiconductor device 100 in the example embodiment may include a clock buffer 110, a clock generation circuit 120, a clock tree 130, and a plurality of unit circuits 141 to 144 (140). The clock buffer 110 may buffer an external clock CK_ext that the semiconductor device 100 has received from an external entity (e.g., a memory controller) and may output the external clock.

[0030] The clock generation circuit 120 can use the external clock CK_ext buffered by the clock buffer 110 to generate the internal clock CK_int, and may include, for example, a DLL circuit, a phase-locked loop (PLL) circuit, etc. Figure 2 In the example embodiment shown, the clock generation circuit 120 may include a delay chain 121, a phase detector 122, a replication circuit 123, etc. The delay chain 121 can operate according to a specific control signal, can delay an external clock CK_ext, and can output an internal clock CK_int. The internal clock CK_int can be synchronized with the external clock CK_ext through a DLL circuit or a PLL circuit.

[0031] The replication circuit 123 can replicate the delay properties of the clock tree 130 and can provide the replicated delay properties. For example, the amount of delay that occurs when a signal passes through the clock tree 130 can be substantially the same as the amount of delay that occurs when the signal passes through the replication circuit 123. The replication circuit 123 can delay the internal clock CK_int output by the delay chain 121 based on the amount of delay reflected by the delay properties of the clock tree 130, and can output the internal clock CK_int to the phase detector 122.

[0032] Phase detector 122 can compare the output of replication circuit 123 with the output of clock buffer 110 and can generate a phase comparison signal. In one example embodiment, phase detector 122 can enable the phase comparison signal when the output of replication circuit 123 has a phase that is faster (earlier) than the output of clock buffer 110, and phase detector 122 can disable the phase comparison signal when the output of replication circuit 123 has a phase that is slower (later) than the output of clock buffer 110. The phase comparison signal output by phase detector 122 can be input as a control signal to delay chain 121.

[0033] Delay chain 121 can generate the internal clock CK_int by increasing or decreasing the delay of the external clock CK_ext according to the phase comparison signal. As an example, when the phase comparison signal is enabled, delay chain 121 can increase the delay of the external clock CK_ext, and when the phase comparison signal is disabled, delay chain 121 can decrease the delay of the external clock CK_ext.

[0034] Clock tree 130 may include multiple transmission circuits for transmitting the internal clock CK_int to unit circuit 140. As an example, each transmission circuit may provide one or more transmission paths, and each transmission path may be implemented as multiple repeaters. When a deviation in the internal clock CK_int occurs in each of unit circuits 140, the operating timing of each of unit circuits 140 may differ, and therefore, errors may occur in the operation of semiconductor device 100. Therefore, clock tree 130 may be designed such that the transmission paths transmitting the internal clock CK_int to unit circuit 140 have the same delay time as each other.

[0035] Figure 3 and Figure 4 This is a diagram illustrating the operation of a semiconductor device according to an example embodiment.

[0036] Reference Figure 3 Semiconductor device 200 may include clock generation circuitry 210 for generating an internal clock CK_int using an external clock CK_ext, and a clock tree 220 for transmitting the internal clock CK_int to a plurality of unit circuits 230. For example, clock tree 220 may include a plurality of repeaters RPT 225, each of which may include at least one buffer. Unit circuits 230 may be circuitry that operates in synchronization with an operating clock CK output by clock tree 220. Hereinafter, the external clock CK_ext may be received from outside the semiconductor device or from a clock buffer included within the semiconductor device.

[0037] exist Figure 3In the example embodiment shown, repeaters 225 included in clock tree 220 can be connected to each other according to an H-tree structure. The transmission paths used to connect clock generation circuit 210 to unit circuit 230 can have the same delay time. For example, each of unit circuits 230 can receive an operating clock CK from clock tree 220. Therefore, the operating clocks CK input to unit circuit 230 can have substantially the same phase.

[0038] Figure 4 This is a diagram showing the internal clock CK_int input to clock tree 220 and the operational clock CK output from clock tree 220. (Refer to...) Figure 4 Depending on the delay amount of each repeater 225 included in the clock tree 220, a specific delay time TD may occur between the internal clock CK_int and the operating clock CK. The delay time TD may vary depending on the number of repeaters 225 in the transmission path of the internal clock CK_int, errors that occur during the manufacture of the semiconductor device 200 including the clock tree 220, the operating environment of the semiconductor device 200, etc.

[0039] When the clock tree 220 is as follows Figure 3 and Figure 4 When configured similarly, the number of repeaters 225 required to transmit the operating clock CK through its path to unit circuit 230 may increase. Therefore, the integration density of semiconductor device 200 may degrade. Furthermore, with the increase in the number of repeaters 225, it may be difficult to adequately ensure the shielding space between transmission paths, thus potentially increasing the jitter element of the operating clock CK.

[0040] In one example embodiment, the clock tree can be implemented as a fly-by type clock tree. Therefore, implementing connections to... Figure 3 The number of repeaters required for the clock tree of the same number of unit circuits can be reduced, and the jitter component of each operating clock CK can be reduced. Furthermore, among the operating clocks CK input to the unit circuits, the delay time of each of the other operating clocks can be adjusted by referring to the operating clock with the longest delay time. Deviations in each operating clock that may occur after the semiconductor device is manufactured and shipped due to changes in the operating environment, operating voltage, etc., can be effectively compensated for.

[0041] Figure 5 This is a block diagram illustrating a semiconductor device according to an example embodiment.

[0042] Reference Figure 5The semiconductor device 300 in the example embodiment may include a clock generation circuit 310, a clock tree 320, multiple unit circuits 330 and 340, and a delay compensation circuit 350. The clock generation circuit 310 may use an external clock CK_ext to generate an internal clock CK_int. As an example, the clock generation circuit 310 may include a delay-locked loop circuit or a phase-locked loop circuit.

[0043] Clock tree 320 may include a first transmission circuit 321 and a second transmission circuit 322. Unit circuits 330 and 340 may include a first unit circuit 330 connected to the first transmission circuit 321 and a second unit circuit 340 connected to the second transmission circuit 322. The first transmission circuit 321 may output a first operating clock CK1, and the second transmission circuit 322 may output a second operating clock CK2. In one example embodiment, the first operating clock CK1 and the second operating clock CK2 may have the same frequency.

[0044] like Figure 5 As shown, the internal clock CK_int can be input from the clock generation circuit 310 to the first transmission circuit 321 via the second transmission circuit 322. Therefore, the first transmission path through which the first transmission circuit 321 transmits the first operating clock CK1 to the first unit circuit 330 can have a greater delay than the second transmission path through which the second transmission circuit 322 transmits the second operating clock CK2 to the second unit circuit 340. As an example, in the initial state of operation of the semiconductor device 300, the delay time of the first operating clock CK1 relative to the internal clock CK_int can be longer than the delay time of the second operating clock CK2. Optionally, it can be understood that in the initial state of operation of the semiconductor device 300, the first operating clock CK1 can have a phase that is slower than the phase of the second operating clock CK2.

[0045] In one example embodiment, the delay compensation circuit 350 can compare a first operating clock CK1 output from the first unit circuit 331 with a second operating clock CK2 output from the second unit circuit 341. In another example embodiment, the delay compensation circuit 350 can compare a first operating clock CK1 input to at least one of the first unit circuits 330 with a second operating clock CK2 input to at least one of the second unit circuits 340, and can adjust the delay amount of the second transmission circuit 322 based on the comparison result. As an example, the second transmission circuit 322 may include a delay chain or the like that adjustable in delay time for the second operating clock CK2. The delay chain in the second transmission circuit 322 may be connected between repeaters directly connected to each other. The delay compensation circuit 350 can adjust the delay amount of the delay chain included in the second transmission circuit 322 based on the comparison result between the first operating clock CK1 and the second operating clock CK2, such that the first operating clock CK1 and the second operating clock CK2 can have substantially the same phase.

[0046] In one example embodiment, the delay compensation circuit 350 can control the second operating clock CK2 to synchronize with the first operating clock CK1 at specific intervals or in response to requests from control logic included in the semiconductor device 300. When the operating environment of the semiconductor device 300 changes, the delay of each of the first operating clock CK1 and the second operating clock CK2 may change, and therefore, a phase difference may occur between the first operating clock CK1 and the second operating clock CK2. Therefore, the delay compensation circuit 350 can adjust the delay time of the second operating clock CK2 according to the first operating clock CK1 at predetermined intervals or based on requests from control logic that has sensed changes in the operating environment, thereby improving the performance of the semiconductor device 300.

[0047] Figure 6 This is a block diagram illustrating a delay compensation circuit included in a semiconductor device according to an example embodiment.

[0048] Reference Figure 6 The delay compensation circuit 400 in the example embodiment may include a comparator 410, a counter 420, and a delay chain 430. The comparator 410 can compare a first operating clock CK1 input to the first unit circuit 401 with a second operating clock CK2 input to the second unit circuit 402.

[0049] Counter 420 can count the output of comparator 410. For example, counter 420 can count the time when the first operating clock CK1 is greater than the second operating clock CK2, or the time when the second operating clock CK2 is greater than the first operating clock CK1. Delay chain 430 can synchronize the first operating clock CK1 and the second operating clock CK2 by delaying the other of the first operating clock CK1 and the second operating clock CK2, referencing one of them.

[0050] In the following description, reference will be made to Figure 7 and Figure 8 The operation of the delay compensation circuit 400 is described in more detail.

[0051] Figure 7 and Figure 8 This is a diagram illustrating a comparative example of a semiconductor device according to an example embodiment.

[0052] Figure 7 and Figure 8 This is a diagram showing the first operating clock CK1 input to the first unit circuit 401, the second operating clock CK2 input to the second unit circuit 402, and the internal clock CK_int. Figure 7 and Figure 8 In the example embodiment shown, the internal clock CK_int can be a clock received by a clock tree, which provides a first operating clock CK1 and a second operating clock CK2 to the first unit circuit 401 and the second unit circuit 402. The internal clock CK_int can have the same frequency and duty cycle as the first operating clock CK1 and the second operating clock CK2.

[0053] Figure 7 This is a diagram showing the state before the delay compensation circuit 400 compensates for the difference in delay between the first operating clock CK1 and the second operating clock CK2. (Refer to...) Figure 7 Relative to the internal clock CK_int, the first operating clock CK1 can be delayed by a first delay time TD1, and the second operating clock CK2 can be delayed by a second delay time TD2. The first delay time TD1 can be longer than the second delay time TD2.

[0054] As an example, when the first operating clock CK1 and the second operating clock CK2 are input to the comparator 410, the counter 420 can count the times when the first operating clock CK1 and the second operating clock CK2 have different values. Figure 7 In the example embodiment shown, counter 420 can count the time difference ΔT between the first delay time TD1 and the second delay time TD2.

[0055] The result of counter 420 counting the time difference ΔT between the first delay time TD1 and the second delay time TD2 can be transmitted to delay chain 430. As an example, delay chain 430 can receive the time difference ΔT counted by counter 420 in the form of a digital code (encoding). Delay chain 430 can adjust at least one of the first operating clock CK1 and the second operating clock CK2 with reference to the time difference ΔT so that the difference between the first delay time TD1 and the second delay time TD2 is 0.

[0056] As an example, delay chain 430 can adjust the delay time of the second operating clock CK2 based on a first operating clock CK1 that has a longer delay time relative to the internal clock CK_int. (See reference...) Figure 8 The delay chain 430 can adjust the delay time of the second operating clock CK2 to the first delay time TD1 based on the time difference ΔT received from the counter 420. Therefore, the deviation between the first operating clock CK1 and the second operating clock CK2 can be reduced.

[0057] Figure 9 This is a diagram illustrating the operation of a semiconductor device according to an example embodiment.

[0058] Reference Figure 9 The semiconductor device 500 in the example embodiment may include a clock generation circuit 510, a clock tree 520, and a plurality of unit circuits 530.

[0059] An internal clock CK_int can be input to a clock tree 520. The clock tree 520 may include a first transmission circuit 521 and a second transmission circuit 522 that transmits the internal clock CK_int to multiple unit circuits 530. Each of the first transmission circuit 521 and the second transmission circuit 522 may include multiple repeaters RPT. Each repeater RPT may include at least one buffer, in which the internal clock CK_int may be delayed.

[0060] Unit circuit 530 may include a first unit circuit 531 and a second unit circuit 532. The first transmission circuit 521 may be defined as a first delay circuit, which can delay the internal clock CK_int by a first delay time and can input the delayed internal clock CK_int into the first unit circuit 531. The second transmission circuit 522 may be defined as a second delay circuit, which can delay the internal clock CK_int by a second delay time and can input the delayed internal clock CK_int into the second unit circuit 532.

[0061] The second delay time can be shorter than the first delay time. (See reference...) Figure 9The first transmission circuit 521 can receive the internal clock CK_int from the clock generation circuit 510 via the second transmission circuit 522. Since the internal clock CK_int input to the first transmission circuit 521 has already passed through at least a portion of the repeater included in the second transmission circuit 522, the first delay time can be longer than the second delay time.

[0062] exist Figure 9 In the example embodiment shown, the first transmission circuit 521 can receive an internal clock CK_int that has been passed through four repeaters RPT included in the second transmission circuit 522. Therefore, due to the delay times of the four repeaters RPT, a difference may occur between the first delay time and the second delay time. The difference between the first delay time and the second delay time may result in a difference between the first operating clock CK1 input to the first unit circuit 531 and the second operating clock CK2 input to the second unit circuit 532. As an example, a phase difference may occur between the first operating clock CK1 and the second operating clock CK2 due to the difference between the first delay time and the second delay time.

[0063] When a phase difference occurs between the first operating clock CK1 and the second operating clock CK2, the timing of the operation of the first unit circuit 531 and the second unit circuit 532 may mismatch, potentially leading to errors in the operation of the semiconductor device 500. In one example embodiment, a delay compensation circuit can compare the first operating clock CK1 detected from the input of the first unit circuit 531 with the second operating clock CK2 detected from the input of the second unit circuit 532, and adjust the second delay time based on the comparison result. Therefore, the phase difference between the first operating clock CK1 and the second operating clock CK2 can be reduced.

[0064] As an example, the delay compensation circuit may include a comparator 541, a counter 542, and a delay chain 543. The comparator 541 may receive a first operating clock CK1 and a second operating clock CK2, and may compare the first operating clock CK1 with the second operating clock CK2. (See reference...) Figure 9 Comparator 541 can receive a first operating clock CK1 from the input of the first unit circuit 531 and a second operating clock CK2 from the input of the second unit circuit 532. In the example embodiment, the input of comparator 541 can also be connected to a node included in the first unit circuit 531 and the second unit circuit 532, or it can also be connected to the output of the first unit circuit 531 and the second unit circuit 532.

[0065] Counter 542 can count segments (or "time periods") where the first operating clock CK1 and the second operating clock CK2 have different values, and can output the counting result to delay chain 543. Delay chain 543 can adjust the second delay time of the second transmission circuit 522 based on the information received from counter 542. As an example, delay chain 543 can increase the second delay time to match the first delay time.

[0066] Delay chain 543 can be connected between the first repeater 522A and the second repeater 522B in the second transmission circuit 522. Delay chain 543 can also delay the difference between the first delay time and the second delay time by the internal clock CK_int of the first repeater 522A, and can input the delayed internal clock CK_int to the second repeater 522B. As an example, the second repeater 522B can be connected to all the second unit circuits 532 via multiple repeater RPTs. Therefore, the delay of the internal clock CK_int input to the second transmission circuit 522 by delay chain 543 based on the difference between the first and second delay times can be reflected in all the second operating clocks CK2 input to the second unit circuit 532.

[0067] exist Figure 9 In the example embodiment shown, the second operating clock CK2 can be adjusted with reference to a first operating clock CK1 having the longest delay time. Since the first operating clock CK1 serves as a reference clock, delay chains may not be included in the first transmission circuit 521 that provides the first operating clock CK1 to the first unit circuit 531. For example, delay chains 543 may be included only in the second transmission circuit 522, allowing the clock skew between the first operating clock CK1 and the second operating clock CK2 to be eliminated, and the circuit area occupied by the clock tree 520 to be effectively reduced. Furthermore, by reducing the number of delay chains 543, process-voltage-temperature (PVT) fluctuations and jitter can be reduced, and the difference between the delay time generated by the replication circuit included in the clock generation circuit 510 and the delay time of the clock tree 520 can also be reduced.

[0068] exist Figure 9 In the example embodiment shown, the clock tree 520 may include two transmission circuits 521 and 522. The number of first unit circuits 531 connected to the first transmission circuit 521 may be the same as the number of second unit circuits 532 connected to the second transmission circuit 522, but their example embodiments are not limited thereto. In the example embodiment, the number of transmission circuits included in the clock tree 520 and the number of unit circuits connected to the transmission circuits may vary.

[0069] The delay time of the first transmission circuit 521 can be the longest delay time among the delay times between the clock generation circuit 510 and the different unit circuits in the unit circuit 530. In one example embodiment, the longest delay time can be shared by a group of unit circuits (e.g., the first unit circuit 531).

[0070] Figures 10 to 12 This is a diagram illustrating the operation of a semiconductor device according to an example embodiment.

[0071] Reference Figure 10 The semiconductor device 600 in the example embodiment may include a clock generation circuit 610, a clock tree 620, and a plurality of unit circuits 630. The clock generation circuit 610 may use an external clock CK_ext to generate an internal clock CK_int, which may be input to the clock tree 620.

[0072] The clock tree 620 may include first transmission circuits 621 to fourth transmission circuits 624, each of which may include multiple repeaters RPT. The first transmission circuits 621 to fourth transmission circuits 624 may input operating clocks CK1 to CK4 to multiple unit circuits 630.

[0073] Unit circuit 630 may include a first unit circuit 631, a second unit circuit 632, a third unit circuit 633, and a fourth unit circuit 634. As an example, the first transmission circuit 621 can input a first operating clock CK1 into the first unit circuit 631, the second transmission circuit 622 can input a second operating clock CK2 into the second unit circuit 632, the third transmission circuit 623 can input a third operating clock CK3 into the third unit circuit 633, and the fourth transmission circuit 624 can input a fourth operating clock CK4 into the fourth unit circuit 634.

[0074] Reference Figure 11 The operating clocks CK1 to CK4 can have different phases. In one example embodiment, among the operating clocks CK1 to CK4, the first operating clock CK1 can have the longest first delay time TD1 relative to the internal clock CK_int, and the fourth operating clock CK4 can have the shortest fourth delay time TD4. The second operating clock CK2 can have the second longest second delay time TD2, and the third operating clock CK3 can have the second shortest third delay time TD3. Therefore, at least a portion of the operating timing of the plurality of unit circuits 630 may be mismatched with each other, which may lead to degradation of the performance of the semiconductor device 600.

[0075] In one example embodiment, the difference in delay times between operating clocks CK1 to CK4 can be compensated using a delay compensation circuit. As an example, the difference in delay times between operating clocks CK1 to CK4 can be reduced by increasing the second delay time TD2 to the fourth delay time TD4 to match the first delay time TD1. (Refer to...) Figure 12 The delay compensation circuit can adjust the delay time of the operating clocks CK1 to CK4 to the first delay time TD1.

[0076] Return to reference Figure 10 and Figure 11 The first comparator 641 compares the first operating clock CK1 with the second operating clock CK2. The first counter 642 counts the output of the first comparator 641 and transmits the output (the count result) to the first delay chain 643. The first delay chain 643 can be connected between the first repeater 622A and the second repeater 622B in the second transmission circuit 622, and the second operating clock CK2 can be adjusted by referring to the output of the first counter 642. As an example, the first counter 642 can count the first time difference ΔT1 corresponding to the difference between the first delay time TD1 and the second delay time TD2. The larger the first time difference ΔT1 is, the more the first delay chain 643 can increase the second delay time TD2. The first delay chain 643 can increase the second delay time TD2 so that the first delay time TD1 and the second delay time TD2 match each other.

[0077] The operation of the second comparator 651, the second counter 652, the second delay chain 653, the third comparator 661, the third counter 662, and the third delay chain 663 can be similar to the operation of the first comparator 641, the first counter 642, and the first delay chain 643. Similarly, the second delay chain 653 can be connected between the first repeater 623A and the second repeater 623B in the third transmission circuit 623, and the third delay chain 663 can be connected between the first repeater 624A and the second repeater 624B in the fourth transmission circuit 624. As an example, the second delay chain 653 can increase the third delay time TD3 to match the second delay time TD2 by referring to the difference between the second delay time TD2 and the third delay time TD3. In an example embodiment, the second comparator 651 connected to the second delay chain 653 can compare the second operating clock CK2 adjusted by the first delay chain 643 with the third operating clock CK3. Therefore, as Figure 12 As shown, the second delay chain 653 can delay the phase of the third operating clock CK3 by a second time difference ΔT2.

[0078] Similarly, the third delay chain 663 can increase the fourth delay time TD4 to match the third delay time TD3 by referring to the difference between the third delay time TD3 and the fourth delay time TD4. The third comparator 661, connected to the third delay chain 663, can compare the third operating clock CK3, adjusted by the second delay chain 653, with the fourth operating clock CK4. For example, the third comparator 661 can compare the third operating clock CK3, whose phase has been delayed by a second time difference ΔT2 by the second delay chain 653, with the fourth operating clock CK4. Therefore, as... Figure 12 As shown, the third delay chain 663 can increase the fourth delay time TD4 of the fourth operating clock CK4 by a third time difference ΔT3, and can synchronize the fourth operating clock CK4 with other operating clocks CK1 to CK3.

[0079] exist Figure 10 In the example embodiment shown, the first delay chain 643, the second delay chain 653, and the third delay chain 663 can sequentially adjust the second operating clock CK2, the third operating clock CK3, and the fourth operating clock CK4 according to the first operating clock CK1. Furthermore, in one example embodiment, the first delay chain 643, the second delay chain 653, and the third delay chain 663 can simultaneously adjust the second operating clock CK2, the third operating clock CK3, and the fourth operating clock CK4. As an example, the second comparator 651 can compare the third operating clock CK3 with the first operating clock CK1 instead of with the second operating clock CK2, and the second delay chain 653 can adjust the third operating clock CK3 based on the comparison result. Furthermore, the third comparator 661 can compare the fourth operating clock CK4 with the first operating clock CK1, and the third delay chain 663 can adjust the fourth operating clock CK4 based on the comparison result.

[0080] Figures 13 to 16 This is a diagram illustrating the operation of a semiconductor device according to an example embodiment.

[0081] Reference Figure 13 The semiconductor device 700 in the example embodiment may include a clock generation circuit 710, a clock tree 720, and a plurality of unit circuits 730. The clock generation circuit 710 may use an external clock CK_ext to generate an internal clock CK_int, and the internal clock CK_int may be input to the clock tree 720.

[0082] Clock tree 720 may include first transmission circuits 721 to third transmission circuits 723, each of which may include multiple repeaters RPT. First transmission circuits 721 to third transmission circuits 723 may input operating clocks CK1 to CK3 to multiple unit circuits 730. In one example embodiment, the number of unit circuits connected to the first transmission circuit 721 may differ from the number of unit circuits connected to each of the second transmission circuits 722 and the third transmission circuit 723. (Refer to...) Figure 13 The number of first unit circuits 731 connected to the first transmission circuit 721 may be greater than the number of second unit circuits 732 connected to the second transmission circuit 722 and the number of third unit circuits 733 connected to the third transmission circuit 723. Furthermore, the first transmission circuit 721 may include a greater number of repeater RPTs than the number of repeater RPTs in the second transmission circuit 722 and the third transmission circuit 723.

[0083] Semiconductor device 700 may include a delay compensation circuit for compensating for differences in delay time between each transmission path provided by the first transmission circuit 721 to the third transmission circuit 723. The delay compensation circuit may include a first comparator 741, a first counter 742, a first delay chain 743, a second comparator 751, a second counter 752, a second delay chain 753, etc. The first delay chain 743 may be connected between a first repeater 722A and a second repeater 722B included in the second transmission circuit 722, and the second delay chain 753 may be connected between a first repeater 723A and a second repeater 723B included in the third transmission circuit 723.

[0084] Unit circuit 730 may include a first unit circuit 731, a second unit circuit 732, and a third unit circuit 733. As an example, the delay time caused by ten repeater RPTs relative to the internal clock CK_int can be reflected in the first operating clock CK1 input to each first unit circuit 731. The delay time caused by six repeater RPTs relative to the internal clock CK_int can be reflected in the second operating clock CK2 input to each second unit circuit 732. The delay time caused by four repeater RPTs relative to the internal clock CK_int can be reflected in the third operating clock CK3 input to each third unit circuit 733.

[0085] The first delay chain 743 can delay the second operating clock CK2 by referring to the comparison result between the first operating clock CK1 and the second operating clock CK2, so that the phase of the first operating clock CK1 and the phase of the second operating clock CK2 are matched. As an example, assuming the delay times occurring in the repeater RPTs are the same, the first delay chain 743 can delay the internal clock CK_int by the delay time caused by four repeater RPTs. Similarly, the second delay chain 753 can delay the internal clock CK_int by the delay time caused by six repeater RPTs.

[0086] Reference Figure 14 The semiconductor device 700A in the example embodiment may include a clock generation circuit 710, a clock tree 720A, and a plurality of unit circuits 730A. The clock tree 720A may include a first transmission circuit 721a to a third transmission circuit 723a, and each of the first transmission circuit 721a to the third transmission circuit 723a may include a plurality of repeaters RPT.

[0087] The first transmission circuit 721a to the third transmission circuit 723a can be connected to multiple unit circuits 730. Figure 14 In the example embodiment shown, the number of first unit circuits 731A connected to the first transmission circuit 721a may be the same as the number of second unit circuits 732A connected to the second transmission circuit 722a. In one example embodiment, the number of third unit circuits 733A connected to the third transmission circuit 723a may be greater than the number of first unit circuits 731A and the number of second unit circuits 732A.

[0088] The operation of the delay compensation circuit can be compared with the reference. Figure 13 The described example embodiment is similar. The delay compensation circuit may include a first comparator 741A, a first counter 742A, a first delay chain 743A, a second comparator 751A, a second counter 752A, a second delay chain 753A, etc. The first operating clock CK1 may be delayed relative to the internal clock CK_int by the delay time generated by nine repeater RPTs. The second operating clock CK2 may be delayed from the internal clock CK_int by the delay time generated by eight repeater RPTs. Therefore, the first delay chain 743A can further delay the second operating clock CK2 by the delay time corresponding to a single repeater RPT, and can synchronize the second operating clock CK2 with the first operating clock CK1. Similarly, the second delay chain 753A can further delay the third operating clock CK3 by the delay time corresponding to four repeater RPTs.

[0089] Reference Figure 15In the example embodiment, the semiconductor device 800 may include a clock generation circuit 810, a clock tree 820, and multiple unit circuits 830. The clock tree 820 may include a first transmission circuit 821 and a second transmission circuit 822. The unit circuits 830 may include a first unit circuit 831 and a second unit circuit 832. The first transmission circuit 821 may input a first operating clock CK1 to the first unit circuit 831, and the second transmission circuit 822 may input a second operating clock CK2 to the second unit circuit 832.

[0090] Unlike the aforementioned example embodiments, in Figure 15 In the example embodiment shown, delay chain 812 may be included in clock generation circuitry 810 instead of clock tree 820. (See also...) Figure 15 The clock generation circuit 810 may include a driver 811, which is used to generate an internal clock CK_int using an external clock CK_ext and output the internal clock CK_int. The driver 811 may include a first output terminal and a second output terminal. The first output terminal is connected to the first transmission circuit 821, and the second output terminal is connected to the second transmission circuit 822 via a delay chain 812 connecting the second output terminal and the second transmission circuit 822. Therefore, in Figure 15 In the example embodiment shown, the first transmission circuit 821 and the second transmission circuit 822 can be connected in parallel to the output terminal of the clock generation circuit 810.

[0091] Reference Figure 15 The first operating clock CK1 can be delayed relative to the internal clock CK_int by the delay time corresponding to nine repeater RPTs. The second operating clock CK2 can be delayed relative to the internal clock CK_int by the delay time corresponding to seven repeater RPTs. Therefore, when the delay chain 812 further delays the internal clock CK_int by the delay time corresponding to two repeater RPTs, the first operating clock CK1 and the second operating clock CK2 can be synchronized with each other.

[0092] The additional delay time required by delay chain 812 to further delay the internal clock CK_int can be determined by comparator 841 and counter 842. Comparator 841 compares the first operating clock CK1 with the second operating clock CK2, and counter 842 counts the output of comparator 841. Therefore, delay chain 812 can determine the additional delay time based on changes in the operating environment (such as temperature, voltage, etc.) and considering fluctuations in operating clocks CK1 and CK2, thus ensuring accurate synchronization between the first operating clock CK1 and the second operating clock CK2.

[0093] exist Figure 16In the example embodiment shown, the semiconductor device 900 may include a clock generation circuit 910, a clock tree 920, and a plurality of unit circuits 930. The clock tree 920 may include a first transmission circuit 921 to a fourth transmission circuit 924, which may output a first operating clock CK1 to a fourth operating clock CK4. The operation for compensating for the difference in delay time between the first transmission circuit 921 and the fourth transmission circuit 924 can be referred to in [reference needed]. Figure 10 The example embodiments described are used for understanding.

[0094] exist Figure 16 In the example embodiment shown, the output of the first counter 942 can be input to the first delay chain 943, and can also be input to the second delay chain 953 and the third delay chain 963. Furthermore, the output of the second counter 952 can be input to the second delay chain 953 and the third delay chain 963.

[0095] Reference Figure 16 The first operating clock CK1 can be a clock relative to the internal clock CK_int, delayed by the delay time corresponding to nine repeater RPTs. The second operating clock CK2 can be a clock relative to the internal clock CK_int, delayed by the delay time corresponding to eight repeater RPTs. The third operating clock CK3 can be a clock relative to the internal clock CK_int, delayed by the delay time corresponding to six repeater RPTs. The fourth operating clock CK4 can be a clock relative to the internal clock CK_int, delayed by the delay time corresponding to four repeater RPTs.

[0096] Because the first comparator 941 compares the first operating clock CK1 with the second operating clock CK2, the second comparator 951 compares the second operating clock CK2 with the third operating clock CK3, and the third comparator 961 compares the third operating clock CK3 with the fourth operating clock CK4, it may be impossible to adjust the third operating clock CK3 before adjusting the second operating clock CK2 using the first operating clock CK1, and it may also be impossible to adjust the fourth operating clock CK4 before adjusting the third operating clock CK3 using the second operating clock CK2. For example, the second operating clock CK2, the third operating clock CK3, and the fourth operating clock CK4 may need to be adjusted sequentially, which may increase the time required for the synchronization operation of operating clocks CK1 to CK4. Figure 16 In the example embodiment shown, when the outputs of counters 942, 952 and 962 are sent to the lower-level delay chains 943, 953 and 963, the operation of synchronizing the operating clocks CK1 to CK4 by the delay chains 943, 953 and 963 can be performed simultaneously.

[0097] As an example, the first counter 942 can also send first information obtained by counting the delay time of a single repeater RPT (corresponding to the difference between the delay time of the first transmission circuit 921 and the delay time of the second transmission circuit 922) to the first delay chain 943, and also to the lower-level second delay chain 953 and third delay chain 963. Furthermore, the second counter 952 can send second information obtained by counting the delay time corresponding to the two repeater RPTs (corresponding to the difference between the delay time of the second transmission circuit 922 and the delay time of the third transmission circuit 923) to the second delay chain 953 and third delay chain 963.

[0098] When the clock generation circuit 910 generates the internal clock CK_int, and the clock tree 920 inputs the operating clocks CK1 to CK4 to the unit circuit 930, the first delay chain 943 can receive the first information from the first counter 942. Furthermore, the second delay chain 953 can receive the first information from the first counter 942 and can also receive the second information from the second counter 952. The first delay chain 943 can delay the second operating clock CK2 based on the first information by the delay time corresponding to a single repeater RPT. The second delay chain 953 can delay the third operating clock CK3 based on the first and second information by the delay time corresponding to three repeater RPTs. Therefore, the second operating clock CK2 and the third operating clock CK3 can be synchronized simultaneously with the first operating clock CK1. The third delay chain 963 can operate similarly to the second delay chain 953.

[0099] exist Figure 16 In the example embodiment shown, the second delay chain 953 can simultaneously receive first information and second information from the first counter 942 and the second counter 952. As an example, the second delay chain 953 may include a delay chain that delays the second operating clock CK2 according to the first information and a delay chain that delays the second operating clock CK2 according to the second information. Therefore, the second delay chain 953 can have a relatively larger area than the first delay chain 943. Similarly, the third delay chain 963 can have a larger area than the first delay chain 943 and the second delay chain 953.

[0100] Figures 17 to 20 This is a diagram illustrating the operation of a semiconductor device according to an example embodiment.

[0101] Reference Figure 17In the example embodiment, the semiconductor device 1000 can be implemented as a memory device capable of storing data. The clock generation circuit 1010 can use an external clock CK_ext to generate an internal clock CK_int, which can be input to the cell circuit 1030 via the clock tree 1020. The external clock CK_ext can be a clock input from the memory controller. The cell circuit 1030 can be connected to multiple pads (or "soldering pads") PADs. Multiple data signals DQ0 to DQ7 and data strobe signals DQS and DQSB can be input to and output from the cell circuit 1030 via the pads. At least one of the pads can be assigned as a dummy DMY. Furthermore, at least one of the pads can be assigned as a DMI pad DMI_P. The DMI pad DMI_P can be set according to predetermined bit units and can be configured to provide data bus inversion (DBI) functionality.

[0102] The clock tree 1020 may include first transmission circuits 1021 to fourth transmission circuits 1024, which may be connected to first unit circuits 1031 to fourth unit circuits 1034. At least a portion of the first unit circuits 1031 to fourth unit circuits 1034 may have different structures. In one example embodiment, the structure of each of the first unit circuits 1031 to fourth unit circuits 1034 may be determined based on signals input to and output from the pad PAD.

[0103] Reference Figure 18 The first unit circuit 1031 can serialize the first data D0 and the second data D1, and can output the serialized data. As an example, the first data D0 and the second data D1 can be input to a multiplexer MUX, which can alternately output the first data D0 and the second data D1 in response to a first operating clock CK1. The first data D0 and the second data D1 can be serialized and can be output as a first data signal DQ0 through a pad PAD. In an example embodiment, the frequency of the first operating clock CK1 can be twice the output frequency of each of the first data D0 and the second data D1.

[0104] Return to reference Figure 17At least one of the first transmission circuits 1021 to the fourth transmission circuit 1024 may have an output terminal not connected to the unit circuit 1030. As an example, a portion of the output terminal of the fourth transmission circuit 1024 may not be connected to the unit circuit 1030, and may output feedback signals FB1 and FB2. Feedback signals FB1 and FB2 may be input to the clock generation circuit 1010. As an example, the first feedback signal FB1 may be input to the duty cycle corrector (DCC), and the second feedback signal FB2 may be a signal providing feedback on the delay time from the internal clock CK_int until the actual data signals DQ0 to DQ7 are output, and may be input to the replication circuit of the clock generation circuit 1010.

[0105] The operation of the clock tree 1020 can be understood with reference to the foregoing example embodiments. The first comparator 1041 compares the first operating clock CK1 output by the first transmission circuit 1021 with the second operating clock CK2 output by the second transmission circuit 1022. The first counter 1042 counts the output of the first comparator 1041 and transmits the output (the result of the count) to the first delay chain 1043. The first delay chain 1043 can further delay the second operating clock CK2 based on the information received from the first counter 1042. Figure 17 The first delay chain 1043 in the example embodiment shown can delay the second operating clock CK2 by the delay time generated when the internal clock CK_int passes through a single repeater RPT. The operation of the second comparator 1051, the second counter 1052, and the second delay chain 1053, as well as the operation of the third comparator 1061, the third counter 1062, and the third delay chain 1063, can be understood with reference to the description of the first comparator 1041, the first counter 1042, and the first delay chain 1043.

[0106] In the following description, reference will be made to Figure 19 and Figure 20 The operation of the semiconductor device 1000 is described in more detail.

[0107] Reference Figure 19 This section describes the operations prior to adjusting the difference in delay times between operating clocks CK1 to CK4 in clock tree 1020. (Refer to...) Figure 19 The first operating clock CK1 can be a clock that is delayed by a first delay time TD1 relative to the internal clock CK_int, and the second operating clock CK2 can be a clock that is delayed by a second delay time TD2 relative to the internal clock CK_int. The first delay time TD1 can be greater than the second delay time TD2.

[0108] The first data signal DQ0 can be synchronized with the first operating clock CK1 and can be output; the data strobe signal DQS can be synchronized with the second operating clock CK2 and can be output. For example... Figure 19 As shown, because the phase of the first operating clock CK1 may not match the phase of the second operating clock CK2 due to the difference between the first delay time TD1 and the second delay time TD2, the first data signal DQ0 and the data strobe signal DQS may not be accurately synchronized with each other. To ensure accurate synchronization between the first data signal DQ0 and the data strobe signal DQS, the rising and falling edges of the data strobe signal DQS may need to be matched with those of the first data signal DQ0.

[0109] In one example embodiment, the first operating clock CK1 and the second operating clock CK2 can be synchronized with each other by delaying the second operating clock CK2 by the difference between the first delay time TD1 and the second delay time TD2 using the first delay chain 1043. (Refer to...) Figure 20 The first operating clock CK1 and the second operating clock CK2 can be synchronized with each other through the first delay chain 1043. Therefore, the second operating clock CK2 can be delayed by a first delay time TD1 relative to the internal clock CK_int, and the first data signal DQ0 and the data strobe signal DQS can be synchronized with each other, thereby improving the reliability of the semiconductor device 1000.

[0110] Figure 21 and Figure 22 This is a diagram illustrating a semiconductor device according to an example embodiment.

[0111] exist Figure 21 and Figure 22 In the example embodiments shown, each of semiconductor devices 1100 and 1200 can be implemented by a memory device. For example, Figure 21 The semiconductor device 1100 may include volatile dynamic random access memory (DRAM). Figure 22 The semiconductor device 1200 may include a non-volatile flash memory device. In addition to memory devices, the semiconductor devices 1100 and 1200 in the example embodiments can be widely used in devices that operate according to a specific internal clock.

[0112] Reference Figure 21Semiconductor device 1100 may include memory controller 1110 and memory device 1120, which may include a plurality of memory chips 1121 to 1123. In each of the plurality of memory chips 1121 to 1123, memory cells may be divided into a plurality of channels CH0 to CHn. Memory controller 1110 may input signals for controlling memory device 1120 (such as data signal DQ, command / address signal CMD / ADDR, and external clock CK_ext, for example) to memory device 1120.

[0113] The memory device 1120 may include the clock generation circuit, clock tree, etc., described in the foregoing example embodiments. The clock generation circuit may use an external clock CK_ext to generate an internal clock, and the clock tree may transmit the internal clock to the unit circuits, which operate in synchronization with the internal clock.

[0114] The internal clock input from the clock tree to the unit circuit can be delayed by a specific delay time from the internal clock generated by the clock generation circuit. At least a portion of the transmission path provided by the clock tree between the clock generation circuit and the unit circuit can have different delay times. In one example embodiment, the clock tree can compare a first delay time detected from the longest first transmission path with a second delay time detected from a relatively short second transmission path. The clock tree can increase the second delay time based on the first delay time, such that the difference in delay time between the internal clock output through the first transmission path and the internal clock output through the second transmission path can be reduced.

[0115] exist Figure 22 In the example embodiment shown, the semiconductor device 1200 may include a memory cell array 1210 and peripheral circuitry 1220. The memory cell array 1210 may include a plurality of memory blocks BLK. The peripheral circuitry 1220 may include a row decoder 1221, a page buffer 1222, input and output circuitry 1223, and control logic 1224. The row decoder 1221 can be connected to the memory cell array 1210 via a ground select line GSL, a word line WL, and a serial select line SSL. The page buffer 1222 can be connected to the memory cell array 1210 via a bit line BL.

[0116] Control logic 1224 may include the clock generation circuit, clock tree, etc., described in the foregoing example embodiments. The clock generation circuit may generate an internal clock using an external clock received from an external entity, and the clock tree may send the internal clock to circuitry operating in synchronization with the internal clock. The clock tree may provide multiple transmission paths with different delay times, and a delay compensation circuit for compensating for differences in delay times between transmission paths may be included in control logic 1224. The delay compensation circuit may compensate for delay time differences by increasing another delay time by referencing the longest delay time generated in the clock tree.

[0117] Figure 23 This is a block diagram illustrating an electronic device including a semiconductor device according to an example embodiment.

[0118] Reference Figure 23 The mobile system 2000 may include a camera 2100, a display 2200, an audio processing unit 2300, a modem 2400, DRAM 2500a and 2500b, flash memory devices 2600a and 2600b, input and output devices 2700a and 2700b, and an application processor 2800 (hereinafter, "AP").

[0119] The mobile system 2000 can be implemented as a laptop computer, portable terminal, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, the mobile system 2000 can be implemented as a server or personal computer.

[0120] Various components in the mobile system 2000 can operate in synchronization with a predetermined clock. For example, the display 2200 can display a screen according to a predetermined refresh rate and may include gate drivers, source drivers, etc., that operate according to the clock to achieve the refresh rate. Furthermore, DRAMs 2500a and 2500b and flash memory devices 2600a and 2600b can operate according to a predetermined clock, thereby storing and retrieving data or exchanging data with other external devices at a predetermined speed. Input and output devices 2700a and 2700b and application processor 2800 can also operate according to a predetermined clock.

[0121] The semiconductor devices disclosed in the embodiments herein can be applied to components that operate in synchronization with a clock in the mobile system 2000. For example, the semiconductor devices of the example embodiments can be applied to circuitry that generates an internal clock in the display 2200 and transmits the internal clock to a gate driver and / or a source driver. The semiconductor devices of the example embodiments can also be applied to input and output interfaces for exchanging image data between the camera 2100 and the AP 2800 and / or between the display 2200 and the AP 2800. Furthermore, the semiconductor devices of the example embodiments can also be applied to other components, including DRAMs 2500a and 2500b and flash memory devices 2600a and 2600b.

[0122] Camera 2100 can acquire still images or videos according to user control. Mobile system 2000 can use the still images / videos acquired by camera 2100 to obtain specific information, or mobile system 2000 can convert still images / videos into different types of data (such as text) and can store the data. Optionally, mobile system 2000 can recognize strings included in the still images / videos acquired by camera 2100 and can provide text or audio translations corresponding to the strings. Therefore, the use of camera 2100 in mobile system 2000 has become increasingly diversified. In one example embodiment, camera 2100 can send data (such as still images / videos) to AP 2800 according to a MIPI-based D-Phy or C-Phy interface.

[0123] Camera 2100 may include multiple cameras with different fields of view or aperture values. In addition to cameras that generate actual images by imaging a target, camera 2100 may also include cameras that can generate depth images using depth information of the target and / or the background.

[0124] Display 2200 can be implemented using liquid crystal display (LCD), organic light-emitting diode (OLED) display, active-matrix organic light-emitting diode (AM-OLED), plasma display panel (PDP), field emission display (FED), electronic paper, etc. In one example embodiment, display 2200 can be used as an input device for mobile system 2000 by providing touchscreen functionality. Furthermore, display 2200 can be integrated with a fingerprint sensor, etc., and can provide security functions for mobile system 2000. In one example embodiment, AP 2800 can send image data to be displayed on display 2200 via a MIPI-based D-Phy or C-Phy interface.

[0125] The audio processing unit 2300 can process audio data stored in flash memory devices 2600a and 2600b, or it can process audio data included in content received from an external entity via modem 2400 or input and output devices 2700a and 2700b. For example, the audio processing unit 2300 can perform various processes on the audio data (such as encoding / decoding, amplification, and noise filtering).

[0126] The modem 2400 can modulate and transmit signals for sending and receiving wired / wireless data, and can also recover the original signal by demodulating signals received from an external entity. Input / output devices 2700a and 2700b can be devices that provide digital input and output, and may include ports capable of connecting to external recording media, input devices (such as touchscreens or mechanical buttons), output devices that can output vibrations via haptic means, etc. In one example embodiment, input and output devices 2700a and 2700b can be connected to external recording media via ports such as USB, Lightning cable, SD card, microSD card, DVD, network adapter, etc.

[0127] AP 2800 can control the overall operation of mobile system 2000. Specifically, AP 2800 can control display 2200, allowing a portion of the content stored in flash memory devices 2600a and 2600b to be displayed on the screen. Furthermore, when user input is received via input and output devices 2700a and 2700b, AP 2800 can perform control operations corresponding to the user input.

[0128] The AP 2800 can be provided as a system-on-chip (SoC) that drives applications, operating systems (OS), etc. Furthermore, the AP 2800 can be included in a single semiconductor package along with other devices included in the mobile system, such as DRAMs 2500a and 2500b, flash memory 2620, and / or memory controller 2610. For example, at least one device different from the AP 2800 can be provided in the form of a package such as a stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), wafer-level processing stack package (WSP), etc. The kernel of the operating system driving the AP 2800 may include an input / output scheduler and a device driver for controlling the flash memory devices 2600a and 2600b. The device driver can control the access performance of the flash memory devices 2600a and 2600b by referring to the number of synchronization queues managed by the input and output scheduler, or it can control the CPU mode, dynamic voltage and frequency scaling (DVFS) level, etc. in the SoC.

[0129] In one example embodiment, the AP 2800 may include a processor block and various other peripheral components connected to the processor block via a system bus. The processor block performs calculations or drives applications and / or an operating system. Peripheral components may include a memory controller, internal memory, a power management block, an error detection block, and a monitoring block. The processor block may include one or more cores. When multiple cores are included in the processor block, each core may include cache memory, and a common cache shared by the cores may be included in the processor block.

[0130] In one example embodiment, AP 2800 may include accelerator block 2820 as dedicated circuitry for AI data computation. Optionally, in the example embodiment, a separate accelerator chip may be provided separately from AP 2800, and DRAM 2500b may be additionally connected to accelerator block 2820 or the accelerator chip. Accelerator block 2820 may be a functional block specifically performing specific functions of AP 2800, and may include a graphics processing unit (GPU) specifically for performing graphics data processing, a neural processing unit (NPU) specifically for performing AI computation and inference, and a data processing unit (DPU) specifically for performing data transmission.

[0131] In one example embodiment, the mobile system 2000 may include multiple DRAMs 2500a and 2500b. In one example embodiment, the AP 2800 may include a controller 2810 for controlling the DRAMs 2500a and 2500b, wherein the DRAM 2500a may be directly connected to the controller 2810 of the AP 2800.

[0132] The AP 2800 can control the DRAM by setting a JEDEC-compliant command and mode register set (MRS). It can configure the specifications and functions required by the Mobile System 2000 (such as low voltage / high speed / reliability and DRAM interface protocols for CRC / ECC) and can perform communication. For example, the AP 2800 can communicate with DRAM 2500a through an interface compliant with JEDEC standards (such as LPDDR4 and LPDDR5). Optionally, the AP 2800 can set a new DRAM interface protocol for accelerator chips that can be arranged separately from the accelerator block 2820 or the AP 2800 to control DRAM 2500b for the accelerator, which has a higher bandwidth than DRAM 2500a, and the AP 2800 can perform communication.

[0133] Figure 23 Only DRAMs 2500a and 2500b are shown, but the example embodiment of mobile system 2000 is not limited to this, and depending on voltage conditions and the bandwidth and response speed of AP 2800 and / or accelerator block 2820, memories other than DRAMs 2500a and 2500b may be included in mobile system 2000. As an example, controller 2810 and / or accelerator block 2820 can control various types of memories (such as PRAM, SRAM, MRAM, RRAM, FRAM, hybrid RAM, etc.). DRAMs 2500a and 2500b may have lower latency than input / output devices 2700a and 2700b or flash memory devices 2600a and 2600b, and may also have higher bandwidth than input / output devices 2700a and 2700b or flash memory devices 2600a and 2600b. DRAM 2500a and 2500b can be initialized when the mobile system 2000 is powered on, and when the operating system and application data are loaded, DRAM 2500a and 2500b can be used as temporary storage locations for operating system and application data or as execution space for various software code.

[0134] In DRAMs 2500a and 2500b, addition / subtraction / multiplication / division arithmetic operations, vector operations, address operations, and / or FFT operation data can be stored. In another example embodiment, DRAMs 2500a and 2500b can be provided as processing in memory (PIM) equipped with computational capabilities. For example, functions to be used for inference in DRAMs 2500a and 2500b can be executed. Inference can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm can include training steps to learn a model from various data and inference steps to identify data using the learned model. For example, functions used for inference can include hyperbolic tangent functions, sigmoid functions, and corrected linear unit (ReLU) functions.

[0135] As an example embodiment, an image obtained by a user through a camera can be signal processed and stored in DRAM 2500b. The accelerator block 2820 or accelerator chip can use the data stored in DRAM 2500b and functions for inference to perform AI data computation for recognizing the data.

[0136] According to an example embodiment, the mobile system 2000 may include multiple storage devices or multiple flash memory devices 2600a and 2600b having a capacity larger than that of DRAMs 2500a and 2500b. Each of the flash memory devices 2600a and 2600b may include a memory controller 2610 and a flash memory 2620. The memory controller 2610 may receive control commands and data from the AP 2800 and may write data to the flash memory 2620 in response to control commands, and / or may read data stored in the flash memory 2620 and may send data to the AP 2800. In one example embodiment, each of the flash memory devices 2600a and 2600b may be Figure 22 The semiconductor device 1200 is included. In this case, the memory controller 2610 can be connected to... Figure 22 The peripheral circuit 1220 corresponds to the flash memory 2620, which can be used with... Figure 22 The memory cell array 1210 corresponds to this. In one example embodiment, the flash memory 2620 can be associated with... Figure 22 The semiconductor device 1200 in the middle corresponds to this.

[0137] According to an example embodiment, the accelerator block 2820 or accelerator chip can use flash memory devices 2600a and 2600b to perform training steps and AI data computations. In one example embodiment, the computational logic capable of performing predetermined computations can be implemented in a memory controller 2610 in the flash memory devices 2600a and 2600b. This computational logic can use data stored in flash memory 2620 to perform at least a portion of the training steps and inference AI data computations performed by AP 2800 and / or accelerator block 2820.

[0138] In one example embodiment, AP 2800 may include interface 2830, so flash memory devices 2600a and 2600b can be directly connected to AP 2800. For example, AP 2800 may be implemented as a SoC, and flash memory device 2600a may be implemented as a separate chip from AP 2800, with AP 2800 and flash memory device 2600a mounted in a single package. However, these example embodiments are not limited to this, and multiple flash memory devices 2600a and 2600b may be electrically connected to mobile system 2000 via connectors.

[0139] Flash memory devices 2600a and 2600b can store data such as still images / videos acquired by camera 2100 and / or data received via a communication network and / or ports included in input and output devices 2700a and 2700b. For example, flash memory devices 2600a and 2600b can store augmented reality / virtual reality content, high-definition (HD) content, or ultra-high-definition (UHD) content.

[0140] In the exemplary embodiments disclosed above, at least one of DRAMs 2500a and 2500b and flash memory devices 2600a and 2600b can be implemented as a memory device. For example, at least one of DRAMs 2500a and 2500b and flash memory devices 2600a and 2600b can perform verification operations at predetermined intervals, and can perform refresh operations and / or repair operations if necessary. Therefore, the operational performance and reliability of the mobile system 2000 can be improved.

[0141] According to the foregoing example embodiments, the transmission circuit of the semiconductor device for transmitting the internal clock to the unit circuit can be included in a clock tree. Among the transmission circuits, the internal clock of the transmission circuit with the longest transmission path can be used as a reference clock for adjusting the internal clocks of other transmission circuits, and the clock deviation between the internal clocks input to the unit circuit can be reduced. Furthermore, by reducing the number of devices implementing the clock tree, the integration density of the semiconductor device can be improved.

[0142] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The internal clock generation circuit is configured to receive an external clock and generate an internal clock. Multiple unit circuits are configured to have a first unit circuit and a second unit circuit, the first unit circuit and the second unit circuit operating in synchronization with the internal clock; Multiple transmission circuits, including: A first transmission circuit is configured to provide a first transmission path having a first delay time and is connected between the first unit circuit and the internal clock generation circuit; and A second transmission circuit is configured to provide a second transmission path having a second delay time different from the first delay time, and is connected between the second unit circuit and the internal clock generation circuit; and The delay compensation circuit is configured to: compare a first operating clock input to the first unit circuit via the first transmission path with a second operating clock input to the second unit circuit via the second transmission path, and adjust the second delay time such that the adjusted second delay time matches the first delay time. Wherein, the first delay time is the longest delay time among the delay times between the internal clock generation circuit and the plurality of unit circuits.

2. The semiconductor device according to claim 1, wherein, The plurality of unit circuits include a plurality of input / output circuits connected to a plurality of pads, each input / output circuit being configured to input and output data signals or data strobe signals.

3. The semiconductor device according to claim 2, wherein, The internal clock generation circuit is configured to receive the external clock from the memory controller, and The plurality of unit circuits are configured to input / output the data signal or the data strobe signal through the plurality of pads in response to the internal clock.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The delay compensation circuit includes a comparator and a counter, the comparator being configured to compare the first operating clock with the second operating clock, and the counter being configured to count the output of the comparator.

5. The semiconductor device according to claim 4, wherein, The delay compensation circuit includes a delay chain configured to adjust the second delay time to match the first delay time based on the output of the counter.

6. The semiconductor device according to claim 4, wherein, The internal clock generation circuit includes: A clock driver is configured to output the internal clock; and A delay chain, connected to the output of the clock driver, is configured to adjust the second delay time to match the first delay time based on the output of the counter.

7. The semiconductor device according to any one of claims 1 to 3, in, The plurality of transmission circuits further includes a third transmission circuit configured to provide a third transmission path having a third delay time and connected to a third unit circuit, the third delay time being different from the first delay time and the second delay time, and The delay compensation circuit is configured to compare the third operating clock input to the third unit circuit with the second operating clock, and adjust the third delay time to match the second delay time.

8. The semiconductor device according to claim 7, wherein, The delay compensation circuit is configured to compare the third operating clock with the second operating clock having the adjusted second delay time.

9. The semiconductor device according to any one of claims 1 to 3, wherein, Among the plurality of unit circuits, the number of unit circuits connected to the first transmission circuit and the number of unit circuits connected to the second transmission circuit are different from each other.

10. The semiconductor device according to any one of claims 1 to 3, wherein, Among the plurality of unit circuits, the number of unit circuits connected to the first transmission circuit and the number of unit circuits connected to the second transmission circuit are the same.

11. The semiconductor device according to any one of claims 1 to 3, wherein, The internal clock generation circuit includes: The delay chain is configured to generate the internal clock by delaying the external clock; A replication circuit is configured to replicate the delay attributes of the first transmission circuit and the second transmission circuit; and A phase detector is configured to compare the phase of the output of the replication circuit with that of the external clock.

12. The semiconductor device according to any one of claims 1 to 3, in, The plurality of transmission circuits include a plurality of repeaters, which are configured to provide multiple transmission paths including the first transmission path and the second transmission path, and The number of repeaters providing the first transmission path is greater than the number of repeaters providing the second transmission path.

13. The semiconductor device according to claim 12, wherein, Of the multiple transmission paths, the first transmission path has the largest number of repeaters.

14. A semiconductor device, comprising: Multiple input / output circuits are configured to input and output data signals according to a clock signal; A delay-locked loop circuit is configured to generate the clock signal; A plurality of repeaters are connected between the delay-locked loop circuit and the plurality of input / output circuits and configured to send the clock signal to the plurality of input / output circuits, wherein the plurality of repeaters form a plurality of transmission circuits, and the plurality of transmission circuits include a first transmission circuit and a second transmission circuit, wherein the first transmission circuit is configured to provide a first transmission path having a first delay time and is connected between the first input / output circuit and the delay-locked loop circuit, and the second transmission circuit is configured to provide a second transmission path having a second delay time different from the first delay time and is connected between the second input / output circuit and the delay-locked loop circuit; A comparator, connected between a first input / output circuit and a second input / output circuit, is configured to compare a first clock signal input to the first input / output circuit via the first transmission path with a second clock signal input to the second input / output circuit via the second transmission path; and The delay chain is configured to adjust the second delay time based on the comparator's output so that the first clock signal and the second clock signal have the same phase. Wherein, the first delay time is the longest delay time among the delay times between the delay-locked loop circuit and the plurality of input / output circuits.

15. The semiconductor device according to claim 14, wherein, The plurality of repeaters includes a first repeater and a second repeater, the second repeater having an input terminal connected to the output terminal of the first repeater, and the delay chain being connected between the first repeater and the second repeater.

16. The semiconductor device according to claim 14, in, The first transmission circuit does not include the delay chain, while the second transmission circuit does include the delay chain.

17. The semiconductor device according to claim 16, wherein, In each of the plurality of transmission circuits, the plurality of repeaters are connected to each other via an H-tree structure.

18. The semiconductor device according to claim 16, wherein, The second transmission circuit is connected between the first transmission circuit and the delay-locked loop circuit.

19. The semiconductor device according to any one of claims 14 to 18, wherein, The delay chain is configured to delay the phase of the second clock signal so that the first clock signal and the second clock signal have the same phase.

20. A semiconductor device, comprising: The clock generation circuit is configured to generate a clock signal; The first delay circuit is configured to delay the clock signal by a first delay time and input the clock signal delayed by the first delay time into the first unit circuit. The second delay circuit is configured to delay the clock signal by a second delay time shorter than the first delay time, and to input the clock signal delayed by the second delay time into a second unit circuit different from the first unit circuit. as well as The delay compensation circuit is configured to: compare the first delay time with the second delay time, and increase the second delay time to obtain an increased second delay time that matches the first delay time. Wherein, the first delay time is the longest delay time among the delay times between the clock generating circuit and the plurality of unit circuits including the first unit circuit and the second unit circuit.

Images