Storage device and method for managing power supply in a storage device

Abstract

A storage device and a method for managing power in a storage device are provided. The storage device can include a connector including a power management pin, a detector circuit configured to detect a transition of a power management signal received on the power management pin, and a power management circuit capable of configuring power to at least a portion of the storage device based at least in part on the detector circuit detecting the transition of the power management signal. The connector can also include a port enable pin, and the power management circuit can be configured to be disabled based at least in part on a state of the port enable pin. The storage device can include a connector including a power management pin, a non-volatile memory, and a power management circuit configured to operate in a first power management mode based on determining a first state of the non-volatile memory.

Description

[0001] This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 010,041, filed April 14, 2020, entitled “Systems, Methods and Apparatus for Supporting Multiple Connectors on Storage Devices,” and U.S. Patent Application No. 16 / 926,636, filed July 10, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to storage devices, and more specifically to systems, methods and apparatus for supporting multiple connectors on a storage device. Background Technology

[0003] The storage device can be connected to the host system via a connector. The connector may include power management pins that allow the storage device to configure power in response to power management signals applied to the power management pins.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background art of the invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] A storage device may include: a connector including a power management pin; detector circuitry configured to detect a transition of a power management signal received on the power management pin; and power management circuitry capable of configuring power to at least a portion of the storage device based at least partially on the detection of the transition of the power management signal by the detector circuitry. The connector may also include a dual-port enable pin, and the power management circuitry may be configured to be disabled at least partially based on the state of the dual-port enable pin. The storage device may also include non-volatile memory, and the power management circuitry may be configured to be disabled or enabled at least partially based on the state of the non-volatile memory (e.g., by firmware). The detector circuitry may be configured to latch the power management signal at least partially based on the state of the non-volatile memory. The power management pin may include a power disable pin, and the power management circuitry may be capable of disabling power to at least a portion of the storage device based on the detection of a transition of the power management signal by the detector circuitry.

[0006] A storage device may include: a connector including power management pins; non-volatile memory; and power management circuitry configured to operate in a first power management mode based on determining a first state of the non-volatile memory. In the first power management mode, the power management circuitry may configure power to at least a portion of the storage device based at least in part on a power management signal received on the power management pins. The storage device may further include: detector circuitry configured to detect a transition of the power management signal received on the power management pins, and the power management circuitry may disable power to at least a portion of the storage device based at least in part on the detection of the transition of the power management signal by the detector circuitry. The connector may further include a dual-port enable pin, and the power management circuitry is configured to disable power to at least a portion of the storage device based at least in part on the state of the dual-port enable pin. The storage device may be configured as a U.3 storage device in the first power management mode. The power management pins may include power disable pins. The power management circuitry may be configured to operate in a second power management mode based on determining a second state of the non-volatile memory. In the second power management mode, the power management circuitry may disable power to at least a portion of the storage device. The storage device can be configured as a U.2 storage device in the second power management mode.

[0007] A method may include: connecting a storage device to a host via a connector; detecting a transition of a power management signal received from the host via the connector at the storage device; and configuring power to at least a portion of the storage device based at least in part on the detected transition of the power management signal. The step of configuring power to at least a portion of the storage device may include: disabling power to at least a portion of the storage device. Power to at least a portion of the storage device may be configured based at least in part on the state of non-volatile memory. The method may further include: latching the power management signal based on a reset signal. Power to at least a portion of the storage device may be configured at least in part based on the state of a dual-port enable signal received from the host via the connector at the storage device. The method may further include: latching the dual-port enable signal based on a reset signal. Attached Figure Description

[0008] The accompanying drawings are not necessarily drawn to scale, and throughout the drawings, elements with similar structures or functions are generally designated by the same reference numerals for illustrative purposes. The drawings are intended only to facilitate the description of the various embodiments described herein. The drawings do not depict every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent obscurity, not all components, connections, etc., may be shown, and not all components may have reference numerals. However, the pattern of component configuration can be readily understood from the drawings. The drawings, together with the specification, illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0009] Figure 1 An example embodiment of a storage device with detector circuitry according to the present disclosure is shown.

[0010] Figure 2 An example embodiment of a storage device with configurable power management according to the present disclosure is shown.

[0011] Figure 3 A truth table is shown for an example embodiment of a storage device with transition detection and configurable power management according to the present disclosure.

[0012] Figure 4 An example embodiment of a detector circuit for a power-off signal of a storage device according to the present disclosure is shown.

[0013] Figure 5 Another example embodiment of a detector circuit for a power-off signal of a storage device according to the present disclosure is shown.

[0014] Figure 6 An embodiment of a sampling circuit according to this disclosure is shown, which can be used, for example, to generate a dual-port enable signal.

[0015] Figure 7 A timing diagram of an example embodiment of a method for generating a dual-port enable valid signal according to the present disclosure is shown.

[0016] Figure 8 A timing diagram of an example embodiment of the method for sampling a power-off signal according to the present disclosure is shown.

[0017] Figure 9 An embodiment of a method for managing power in a storage device according to the present disclosure is shown. Detailed Implementation

[0018] In some embodiments, the storage device may manage power within the device in response to detecting a transition in a power management signal received from the host via a connector. In some embodiments, detecting a transition in the power management signal may enable the storage device to be compatible with different host connectors that have different pin definitions, which would otherwise be incompatible with different host connectors. For example, a first host connector may have a power-off pin defined as a low (i.e., low-level) active signal. A second host connector may use the same (or mechanically compatible) connector, but define the same power-off pin as a high (i.e., high-level) active signal. This may cause a storage device designed for the second host connector to behave incorrectly (e.g., enter a power-off state) when inserted into the first host connector.

[0019] However, in some embodiments of the first host connector, the power-off pin may always be pulled high (e.g., it may not have any transition), while in some embodiments of the second host connector, the power-off signal is active high and may have a transition from low to high. Therefore, by detecting the transition of the power-off signal, the storage device can distinguish between a valid power-off event on the second host connector and a non-existent power-off event on the first host connector.

[0020] In some embodiments, the power management features of the storage device can be configured in response to the state of the non-volatile memory. For example, the storage device may have power management circuitry that can enable or disable power to at least a portion of the storage device in response to the state of configuration bits in the non-volatile memory. In some embodiments, such configurable power management features can enable a single storage device to be programmed or configured for use, for example, with different types of host connectors.

[0021] The features described in this disclosure may have independent utility and may be implemented individually, and not every feature can be utilized in every embodiment. Furthermore, the features may also be implemented in various combinations, some of which may synergistically amplify the benefits of the various principles.

[0022] Some example embodiments of systems, processes, methods, etc., illustrating details of some possible implementations according to this disclosure are described below. These examples are provided to illustrate the principles of this disclosure, but the principles are not limited to these embodiments, implementation details, etc.

[0023] Figure 1 An example embodiment of a storage device with detector circuitry according to the present disclosure is shown. Figure 1 The storage device 100 shown may include a connector 102, a detector circuit 104, a power management circuit 106, a storage device controller 108, and a storage medium 110. The connector 102 may include a power management pin 112.

[0024] Connector 102 can be implemented using any type of standard or non-standard connector that can be used to connect a storage device to a host. Some examples may include connectors described in the SFF-8639 specification (such as connectors referred to as U.2 and / or U.3 (SFF-TA-1001 specification) connectors), expandable connectors (such as connectors described in the SFF-TA-1002 specification), M.2 connectors, any connector that can be used with any storage interconnect (such as connectors used with Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), and / or Serial Connected SCSI (SAS), etc.), and / or any other connector with pins of any mechanical and / or electrical configuration and / or any configuration.

[0025] Detector circuit 104 can be implemented using any analog and / or digital hardware, software, and / or any combination thereof, as described above, capable of detecting transitions in power management signals received on power management pin 112. As described in more detail below, for example, in some embodiments where the connector can be implemented as a U.3 connector, detector circuit 104 can detect a low-to-high transition of the PWRDIS signal on pin P3 of the connector to identify a valid power-off event.

[0026] The power management circuit 106 may be implemented using any analog and / or digital hardware, software, and / or any combination thereof that can, for example, enable and / or disable or reduce power to all or any part of the storage device 100. For example, the power management circuit 106 may include various power distribution and / or regulation circuits to receive power from the host through various additional pins of the connector 102 and distribute power throughout the storage device 100.

[0027] Storage medium 110 can be implemented using magnetic, solid-state, optical, and / or any other type of data storage technology or a combination thereof. Therefore, storage device 100 can be implemented as a hard disk drive (HDD), solid-state drive (SSD), optical disk drive (ODD), and / or any other type of storage device.

[0028] The storage device controller 108 can be implemented using any hardware, software, and / or any combination thereof that can control the storage and other functions of the storage device 100. For example, in some embodiments where flash memory (such as NAND memory) can be used as the storage medium 110, the storage device controller 108 may include a flash translation layer (FTL).

[0029] Storage device 100 may include Figure 1Additional components and / or sub-components and / or interconnections between additional components and sub-components are not shown. For example, some embodiments may include one or more communication interfaces (e.g., network interfaces such as Ethernet, Fibre Channel, InfiniBand, etc.), storage or other interconnects and / or protocols (e.g., PCIe, SAS, SATA, NVMe, NVMe over Fabric, NVMe-oF), etc.) to interface storage device controllers and / or other components to various pins of connector 102. As another example, some embodiments may include one or more computing components (e.g., field-programmable gate arrays (FPGAs), embedded graphics processors (GPUs), etc.).

[0030] Despite Figure 1 Some components may be shown as separate components, but some or all of the components may be integrated into other components and / or distributed among other components.

[0031] Figure 2 An example embodiment of a storage device with configurable power management according to the present disclosure is shown. Figure 2 The storage device 114 shown may include, in conjunction with, Figure 1 The components shown in the embodiments are similar to some of the components (such as connector 102 with power management pin 112, power management circuitry 106, storage device controller 108, and storage medium 110). However, Figure 2 The storage device 114 shown may also include a non-volatile memory (NVM) 116, which can be used to configure and / or reconfigure any power management features of the storage device 114. For example, in some embodiments, the NVM 116 can be used to control the power management circuitry 106 to enable or disable power to all or one or more portions of the storage device.

[0032] The NVM 116 can be implemented using any technology that can store any power management features or configuration of the storage device 114. Some examples may include one or more bits of read-only memory (ROM), programmable read-only memory (PROM), battery-supported random access memory (RAM), and / or flash memory, etc. Some additional examples may include one or more fuses, cut traces, jumpers, DIP switches, headers, wires inserted into or removed from the board, etc.

[0033] In some embodiments, depending on the implementation details, configuring power management features based on non-volatile memory allows the storage device to be configured and / or reconfigured anywhere along the supply chain (e.g., through manufacturers, distributors, users, etc.). For example, if NVM is implemented using one or more bits of electrically reprogrammable memory (such as flash memory), manufacturers, distributors, users, etc., can reprogram the power management configuration of the storage device by accessing the flash memory via any technology (such as a firmware update utility). Furthermore, storage devices with configurable power management can improve economies of scale by enabling manufacturers to produce more devices of a single design and program them into different types of devices.

[0034] Figure 3 A truth table is shown for an example embodiment of a storage device with signal transition detection and configurable power management according to this disclosure. The description pertains to a storage device that can be configured to be used with a host having a U.3 connector. Figure 3 The embodiments shown are not limited to these exemplary details.

[0035] In some embodiments, the U.2 host connector can be configured for use with the SATA Express specification, which defines pin P3 of the connector as a low active clock request signal (CLKREQ#). When identified (low), the CLKREQ# signal can cause a storage device inserted into the connector to enter a power-disabled state. In some embodiments, pin P3 of the U.2 host connector can be permanently pulled high by the host to prevent U.2 storage devices inserted into the U.2 host connector from entering a power-disabled state. In some embodiments, for hosts that may not be SATA-based (e.g., SAS or NVMe-based), pin P3 of the U.2 host connector can be pulled high to disable the power-disabled feature by default.

[0036] In some embodiments, the U.3 host connector may be configured with a connector pin P3 defined as having a high active power disabled signal (PWRDIS). Therefore, if a U.3 storage device is inserted into the U.2 host connector, the U.3 storage device may incorrectly operate by entering a power disabled state in response to a high logic level on pin P3 of the connector. Therefore, separate U.2 and U.3 storage devices can be used to provide correct operation with both the U.2 and U.3 host connectors. In some embodiments, depending on the implementation details, this can increase the quantity of device types that manufacturers, distributors, users, etc., may need to manufacture, stock, etc.

[0037] Furthermore, in some embodiments, the dual-port feature of the storage device can complicate the implementation of power management features. For example, in some embodiments, power-disabled or other power management features may be disabled when the storage device is configured for dual-port operation. For instance, because dual-port operation can be part of a high-availability configuration, power management may be disabled, and in some implementations, the high-availability configuration may be inconsistent with a power-disabled state. Therefore, storage devices with dual-port enabled versions of each of the U.2 and / or U.3 versions of the storage device can further increase the number of device types that manufacturers, distributors, users, etc., may need to manufacture, stock, etc.

[0038] In some embodiments, according to the details of the implementation, the storage device with signal transition detection and configurable power management according to the present disclosure enables a single storage device to operate correctly in both the U.2 host connector and the U.3 host connector, while also enabling both single-port and dual-port configurations using the same device.

[0039] For example, in order to implement Figure 3 Features shown in the figure, such as Figure 1 As shown in the embodiments illustrated, embodiments of the storage device may implement detector circuitry to detect transitions in the PWRDIS signal on pin P3 of the U.3 connector. Such embodiments may also be based on, for example... Figure 2 The NVM cell programming state shown in the embodiment enables or disables the power management circuitry.

[0040] Refer again Figure 3 Embodiments of the storage device can operate in response to the states of pins P3 and E25, as shown in the column labeled "Operation," depending on the programming state of the NVM cell. Specifically, the NVM cell can be programmed to a first state to configure the storage device as a U.2 storage device. Alternatively, the NVM cell can be programmed to a second state to configure the storage device as a U.3 storage device. Pin E25 can be defined as a low-active dual-port enable signal (DualPortEn#) for both the U.2 and U.3 devices and the host connector. When the storage device is configured as a U.2 device, pin P3 can be defined as a low-active clock request signal (CLKREQ#), and when the storage device is configured as a U.3 device, pin P3 can be defined as a high-active power disable signal (PWRDIS).

[0041] Reference Figure 3The second line, where both pins P3 (PWRDIS / CLKREQ#) and E25 (DualPortEn#) are low, allows the storage device to operate in dual-port mode with power management disabled, regardless of whether the device is configured as a U.2 or U.3 device by the NVM unit. In some embodiments that may not be SATA-based (e.g., SAS and / or NVMe-based), the NVM unit's state may be ignored, for example, because the NVM unit's state may not be applicable. In some implementations, pin P3 may be sampled during the low-to-high transition of the PCIe reset signal (PERST#).

[0042] Reference Figure 3 The third line, where pin P3 (PWRDIS / CLKREQ#) is low and E25 (DualPortEn#) is high, allows the storage device to operate in single-port mode with power management disabled, regardless of whether the device is configured as a U.2 device or a U.3 device by the NVM unit.

[0043] Reference Figure 3 The fourth line, where pin P3 (PWRDIS / CLKREQ#) is high and E25 (DualPortEn#) is low, allows the storage device to operate in dual-port mode with power management disabled, regardless of whether the device is configured as a U.2 device or a U.3 device by the NVM unit.

[0044] Reference Figure 3 In the fifth line, where both pins P3 (PWRDIS / CLKREQ#) and E25 (DualPortEn#) are high, the memory device can operate in single-port mode, regardless of whether the device is configured as a U.2 or U.3 device by the NVM cell. If the device is configured as a U.2 device, power management can be disabled. However, if the device is configured as a U.3 device, power management can be enabled, and the device can enter a power-disabled state in response to detecting a low-to-high transition of the PWRDIS signal.

[0045] Therefore, in some embodiments, depending on the implementation details, such as Figure 3 The storage device shown in the diagram can operate correctly as a U.3 storage device when the U.3 host connector is inserted (e.g., appropriate power management in response to the PWRDIS signal), while remaining operational when the U.2 host connector is inserted (without entering a power-off state).

[0046] Figure 4 An example embodiment of a detector circuit for a power-off signal of a storage device according to the present disclosure is shown. Figure 4The circuit 120 shown may include an input terminal 122 for receiving a power-disabled input signal (PWRDIS), which may be filtered by a filter circuit including resistors R1, R2 and capacitor C1. For example, the PWRDIS signal may be received from a power management pin on a connector (e.g., pin P3 on a U.3 connector). The filtered input signal VD_IN may be applied to one input of a 3-input AND gate 126 via a complex programmable logic device (CPLD) 124 and as VD_OUT. The output of the AND gate may be applied to the G input of a D flip-flop 128, which may provide an output power-enabled signal (CHIP_EN) via its D terminal. The S terminal of the D flip-flop 128 is grounded. A power management enable / GPIO signal (power management enable) may be applied to a second input of the 3-input AND gate 126, and a dual-port enable valid signal (DualPortEN_Valid) may be applied to a third input of the 3-input AND gate 126.

[0047] In some embodiments, the input terminal 122, the filter circuit, the CPLD 124, and the D flip-flop 128 may be part of existing circuitry in the storage device (e.g., the input terminal 122, the filter circuit, the CPLD 124, and the D flip-flop 128 may be used as...). Figure 1 (A portion of the storage device controller 108 shown). Therefore... Figure 4 The detector circuit 120 shown can acquire the existing signal VD_OUT and qualify it with a power management enable signal and a dual-port enable signal before VD_OUT is latched by the flip-flop 128.

[0048] The CHIP_EN signal can disable power to all or some parts of the storage device. For example, the CHIP_EN signal can be applied as a gate signal to a power management circuit that receives power from the host via a connector pin and distributes power throughout the storage device.

[0049] For example, the power management enable signal can be generated by the firmware in the storage device based on the state of the configuration bits in the registers in the NVM. Therefore, for example, as... Figure 3 As shown, in some embodiments, the power management enable signal enables circuit 120 to be used to configure the storage device as a U.2 device or a U.3 device.

[0050] The DualPortEN_Valid signal can be generated, for example, by reading the state of the dual-port enable pin on the connector (e.g., pin E25 on a U.3 connector) directly or via an inverter. Alternatively, as described in more detail below, the DualPortEN_Valid signal can be generated, for example, by latching the state of the dual-port enable pin on the connector in response to a reset signal.

[0051] Therefore, in some embodiments, the DualPortEN_Valid signal can provide a single-port indication to the power management circuitry, which can be used to qualify pin P3 only when the memory device is in a single-port configuration. For example, as Figure 3 As shown, in a two-port configuration, pin P3 can be ignored. (See also: Regarding...) Figure 3 As described, in some embodiments, the power-disable feature may be available only in a single-port configuration. For a two-port configuration, for example, power-disable may not be supported because it may be inconsistent with high-availability operation. Therefore, in some embodiments, when the storage device operates in a single-port configuration, AND gate 126 may only enable the PWRDIS signal to be latched by flip-flop 128.

[0052] Figure 5 Another example embodiment of a detector circuit for a power-off signal of a storage device according to the present disclosure is shown. Figure 5 The circuit 130 shown may include, with Figure 4 The components shown in the embodiments are similar to some of the components. However, in Figure 5 In the embodiment shown, AND gate 132 can be implemented as a 2-input AND gate, and the power management enable signal can instead be applied to the D input of D flip-flop 134 in CPLD 136 via resistor R3. VD_OUT can be output from the Q input of D flip-flop 134. In this embodiment, the PWRDIS signal can be applied as a clock input to flip-flop 134. Therefore, the state of the power management enable signal can be latched on the low-to-high transition of the PWRDIS signal, which allows circuit 130 to detect the low-to-high transition of the PWRDIS signal, which can be used to enter a power-off state, but is limited by the state of the power management enable signal. Therefore, in contrast to the constant high logic level on the U.2 host connector, when implemented in a U.3 memory device, circuit 130 allows the memory device to correctly determine that the memory device is connected to the U.3 host connector, and thus determine that a high logic level on the PWRDIS pin signal indicates a valid power-off event.

[0053] In some embodiments, depending on the implementation details, either of detector circuits 120 and / or 130 may be implemented as, for example, a dongle or add-on board that can be attached to an existing circuit board of the storage device. Therefore, in some embodiments, an existing storage device can be converted to provide power management reconfiguration and / or proper power disable and / or dual-port operation with relatively low impact on manufacturing and / or modification operations. Furthermore, in some embodiments, depending on the implementation details, either of detector circuits 120 and / or 130 may be integrated into a new design with little or no increase in cost, development time, etc.

[0054] Figure 6 An embodiment of a sampling circuit according to this disclosure is shown, which can be used, for example, to generate a dual-port enable signal. Figure 6 The circuit 140 shown may include an input terminal 142 for receiving, for example, a low-active PCIe reset signal PERST# from a pin of the connector. After being filtered by a filter circuit including resistors R4, R5, and capacitor C2, the PERST# signal may be applied to the clock input of the D flip-flop 144 in the CPLD 146. For example, a dual-port enable signal (DualPortEN#) from a dual-port enable pin on the connector (e.g., pin E25 on a U.2 or U.3 connector) may be applied as a D input to the flip-flop 144 via resistor R6. Therefore, a low-active DualPortEN#_Valid signal can be generated by latching the DualPortEN# signal in response to a low-to-high transition of the PERST# signal. A complementary DualPortEN_Valid signal may be provided via inverter 148.

[0055] Figure 7 A timing diagram of an example embodiment of a method for generating a dual-port enable valid signal according to the present disclosure is shown. Figure 7 The method shown can be used, for example, during power-up with... Figure 6 Used together with the sampling circuit shown in the figure. (Refer to...) Figure 7 Before time t1, one or more power rails may be stable, and the DualPortEN# signal may be invalid. The state of the DualPortEN# signal can be latched at time t2 in response to the activation of the active-low PCIe reset signal PERST#. The time period T1 between time t1 and t2 can be specified, for example, based on the hold time of the DualPortEN# signal, the minimum time after one or more power rails are within a specified tolerance, etc.

[0056] In some embodiments, power management signals (e.g., power disable signals such as PWRDIS) may be latched in response to a reset signal (such as the PCIe reset signal PERST#). In some embodiments, signals such as... Figure 6 The sampling circuit 140 shown for the dual-port enable signal is similar to that used to latch the power management signal. In some embodiments, the power management signal may be latched at least in part based on the state of the non-volatile memory.

[0057] Figure 8 A timing diagram of an example embodiment of a method for sampling a power-off signal according to the present invention is shown. The method may begin with the active power-off signal PWRDIS at a low logic level and the PCIe reset signal PERST# in an indeterminate state. The PWRDIS signal may be driven to an active state at time t1 and remain active during the time period Tpwrdis until time t2 when the PWRDIS signal can be deactivated to a low state. The PERST# signal may be driven to a low active state at some point before PWRDIS is deactivated at time t2. The PERST# signal may then be deactivated at time t3, which may occur after a hold time Tdisrst following the deactivation of the PWRDIS signal at time t2.

[0058] Figures 6 to 8 The embodiments shown may be beneficial for providing, for example, defined and / or determined behavior, and / or for conforming to embodiments of storage devices that can be used with scalable connectors (such as scalable connectors that use signals as defined, for example, in the STT-TA-1009 specification, as described in the SFF-TA-1002 specification).

[0059] Figure 9 An embodiment of a method for managing power in a storage device according to the present disclosure is shown. The method may begin in operation 150 by connecting the storage device to a host via a connector. In operation 152, the method may detect a change in a power management signal received from the host at the storage device via the connector. In operation 154, the method may configure power to at least a portion of the storage device based at least in part on the detected change in the power management signal.

[0060] against Figure 9 The operations and / or components described in the embodiments shown herein, as well as any other embodiments described herein, are example operations and / or components. In some embodiments, some operations and / or components may be omitted, and / or other operations and / or components may be included. Furthermore, in some embodiments, the temporal and / or spatial order of operations and / or components may be changed.

[0061] The embodiments disclosed above have been described in the context of various implementation details, but the principles of this disclosure are not limited to these specific details or any other specific details. For example, some functions have been described as being implemented by specific components, but in other embodiments, the functions may be distributed among different systems and components located in different locations and having various user interfaces. Specific embodiments have been described as having specific processes, steps, etc., but these terms also include embodiments in which specific processes, steps, etc. may be implemented by multiple processes, steps, etc., or in which multiple processes, steps, etc. may be integrated into a single process, step, etc. References to components or elements may refer to only a portion of a component or element. For example, a reference to an integrated circuit may refer to all or only a portion of an integrated circuit, and a reference to a block may refer to an entire block or one or more sub-blocks. Unless otherwise clear from the context, the use of terms such as “first” and “second” in this disclosure and claims is only for distinguishing what they modify and may not indicate any spatial or temporal order. In some embodiments, “based on” may mean “at least partially based on”. In some embodiments, “disabled” may mean “at least partially disabled”. References to a first thing do not imply the presence of a second thing.

[0062] The various details and embodiments described above can be combined to produce additional embodiments based on the inventive principles disclosed in this patent. Since modifications to the arrangement and details of the inventive principles disclosed in this patent can be made without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the claims.

Claims

1. A storage device, comprising: Connector, including power management pins and dual-port enable pins; The detector circuit is configured to detect transitions in the power management signal received on the power management pin; The non-volatile memory is configured to store configuration bits, wherein the state of the configuration bits is used to generate a power management enable signal to configure the memory device as a U.2 memory device or a U.3 memory device. The power management circuit is configured to: at least partially configure power to at least a portion of the storage device based on a power management signal transition detected by the detector circuit. Specifically, when the dual-port enable pin is active, the storage device operates in dual-port mode, and the power management circuitry is disabled, regardless of whether the storage device is configured as a U.2 or U.3 storage device by the non-volatile memory. When the dual-port enable pin is invalid, the storage device operates in single-port mode, and the power management circuit is enabled or disabled based on the detector circuit detecting the transition of the power management signal and the state of the configuration bit in the non-volatile memory.

2. The storage device as claimed in claim 1, wherein, When the dual-port enable pin is invalid, the power management circuitry is disabled if the power management pin is low, regardless of whether the storage device is configured as a U.2 or U.3 storage device by the non-volatile memory.

3. The storage device as claimed in claim 1, wherein, The power management circuitry is configured to be disabled, at least in part, based on the state of configuration bits in non-volatile memory. Specifically, when the dual-port enable pin is invalid, if the storage device is configured as a U.2 storage device by a non-volatile memory, the power management circuitry is disabled. Specifically, when the dual-port enable pin is invalid, if the storage device is configured as a U.3 storage device by non-volatile memory and the power management pin is high, the power management circuit disables power to at least a portion of the storage device based on the detector circuit detecting a low-to-high transition of the power management signal.

4. The storage device as claimed in claim 1, wherein, The detector circuit is configured to latch power management signals based at least in part on the state of configuration bits in a non-volatile memory.

5. The storage device according to any one of claims 1 to 4, wherein, The power management pins include a power disable pin; and The power management circuit is configured to disable power to at least a portion of the storage device based on a change in the power management signal detected by the detector circuit.

6. A storage device, comprising: Connector, including power management pins and dual-port enable pins; The detector circuit is configured to detect transitions in the power management signal received on the power management pin; A non-volatile memory is configured to store configuration bits, wherein the state of the configuration bits is used to generate a power management enable signal to configure the memory device as a U.2 memory device or a U.3 memory device; and The power management circuitry is configured to enable or disable power to at least a portion of the storage device in response to the state of a configuration bit in the non-volatile memory. Specifically, when the configuration bits in the non-volatile memory are programmed to the first state, the storage device is configured as a U.3 storage device. Specifically, when the dual-port enable pin is active, the storage device operates in dual-port mode, and the power management circuitry is disabled, regardless of whether the storage device is configured as a U.2 or U.3 storage device by the non-volatile memory. When the dual-port enable pin is invalid, the storage device operates in single-port mode, and the power management circuit is configured to disable power to at least a portion of the storage device based on determining that a configuration bit in the non-volatile memory is programmed to a first state, at least in part based on the detector circuit detecting a transition in the power management signal.

7. The storage device as claimed in claim 6, wherein, When the configuration bits in the non-volatile memory are programmed to the second state, the storage device is configured as a U.2 storage device.

8. The storage device as claimed in claim 6, wherein, When the dual-port enable pin is invalid, the power management circuitry is disabled if the power management pin is low, regardless of whether the storage device is configured as a U.2 or U.3 storage device by the non-volatile memory.

9. The storage device as claimed in claim 8, wherein, The power management pins include a power disable pin.

10. The storage device of claim 6, wherein, When the dual-port enable pin is invalid, if the storage device is configured as a U.3 storage device by non-volatile memory and the power management pin is high, the power management circuit disables power to at least a portion of the storage device based on the detector circuit detecting a low-to-high transition of the power management signal.

11. The storage device of claim 10, wherein, When the dual-port enable pin is invalid, the power management circuitry is disabled if the storage device is configured as a U.2 storage device by non-volatile memory.

12. A method for managing power in a storage device, comprising: Connect the storage device to the host via a connector; The dual-port enable signal is received from the host via a connector at the storage device. Detect the transition of power management signals received from the host via a connector at the storage device; as well as Power to at least a portion of the storage device is configured based at least in part on the state of configuration bits in non-volatile memory and the detection of power management signal transitions. The state of the configuration bits in the non-volatile memory is used to generate a power management enable signal to configure the memory device as a U.2 memory device or a U.3 memory device. Specifically, when the dual-port enable signal is active, the storage device operates in dual-port mode, and power management is disabled, regardless of whether the storage device is configured as a U.2 or U.3 storage device. When the dual-port enable signal is invalid, the storage device operates in single-port mode, and power management is enabled or disabled based on the detector circuit detecting the transition of the power management signal and the state of the configuration bits in the non-volatile memory.

13. The method of claim 12, wherein, The step of configuring power to at least a portion of the storage device includes: disabling power to at least a portion of the storage device.

14. The method of claim 12, further comprising: Power management signals are latched based on the reset signal.

15. The method according to any one of claims 12 to 14, in, When the dual-port enable signal is invalid, power management is disabled if the storage device is configured as a U.2 storage device. Specifically, when the dual-port enable signal is invalid, if the storage device is configured as a U.3 storage device and the power management pin is high, at least a portion of the power to the storage device is disabled based on the detected low-to-high transition of the power management signal.

16. The method of claim 15, further comprising: The dual-port enable signal is latched based on the reset signal.

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