Vector generation for maximum instantaneous peak power

Abstract

The present disclosure relates to vector generation for maximum instantaneous peak power. A system and method for performing operational state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating switching operations of one or more cells of the IC design from a first operational state to a second operational state using a plurality of vectors corresponding to one or more user-specified constraints. The method includes generating time-based waveforms for each of the one or more cells changing the operational state from the first operational state to the second operational state, and identifying one or more operational state changes corresponding to the operational state analysis and associated timing window and cell information based on the generated time-based waveforms. The method includes verifying, by each of the one or more cells of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints for generating an analysis report.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 011,565, filed April 17, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure generally relates to integrated circuit design analysis and verification. In particular, this disclosure relates to the power and voltage usage of integrated circuits using vectors. Background Technology

[0004] In integrated circuit (IC) design, two key factors for power integrity are worst-case power consumption analysis and worst-case voltage drop analysis. IC designers therefore need to leverage worst-case power consumption analysis and worst-case voltage drop analysis to identify any weaknesses in the IC design. However, determining the worst-case power consumption and / or worst-case voltage drop of an IC design is extremely difficult. One method currently used to assist IC designers in identifying weaknesses in IC designs is capturing real-world circuit behavior from simulations of real-world scenarios. The output of such simulations can include data on how the individual cells of the IC design switch over billions of clock cycles. Another method currently used to assist IC designers in identifying weaknesses in IC designs is logic-based simulation. Based on a given master input, as many input conditions as possible are enumerated and then propagated down the IC design components. Similar to the first method, in logic-based simulation, the generated data may correspond to results over millions of clock cycles. In a third method, long vectors are generated over millions or billions of clock cycles based on the simulation data. These generated long vectors are fed into power or voltage drop analysis tools. The third approach is typically used in gate-level analysis tools, where an algorithm generates a switching vector based on switching activity, followed by native power and voltage drop analysis. In this method, a random number generator is used to determine whether a cell is switching to identify the switching activity. The switching condition is determined at the main input or output of the register, followed by propagation down the logic. Finally, almost all cell states can be determined. The same process can be repeated for multiple clock cycles with different random seeds. In terms of time and cost, performing power and / or voltage drop analysis using the aforementioned current methods is very expensive. Summary of the Invention

[0005] In one embodiment, a method is disclosed. The method is executed by one or more processors. The method includes: simulating a switching operation from a first operating state to a second operating state for one or more cells of an IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method includes: generating a time-based waveform for each cell of the one or more cells of the IC design to change its operating state from the first operating state to the second operating state during the switching operation. The method includes: identifying one or more operating state changes by each cell of the one or more cells of the IC design based on the generated time-based waveforms, the one or more operating state changes corresponding to operating state analysis and associated timing windows and cell information. The method includes: verifying that the one or more operating state changes satisfy one or more user-specified constraints by each cell of the one or more cells of the IC design; and generating an analysis report including a subset of the plurality of vectors corresponding to the one or more operating state changes verified by each cell of the one or more cells of the IC design.

[0006] In another embodiment, a system for performing operational state analysis of an integrated circuit (IC) design is disclosed. The system includes: a memory configured to store operations; and one or more processors configured to perform the operations, the operations including: simulating a switching operation from a first operational state to a second operational state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The operation includes: for each cell of the one or more cells of the IC design, changing the operational state from the first operational state to the second operational state during the switching operation, generating a time-based waveform. The operation includes: based on the generated time-based waveform, identifying one or more operational state changes by each cell of the one or more cells of the IC design, the changes corresponding to operational state analysis and associated timing windows and cell information. The operation includes: each cell of the one or more cells of the IC design verifying that the one or more operational state changes satisfy one or more user-specified constraints; and generating an analysis report including a subset of a plurality of vectors corresponding to one or more verified operational state changes by each cell of the one or more cells of the IC design.

[0007] In another embodiment, a non-transitory tangible computer-readable device having instructions stored thereon is disclosed. When executed by at least one computing device, the instructions cause the at least one computing device to perform operations for operational state analysis of an integrated circuit (IC) design. The operations include: simulating a switching operation from a first operational state to a second operational state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The operations include: for each cell of the one or more cells of the IC design, during the switching operation, changing the operational state from the first operational state to the second operational state, generating a time-based waveform. The operations include: based on the generated time-based waveform, identifying one or more operational state changes by each cell of the one or more cells of the IC design, the changes corresponding to operational state analysis and associated timing windows and cell information. The operations include: each cell of the one or more cells of the IC design verifying that the one or more operational state changes satisfy one or more user-specified constraints; and generating an analysis report including a subset of a plurality of vectors corresponding to one or more operational state changes verified by each cell of the one or more cells of the IC design. Attached Figure Description

[0008] This disclosure will be more fully understood from the following detailed description and the accompanying drawings illustrating embodiments of the present disclosure. The drawings are provided to give knowledge of and understanding of embodiments of the present disclosure, but are not intended to limit the scope of the disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0009] Figure 1 The figure illustrates a high-level flowchart of vector generation for power or voltage drop analysis according to some embodiments.

[0010] Figure 2 The figure illustrates some embodiments. Figure 1 A flowchart of an embodiment of the flowchart.

[0011] Figure 3 The figure illustrates some embodiments. Figure 1 A flowchart of another embodiment of the flowchart.

[0012] Figure 4 The figure illustrates a simulation of an integrated circuit (IC) design using compliant vectors according to some embodiments.

[0013] Figure 5 The figure illustrates time-based power consumption waveforms for multiple cells in an IC design according to some embodiments.

[0014] Figure 6The figure illustrates the peak power consumption over time calculated according to some embodiments.

[0015] Figure 7 The figure illustrates the application of user constraints for vector generation according to some embodiments.

[0016] Figure 8A The figure illustrates the logical correlations and event propagation used for determining the maximum instantaneous peak power according to some embodiments.

[0017] Figure 8B The figure shows a graph illustrating power consumption over multiple clock cycles over time, according to some embodiments.

[0018] Figure 9 The figure illustrates the propagation of activity across multiple clock paths according to some embodiments.

[0019] Figure 10 The figure illustrates a conflict resolution method for vector generation according to some embodiments.

[0020] Figure 11 The figure illustrates the maximization of clock network power according to some embodiments.

[0021] Figure 12 The figure illustrates a D flip-flop with low effective preset and clear according to some embodiments.

[0022] Figure 13 The figure illustrates the processing of a high fan-out network (HFN) according to some embodiments.

[0023] Figure 14 The figure illustrates flowcharts of various processes used during the design and manufacture of integrated circuits, according to some embodiments.

[0024] Figure 15 A diagram illustrates an example computer system in which embodiments of the present disclosure can be operated.

[0025] To facilitate the identification of any particular element or action in discussion, one or more of the most significant digits in the reference numerals refer to the drawing number in which the element was first introduced. Detailed Implementation

[0026] Due to the complexity and size of integrated circuits (ICs), it is impossible to enumerate all possible vectors for power and voltage drop analysis that can be generated using the currently known methods mentioned above in this disclosure to identify the worst-case scenarios for power consumption and voltage drop analysis. However, the systems and methods described herein for generating a set of vectors for power and voltage drop analysis can be used to identify the worst-case scenarios for power and voltage drop analysis.

[0027] Figure 1 The figure illustrates a high-level flowchart of vector generation for power or voltage drop analysis according to some embodiments. An integrated circuit may include multiple cells. Each of the multiple cells may not switch during a clock cycle. Furthermore, each cell has a different cell state over time within different clock cycles. Taking maximizing instantaneous peak power and / or voltage drop as an example, the method described herein can start from all cells in the IC design. Therefore, for power and voltage drop analysis, as shown in 110, the IC design can be simulated, and only the generated vectors satisfying user-specified constraints are considered for power and voltage drop analysis. As a non-limiting example, user-specified constraints may include information about nets with a constant logic zero or one value (i.e., non-switching nets). User-specified constraints may also include clock definitions describing the clock frequency, the rising edge of the clock, and / or the falling edge of the clock. User-specified constraints may also include how often a cell switches based on clock gating. As a non-limiting example, user-specified constraints may be applied to a subset of multiple cells. Therefore, user-specified constraints may be applied to the entire IC design before vector generation, such that all cells of the IC design under user-specified constraints are processed according to those constraints. Therefore, the circuit operation of the IC design is simulated according to the constraints specified by the user.

[0028] At 120, time-based power and / or current waveforms can be generated for each state change in multiple cells of the IC design. These waveforms can be generated based on the simulation results from 110 above. For each time-based power and / or current waveform, the power and / or current consumed by each cell for each state can be determined for each timing window of the cell's clock. All switching conditions for each cell can be enumerated by the user. The power value for each switching condition can then be calculated. Each switching condition in a cell is called a cell state. The power figure is then associated with a timing window from which the pin begins to rise or fall. The timing window includes minimum and maximum arrival times. Finally, each cell state is represented by a rectangle, where the width represents the timing window and the height represents the power. The timing window represents a time interval in which a switching condition can rise or fall. When it occurs, the power value indicates how much power it will consume. Finally, the accumulated time-based power can be calculated based on all cell states represented by the rectangles.

[0029] At position 130, based on the power and / or current waveforms generated by each state change in multiple cells of the IC design, peak power and / or current usage and the corresponding timing window can be identified. Additionally, based on the generated power and / or current waveforms, one or more cells contributing to peak power and / or current usage can be determined. Peak power and / or current usage for a given timing window can be determined based on the power and / or current usage for each cell during that window. Therefore, the cells and corresponding cell states during peak power and / or current usage can be determined. Thus, based on the time-based power waveforms, one or more peaks at which peak power consumption occurs can be calculated. For each peak and peak time, all cell states can be analyzed or scanned so that only those cell states whose timing windows overlap with the peak times are retained to form a cell state list. The list can then be sorted according to power values ​​from highest to lowest.

[0030] At point 140, it can be verified that the power and / or current usage of each cell during the timing window in which peak power and / or current usage occurs is within the user-specified constraints. If the power and / or current usage of any cell during the timing window in which peak power and / or current usage occurs is not within the user-specified constraints, then the cell and its corresponding cell status can also be identified for user notification. As a non-limiting example, a notation in a value change dump (VCD) file can be used to notify the user.

[0031] According to some embodiments, cell states used for vector generation can be determined. In this step, user-specified constraints can be used for vector generation. As a non-limiting example, user-specified constraints may also include one or more nets that will never switch (and therefore have constant logic zero or one values), clock definitions in terms of cycles, rising / falling edges, and how often clock-gated cells should switch. Before vector generation, the user-specified constraints are followed and propagated throughout the design so that all cells under the user-specified constraints are correctly processed. Cell states from highest to lowest power usage can also be identified from the cell state list. The cell states are checked against the user constraints and the current pin conditions propagated so far to determine whether such cell states can be retained or filtered out. If a cell state is to be retained, its pin state is propagated forward and / or backward. After propagation, if no logic conflicts are found, the cell state is ultimately retained. Otherwise, the cell state is filtered out. This filtering process is repeated for each cell state in the list until no states remain.

[0032] At point 150, an analysis report can be generated, including vectors corresponding to each cell state of multiple cells in the IC design. Vectors corresponding to all cell states are generated. The final list of cell states will satisfy both user-specified constraints and logical consistency. Cell states that do not satisfy user-specified constraints and / or logical consistency can be excluded from the analysis report. The analysis report can be in VCD file format. As a non-limiting example, the Fast Signal Database (FSDB) file format can also be used to generate the analysis report. This analysis report can then be used by IC designers to determine the maximum instantaneous peak power of the IC design. Cell states in the analysis report can be sorted according to their maximum arrival time from shortest to longest. Vectors in the analysis report can be sorted according to the order of cell arrival times. Cell arrival times can be referred to as event times in the analysis report.

[0033] As mentioned above, based on Figure 1 The high-level flowchart shown illustrates a method that begins by calculating the power of all enumerated individual cell states for each cell in the IC design. Since the number of individual states from a cell is relatively small throughout the design, the worst-case power usage can also be correlated with those enumerated cell states and cells. Therefore, compared to currently known methods for power and voltage drop analysis, the method used herein offers advantages. Figure 1 The generated vectors described are faster and more accurate. Based on the use of Figure 1 The accuracy of power and voltage drop analysis of vectors generated using the method described herein is due to the fact that the disclosed method does not use random numbers to determine the vectors. Therefore, compared to other methods that use random numbers, the method... Figure 1 Power and voltage drop analyses using the methods described in this paper may be closer to the worst-case scenario.

[0034] By comparison, currently known vectorless solutions are based on switching activity and use a random number generator to determine whether a network switch should occur. Therefore, networks with high switching activity are more likely to be switched, generating events for vector generation. However, power and / or voltage drop analysis requires vectors that can generate worst-case power or voltage drop values. Therefore, high instantaneous power or voltage drop can occur regardless of switching activity, as long as networks are switching simultaneously. The method described herein, according to some embodiments, does not use random numbers to determine whether a network switch should occur. Whether a cell switches depends on whether its power contributes to the total cumulative instantaneous power. Therefore, the method described herein, according to some embodiments, naturally follows user-specified constraints. It also maintains logical consistency because all logically conflicting cell states are filtered in this method.

[0035] Figure 2 The figure shows Figure 1A flowchart of an embodiment of the flowchart. Specifically, Figure 2 The embodiments described herein are relevant to worst-case or maximum power usage analysis. For example... Figure 2 As shown, at 210, user-specified constraints on the logic constants of one or more grids can be mapped to one or more pin conditions of one or more cells in the IC design under test. As previously mentioned, during simulation, user-specified constraints are first considered and applied to the entire IC design. As a non-limiting example, the entire IC design can be divided into two or more parts; for example, each part can be referred to as a grid. Thus, the entire IC design can be divided into multiple grids. Therefore, user-specified constraints can be applied to one or more grids of the entire IC design. At 220, as described above, user-specified constraints on one or more clock waveforms can be applied to the entire IC design and / or to one or more grids of the IC design. The rising and / or falling edges of one or more clock waveforms can cause switching of one or more cells and power consumption of one or more cells. Therefore, at 230, the power consumed by one or more cells during the timing window of the applied one or more clock waveforms can be calculated. Thus, the power consumed by one or more cells for each state of that cell can be determined and associated with the timing window.

[0036] At position 240, a time-based power waveform can be generated. This waveform represents the total power used by one or more cells or grids in the IC design. At position 250, the peak power and corresponding time can be determined based on the time-based power waveform. Furthermore, at position 260, one or more cells contributing to the peak power can be identified. Since the peak power is the result of the cumulative power usage of one or more cells in the IC design, a list of cell states contributing to the peak power usage can also be determined using the time-based power waveform.

[0037] At position 270, the cell state list can be checked against the current pin conditions of one or more pins of one or more cells based on user-specified constraints. If a cell state from the cell state list conforms to the user-specified constraints, then the cell state can be propagated in the forward and / or backward directions. Furthermore, if the propagation of the cell state does not cause any logical conflict, then the cell state can be accepted for use in generating vectors. Otherwise, the cell state can be excluded from generating vectors.

[0038] At position 280, an analysis report can be generated, which includes the generated vectors corresponding to the accepted cell states. As mentioned above, the analysis report can be in VCD or FSDB file format.

[0039] Figure 3The figure shows Figure 1 A flowchart of another embodiment of the flowchart. Specifically, in Figure 3 The embodiments described herein are relevant to worst-case or maximum voltage drop analysis. For example... Figure 3 As shown, at 310, user-specified constraints on the logic constants of one or more grids can be mapped to one or more pin conditions of one or more cells in the IC design under test. As previously mentioned, during simulation, the user-specified constraints are first considered and applied to the entire IC design. As a non-limiting example, at 330, the entire IC design can be divided into two or more parts; for example, each part can be referred to as a grid. Thus, the entire IC design can be divided into multiple grids. Therefore, user-specified constraints can be applied to one or more grids of the entire IC design. Thus, as described above, when user-specified constraints on one or more clock waveforms can be applied to the entire IC design and / or to one or more grids of the IC design, the rising and / or falling edges of one or more clock waveforms can cause switching of one or more cells and cause current to flow through one or more cells. Therefore, at 340, the current flowing through one or more cells during the timing window of the applied one or more clock waveforms can be calculated. Thus, the peak current through one or more cells for each state of the cell can be determined and associated with the timing window.

[0040] At position 350, a time-based current waveform can be generated for one or more grids or the entire IC design. The time-based current waveform represents the total current flowing through one or more cells or grids of the IC design. Based on the time-based current waveform, the peak current and its corresponding time can also be determined. Furthermore, at position 350, one or more cells or grids that contribute to the peak current drawn can be identified. Since the peak current is the result of the accumulated current drawn by one or more cells or grids of the IC design, a list of cell states for one or more cells that contribute to the peak current can also be determined using the time-based current waveform.

[0041] At position 360, the cell state list can be checked against the current pin conditions of one or more pins of one or more cells based on user-specified constraints. If a cell state from the cell state list conforms to the user-specified constraints, then the cell state can be propagated in the forward and / or backward directions. Furthermore, if the propagation of the cell state does not cause any logical conflict, then the cell state can be accepted for use in generating vectors. Otherwise, the cell state can be excluded from generating vectors.

[0042] At position 370, an analysis report can be generated, which includes generated vectors corresponding to the accepted cell states. As mentioned above, the analysis report can be in VCD or FSDB file format. Therefore, the analysis report helps IC designers identify the maximum voltage drop of the IC design and the corresponding cell states of one or more IC design cells. Multiple generated VCD or FSDB files can exist, and each VCD or FSDB file can correspond to a single clock cycle.

[0043] According to some embodiments, vector generation for maximum voltage drop analysis differs from vector generation for maximum power usage in two aspects. First, instead of calculating power for each cell state in the design, a current waveform can be calculated for each cell state. Second, time-based current waveforms can be generated from a group of cells in the same neighborhood rather than from all IC design cells. As mentioned above, to achieve this, the entire IC design can be divided into multiple grids, and then the cells can be grouped into different grids based on their physical location on the IC. As a non-limiting example, vector generation can be performed at each grid or from multiple grids together.

[0044] According to some embodiments, as non-limiting examples, the above uses Figure 2 and / or Figure 3 The described steps can also be applied to generate vectors to achieve maximum voltage drop feedback along the timing path, thereby minimizing its delay impact. In this disclosure, when using vector generation for maximum power, the cost function is therefore power. Similarly, when generating a vector for maximum voltage drop, the cost function is therefore peak current, and when generating a vector for maximum voltage drop feedback, the cost function is the delay caused by the voltage drop. Vectors for maximum voltage drop feedback can be generated along the timing path for a group of cells in the same neighborhood or nearby on the IC.

[0045] Figure 4 The figure illustrates a simulation of an integrated circuit (IC) design using compliance vectors according to some embodiments. As described above and as... Figure 4 As shown, an IC design 416 described using a hardware description language (such as Verilog) may include multiple cells 412. The multiple cells 412 may be connected via multiple signal paths 414. Depending on user-specified constraints, when a clock waveform is applied to one or more of the multiple cells 412, it may cause a switching of the network of one or more of the multiple cells 412. The switching of the network may cause power consumption and / or current flow through one or more cells. Furthermore, as mentioned above, the individual cells may be grouped into one or more sections called grids. The cells may be grouped into grids based on their location on the IC design.

[0046] Based on cell switching, cells can be coupled to timing-critical paths, for example, in terms of time and / or spatial relationships. All cells can cause some voltage drop, and their IR sensitivity can be calculated when a cell switches during the rising and / or falling edges of the clock. Furthermore, the delays of critical timing paths can be determined. Therefore, as a non-limiting example, a switching vector can be determined in addition to the maximum power usage vector. The switching vector can describe the timing degradation for each switching event. As mentioned above, vectors that do not meet user-specified constraints may be excluded and may not be included in the analysis report. As a non-limiting example, user-specified constraints may relate to fan-out, reset logic, integrated clock gating (ICG) efficiency, scan mode, etc.

[0047] Figure 5 The figure illustrates time-based power consumption waveforms for multiple cells in an IC design according to some embodiments. As described above and as... Figure 5 As shown, timer-based power consumption waveforms 512, 514, and 516 are illustrated. Power consumption waveforms 512, 514, and 516 are associated, for example, with cells C1, C2, and C10. For each cell C1, C2, and C10, the power consumption waveform shows the power used over time over multiple clock cycles. Power can be used by the cell as the cell state switches during the rising and / or falling phases of the applied clock waveform. The power used can then be represented as a rectangle, where the height of the rectangle represents the amount of power used, and the width represents the timing window.

[0048] Figure 6 The figure illustrates the peak power consumption over time calculated according to some embodiments. For multiple units... Figure 5 The time-based power waveform shown is in Figure 6 The X-axis 604 is shown along time. Since the time-based power waveforms for multiple cells are stacked on top of each other along the X-axis over time, a power consumption waveform 602 can be generated for the entire IC design and / or multiple cells, showing the total power consumed at a given time. Figure 6 As shown, the power consumption waveform 602 can therefore be used to identify peak power, cells that contribute to peak power, and also to identify cell states and corresponding times when peak power is used.

[0049] Figure 7 The figure illustrates an application of user constraints for vector generation according to some embodiments. An example of a user constraint for vector generation could be 50% or lower ICG efficiency. Without ICG efficiency constraints, all inverters can be switched in a manner that contributes to the use of the maximum instantaneous peak power. For example... Figure 7As shown, inverters i1 708, i2 710, and i4 706 are triggered by ICG1 702, while inverters i3 712 and i5 714 are triggered by ICG2 704. Therefore, inverters i1 708, i2 710, and i4 706 may consume power based on the rising and / or falling edges of the enable signal and clock signal CLK at ICG1 702. Similarly, inverters i3 712 and i5 714 may consume power based on the enable signal and clock signal CLK at ICG2 704. Figure 7 As shown, without a user-specified constraint describing the maximum instantaneous peak power, all inverters can switch simultaneously, resulting in a maximum simultaneous peak power, as shown in 716. As a non-limiting example, a user-specified constraint can limit the maximum simultaneous peak power usage to below 50%. Since the vectors i3 712 and i5 714 triggered by ICG2 704 consume less instantaneous peak power compared to the vectors i1 708, i2 710, and i4 706 triggered by ICG1 702, the vectors triggered by ICG2 704 can be excluded from consideration. Therefore, vectors can be generated based on the simultaneous power usage of inverters i1 708, i2 710, and i4 706, as shown in 718.

[0050] Figure 8A The diagram illustrates the logic dependency and event propagation for determining the maximum instantaneous peak power according to some embodiments. As a non-limiting example, a user-specified constraint may require the input signal at inverter i1 to be a rising signal. Therefore, when event R 802 is rising at inverter i1, this event is propagated forward to other flip-flops. Figure 8A As shown, some pins can have constant logic. Therefore, the voltage level at those pings with constant logic can remain either 1 or 0. After the event propagates, for... Figure 8A The resulting vector of the circuit shown can have logical dependencies on event R at inverter i1, flip-flop ff1, OR gate or1, flip-flop ff2, flip-flop ff3, XOR gate XOR1, flip-flops ff4 and ff5, and inverter i3. Therefore, vectors satisfying logical dependencies can be generated, and only those events satisfying user-specified constraints for logical dependencies can propagate in the forward and / or reverse directions.

[0051] Figure 8B The figure illustrates a graph showing power consumption over multiple clock cycles according to some embodiments. As a non-limiting example, it is assumed that all cells are clock cells and that there are no data cells in the IC design that represent power consumption over multiple clock cycles, such as... Figure 8B As shown in the diagram. It is assumed that the cell switching occurs at the rising edge of the clock, as... Figure 8B As shown, the worst or maximum simultaneous power consumption may occur during periods 1 (808), 2 (810), and 3 (812). Therefore, according to user-specified constraints, during vector generation, only clock periods 808, 810, and 812 may be considered for all clocks. Since all other clock periods do not meet the user-specified constraints, they can be ignored. However, when generating an analysis report for vectors for periods 808, 810, and 812, the output VCD file may appear incoherent. As a non-limiting example, to generate an analysis report that includes vectors showing coherent logic, dummy additional clock periods can be generated. As a result, a single VCD or FSDB file can be generated.

[0052] Figure 9 The diagram illustrates the propagation of activity across multiple clock paths according to some embodiments. As a non-limiting example, user-specified constraints may include the propagation of events across multiple clock paths. In this case, the user-specified constraints may specify how event propagation should be delayed. Figure 9 As shown, clock 902 is a 1 GHz clock, while another clock, 904, is a 500 MHz clock. When an option (such as "set_power_analysis_options-through_mode") is enabled, events will propagate along multiple clock paths. Derating factors can be specified for components along the clock paths to achieve maximum clock transition at the destination.

[0053] Figure 10 The figure illustrates a conflict resolution method for vector generation according to some embodiments. As a non-limiting example, user-specified constraints may include one or more conditions corresponding to the worst-case internal energy consumption for multiple instances. User-specified constraint 1002 may require that propagated clock transitions and signal values ​​to the network be ignored, as part of one or more conditions corresponding to the worst-case internal energy consumption.

[0054] Figure 11 The figure illustrates the maximization of clock network power according to some embodiments. As a non-limiting example, user-specified constraints may include the worst-case clock network power of the IC design, one or more cells or grids of the IC design, and a user-specified target power consumption. Figure 11 The IC design shown may include, for example, clocks CLK1102, ICG1 1104, ICG2 1106, ICG3 1108, and flip-flops 1110, 1112, 1114, and 1116. The cost function or parameter used for this user-specified constraint can be the internal energy of multiple endpoints. Figure 11As shown, an ICG that feeds another ICG can be enabled using an SP with a value of 1.

[0055] Figure 12 The figure illustrates a D flip-flop with a low active preset and clear according to some embodiments. As a non-limiting example, user-specified constraints may include how the control pin can be configured to allow data to propagate to the output. Figure 12 The diagram shows clock pin 1204, data pins 1202 and 1206, and control pins 1208 and 1210. Control pins can be manipulated using a hardware description language that specifies the preset and clear signals for the enable signal. Data pins can have their TR and SP values ​​obtained through user-defined comments or rule propagation and notation. Clock pins have their TR and SP values ​​obtained through node clock activity propagation.

[0056] Figure 13 The diagram illustrates the processing of high fan-out nets according to some embodiments. As a non-limiting example, user-specified constraints may include high fan-out net (HFN) processing. In IC design, unbuffered nets can cause significant power consumption, potentially masking actual power issues during early design phases prior to clock tree synthesis (CTS) or buffering. User-specified constraints can define limits for HFNs. For example, HFN can be set to 10. Therefore, all nets with 10 or more pins can be defined as HFNs. For driver 1302 and receivers 1304, 1306, and 1308, power calculations can be based solely on leakage. Slew and load calculations for nets identified as having HFNs can be disabled based on user-specified constraints.

[0057] Figure 14 The diagram illustrates a set of example processes 1400 used during the design, verification, and manufacturing of articles such as integrated circuits to transform and verify design data and instructions representing integrated circuits. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA" refers to the term "Electronic Design Automation." These processes begin with the creation of a product concept 1410 using information provided by a designer, which is then transformed to create an article of art using a set of EDA processes 1412. After the design is completed, the design is tape-out 1434, which occurs when the artwork for the integrated circuit (e.g., a geometric pattern) is sent to a manufacturing plant to create a mask set, which is subsequently used to manufacture the integrated circuit. Following tape-out, semiconductor dies are manufactured 1436, and packaging and assembly processes 1438 are performed to produce a finished integrated circuit 1440.

[0058] The specification of a circuit or electronic structure can range from low-level transistor material placement to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer-level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower-level representation, as a more detailed description, adds more useful details to the design description, such as more details about the modules described. These lower-level representations, as more detailed descriptions, can be computer-generated, exported from design libraries, or created by another design automation process. An example specification language used to specify lower-level representations that are more detailed is SPICE, which is used to describe circuits with many analog components in detail. The descriptions at each representation level are enabled for use by the corresponding tools (e.g., formal verification tools) targeting that layer. The design process can use... Figure 14 The sequence described in the document. The process is described or supported by EDA products (or tools).

[0059] During system design 1414, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0060] During logic design and functional verification 1416, modules or components in a circuit are specified using one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components referred to as a “simulator” or “prototype system” is used to accelerate functional verification.

[0061] During the synthesis and design phase 1418 of the test, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and the nodes of the graph structure represent the interconnections between components. Both the HDL code and the netlist are fabricated layered products that can be used by EDA products to verify that the integrated circuit performs as specified in the design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that the integrated circuit meets specification requirements.

[0062] During netlist verification 1420, the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning 1422, the overall planar diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0063] During layout or physical implementation 1424, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components via multiple conductors) occur, and cells are selected from a library so that specific logic functions can be performed. As used herein, the term "cell" can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be enabled simultaneously as physical structures and enabled in simulation. (Based on "standard cells") Parameters such as size are specified for the selected cells, and they are made accessible in the database for use in EDA products.

[0064] During Analysis and Extraction 1426, circuit functionality is verified at the layout level, allowing for improvements to the layout design. During Physical Verification 1428, the layout design is examined to ensure that manufacturing constraints such as DRC constraints, electrical constraints, and lithographic constraints are correct and that the circuit system functionality matches the HDL design specifications. During Resolution Enhancement 1430, the geometry of the layout is transformed to improve the fabrication of the circuit design.

[0065] During the tape-out process, data is created for the production of the photomask (if appropriate, after the application of photolithography enhancement). During mask data preparation 1432, the "tape-out" data is used to generate the photomask, which is used to produce the finished integrated circuit.

[0066] Computer systems (such as) Figure 15 The storage subsystem of a computer system (1500) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as by products used for developing units targeting libraries and for physical and logical designs that use those libraries.

[0067] Figure 15The figure illustrates an example machine of computer system 1500, in which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0068] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, or any machine capable of executing a set of instructions that specify the actions to be taken by the machine (sequentially or otherwise). Furthermore, while a single machine is illustrated, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0069] Example computer system 1500 includes processing device 1502, main memory 1504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 1506 (e.g., flash memory, static random access memory (SRAM), etc.) and data storage device 1518, which communicate with each other via bus 1530.

[0070] Processing device 1502 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements combinations of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1502 may be configured to execute instructions 1526 to perform the operations and steps described herein.

[0071] The computer system 1500 may also include a network interface device for communication via network 1520. The computer system 1500 may also include a video display unit 1510 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1512 (e.g., a keyboard), a cursor control device 1514 (e.g., a mouse), a graphics processing unit 1522, a signal generation device 1516 (e.g., a speaker), a graphics processing unit 1522, a video processing unit 1528, and an audio processing unit 1532.

[0072] Data storage device 1518 may include machine-readable storage medium 1524 (also referred to as non-transitory computer-readable medium) storing one or more sets of instructions 1526 or software embodying any one or more of the methods or functions described herein. During the execution of instructions by computer system 1500, main memory 1504, and processing device 1502, which also constitutes a machine-readable storage medium, the instructions 1526 may also reside wholly or at least partially in main memory 1404 and / or processing device 1502.

[0073] In some implementations, instruction 1526 includes instructions for implementing functionality corresponding to this disclosure. Although machine-readable storage medium 1524 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions to be executed by a machine and to cause the machine and processing device 1502 to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0074] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. An algorithm can be a series of operations that lead to a desired result. These operations are those that require physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0075] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise explicitly stated as is apparent from this disclosure, it should be appreciated that throughout the specification, certain terms refer to the operation and processes of a computer system or similar electronic computing device that manipulates data represented as physical quantities (electronic quantities) within the registers and memories of the computer system and converts them into other data represented similarly as physical quantities within the computer system's memory or registers or other such information storage devices.

[0076] This disclosure also relates to means for performing the operations described herein. Such means may be specifically constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0077] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. Furthermore, no particular programming language is referenced in describing this disclosure. It should be appreciated that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0078] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0079] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific example implementations. It will be apparent that various modifications may be made thereto without departing from the broader scope of implementation of this disclosure as set forth in the appended claims. Elements are referred to in the singular in this disclosure, and more than one element may be depicted in the drawings, with similar elements labeled with similar numbers. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A computer-implemented method for performing operational state analysis of an integrated circuit (IC) design, the method comprising: Using multiple vectors corresponding to one or more user-specified constraints, simulate the switching operation of one or more cells of the IC design from a first operating state to a second operating state; Each of the one or more units in the IC design changes its operating state from the first operating state to the second operating state during the switching operation, generating a time-based waveform; Based on the generated time-based waveform, each of the one or more cells in the IC design identifies one or more operational state changes, which correspond to the operational state analysis and associated timing windows and cell information. Each of the one or more cells designed by the IC verifies that the one or more operational state changes satisfy the one or more user-specified constraints. as well as An analysis report is generated for one clock cycle. The analysis report includes a subset of the plurality of vectors, the subset of the plurality of vectors corresponding to the one or more operational state changes that have been verified for each of the one or more cells in the one or more cells designed by the IC.

2. The computer-implemented method of claim 1, wherein the operational state analysis performed is the maximum simultaneous power consumption of the one or more units of the IC design.

3. The computer-implemented method of claim 1, wherein the operational state analysis performed is the maximum voltage drop of the one or more cells of the IC design.

4. The computer-implemented method of claim 1, wherein the operational state analysis performed is a timing path analysis for one or more clock paths of the IC design.

5. The computer-implemented method of claim 1, wherein verifying the one or more operational state changes comprises: For each cell in one or more units of the IC design, verify that the cell state matches the pin conditions according to the user-specified constraints; and The unit state is propagated after verification, based on the user-specified constraints.

6. The computer-implemented method of claim 5, wherein verifying the change of the one or more operating states further comprises: Verify logical conflicts during the propagation of the unit state; as well as Exclude the cell states that cause the logical conflict during the propagation of the cell states.

7. The computer-implemented method according to claim 1, wherein generating the analysis report comprises: The analysis report is generated by changing the values ​​in either the VCD format or the Fast Signal Database (FSDB) format.

8. The computer-implemented method of claim 1, wherein the user-specified constraints include high fan-out HFN, reset logic, and integrated clock gating (ICG) efficiency.

9. The computer-implemented method according to claim 1, wherein generating the analysis report comprises: The analysis report is generated for multiple clock cycles.

10. The computer-implemented method of claim 9, wherein one or more of the plurality of clock cycles are discontinuous.

11. A system for performing operational state analysis of integrated circuit (IC) design, comprising: The memory is configured for storage operations; and One or more processors are configured to perform the operation, the operation including: Using multiple vectors corresponding to one or more user-specified constraints, simulate the switching operation of one or more cells of the IC design from a first operating state to a second operating state; Each of the one or more units in the IC design changes its operating state from the first operating state to the second operating state during the switching operation, generating a time-based waveform; Based on the generated time-based waveform, each of the one or more cells in the IC design identifies one or more operational state changes, which correspond to the operational state analysis and associated timing windows and cell information. Each of the one or more cells designed by the IC verifies that the one or more operational state changes satisfy the one or more user-specified constraints; and An analysis report is generated for one clock cycle. The analysis report includes a subset of the plurality of vectors, the subset of the plurality of vectors corresponding to the one or more operational state changes that have been verified for each of the one or more cells in the one or more cells designed by the IC.

12. The system of claim 11, wherein the operational state analysis performed for the IC design includes one of the following: the maximum simultaneous power consumption of the one or more cells of the IC design, the maximum voltage drop of the one or more cells of the IC design, and timing path analysis for one or more clock paths of the IC design.

13. The system of claim 11, wherein, in order to verify the change of the one or more operational states, the operation includes: For each cell in one or more units of the IC design, verify that the cell state matches the pin conditions according to the user-specified constraints; as well as The unit state is propagated after verification, based on the user-specified constraints.

14. The system of claim 13, wherein, in order to verify the change of the one or more operational states, the operation further includes: Verify logical conflicts during the propagation of the unit state; as well as Exclude the cell states that cause the logical conflict during the propagation of the cell states.

15. The system of claim 11, wherein, in order to generate the analysis report, the operation further includes: The analysis report is generated by changing the values ​​in either the VCD format or the Fast Signal Database (FSDB) format.

16. The system of claim 11, wherein the user-specified constraints include high fan-out HFN, reset logic, and integrated clock gating (ICG) efficiency.

17. The system of claim 11, wherein, in order to generate the analysis report, the operation includes: The analysis report is generated for one or more of the multiple clock cycles.

18. The system of claim 17, wherein two or more of the plurality of clock cycles are discontinuous.

19. A non-transitory tangible computer-readable device having instructions stored thereon, the instructions, when executed by at least one computing device, causing the at least one computing device to perform operations for operational state analysis of integrated circuit (IC) design, the operations comprising: Using multiple vectors corresponding to one or more user-specified constraints, simulate the switching operation of one or more cells of the IC design from a first operating state to a second operating state; Each of the one or more units in the IC design changes its operating state from the first operating state to the second operating state during the switching operation, generating a time-based waveform; Based on the generated time-based waveform, each of the one or more cells in the IC design identifies one or more operational state changes, which correspond to the operational state analysis and associated timing windows and cell information. Each of the one or more units designed by the IC verifies that the one or more operational state changes satisfy the one or more user-specified constraints. as well as An analysis report is generated for one clock cycle. The analysis report includes a subset of the plurality of vectors, which corresponds to one or more verified operational state changes of each of the one or more cells in the IC design.

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