Ray tracing methods and graphics pipeline

Abstract

A ray tracing method and graphics pipeline are disclosed. It is determined whether the ray bounce of a first ray intersects with a first primitive, where the first primitive is the closest primitive to the ray bounce. The first ray is a portion of a first group of rays processed by a first Single Instruction Multiple Data (SIMD) process. Based on the intersection of the first primitive, the first ray is assigned to a second group of rays by a sorting unit or a pixel combination unit. The second group of rays is processed by a second SIMD process. The first ray is assigned to the second group of rays based on the material identifier of the first primitive, the identifier of the first primitive intersecting with the ray bounce of the first ray, the pixel position, and the number of bounces of the ray bounce intersecting with the first primitive.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 012,049, filed April 17, 2020, and U.S. Application No. 16 / 930,310, filed July 15, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The subject matter disclosed here relates to graphics processing units (GPUs), and more specifically, a technique for efficiently using material shaders when performing ray tracing. Background Technology

[0003] Ray tracing is a technique used to render objects intended to be viewed as images, inspired by how light works in nature. Ray tracing helps make rendered images more realistic. Ray tracing results in better rendering of shadows, specular highlights, reflections, penumbra (soft shadows), global illumination, and more.

[0004] Based on the DirectX ray tracing standard and the Vulkan RT standard, rays are generated from ray generation shaders. The generated rays invoke the "traceRay" structure, which allows the GPU to traverse the acceleration structure to determine if the ray intersects with a primitive. Once the intersection with a primitive has been determined, any hit shaders can be executed. The GPU determines the closest primitive among all primitives determined to intersect with the ray, and the properties of the closest primitive are used to influence the shading of a specific pixel. That is, the shading of a specific pixel can be determined by an appropriate closest hit shader procedure, which can be invoked based on the material (or texture) properties of the closest hit primitive, evaluated at the ray intersection, to calculate the color. This color is then used to modify the shading of the specific pixel.

[0005] According to the DirectX ray tracing specification and the Vulkan RT specification, several rays can be bundled into a warp (or wavefront), which is an execution unit on the GPU shader core. Because different rays potentially cause different primitives to intersect with different material shaders, warps and wavefronts tend to exhibit branching (i.e., not all threads execute the same part of the code), leading to potential misutilization of the shader core. In other words, when only a portion of the rays in a warp or wavefront are actually executing while the rest remain idle, GPU resources are being consumed without actually producing any useful work. Summary of the Invention

[0006] An example embodiment provides a ray tracing method, which may include: determining, via a GPU ray tracing pipeline, whether a ray bounce of a first ray intersects with a first primitive, wherein the first ray may be a portion of a first group of rays processed by a first single instruction multiple data processing (SIM); and assigning the first ray to a second group of rays based on the intersection of the ray bounce of the first ray with the first primitive via a GPU sorting unit, wherein the second group of rays may be processed by a second SIM. In one embodiment, the first primitive may include the nearest primitive intersecting with the ray bounce of the first ray, and the step of assigning the first ray to the second group of rays may also be based on the material identifier of the first primitive and the identifier of the first primitive intersecting with the ray boundary of the first ray. In another embodiment, the assignment from the first ray to the second group of rays may also be based on pixel position and the number of bounces of the ray bounce intersecting with the first primitive.

[0007] An example embodiment provides a ray tracing method, which may include: invoking a ray generation shader of a GPU to generate a first ray, the first ray being a portion of a first group of rays processed by a first single instruction multiple data processing (SIM); determining, via a ray tracing pipeline, whether a ray bounce of the first ray intersects with a first primitive; sending, via the ray tracing pipeline, first metadata related to the ray bounce of the first ray intersecting with the first primitive to a sorting unit of the GPU; and assigning the first ray to a second group of rays by the GPU's sorting unit based on the first metadata related to the ray bounce of the first ray intersecting with the first primitive, wherein the second group of rays may be processed by a second SIM. In one embodiment, the first primitive may include the nearest primitive intersecting with the ray bounce of the first ray, and the first metadata may include a material identifier of the first primitive and an identifier of the first primitive intersecting with the ray bounce of the first ray. In another embodiment, the first metadata may further include a pixel position and the number of bounces of the ray bounce intersecting with the first primitive. In another embodiment, the ray tracing method may include: determining, via a ray tracing pipeline, whether the ray bounce of a second ray intersects with a second primitive, wherein the second ray is part of a second group of rays; sending, via the ray tracing pipeline, second metadata related to the ray bounce of the second ray intersecting with the second primitive to a sorting unit; and assigning, via the sorting unit, the second ray to a third group of rays based on the second metadata, wherein the third group of rays may be processed by a third single instruction multiple data processing (SID).

[0008] An example embodiment provides a graphics pipeline for a GPU, which may include a ray generation shader, an intersection shader, and a sorting unit. The ray generation shader generates a first ray, which is a portion of a first set of rays processed by a first single instruction multiple data process (SIM). The intersection shader determines whether a ray bounce of the first ray intersects with a first primitive. The sorting unit receives first metadata related to the ray bounce of the first ray intersecting with the first primitive and assigns the first ray to a second set of rays based on the first metadata, wherein the second set of rays may be processed by a second SIM. In one embodiment, the first primitive may include the nearest primitive intersecting with the ray bounce of the first ray, and the first metadata may include a material identifier of the first primitive, an identifier of the first primitive intersecting with the ray boundary of the first ray, a pixel position, and the number of bounces of the ray bounce intersecting with the first primitive. In another embodiment, the intersection shader may also determine whether a ray bounce of a second ray intersects with a second primitive, wherein the second ray may be a portion of a second set of rays. The sorting unit can also receive second metadata related to the ray bounce of the second ray that intersects with the second primitive, and assign the second ray to a third group of rays based on the second metadata. The third group of rays can be processed by a third single instruction multiple data processing. The second metadata may include the material identifier of the second primitive, the identifier of the second primitive that intersects with the ray boundary of the second ray, the pixel position, and the number of bounces of the ray that intersects with the second primitive. Attached Figure Description

[0009] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, wherein:

[0010] Figure 1 This is an execution control flowchart of a typical ray tracing technique based on the DirectX ray tracing and Vulkan RT standards;

[0011] Figure 2 This is an execution control flowchart based on an example embodiment of a ray tracing technique including ray tracing sorting, according to the subject matter disclosed herein;

[0012] Figure 3 It is an execution control flowchart of a typical ray tracing technique that supports the generation of secondary rays based on DirectX ray tracing and the Vulkan RT standard;

[0013] Figure 4 This is an execution control flowchart based on an example embodiment of ray tracing techniques, including ray tracing sorting and secondary ray generation, according to the subject matter disclosed herein;

[0014] Figure 5This is an execution control flowchart based on an example embodiment of the inline ray-tracing technique disclosed herein; and

[0015] Figure 6 The description may include an electronic device that provides ray tracing technology, including ray tracing sorting, according to the subject matter disclosed herein. Detailed Implementation

[0016] In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure. However, those skilled in the art will understand that the aspects of the disclosure may be practiced without these specific details. In other instances, well-known methods, steps, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0017] Throughout this specification, references to "an embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment," "in an embodiment," or "according to an embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification may not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be construed as necessarily preferred or superior to other embodiments. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner. Additionally, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with their non-hyphenated versions (e.g., "two-dimensional", "pre-determined", "pixel specific", etc.), and uppercase entries (e.g., "counter clock", "row select", "pixout", etc.) may be used interchangeably with their non-uppercase versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeability should not be considered inconsistent with each other.

[0018] Furthermore, depending on the context of this discussion, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various figures (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. Similarly, various waveforms and timing diagrams are shown for illustrative purposes only. For example, for clarity, the dimensions of some components may be exaggerated relative to others. Furthermore, reference numerals are repeated in the figures where deemed appropriate to indicate corresponding and / or similar components.

[0019] The terminology used herein is for the purpose of describing some exemplary embodiments only and is not intended to limit the claimed subject matter. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless expressly defined as such, the terms “first,” “second,” etc., as used herein, are used as labels for nouns following them and do not indicate any type of ordering (e.g., spatial, temporal, logical, etc.). Furthermore, the same reference numerals may be used in two or more figures to denote parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is merely for simplification and ease of discussion; it does not imply that the structural or construction details of such components or units are identical in all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0020] It will be understood that when an element or layer is referred to as being on, "connected to," or "bonded to" another element or layer, it may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers. The same reference numerals always denote the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] Unless explicitly defined herein, terms such as “first,” “second,” etc., as used herein, are used as labels preceding nouns and do not indicate any type of ordering (e.g., spatial, temporal, logical, etc.). Furthermore, the same reference numerals may be used in two or more figures to denote parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is merely for simplification and ease of discussion; it does not imply that the structural or construction details of such components or units are identical in all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense.

[0023] As used herein, the term "module" means any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with modules. Software may be implemented as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any implementation described herein may individually include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, and / or firmware storing instructions executed by the programmable circuitry, or may include any combination of hardwired circuitry, programmable circuitry, state machine circuitry, and / or said firmware. Modules may be implemented collectively or individually as part of a larger system (e.g., but not limited to, integrated circuits (ICs), system-on-a-chip (SoCs), etc.).

[0024] The subject matter disclosed herein provides a technique for reallocating ray intersection processing from one warp (or wavefront) of a GPU to other warps (or wavefronts). A set of rays initially assigned to a particular warp / wavefront passes through an acceleration structure to identify objects in the graphics scene that have been hit by the rays. In one example, a set of rays may be processed by a corresponding Single Instruction Multiple Data (SIMD) process. For example, a first set of rays may be processed by a first SIMD process, and a second set of rays may be processed by a second SIMD process. However, the above example is exemplary, and the invention does not limit the number of ray sets, and the number of ray sets may be three or more. Additionally, the first set of rays may correspond to a first warp or a first wavefront, and the second set of rays may correspond to a second warp or a second wavefront. Bounce rays (also known as ray bounces) may be generated based on the ray's hit on an object and based on the material properties of the hit object. The bounce rays pass through the acceleration structure to determine further hits on the object by the bounce rays. Ray intersections from primary (initial) rays or secondary (bounce) rays can be reassigned to other thread bundles based on the material identifier (ID) used to determine a specific material shader (closest hit), the primitive ID used to identify the specific primitive being intersected, the pixel (x,y) position, and the bounce number used to locate information associated with the ray intersection. In one embodiment, the pixel (x,y) position and bounce number can uniquely identify the intersection of a given ray.

[0025] To avoid potential branch divergence during the execution of the nearest-hit shader, the call to the nearest-hit shader can be deferred or delayed, and it is not called as part of the ray generation process as is traditionally done. Deferring the call to the nearest-hit shader can cause the ray generation shader to be separated from the final color of the generated pixel. Therefore, as disclosed herein, ray tracing can be implemented as a separate unit or can be implemented using a sorting unit on the GPU or existing pixel binning infrastructure (if available).

[0026] Traditionally, mobile GPUs implement complete primitive pixel combinations before rendering, while modern desktop GPUs can implement some form of batch pixel combination, where small batches of primitives can be combined based on the pixels they touch. Pixel combination involves sorting primitives and generating a structure that indicates which primitives contain the coverage in each pixel combination (which typically corresponds to a given rectangular array of pixels in screen space). The subject matter disclosed herein provides a similar sorting process to sort each ray / primitive intersection for various keys such as (x,y) position, material ID, etc. That is, the subject matter disclosed herein can use sorting units or pixel combination units to sort rays so that rays that need to execute the same material shader and may touch pixels in the same spatial proximity run as part of the same thread bundle or run as close together in time as possible. Therefore, the ray tracing technique disclosed herein reduces as much as possible the inefficiency experienced by conventional ray tracing techniques in the local domain. In conventional ray tracing, only a portion of the rays in the thread beam / wavefront material shader are actually being executed, while the remaining rays remain idle, and GPU resources are being consumed without actually producing any useful work. By reordering the rays to different thread beams / wavefronts, the material shader can be used more efficiently.

[0027] Figure 1 This is an execution control flow diagram of a typical ray tracing technique 100 based on the DirectX ray tracing and Vulkan RT standards. At 101, a ray generation shader is initiated on a group of rays with spatially proximal origins by grouping rays together as thread bundles / wavefronts. At 102, the ray generation shader invokes the accelerated structure traversal method (or device). At 103, during the accelerated structure traversal, the intersection shader determines whether each ray of the thread bundle / wavefront intersects a primitive, and if so, determines which primitive among those intersecting the ray is the first primitive to intersect the ray. Different rays can intersect different primitives.

[0028] Once the first primitive intersecting each ray has been determined, in step 104, any hit shader is executed for all rays of the thread beam / wavefront, if necessary. Based on the intersecting primitives, any hit shader executed for all rays can be the same or different. Any hit shader can be called on the ray-generating shader's function stack. The accelerated processing of structure traversal, intersection shader execution, and any hit shader execution continues for all rays until the nearest hit primitive for each ray has been determined (or until it has been determined that the ray does not intersect with any primitive).

[0029] If, at step 105, the nearest primitive that has been hit by a ray from the thread beam / wavefront has been identified, the process continues to step 106, where the nearest hit shader is invoked for each ray that intersects with the primitive, and the color at the intersection between the ray and the primitive is evaluated. If, at step 105, it is determined that the ray does not intersect with the primitive, at step 107, the miss shader is invoked for that ray to generate a result such as "sky" or other environmental values ​​based on the environment (e.g., a space scene or a starry night). Upon completion of control flow 100, the ray generation shader returns the final color of the pixel being processed. This color can then be used to appropriately perturb the original color at the pixel being processed.

[0030] Each ray in the set can potentially intersect with different primitives, each with different primitive properties. Therefore, there is a possibility of branching and diverging within the threads of the thread bundle. The shooting rate is determined by the ray closest to any of the hit shader, miss shader, or ray-generating shader that can trigger a secondary ray.

[0031] Figure 2 This is an execution control flowchart based on an example embodiment of a ray tracing technique 200 including ray tracing ordering, according to the subject matter disclosed herein. Figure 2 As shown, the ray tracing is performed as previously described until the closest hit primitive is determined at step 205. That is, Figure 2 Operations 201 to 205 in the text correspond to Figure 1 The conventional operations 101 to 105 are described herein. Furthermore, operations 201 to 207 can be implemented as modules comprising any combination of software, firmware, and / or hardware configured to provide the functions described herein in conjunction with the modules.

[0032] The result of ray tracing operations is a color value that can be applied to a specific pixel location (x, y). In the case of primary rays (emitted from the eye to the screen), the pixel location (x, y) corresponds to the point on the screen where the ray intersects with the screen (i.e., the pixel). In the case of secondary rays, the pixel location (x, y) corresponds to the origin of the pixel. In the case of bounced rays, the specific pixel location (x, y) corresponds to the origin of the secondary ray. In other words, the color applied to a pixel can undergo a series of bounces (i.e., even if the object itself is not directly illuminated, the set of mirrors can cause specular highlights on the object). Instead of traditionally performing the closest hit shader (in... Figure 1 106 in Figure 2In step 206, the data used by the closest hit shader can be stored in the attribute storage device, and the metadata (i.e., material ID, primitive ID, pixel position (x,y) of ray / primitive intersection, and bounce count) can be sent to the sorting unit or pixel combination unit for sorting, so that the intersection of primary rays (or secondary rays) can be reassigned to other thread bundles, which then run as part of the same thread bundle or run as close as possible in time.

[0033] Ray intersections can be sorted using 4-tuple metadata in 206, listed in dictionary order. That is, when the primitive corresponding to the material ID metadata is determined to be the closest hit for a ray, the material ID metadata can be used to determine which specific material shader (closest hit) is executed. The primitive ID metadata identifies the specific primitive being intersected, which can help group all accesses to the same primitive together and potentially lead to better spatial locality during texture accesses in the material shader. Sort using pixel position (x,y) metadata can be optional but can be used to help achieve good spatial and temporal locality in texture caches and / or color buffers. Pixel position (x,y) can also be useful for tile-based architectures. Bounce count metadata can be used to locate information associated with ray intersections (such as the centroid factor of the intersection, the ray origin, and the ray direction). In one embodiment, pixel position (x,y) and bounce count together uniquely identify the intersection of a given ray.

[0034] In 207, missed ray data can be sent to the sorting unit or pixel combination unit for processing. In this case, the missed shader can be considered a special case of the closest hit shader, where the primitive ID is always empty (NULL) and the bounce count is zero. The material ID can be set to a default value representing the missed shader. For the same efficiency considerations to avoid branch divergence, all missed shader rays can be grouped together into a thread bundle. (Typical missed shaders may have internal divergence; therefore, sorting the missed shader calls based on the ray vector and ray origin can also improve efficiency.)

[0035] Some modern GPU architectures employ pixel combining units, which increase the spatial and temporal locality of access to the depth / color buffer and also minimize read / write traffic. In architectures that support pixel combining, the hardware architecture can be reused and appropriately modified to accelerate ray tracing according to the topics disclosed herein.

[0036] As mentioned above, Figure 2The ray tracing technique 200, which includes ray tracing sorting, is separated from the generation of the final color output of the pixels. Therefore, the ray generation shader 201 can be responsible only for sending intersecting or missing data to the sorting unit. The final color data can be available after the rays have been reassigned to other ray groups (thread beams / wavefronts) and after all the ray groups whose closest hit shaders have been reassigned have been executed.

[0037] Because the ray generation shader 200 is separated from the color output generation, the closest hit shader can leverage the existing graphics architecture to optimize ray tracing functionality. The closest hit shader can... Figure 2 Executed after 206, and may include the following operations: Some (or all) of the ray intersections may be collected and sorted based on the criteria described above. Thread bundles / wavefronts may be created using rays with the same material ID. Multiple thread bundles / wavefronts may be created if there are more ray intersections than the capacity of a thread bundle. Data may be sent to a color buffer (or tile buffer) unit for writing to memory. Blending may potentially be performed in the color buffer unit. Alternatively, blending may be performed in the shader kernel, and the color buffer unit may simply write the data to memory. For example, if the color interference expression is relatively uncomplicated, an existing color rendering operation (CROP) unit may be able to handle blending the color obtained from the ray with the pixel color of the ray interference. If the color interference expression is relatively more complex, the color interference may be performed within the nearest hit shader, and the color output is written to the color buffer. In this case, the color calculated during the previous pass (if any) may be loaded as a texture.

[0038] Figure 3 This is an execution control flowchart for typical ray tracing techniques 300 that support the generation of secondary rays based on DirectX ray tracing and the Vulkan RT standard. Both DirectX ray tracing and the Vulkan RT standard support never hitting the shader ( Figure 1 107 in the middle) and the closest hit shader ( Figure 1 (106) generates secondary rays. Figure 3 Operations 301 to 307 correspond to Figure 1Operations 101 through 107 are performed. After calling the nearest hit shader at 306 or the miss shader at 307, it is determined at 308 and 309, respectively, that there is a ray bounce. If a ray bounce exists at 308 or 309, the process returns to the accelerated structure traversal at 302, respectively. If there is no ray bounce at 308 or 309, the process continues to 310 or 311 to return from the ray generation process, respectively. It should be noted that, according to the DirectX ray tracing and Vulkan RT standards, the ray generation process can result in recursive calls to the accelerated structure traversal, which in turn can call the miss shader or the nearest hit shader.

[0039] As disclosed herein, ray tracing techniques include ray tracing ordering; however, the determination of bounced rays is performed after the nearest hit or miss shader has been executed, which occurs much later than in conventional ray tracing methods. The later execution of the nearest hit or miss shader can result in much longer recursive loops, but this can be potentially shortened by running only the determination of whether to create a secondary ray for the nearest hit (or miss) shader without evaluating the color portion. The determination of whether to bounce a secondary ray is typically based on material properties, and the compiler can be modified to create ray bounce shaders from the nearest hit and miss shaders, wherein the ray bounce shader can be a lightweight nearest hit shader. As used herein, the term "lightweight nearest hit shader" refers to a shader that determines whether a bounced ray is needed only by considering a portion, not all, of the material properties, thus allowing less processing at this point when all that is needed is to determine the bounced ray (or multiple rays). No computations that do not lead to its result are excluded. Therefore, the techniques disclosed herein provide a method where color is not evaluated when a secondary ray is created.

[0040] Figure 4 This is an execution control flowchart based on an example embodiment of a ray tracing technique 400, including ray tracing ordering and secondary ray generation, according to the subject matter disclosed herein. Ray tracing is performed until the closest primitive to the hit is determined (i.e., operations 401 to 405). Figure 2 As indicated in operations 201 to 205. Furthermore, operations 401 to 409 can be implemented as modules comprising any combination of software, firmware, and / or hardware configured to provide the functions described herein in conjunction with the modules described.

[0041] In 406, it's similar to... Figure 2 In operation 206, the data used by the closest hit shader can be stored in the attribute storage device, and the metadata can be sent to the sorting unit or pixel combination unit for sorting. Figure 4In section 406, data used by the closest hitting shader can be stored in the attribute store, and metadata (i.e., material ID, primitive ID, pixel (x, y), and bounce count) can be sent to a sorting unit or pixel combination unit for sorting, so that the intersection of primary rays (or secondary rays) can be reassigned to other thread bundles, which then run as part of the same thread bundle or as close in time as possible. In section 407, similarly... Figure 2 Operation 207 in the code can invoke a missed shader.

[0042] After sending the intersecting ray data for sorting at 406 or the missing ray data for sorting at 407, it can be determined at 408 and 409, respectively, whether there is ray bounce. If yes, the process returns to the accelerated structure traversal at 402. If not, the process continues to 410 or 411 to return from the ray generation process, respectively.

[0043] exist Figure 4 In this process, the ray bounce phase (operations 408 and 409) is instructed to return to the accelerated traversal operation in 402. A recursive function call mechanism can be used to handle ray bounces. Optionally, if the GPU running the ray generation shader 401 does not support function recursion, information can be returned to the ray generation shader 401. It should also be noted that the execution of the ray tracing processing disclosed herein is completely independent of any stage of pixel rendering.

[0044] The ray tracing technique with ray tracing sorting disclosed herein ( Figure 2 and Figure 4 This can be implemented in an Immediate Mode Rendering (IMR) architecture (such as that used in desktops) that provides some form of primitive batch pixel combination. Material ID, primitive ID, pixel (x,y) and bounce count data can be sent to a batch pixel combiner (or a batch pixel combination structure including a spatial sorting structure) for sorting. Ray intersection properties can be sent to an attribute store (which may be referred to as a parameter cache on an AMD architecture). When the batch is full, the intersections in the batch can be sorted and used to build thread bundles. The thread bundle closest to the hit shader can be completed, and the color value is sent to a color buffer. At any given time, one batch of intersections can be pixel-combined, while another batch of intersections can be executing the closest hit shader.

[0045] In a tile-based rendering (TBR) architecture where a full pixel combiner is implemented, metadata from ray-generating shaders 200 or 400 can be sent to the pixel combiner. The pixel combiner can sort the following 6-tuple: (tileID, material ID, prim ID, tile_X, tile_Y, bounce#), where tile ID represents the tile ID, material ID (or material ID) represents the material ID, prim ID represents the primitive ID, tile_X represents the tile's X coordinate, tile_Y represents the tile's Y coordinate, and bounce# represents the number of bounces. Conceptually, the 6-tuple may not differ from the general 4-tuple described above. The 6-tuple rearranges the (x, y) coordinates to separate the tile coordinates or ID (which can be different ways of representing the same information) from the x and y offsets within the tile. Because all rendering of the color buffer can be done only within the tile, the tile ID can be moved to the beginning of the 6-tuple. The pixel combiner creates a stream and outputs the data structure along with attribute information to memory. Once all rays have been generated (using the ray bounce shader described above), the ray pixel combination data structure can be traversed, and the nearest-hit shader for each of these intersections can be executed, with color information sent to the tile buffer. Colors can be blended in the clipping unit or in the shader.

[0046] In one embodiment, inline ray-tracing can be performed in a manner similar to combining... Figure 2 and Figure 4 Ray tracing is performed in a manner described in the ray tracing technique. That is, inline ray tracing can be invoked from any shader, and as the name of the technique variant suggests, inline ray tracing can be invoked inline within any current shader. In such an implementation, there are typically no multiple shaders (e.g., ray-generating shader, nearest-hit shader, etc.). All functions available for generating rays, performing intersections, and shading after intersection (provided by code in one example embodiment) are "inlined" into a single shader. Furthermore, each of the materials to be shaded after intersection can be listed as part of an if-else ladder.

[0047] Inline ray tracers can exhibit ray divergence issues. To address this problem, the inline ray tracing technique disclosed herein stops the shader at the point where the material shader will begin processing. At this stopping point, the shader can invoke a ray intersection test, and, if combined... Figure 2 and Figure 4As described in ray tracing technology, if ray intersections are identified, then the details of the ray intersections (i.e., metadata) are sent to the pixel combiner for sorting and reassignment to another ray beam / wavefront.

[0048] The if-then structure processed after the ray intersection test can be split into one or more shaders. If multiple shaders are implemented, each shader can contain functionality for one material (provided by code in one example embodiment). If only one shader is available, all if-then functions can be included in that shader. However, since the material shader is executed after the ray intersections are sorted, no branch divergence is expected because all ray intersections have the same material ID.

[0049] Figure 5 This is an execution control flowchart based on a portion of an example embodiment of the inline ray tracing technique 500 disclosed herein. Specifically, Figure 5 The inline ray tracing technique 500 describes a pixel shader 501 that includes a ray generation function (i.e., the raygen() function). The pixel shader 501 may call one or more material shaders 502a to 502n (e.g., material #1 502a, material #2 502b, ..., and material #n 502n), wherein each material calls one of the material shaders 502a to 502n. The pixel shader 501 and the material shaders 502a to 502n may be implemented as modules comprising any combination of software, firmware, and / or hardware configured to provide the functionality described herein.

[0050] Figure 6 The description includes an electronic device 600 that may include a GPU providing ray tracing technology, including ray tracing sequencing, according to the subject matter disclosed herein. The electronic device 600 can be used, but is not limited to, computing devices, personal digital assistants (PDAs), laptop computers, mobile computers, network tablets, wireless phones, cellular phones, smartphones, digital music players, wired or wireless electronic devices, head-up displays, and displays for automotive applications. The electronic device 600 may include a controller 610, input / output (I / O) devices 620 (such as, but not limited to, keypads, keyboards, displays, touchscreen displays, cameras, and / or image sensors), memory 630, interface 640, GPU 650, and image processor 660, all coupled together via a bus 670. The controller 610 may include, for example, at least one microprocessor, at least one digital signal processor, at least one microcontroller, etc. The memory 630 may be configured to store command codes or user data to be used by the controller 610.

[0051] Electronic device 600 and its various system components may include a GPU that provides ray tracing techniques, including ray tracing sequencing, according to the subject matter disclosed herein. Interface 640 may be configured to include a wireless interface configured to transmit or receive data from a wireless communication network using radio frequency (RF) signals. Wireless interface 640 may include, for example, an antenna, a wireless transceiver, etc. Electronic System 600 can also be used in communication interface protocols of communication systems, such as, but not limited to, Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Communications (NADC), Extended Time Division Multiple Access (E-TDMA), Wideband CDMA (WCDMA), CDMA2000, Wi-Fi, Municipal Wi-Fi (Muni Wi-Fi), Bluetooth, Digital Enhanced Radiotelephone System (DECT), Wireless Universal Serial Bus (Wireless USB), Fast Low Latency Access with Seamless Switching Orthogonal Frequency Division Multiplexing (Flash-OFDM), IEEE 802.20, General Packet Radio Service (GPRS), iBurst, Wireless Broadband (WiBro), WiMAX, Advanced WiMAX, Universal Mobile Telecommunications Service - Time Division Duplex (UMTS-TDD), High Speed ​​Packet Access (HSPA), Evolved Data Optimized (VDO), Advanced Long Term Evolution (LTE-Advanced), Multichannel Multipoint Allocation Service (MMDS), etc.

[0052] The embodiments of the subject matter and operation described in this specification can be implemented in digital electronic circuits, or in computer software, firmware, or hardware, or a combination thereof, including the structures disclosed in this specification and their equivalents. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs (i.e., one or more modules of computer program instructions) encoded on a computer storage medium for execution by or control of the operation of a data processing device. Optionally or additionally, the program instructions may be encoded on artificially generated propagation signals (e.g., machine-generated electrical, optical, or electromagnetic signals) generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random access memory array or device, or a serial access memory array or device, or a combination thereof, or may be included in a computer-readable storage device, a computer-readable storage substrate, a random access memory array or device, or a serial access memory array or device, or a combination thereof. Furthermore, although the computer storage medium is not a propagation signal, it may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. Computer storage media may also be one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices), or may be included within one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Furthermore, the operations described in this specification can be implemented as operations performed by a data processing device on data stored on one or more computer-readable storage devices or on data received from other sources.

[0053] While this specification may contain numerous specific implementation details, these details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of features specific to particular embodiments. Specific features described in this specification within the context of individual embodiments may also be implemented in combination with a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually with multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as functioning in a particular combination and even initially claimed in this way, one or more features from a claimed combination may be removed from the combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0054] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or sequentially, or to perform all shown operations to achieve the desired result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments; it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0055] Therefore, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.

[0056] As those skilled in the art will recognize, the novel concepts described herein can be modified and altered within the broad scope of the application. Therefore, the scope of the claimed subject matter should not be limited to any particular exemplary teachings discussed above, but is defined by the claims.

Claims

1. A ray tracing method, comprising: The ray tracing pipeline of the graphics processor determines the intersection of the ray bounce of the first ray with the first primitive. The first ray is a part of the first group of rays processed by the first single instruction multiple data processing. as well as The sorting unit of the graphics processor assigns the first ray to the second group of rays based on the intersection of the ray bounce of the first ray with the first primitive. The second group of rays is then processed by the second single instruction multiple data processing unit. The step of assigning the first ray to the second group of rays is further based on the material identifier of the first primitive and the identifier of the first primitive that intersects with the ray bounce of the first ray. The step of assigning the first ray to the second group of rays is also based on the pixel position and the number of bounces of the rays that intersect with the first primitive.

2. The ray tracing method according to claim 1, wherein, The first primitive includes the nearest primitive that intersects with the ray bounce of the first ray.

3. The ray tracing method according to claim 1 further includes: The ray tracing pipeline is used to determine that the ray bounce of the second ray intersects with the second primitive, and the second ray is part of the second group of rays; as well as The sorting unit, based on the intersection of the second ray's bounce with the second primitive, assigns the second ray to the third group of rays. The third group of rays is then processed by the third single-instruction multiple-data processing unit. The step of assigning the second ray to the third group of rays is further based on the material identifier of the second primitive and the identifier of the second primitive that intersects with the ray bounce of the second ray. The step of assigning the second ray to the third group of rays is also based on the pixel position and the number of bounces of the rays that intersect with the second primitive.

4. The ray tracing method according to claim 3 further includes: The ray tracing pipeline sends ray intersection information, related to the intersection of the ray bounce of the first ray with the first primitive, to the sorting unit.

5. The ray tracing method according to any one of claims 1 to 4, wherein, The ray tracing method is part of the inline ray tracing technology.

6. The ray tracing method according to any one of claims 1 to 4, wherein, The first set of rays corresponds to the first thread beam or the first wavefront, and the second set of rays corresponds to the second thread beam or the second wavefront.

7. The ray tracing method according to any one of claims 1 to 4, wherein, The first group of light rays includes light rays that are spatially close, and the second group of light rays includes light rays that are spatially close.

8. A ray tracing method, comprising: The ray generation shader of the graphics processor is invoked to generate a first ray, which is a portion of a first set of rays processed by the first single instruction multiple data processing. The ray tracing pipeline is used to determine the intersection of the ray bounce of the first ray with the first primitive; The ray tracing pipeline sends first metadata related to the ray bounce of a first ray intersecting with a first primitive to the sorting unit of the graphics processor. The first metadata includes a material identifier of the first primitive and an identifier of the first primitive intersecting with the ray bounce of the first ray. The graphics processor's sorting unit assigns the first ray to a second group of rays based on first metadata related to the ray bounce of the first ray intersecting with the first primitive. The second group of rays is then processed by a second single instruction multiple data processing unit. The first metadata also includes the pixel position and the number of bounces of the light rays that intersect with the first primitive.

9. The ray tracing method according to claim 8, wherein, The first primitive includes the nearest primitive that intersects with the ray bounce of the first ray.

10. The ray tracing method according to claim 8, further comprising: The ray tracing pipeline is used to determine that the ray bounce of the second ray intersects with the second primitive, and the second ray is part of the second group of rays; The ray tracing pipeline sends second metadata related to the ray bounce of the second ray intersecting the second primitive to the sorting unit. This second metadata includes the material identifier of the second primitive and the identifier of the second primitive intersecting the ray bounce of the second ray; and The sorting unit assigns the second ray to the third group of rays based on the second metadata. The third group of rays is then processed by the third single instruction multiple data processing unit. The second metadata also includes the pixel location and the number of bounces of the light rays that intersect with the second primitive.

11. The ray tracing method according to any one of claims 8 to 10, wherein, The ray tracing method is part of the inline ray tracing technology.

12. The ray tracing method according to any one of claims 8 to 10, wherein, The first set of rays corresponds to the first thread beam or the first wavefront, and the second set of rays corresponds to the second thread beam or the second wavefront.

13. The ray tracing method according to any one of claims 8 to 10, wherein, The first group of light rays includes light rays that are spatially close, and the second group of light rays includes light rays that are spatially close.

14. A graphics pipeline, comprising: The graphics processor's ray generation shader generates a first ray, which is a portion of a first set of rays processed by the first single instruction multiple data processing (SIMDF). The intersection shader determines where the bounce of the first ray intersects with the first primitive; as well as The sorting unit receives first metadata related to the ray bounce of a first ray intersecting with a first primitive, and assigns the first ray to a second group of rays based on the first metadata. The second group of rays is processed by a second single-instruction multiple-data process. The first metadata includes the material identifier of the first primitive and the identifier of the first primitive intersecting with the ray bounce of the first ray. The first metadata also includes the pixel position and the number of bounces of the light rays that intersect with the first primitive.

15. The graphic pipeline according to claim 14, wherein, The first primitive includes the nearest primitive that intersects with the ray bounce of the first ray.

16. The graphic pipeline according to claim 15, wherein, The intersection shader also determines that the ray bounce of the second ray intersects with the second primitive, and that the second ray is part of the second set of rays. The sorting unit also receives second metadata related to the ray bounce of the second ray that intersects with the second primitive, and assigns the second ray to a third group of rays based on the second metadata. The third group of rays is processed by a third single instruction multiple data processing. The second metadata includes the material identifier of the second primitive, the identifier of the second primitive that intersects with the ray bounce of the second ray, the pixel position, and the number of bounces of the ray that intersects with the second primitive.

17. The graphics pipeline according to any one of claims 14 to 16, wherein, The graphics pipeline is performing inline ray tracing.

18. The graphics pipeline according to any one of claims 14 to 16, wherein, The first set of rays corresponds to the first thread beam or the first wavefront, and the second set of rays corresponds to the second thread beam or the second wavefront.

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