Display device

Abstract

A display device includes a display area including pixels for displaying an image, a non-display area adjacent to the display area, scan lines connected to the pixels, a first scan driver circuit disposed in the non-display area, wherein the first scan driver circuit is connected to a first scan line among the scan lines and outputs a first scan signal to the first scan line, and a second scan driver circuit disposed in the non-display area, wherein the second scan driver circuit is connected to a second scan line among the scan lines and outputs a second scan signal to the second scan line. The second scan driver circuit is disposed farther from the display area than the first scan driver circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices. Background Technology

[0002] With the development of the information society, the demand for display devices is constantly increasing. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and organic light-emitting diode (OLED) displays. OLED displays offer a variety of desirable characteristics, including wide viewing angles, high contrast, and fast response times. Furthermore, because OLED displays can be bent or flexed, they are widely used in various electronic devices.

[0004] Recently, a display device for displaying images on sides bent at the four edges of the front surface of an organic light-emitting display device has been studied. Such a display device includes a corner between a first side surface bent at a first side edge of the front surface and a second side surface bent at a second side edge of the front surface. The corner may have a hyperbola due to the curvature of the first side surface and the curvature of the second side surface. Summary of the Invention

[0005] Embodiments of the present invention provide a display device that can reduce the size of the non-display area at a corner with hyperbola.

[0006] Embodiments of the present invention provide a display device, comprising: a display area including pixels for displaying an image; a non-display area adjacent to the display area; scan lines connected to the pixels; a first scan driver circuit disposed in the non-display area, wherein the first scan driver circuit is connected to a first scan line among the scan lines and outputs a first scan signal to the first scan line; and a second scan driver circuit disposed in the non-display area, wherein the second scan driver circuit is connected to a second scan line among the scan lines and outputs a second scan signal to the second scan line. In such an embodiment, the second scan driver circuit is disposed further away from the display area than the first scan driver circuit.

[0007] Embodiments of the present invention provide a display device, comprising: a display area having pixels arranged thereon; a first scan line connected to a first pixel among the pixels; a second scan line connected to a second pixel among the pixels; a scan driver circuit connected to the first scan line and the second scan line, wherein the scan driver circuit outputs scan signals to the first scan line and the second scan line; and a first power supply voltage line arranged between the scan driver circuit and the display area, wherein a first power supply voltage is applied to the first power supply voltage line. In such an embodiment, the area overlapping between one of the second scan lines and the first power supply voltage line is larger than the area overlapping between one of the first scan lines and the first power supply voltage line.

[0008] Embodiments of the present invention provide a display device, comprising: a display panel including a front surface, a first side surface extending from a first side of the front surface, a second side surface extending from a second side of the front surface; and a corner disposed between the first side surface and the second side surface. In such an embodiment, the corner includes: a corner display area disposed of pixels for displaying images; and a corner auxiliary display area adjacent to the corner display area disposed of pixels. In such an embodiment, the number of pixels per unit area in the corner display area is greater than the number of pixels per unit area in the corner auxiliary display area. Attached Figure Description

[0009] These and / or other features of the invention will become apparent and more readily understood through a further detailed description of embodiments of the invention with reference to the accompanying drawings, wherein:

[0010] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0011] Figure 2 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0012] Figure 3 This is a schematic plan view illustrating a display device according to an embodiment of the present disclosure.

[0013] Figure 4 This is a diagram illustrating the layout of a display device according to an embodiment of the present disclosure.

[0014] Figure 5A It is shown in detail Figure 4 An enlarged view of an embodiment of the layout of region A.

[0015] Figure 5B It is shown in detail Figure 5A An enlarged view of an embodiment of the layout of region A'.

[0016] Figure 6A It is shown Figure 5AA circuit diagram of an embodiment of the pixel.

[0017] Figure 6B It is shown Figure 5A Circuit diagrams of alternative embodiments of the pixels,

[0018] Figure 7 It is shown Figure 5A A circuit diagram of an embodiment of the scan driver circuit.

[0019] Figure 8 It is shown Figure 5A A circuit diagram of an embodiment of the transmitter driver circuit.

[0020] Figure 9A This is a diagram illustrating the layout of the first corner according to an alternative embodiment.

[0021] Figure 9B It is shown in detail Figure 9A An enlarged view of the layout of region B.

[0022] Figure 9C It is shown Figure 9A A diagram showing the width of the non-display area at the first corner, the width of the first side surface, the width of the fourth side surface, the width of the first circuit area, and the width of the second circuit area.

[0023] Figure 10 It shows along Figure 9B A cross-sectional view of an embodiment of the display panel, taken by line I-I'.

[0024] Figure 11 It shows along Figure 9B A cross-sectional view of an embodiment of the display panel, taken by line II-II'.

[0025] Figure 12 It shows along Figure 9B A cross-sectional view of an embodiment of the display panel, taken by line III-III'.

[0026] Figure 13A This is a diagram illustrating the layout of the first corner according to an alternative embodiment.

[0027] Figure 13B It is shown Figure 13A An exemplary diagram showing the width of the first corner non-display area, the width of the first circuit area, and the width of the second circuit area.

[0028] Figure 14 It shows along Figure 13A A cross-sectional view of an example display panel taken by line IV-IV'.

[0029] Figure 15This is a diagram illustrating the layout of the first corner according to another alternative embodiment.

[0030] Figure 16 This is a diagram illustrating the layout of the first corner according to yet another alternative embodiment.

[0031] Figure 17 This is a diagram illustrating the layout of the first corner according to yet another alternative embodiment.

[0032] Figure 18 This is a diagram illustrating the layout of the first corner according to yet another alternative embodiment.

[0033] Figure 19 This is a diagram illustrating the layout of a display device according to yet another alternative embodiment of the present disclosure, and

[0034] Figure 20 This is a diagram illustrating the layout of a display device according to yet another alternative embodiment of the present disclosure. Detailed Implementation

[0035] The invention will now be described more fully below with reference to the accompanying drawings, in which embodiments of the invention are illustrated. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be exhaustive and comprehensive, and will fully convey the scope of the invention to those skilled in the art. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0036] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings of this document, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second area, second layer, or second part.

[0037] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on that other layer or substrate, or there may be an intermediate layer. Conversely, when an element is referred to as being "directly" on another element, there is no intermediate element.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms that include “at least one”, unless the context clearly indicates otherwise. “Or” means “and / or”. “At least one of A and B” means “A and / or B”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” or “including” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0039] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), as used herein, “about” or “approximately” includes the stated values ​​and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art.

[0040] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and in this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] In this document, the embodiment references are cross-sectional descriptions of schematic diagrams of idealized embodiments. Thus, variations in the illustrated shapes can be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas illustrated herein, but are to include deviations in shape caused, for example, by manufacturing processes. For example, areas illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, the sharp corners illustrated may be rounded. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the areas and are not intended to limit the scope of the claims.

[0042] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0044] The display device 10 according to embodiments of this disclosure can be employed by portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). Alternatively, the display device 10 can be used as a display unit for televisions, laptop computers, monitors, electronic billboards, or the Internet of Things (IoT). Alternatively, the display device 10 can be applied to wearable devices such as smartwatches, smartwatch phones, glasses displays, and head-mounted display (HMD) devices. Alternatively, the display device 10 can be used as a central information display (CID) arranged in the instrument cluster, central dashboard, or instrument panel of a vehicle, as an interior mirror display representing the side mirrors of the vehicle, or as a display located behind each of the front seats (which is an entertainment system for passengers in the rear seats of the vehicle).

[0045] refer to Figure 1 An embodiment of the display device 10 includes a display panel 100 for displaying images.

[0046] As used herein, the first direction (X-axis direction) may refer to the direction in which the shorter side of the display panel 100 extends, for example, the horizontal direction of the display panel 100. The second direction (Y-axis direction) may refer to the direction in which the longer side of the display panel 100 extends, for example, the vertical direction of the display panel 100. The third direction (Z-axis direction) may refer to the thickness direction of the display panel 100.

[0047] Display panel 100 may be a light-emitting display panel including light-emitting elements. For example, in one embodiment, display panel 100 may be an organic light-emitting display panel using organic light-emitting diodes including organic emission layers, a micro light-emitting diode display panel using micro LEDs, a quantum dot light-emitting display panel including quantum dot light-emitting diodes containing quantum dot emission layers, or an inorganic light-emitting display panel using inorganic light-emitting elements including inorganic semiconductors. In the following description, for ease of description, embodiments of display panel 100 as organic light-emitting display panels will be described in detail, but are not limited thereto.

[0048] Embodiments of the display panel 100 include a front surface FS, a first side surface SS1, a second side surface SS2, a third side surface SS3, and a fourth side surface SS4.

[0049] When viewed from a top (or front) view, the front surface FS may have, but is not limited to, a rectangular shape having a shorter side in a first direction (X-axis direction) and a longer side in a second direction (Y-axis direction). When viewed from a top view, the front surface FS may have one of other polygonal, circular, or elliptical shapes. Each of the corners of the front surface FS where the shorter side in the first direction (X-axis direction) intersects the longer side in the second direction (Y-axis direction) may be a circle with a predetermined curvature or a right angle. The front surface FS may be formed as a flat surface or may include a curved surface.

[0050] A first side surface SS1 may extend from a first side of the front surface FS. The first side surface SS1 bends along a first bend line BL1 on the first side of the front surface FS. The first side surface SS1 may have a first curvature (or a first radius of curvature). The angle formed between the front surface FS and the first side surface SS1 may be approximately 90 degrees or less. The first side of the front surface FS may be the left side of the front surface FS.

[0051] The second side surface SS2 may extend from the second side of the front surface FS. The second side surface SS2 bends along the second bend line BL2 on the second side of the front surface FS. The second side surface SS2 may have a second curvature (or a second radius of curvature). The second curvature may be substantially equal to or different from the first curvature. The angle formed between the front surface FS and the second side surface SS2 may be approximately 90 degrees or less. The second side of the front surface FS may be the right side of the front surface FS.

[0052] The third side surface SS3 may extend from the third side of the front surface FS. The third side surface SS3 bends along the third bend line BL3 on the third side of the front surface FS. The third side surface SS3 may have a third curvature (or a third radius of curvature). The angle formed between the front surface FS and the third side surface SS3 may be approximately 90 degrees or less. The third side of the front surface FS may be the underside of the front surface FS.

[0053] The fourth side surface SS4 can extend from the fourth side of the front surface FS. The fourth side surface SS4 bends along the fourth bend line BL4 on the fourth side of the front surface FS. The fourth side surface SS4 can have a fourth curvature (or a fourth radius of curvature). The fourth curvature can be substantially equal to or different from the third curvature. The angle formed between the front surface FS and the fourth side surface SS4 can be approximately 90 degrees or less. The fourth side of the front surface FS can be the upper side of the front surface FS.

[0054] Figure 2 This is a plan view illustrating a display device according to an embodiment of the present disclosure. Figure 3 This is a schematic plan view illustrating a display device according to an embodiment of the present disclosure. Figure 4This is a diagram illustrating the layout of a display device according to an embodiment of the present disclosure.

[0055] refer to Figures 2 to 4 An embodiment of the display panel 100 may include a front surface FS, a first side surface SS1, a second side surface SS2, a third side surface SS3 and a fourth side surface SS4, as well as a first corner CS1, a second corner CS2, a third corner CS3 and a fourth corner CS4.

[0056] The front surface FS of the display panel 100 includes a front display area FDA for displaying images. The front surface FS may be defined solely by the front display area FDA.

[0057] The first side surface SS1 includes a first side display area SDA1 for displaying images and a first side non-display area SNA1 for not displaying images. The first side display area SDA1 may be arranged to the left of the front display area FDA, and the first side non-display area SNA1 may be arranged to the left of the first side display area SDA1. The first side non-display area SNA1 may be arranged on the left edge of the display panel 100.

[0058] The front display area FDA and the first side display area SDA1 can be divided by a first bend line BL1. That is, the front display area FDA can be the area located to the right of the first bend line BL1, and the first side display area SDA1 can be the area located to the left of the first bend line BL1.

[0059] The second side surface SS2 includes a second side display area SDA2 for displaying images and a second side non-display area SNA2 for not displaying images. The second side display area SDA2 can be arranged to the right of the front display area FDA, and the second side non-display area SNA2 can be arranged to the right of the second side display area SDA2. The second side non-display area SNA2 can be arranged on the right edge of the display panel 100.

[0060] The front display area FDA and the second side display area SDA2 can be divided by the second bend line BL2. That is, the front display area FDA can be the area located to the left of the second bend line BL2, and the second side display area SDA2 can be the area located to the right of the second bend line BL2.

[0061] The third side surface SS3 includes a third side display area SDA3 for displaying images and a third side non-display area SNA3 for not displaying images. The third side display area SDA3 can be disposed below the front display area FDA, and the third side non-display area SNA3 can be disposed below the third side display area SDA3. The third side non-display area SNA3 can be disposed on the lower edge of the display panel 100.

[0062] The front display area FDA and the third side display area SDA3 can be divided by the third bend line BL3. That is, the front display area FDA can be the area located above the third bend line BL3, and the third side display area SDA3 can be the area located below the third bend line BL3.

[0063] The fourth side surface SS4 includes a fourth side display area SDA4 for displaying images and a fourth side non-display area SNA4 for not displaying images. The fourth side display area SDA4 can be disposed above the front display area FDA, and the fourth side non-display area SNA4 can be disposed above the fourth side display area SDA4. The fourth side non-display area SNA4 can be disposed on the upper edge of the display panel 100.

[0064] The front display area FDA and the fourth side display area SDA4 can be divided by the fourth bend line BL4. That is, the front display area FDA can be the area located below the fourth bend line BL4, and the fourth side display area SDA4 can be the area located above the fourth bend line BL4.

[0065] The first corner CS1 can be disposed between the first side surface SS1 and the fourth side surface SS4. The first corner CS1 can be defined as a corner region bending along the first bend line BL1 and the fourth bend line BL4. Therefore, the first corner CS1 can have a hyperbola due to the first curvature of the first side surface SS1 and the fourth curvature of the fourth side surface SS4.

[0066] The first corner CS1 includes a first corner display area CDA1 for displaying an image and a first corner non-display area CNA1 for not displaying an image. The first corner display area CDA1 can be arranged at the upper left corner of the front display area FDA, and the first corner non-display area CNA1 can be arranged at the upper left side of the first corner display area CDA1. The first corner non-display area CNA1 can be arranged on the upper left edge of the display panel 100.

[0067] The second corner CS2 can be disposed between the first side surface SS1 and the third side surface SS3. The second corner CS2 can be defined as a corner region bending along the first bend line BL1 and the third bend line BL3. Therefore, the second corner CS2 can have a hyperbola due to the first curvature of the first side surface SS1 and the third curvature of the third side surface SS3.

[0068] The second corner CS2 includes a second corner display area CDA2 for displaying images and a second corner non-display area CNA2 for not displaying images. The second corner display area CDA2 can be arranged at the lower left corner of the front display area FDA, and the second corner non-display area CNA2 can be arranged at the lower left side of the second corner display area CDA2. The second corner non-display area CNA2 can be arranged on the lower left edge of the display panel 100.

[0069] The third corner CS3 can be arranged between the second side surface SS2 and the third side surface SS3. The third corner CS3 can be defined as a corner region that bends along the second bend line BL2 and the third bend line BL3. Therefore, the third corner CS3 can have a hyperbola due to the second curvature of the second side surface SS2 and the third curvature of the third side surface SS3.

[0070] The third corner CS3 includes a third corner display area CDA3 for displaying images and a third corner non-display area CNA3 for not displaying images. The third corner display area CDA3 can be positioned at the lower right corner of the front display area FDA, and the third corner non-display area CNA3 can be positioned at the lower right side of the third corner display area CDA3. The third corner non-display area CNA3 can be positioned on the lower right edge of the display panel 100.

[0071] The fourth corner CS4 can be arranged between the second side surface SS2 and the fourth side surface SS4. The fourth corner CS4 can be defined as a corner region that bends along the second bend line BL2 and the fourth bend line BL4. Therefore, the fourth corner CS4 can have a hyperbola due to the second curvature of the second side surface SS2 and the fourth curvature of the fourth side surface SS4.

[0072] The fourth corner CS4 includes a fourth corner display area CDA4 for displaying images and a fourth corner non-display area CNA4 for not displaying images. The fourth corner display area CDA4 can be positioned at the upper right corner of the front display area FDA, and the fourth corner non-display area CNA4 can be positioned at the upper right side of the fourth corner display area CDA4. The fourth corner non-display area CNA4 can be positioned on the upper right edge of the display panel 100.

[0073] The sub-region SBA can protrude from the underside of the third side surface SS3 in the second direction (Y-axis direction). The length of the sub-region SBA in the first direction (X-axis direction) can be less than the length of the third side surface SS3 in the first direction (X-axis direction). The sub-region SBA can be bent and can be arranged under the third side surface SS3 and the front surface FS.

[0074] The display driver circuit 200 and the display circuit board 300 can be arranged in the sub-region SBA.

[0075] The display driver circuit 200 can receive control signals and power supply voltages through the display circuit board 300, and can generate and output signals and voltages for driving the display panel 100. The display driver circuit 200 can be attached to a sub-region SBA of the display panel 100 by means of, for example, chip-on-plastic (COP) technology or ultrasonic technology.

[0076] The display circuit board 300 can be a flexible printed circuit board that can be bent, a rigid printed circuit board that is rigid and cannot be bent, or a hybrid printed circuit board that includes both rigid and flexible printed circuit boards. The display circuit board 300 can be attached to the pads of the sub-region SBA of the display panel 100 using low-resistance, high-reliability materials such as anisotropic conductive film and self-assembling anisotropic conductive adhesive (SAP).

[0077] In an embodiment, such as Figure 4 As shown, the first scan driver SDU1 can be arranged in the first side non-display area SNA1, the third side non-display area SNA3, the fourth side non-display area SNA4, the first corner non-display area CNA1, and the second corner non-display area CNA2 of the display panel 100. The first scan driver SDU1 can output scan signals to the scan lines of the display areas FDA, SDA1, SDA2, SDA3, SDA4, CDA1, CDA2, CDA3, and CDA4 of the display panel 100, and can also output transmission signals to the transmission lines. (Refer to...) Figure 5A Provide a detailed description of the scan lines and emission lines.

[0078] In such an embodiment, the second scan driver SDU2 can be arranged in the second-side non-display area SNA2, the third-side non-display area SNA3, the fourth-side non-display area SNA4, the third corner non-display area CNA3, and the fourth corner non-display area CNA4 of the display panel 100. The second scan driver SDU2 can output scan signals to the scan lines of the display areas FDA, SDA1, SDA2, SDA3, SDA4, CDA1, CDA2, CDA3, and CDA4 of the display panel 100, and can also output transmission signals to the transmission lines. The first scan driver SDU1 and the second scan driver SDU2 can output scan signals and transmission signals that are synchronized with each other.

[0079] In an embodiment, such as Figures 2 to 4 As shown, the front surface FS and side surfaces SS1, SS2, SS3 and SS4 of the display panel 100 include display areas FDA, SDA1, SDA2, SDA3 and SDA4 for displaying images, and thus, a user can view images displayed on the front surface FS and side surfaces SS1, SS2, SS3 and SS4 of the display panel 100.

[0080] In such an embodiment, when... Figure 2 As shown, when viewing the display device 10 from the front, the side surfaces SS1, SS2, SS3, and SS4 are bent from the front surface FS, and therefore, the first side non-display area SNA1 of the first side surface SS1, the second side non-display area SNA2 of the second side surface SS2, the third side non-display area SNA3 of the third side surface SS3, and the fourth side non-display area SNA4 of the fourth side surface SS4 are not visible. However, when viewed from the front, the side surfaces SS1, SS2, SS3, and SS4 are not visible. Figure 2 As shown, when viewing the display device 10 from the front, the first corner non-display area CNA1 of the first corner CS1, the second corner non-display area CNA2 of the second corner CS2, the third corner non-display area CNA3 of the third corner CS3, and the fourth corner non-display area CNA4 of the fourth corner CS4 are visible. In such an embodiment, since each of the corners CS1, CS2, CS3, and CS4 has hypercurvature, it is difficult to reduce the area of ​​each of the corner non-display areas CNA1, CNA2, CNA3, and CNA4. Since the aesthetics of the display device 10 are degraded due to the corner non-display areas CNA1, CNA2, CNA3, and CNA4, it is desirable to reduce the area of ​​each of the corner non-display areas CNA1, CNA2, CNA3, and CNA4.

[0081] Figure 5A It is shown in detail Figure 4 An enlarged view of an embodiment of the layout of region A. Figure 5B It is shown in detail Figure 5AAn enlarged view of an embodiment of the layout of region A'. Figure 5A It shows Figure 4 The first corner CS1 and its surrounding area.

[0082] refer to Figure 5A and Figure 5B The first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4 may be circles with a predetermined curvature. A portion of the first side surface SS1 may be adjacent to the first corner CS1 in the first side surface SS1, and a portion of the fourth side surface SS4 may be adjacent to the first corner CS1 in the fourth side surface SS4.

[0083] The first corner display area CDA1, the front display area FDA, the first side display area SDA1, and the fourth side display area SDA4 include pixels PX for displaying images. Pixels PX can be arranged in a matrix form in a first direction (X-axis direction) and a second direction (Y-axis direction). Scan lines SL and emission lines EL can extend in the first direction (X-axis direction). Scan lines SL and emission lines EL can be arranged side-by-side. Data lines can extend in the second direction (Y-axis direction). Data lines can intersect scan lines SL and emission lines EL. For ease of illustration, in... Figure 5A Data lines are not depicted. Each pixel PX may be connected to, but is not limited to, two scan lines SL, one emission line EL, and a data line that intersects with the scan lines SL and the emission line EL.

[0084] In an embodiment, the scan driver circuit SDC and the transmit driver circuit EDC of the first scan driver SDU1 can be arranged in a predetermined area of ​​the first corner non-display area CNA1, the first side non-display area SNA1, and the fourth side non-display area SNA4. The scan driver circuit SDC includes a scan level SST and a dummy scan level DST, and the transmit driver circuit EDC includes a transmit level EST and a dummy transmit level DET.

[0085] The scan level SST and dummy scan level DST of the first scan driver SDU1 can be arranged along the curvature of the first corner CS1 in the predetermined areas of the first corner non-display area CNA1, the first side non-display area SNA1, and the fourth side non-display area SNA4.

[0086] Each scan level SST can be connected to a scan line SL. Each scan line SL can branch into two scan lines SL. For example, in one embodiment, the k-th scan line SLk can branch into the (k-1)-th scan line SL(k-1) and the k-th scan line SLk, where k is a positive integer equal to or greater than 2. The branched scan lines SL can be arranged side by side in a first direction (X-axis direction). The branched scan lines SL can be connected to different pixels PX.

[0087] Each of the scan stages SST can be connected to the scan control line SCL. The scan control line SCL can be arranged between the scan driver circuit SDC and the transmit driver circuit EDC. Each of the scan stages SST can generate a scan signal in response to a scan control signal from the scan control line SCL, and can output the scan signal to the scan line SL.

[0088] Each of the dummy scan levels (DSTs) can be arranged between adjacent (or corresponding) scan levels (SSTs). Alternatively, two or more dummy scan levels (DSTs) can be set consecutively. Each of the dummy scan levels (DSTs) is not connected to the scan control line (SCL) and the scan line (SL). That is, each of the dummy scan levels (DSTs) does not generate a scan signal and does not output a scan signal to the scan line (SL).

[0089] In embodiments where the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4 are circular with a predetermined curvature, the space between scan levels SST may become large, or empty spaces may exist between scan levels SST if a dummy scan level DST is not arranged. In the case where a dummy scan level DST is not arranged or provided, the active layer, gate electrode, source electrode, and drain electrode of some transistors in the scan level SST may be over-etched, which may affect the driving of the scan level SST in the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4. In this case, for example, the pulse width of the scan signal output from some of the scan level SSTs in the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4 may be different from the pulse width of the scan signal output from the scan level SSTs in other regions of the first side surface SS1. Other regions of the first side surface SS1 may be regions in which the scan level SSTs are positioned in the second direction (Y-axis direction). In embodiments of the invention, as Figure 5A As shown, the scan driver circuit SDC includes a dummy scan level DST, which effectively prevents the active layer, gate electrode, source electrode, and drain electrode of some of the transistors in the scan level SST in the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4 from being over-etched.

[0090] The transmitter stage EST and the dummy transmitter stage DET can be arranged along the curvature of the first corner CS1 in a portion of the first side surface SS1 and a portion of the fourth side surface SS4.

[0091] The transmitter stage EST can be connected to the transmitter line EL. The transmitter line EL can be connected to the transmitter stage EST via the scan stage SST.

[0092] Each of the transmitter stages EST can be connected to the transmit control line ECL. The transmit control line ECL can be arranged between the transmit driver circuit EDC and the edge of the display panel 100. Each of the transmitter stages EST can generate a transmit signal in response to a transmit control signal from the transmit control line ECL, and can output the transmit signal to the transmit line EL.

[0093] Each of the dummy transmitter stages (DETs) can be arranged between adjacent transmitter stages (ESTs). Alternatively, two or more dummy transmitter stages (DETs) can be arranged consecutively. Each of the dummy transmitter stages (DETs) is not connected to the transmit control line (ECL) and the transmit line (EL). That is, each of the dummy transmitter stages (DETs) does not generate a transmit signal and does not output a transmit signal to the transmit line (EL).

[0094] In embodiments where the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4 are circular with a predetermined curvature, the space between emitter ESTs may become large, or empty spaces may exist between emitter ESTs if no dummy emitter DETs are arranged. In the case where no dummy emitter DETs are arranged or provided, the active layer, gate electrode, source electrode, and drain electrode of some transistors in the emitter ESTs may be over-etched, potentially affecting the driving of the emitter ESTs at the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4. In this case, for example, the pulse width of the transmit signal output from some of the emitter ESTs at the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4 may differ from the pulse width of the transmit signal output from the emitter ESTs in other regions of the first side surface SS1. In embodiments of the invention, as Figure 5A As shown, the emitter driver circuit EDC includes a dummy emitter stage DET, which effectively prevents the active layer, gate electrode, source electrode, and drain electrode of some of the transistors in the emitter stage EST in the first corner CS1, a portion of the first side surface SS1, and a portion of the fourth side surface SS4 from being over-etched.

[0095] In this embodiment, a first power supply voltage line VDDL and a second power supply voltage line VIL can be arranged between a first corner display area CDA1 and a first corner non-display area CNA1, between a first side display area SDA1 and a first side non-display area SNA1, and between a fourth side display area SDA4 and a fourth side non-display area SNA4. The first power supply voltage line VDDL and the second power supply voltage line VIL can extend along the curvature of the first corner CS1. Each of the first power supply voltage line VDDL and the second power supply voltage line VIL can intersect with a scan line SL and an emission line EL. A first power supply voltage can be applied to the first power supply voltage line VDDL, and a second power supply voltage can be applied to the second power supply voltage line VIL.

[0096] The first power supply voltage line VDDL may include a first horizontal power supply voltage line HVDL protruding from the first power supply voltage line VDDL and arranged parallel to the scan line SL. The second power supply voltage line VIL may include a second horizontal power supply voltage line HVIL protruding from the second power supply voltage line VIL and arranged parallel to the scan line SL. The first horizontal power supply voltage line HVDL and the second horizontal power supply voltage line HVIL may extend in a first direction (X-axis direction). Each of the pixels PX may be connected to the first horizontal power supply voltage line HVDL and the second horizontal power supply voltage line HVIL, and is electrically connected to the first power supply voltage line VDDL and the second power supply voltage line VIL.

[0097] In an embodiment, the first power supply voltage line VDDL can be arranged closer to the first corner display area CDA1 than the second power supply voltage line VIL, such as... Figure 5A and Figure 5B As shown in the diagram. In such an embodiment, the second horizontal power supply voltage line HVIL may cross the first power supply voltage line VDDL.

[0098] Because the first scan driver SDU1, which is arranged in the second corner CS2, is related to the above reference Figure 5A and Figure 5B The description of the first scan driver SDU1 arranged in the first corner CS1 is similar, and therefore, any repeated detailed description of the first scan driver SDU1 arranged in the second corner CS2 will be omitted. Additionally, the second scan driver SDU2 arranged in the third corner CS3 and the fourth corner CS4 can be similar to the one described above. Figure 5A and Figure 5B The first scan driver SDU1 is substantially the same as described, and therefore any repeated detailed description of the second scan driver SDU2, which is arranged in the third corner CS3 and the fourth corner CS4, will be omitted.

[0099] Figure 6A It is shown Figure 5AA circuit diagram of an embodiment of the pixels.

[0100] refer to Figure 6A Each pixel PX can be connected to two of the scan lines SL, one of the emission lines EL, and one of the data lines. For example, in one embodiment, as... Figure 6A As shown, each of the pixels PX can be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the emit line EL, and the data line DL. According to embodiments of this disclosure, the write scan line GWL and the control scan line GCL can be... Figure 5B The k-th scan line SLk is initialized, and the initial scan line GIL can be the (k-1)-th scan line SL(k-1). However, it should be understood that this disclosure is not limited thereto.

[0101] Pixel PX includes driving transistor DT, light-emitting element LEL, switching element and capacitor C1, such as Figure 6A As shown in the diagram. The switching element includes first transistors through sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6. In an embodiment, as... Figure 6A As shown, the first transistor ST1 may include a first sub-transistor ST1-1 and a second sub-transistor ST1-2, and the third transistor ST3 may include a first sub-transistor ST3-1 and a second sub-transistor ST3-2.

[0102] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The drain-source current (hereinafter referred to as the "driving current") flowing between the first and second electrodes of the driving transistor DT is controlled based on the data voltage applied to the gate electrode.

[0103] As a driving current flows through it, the light-emitting element (LEL) emits light. The amount of light emitted from the LEL is proportional to the driving current.

[0104] The light-emitting element (LEL) can be an organic light-emitting diode (OLED) comprising an anode, a cathode, and an organic emitting layer disposed between the anode and the cathode. Alternatively, the LEL can be an inorganic light-emitting element comprising an anode, a cathode, and an inorganic semiconductor disposed between the anode and the cathode. Alternatively, the LEL can be a quantum dot light-emitting element comprising an anode, a cathode, and a quantum dot emitting layer disposed between the anode and the cathode. Alternatively, the LEL can be a micro LED.

[0105] The anode of the light-emitting element (LEL) can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, while the cathode of the LEL can be connected to the third power supply voltage line VSSL. A parasitic capacitance Cel can be formed between the anode and cathode of the LEL.

[0106] Capacitor C1 is connected between the second electrode of the driving transistor DT and the first power supply voltage line VDDL. One electrode of capacitor C1 can be connected to the second electrode of the driving transistor DT, while the other electrode of capacitor C1 can be connected to the first power supply voltage line VDDL.

[0107] In an embodiment, when the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, and the driving transistor DT, is a source electrode, its second electrode may be a drain electrode. Alternatively, when the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, and the driving transistor DT, is a drain electrode, its second electrode may be a source electrode.

[0108] The active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, and the driving transistor DT, may include, or be made of, polycrystalline silicon, amorphous silicon, and oxide semiconductor. In an embodiment, where the semiconductor layer of each of the first transistors ST1 to ST6 and the driving transistor DT includes or is made of polycrystalline silicon, a low-temperature polycrystalline silicon (LTPS) process may be employed.

[0109] Although the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, as well as the drive transistor DT, are p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), such as Figure 6A As shown, but this is merely an example. Alternatively, the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, as well as the drive transistor DT, can be n-type MOSFETs.

[0110] In an embodiment, the first power supply voltage from the first power supply voltage line VDDL, the second power supply voltage from the second power supply voltage line VIL, and the third power supply voltage from the third power supply voltage line VSSL can be determined based on the characteristics of the driving transistor DT and the characteristics of the light-emitting element LEL.

[0111] Figure 6B It is shown Figure 5A Circuit diagram of alternative embodiments of the pixels.

[0112] Figure 6B Implementation examples and Figure 6AThe embodiments are essentially the same, except that the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 are implemented as p-type MOSFETs and the first transistor ST1 and the third transistor ST3 are each defined by a single transistor implemented as an n-type MOSFET.

[0113] refer to Figure 6B The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, which are implemented as p-type MOSFETs, may include polysilicon or be made of polysilicon, and the active layers of the first transistor ST1 and the third transistor ST3, which are implemented as n-type MOSFETs, may include oxide semiconductor or be made of oxide semiconductor. In such an embodiment, since transistors comprising polysilicon or formed of polysilicon and transistors comprising oxide semiconductor or formed of oxide semiconductor can be arranged on different layers, the area of ​​the pixel PX can be reduced.

[0114] Figure 6B Implementation examples and Figure 6A The embodiments are basically the same, except that the gate electrodes of the second transistor ST2 and the fourth transistor ST4 are connected to the write scan line GWL and the gate electrode of the first transistor ST1 is connected to the control scan line GCL. In the embodiments, as Figure 6B As shown, since the first transistor ST1 and the third transistor ST3 are n-type MOSFETs, a gate high voltage scan signal can be applied to the control scan line GCL and the initialization scan line GIL. In such an embodiment, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are p-type MOSFETs, a gate low voltage scan signal can be applied to the write scan line GWL and the emitter line EL.

[0115] Figure 7 It is shown Figure 5A A circuit diagram of an embodiment of the scan driver circuit.

[0116] For ease of explanation, Figure 7 Only the k-th scan level SSTk connected to the k-th scan line SLk and the (k+1)-th scan level SST(k+1) connected to the (k+1)-th scan line SL(k+1) are shown.

[0117] refer to Figure 7An embodiment of the scan driver circuit SDC includes scan stages SSTk and SST(k+1) cascaded together. Scan stages SSTk and SST(k+1) can sequentially output scan signals. For example, in one embodiment, the k-th scan stage SSTk can be connected to the k-th scan line SLk to output the k-th scan signal. The (k+1)-th scan stage SST(k+1) can be connected to the (k+1)-th scan line SL(k+1) to output the (k+1)-th scan signal.

[0118] Each of the scan stages SSTk and SST(k+1) includes a first pull-up node NQ1, a first pull-down node NQB1, a first pull-up transistor TU1 that is turned on when the first pull-up node NQ1 has a first gate on-voltage, a first pull-down transistor TD1 that is turned on when the first pull-down node NQB1 has a first gate on-voltage, and a first node controller NC1 that controls the charging and discharging of the first pull-up node NQ1 and the first pull-down node NQB1. The scan control line SCL connected to the scan stages SSTk and SST(k+1) includes a scan start signal line from which a scan start signal is applied, scan clock lines SCL1 and SCL2 from which a scan clock signal is applied, a first gate on-voltage line VGHL1, and a first gate off-voltage line VGLL1.

[0119] Each of the scan stages SSTk and SST(k+1) includes a first start terminal ST1, a first reset terminal RT1, a first gate on voltage terminal VGHT1, a first gate off voltage terminal VGLT1, a first clock terminal CT1, and a first output terminal OT1. The first start terminal ST1 can be connected to a scan start line with an applied scan start signal or a first previous stage carry line PCL1 with an applied output signal from a previous stage. The first reset terminal RT1 can be connected to a first subsequent stage carry line RCL1 with an input output signal from a subsequent stage. The first gate on voltage terminal VGHT1 can be connected to a first gate on voltage line VGHL1 with an applied first gate on voltage. The first gate off voltage terminal VGLT1 can be connected to a first gate off voltage line VGLL1 with an applied gate off voltage. The first gate on voltage can be a first level voltage, and the first gate off voltage can be a second level voltage. The first node controller NC1 includes a plurality of thin-film transistors.

[0120] The first clock terminal CT1 can be connected to either the first scan clock line SCL1 to which a scan clock signal is applied, or the second scan clock line SCL2 to which a second scan clock signal is applied. Levels SSTk and SST(k+1) can be alternately connected to the first scan clock line SCL1 and the second scan clock line SCL2. For example, in one embodiment, if the first clock terminal CT1 of the k-th scan level SSTk is connected to the first scan clock line SCL1, the first clock terminal CT1 of the (k+1)-th scan level SST(k+1) can be connected to the second scan clock line SCL2. Figure 7 An embodiment is shown in which stages SSTk and SST(k+1) are alternately connected to two scan clock lines SCL1 and SCL2, but this disclosure is not limited thereto. For example, in an alternative embodiment, stages SSTk and SST(k+1) may be alternately connected to three or more scan clock lines.

[0121] The first output terminal OT1 can be connected to one of scan lines SLk and SL(k+1). Levels SSTk and SST(k+1) can be sequentially connected to scan lines SLk and SL(k+1). For example, in one embodiment, the first output terminal OT1 of the k-th level SSTk can be connected to the k-th scan line SLk, and the first output terminal OT1 of the (k+1)-th level SST(k+1) can be connected to the (k+1)-th scan line SL(k+1).

[0122] In the embodiment, the first pull-up transistor TU1, the first pull-down transistor TD1, and the plurality of transistors of the first node controller NC1 in each of stages SSTk and SST(k+1) are p-type MOSFETs, such as Figure 7 As shown, but embodiments of this disclosure are not limited thereto. Alternatively, the first pull-up transistor TU1, the first pull-down transistor TD1, and the plurality of transistors of the first node controller NC1 in each of stages SSTk and SST(k+1) may be n-type MOSFETs.

[0123] Figure 8 It is shown Figure 5A A circuit diagram of an embodiment of the transmitter driver circuit.

[0124] For ease of explanation, Figure 8 Only the k-th transmitter stage ESTk connected to the k-th transmitter line ELk and the k+1-th transmitter stage EST(k+1) connected to the k+1-th transmitter line EL(k+1) of the transmitter driver circuit EDC are shown.

[0125] refer to Figure 8The transmit driver circuit EDC includes transmit stages ESTk and EST(k+1) cascaded together. Transmit stages ESTk and EST(k+1) can sequentially output transmit signals. For example, in one embodiment, the k-th transmit stage ESTk can be connected to the k-th transmit line ELk to output the k-th transmit signal. The (k+1)-th transmit stage EST(k+1) can be connected to the (k+1)-th transmit line EL(k+1) to output the (k+1)-th transmit signal.

[0126] In an embodiment, such as Figure 8 As shown, each of the emitter stages ESTk and EST(k+1) includes a second pull-up node NQ2, a second pull-down node NQB2, a second pull-up transistor TU2 that is turned on when the second pull-up node NQ2 has a second gate on-voltage, a second pull-down transistor TD2 that is turned on when the second pull-down node NQB2 has a second gate on-voltage, and a second node controller NC2 that controls the charging and discharging of the second pull-up node NQ2 and the second pull-down node NQB2. The emitter control lines ECL connected to the emitter stages ESTk and EST(k+1) include an emitter start signal line with an applied emitter start signal, emitter clock lines ECL1 and ECL2 with applied emitter clock signals, a second gate on-voltage line VGHL2, and a second gate off-voltage line VGLL2.

[0127] Each of the emitter stages ESTk and EST(k+1) includes a second start terminal ST2, a second reset terminal RT2, a second gate on voltage terminal VGHT2, a second gate off voltage terminal VGLT2, a second clock terminal CT2, and a second output terminal OT2. The second start terminal ST2 can be connected to a scan start line with an applied scan start signal or a second previous stage carry line PCL2 with an applied output signal from a previous stage. The second reset terminal RT2 can be connected to a second subsequent stage carry line RCL2 with an input output signal from a subsequent stage. Emitter stages ESTk and EST(k+1) are referenced above. Figure 7 The scan levels SSTk and SST(k+1) are described as essentially the same, except that they receive a transmit start signal that is different from the scan start signal and a transmit clock signal that is different from the scan clock signal; and therefore, any repeated detailed descriptions of them will be omitted.

[0128] In such an embodiment, since the first corner non-display area CNA1 may degrade the aesthetic appeal of the display device 10, it is desirable to reduce the area of ​​the first corner non-display area CNA1. However, since the scan driver circuit SDC and the transmit driver circuit EDC are arranged within the first corner non-display area CNA1, leaving almost no space, it is difficult to reduce the area of ​​the first corner non-display area CNA1. Hereinafter, embodiments for reducing the area of ​​the first corner non-display area CNA1 and increasing the area of ​​the first corner display area CDA1 within the first corner CS1 will be described in detail.

[0129] Figure 9A This is a diagram illustrating the layout of the first corner according to an alternative embodiment. Figure 9B It is shown in detail Figure 9A An enlarged view of the layout of region B.

[0130] refer to Figure 9A and Figure 9B An embodiment of the display panel 100 further includes a first circuit region CCA1 disposed between a first side non-display area SNA1 and a first corner non-display area CNA1, and a second circuit region CCA2 disposed between a fourth side non-display area SNA4 and the first corner non-display area CNA1. In such an embodiment, the first corner CS1 includes a first corner display area CDA1, a prominent display area PDA, and a first corner non-display area CNA1.

[0131] Each of the first circuit region CCA1 and the second circuit region CCA2 is a non-display region where no image is displayed. In an embodiment, the first scan driver circuit SDC1 and the second scan driver circuit SDC2 of the scan driver circuit SDC, and the first transmit driver circuit EDC1 and the second transmit driver circuit EDC2 of the transmit driver circuit EDC are arranged in each of the first circuit region CCA1 and the second circuit region CCA2.

[0132] In one embodiment, the first scan driver circuit SDC1 can be arranged closer to the first corner display area CDA1 and the highlighted display area PDA than the second scan driver circuit SDC2. In such an embodiment, the second scan driver circuit SDC2 can be arranged further away from the first corner display area CDA1 and the highlighted display area PDA than the first scan driver circuit SDC1.

[0133] In one embodiment, the first transmit driver circuit EDC1 can be arranged closer to the first corner display area CDA1 and the highlighted display area PDA than the second transmit driver circuit EDC2. In such an embodiment, the second transmit driver circuit EDC2 can be arranged further away from the first corner display area CDA1 and the highlighted display area PDA than the first transmit driver circuit EDC1.

[0134] The first scan driver circuit SDC1 can be arranged at the innermost position, and the second scan driver circuit SDC2 can be arranged at the outermost position. The first transmit driver circuit EDC1 and the second transmit driver circuit EDC2 can be arranged between the first scan driver circuit SD1 and the second scan driver circuit SDC2. The first transmit driver circuit EDC1 can be arranged adjacent to the first scan driver circuit SD1, and the second transmit driver circuit EDC2 can be arranged adjacent to the second scan driver circuit SDC2.

[0135] The first scan control line SCL1 can be arranged between the first scan driver circuit SDC1 and the first transmit driver circuit EDC1. The transmit control line ECL can be arranged between the first transmit driver circuit EDC1 and the second transmit driver circuit EDC2. No additional control lines can be arranged between the second transmit driver circuit EDC2 and the second scan driver circuit SDC2. The second scan control line SCL2 can be arranged between the second scan driver circuit SDC2 and the edge of the display panel 100. The first scan control line SCL1 and the second scan control line SCL2 can branch from the scan control line SCL and then combine or merge back into the scan control line SCL.

[0136] The first scan driver circuit SDC1 includes a first scan level SST1, and the second scan driver circuit SDC2 includes a second scan level SST2.

[0137] The first scan level SST1 can be connected to a first scan line SL1 that is connected to the pixels PX of the first side display area SDA1 and the second side display area SDA2, respectively. The scan line SL connected to the first scan level SST1 can be defined as the first scan line SL1. Each of the first scan levels SST1 can be connected to a first scan control line SCL1. Each of the first scan levels SST1 can generate a scan signal in response to a scan control signal from the first scan control line SCL1, and can output the scan signal to the first scan line SL1. The first scan level SST1 of the first scan driver circuit SDC1 can be referenced above. Figure 7 The descriptions are basically the same.

[0138] Each of the second scan levels SST2 can be connected to a second scan line SL2 connected to a pixel PX of the highlighted display area PDA. The scan line SL connected to the second scan level SST2 can be defined as the second scan line SL2. Each of the second scan levels SST2 can be connected to a second scan control line SCL2. Each of the second scan levels SST2 can generate a scan signal in response to a scan control signal from the second scan control line SCL2, and can output the scan signal to the second scan line SL2. The second scan level SST2 of the second scan driver circuit SDC2 can be referenced above. Figure 7 The descriptions are basically the same.

[0139] In one embodiment, a first scan line SL1 connected to the first scan level SST1 can be connected to a pixel PX of the first corner display area CDA1 via the shortest path. In such an embodiment, a second scan line SL2 connected to the second scan level SST2 can extend along the edge of the display panel 100 to the first corner non-display area CNA1, and then bend and connect to a pixel PX of the protruding display area PDA. Therefore, the length of the second scan line SL2 can be greater than the length of the first scan line SL1. In another embodiment, the second scan line SL2 can bend more times than the first scan line SL1.

[0140] Since the first scan control line SCL1 and the second scan control line SCL2 branch from the scan control line SCL and then combine or merge back into the scan control line SCL, the first scan level SST1 and the second scan level SST2 can have essentially the same scan control signal applied to the first scan control line SCL1 and the second scan control line SCL2.

[0141] In the display areas FDA, SDA1, SDA4, CDA1, and PDA, scan signals can be applied sequentially from the scan line SL arranged on the lower side to the scan line SL arranged on the upper side. In such an embodiment, in the first circuit area CCA1, the first scan line SL1 connected to the first scan level SST1 is arranged below the second scan line SL2 connected to the second scan level SST2. Therefore, the first scan level SST1 can output a scan signal to the first scan line SL1, and then the second scan level SST2 can output a scan signal to the second scan line SL2. In the second circuit area CCA2, the first scan line SL1 connected to the first scan level SST1 is arranged above the second scan line SL2 connected to the second scan level SST2. After the second scan level SST2 outputs a scan signal to the second scan line SL2, the first scan level SST1 can output a scan signal to the first scan line SL1.

[0142] Each of the first emitter levels EST1 can be connected to a first emitter line EL1 connected to a pixel PX of the first side display area SDA1 and the second side display area SDA2. A scan line SL connected to the first scan level SST1 can be defined as a first scan line SL1. An emitter line EL connected to the first emitter level EST1 can be defined as a first emitter line EL1. Each of the first emitter lines EL1 can be connected to the first emitter level EST1 via the first scan level SST1.

[0143] Each of the second emitter stages EST2 can be connected to a second emitter line EL2 connected to the pixel PX of the highlighted area PDA. Emitter lines EL connected to the second emitter stage EST2 can be defined as second emitter lines EL2. Each of the second emitter lines EL2 can be connected to the second emitter stage EST2 via the second scan stage SST2.

[0144] In one embodiment, each of the first transmitter stage EST1 and the second transmitter stage EST2 can be connected to the transmit control line ECL. In such an embodiment, the first transmitter stage EST1 and the second transmitter stage EST2 can share the transmit control line ECL. Each of the first transmitter stage EST1 and the second transmitter stage EST2 can generate a transmit signal in response to a transmit control signal from the transmit control line ECL to output the transmit signal to the transmit line EL. Each of the first transmitter stage EST1 of the first transmitter driver circuit EDC1 and the second transmitter stage EST2 of the second transmitter driver circuit EDC2 can be connected to the aforementioned reference... Figure 8 The descriptions are basically the same.

[0145] In one embodiment, the first emitter line EL1 connected to the first emitter stage EST1 can be connected to the pixel PX of the first corner display area CDA1 via the shortest path. In such an embodiment, the second emitter line EL2 connected to the second emitter stage EST2 can extend along the edge of the display panel 100 to the first corner non-display area NDA1, and then bend and connect to the pixel PX of the protruding display area PDA. Therefore, the length of the second emitter line EL2 can be greater than the length of the first emitter line EL1. In another embodiment, the second emitter line EL2 can be bent more times than the first emitter line EL1.

[0146] In the display areas FDA, SDA1, SDA4, CDA1, and PDA, the transmit signal can be sequentially applied from the lower transmit line EL to the upper transmit line EL. In such an embodiment, in the first circuit area CCA1, the transmit line EL connected to the first transmit stage EST1 is arranged below the transmit line EL connected to the second transmit stage EST2. Therefore, the first transmit stage EST1 can output a transmit signal to the transmit line EL, and then the second transmit stage EST2 can output a transmit signal to the transmit line EL. In the second circuit area CCA2, the transmit line EL connected to the first transmit stage EST1 is arranged above the transmit line EL connected to the second transmit stage EST2. Therefore, the second transmit stage EST2 can output a transmit signal to the transmit line EL, and then the first transmit stage EST1 can output a transmit signal to the transmit line EL.

[0147] In the first corner non-display area CNA1, the scan line SL connected to the second scan stage SST2, the transmit line EL connected to the second transmit stage EST2, the scan control line SCL, and the transmit control line ECL can be arranged. Since the scan driver circuit SDC and the transmit driver circuit EDC are not arranged in the first corner non-display area CNA1, the width of the first corner non-display area CNA1 can be greatly reduced.

[0148] Figure 9C It is shown Figure 9A A diagram showing the width of the first corner non-display area, the width of the first side surface, the width of the fourth side surface, the width of the first circuit area, and the width of the second circuit area.

[0149] In an embodiment, such as Figure 9C As shown, the width WCNA1 of the first corner non-display area CNA1 can be smaller than the width WSS1 of the first side surface SS1, the width WSS4 of the fourth side surface SS4, the width WCC1 of the first circuit area CCA1, and the width WCC2 of the second circuit area CCA2. In such an embodiment, the width WCC1 of the first circuit area CCA1 can be larger than the width WSS1 of the first side surface SS1, and the width WCC2 of the second circuit area CCA2 can be larger than the width WSS4 of the fourth side surface SS4.

[0150] The width WCNA1 of the first corner non-display area CNA1 can be defined as the minimum distance between the edge ECS1 of the first corner CS1 and the protruding display area PDA. The width WSS1 of the first side surface SS1 can be defined as the minimum distance between the edge ESS1 of the first side surface SS1 and the first side display area SDA1. The width WSS4 of the fourth side surface SS4 can be defined as the minimum distance between the edge ESS4 of the fourth side surface SS4 and the fourth side display area SDA4. The width WCC1 of the first circuit area CCA1 can be defined as the distance between the edge ECA1 of the first circuit area CCA1 and the first side display area SDA1 in a direction perpendicular to the edge ECA1 of the first circuit area CCA1. The width WCC2 of the second circuit area CCA2 can be defined as the distance between the edge ECA2 of the second circuit area CCA2 and the fourth side display area SDA4 in a direction perpendicular to the edge ECA2 of the second circuit area CCA2.

[0151] The first power supply voltage line VDDL and the second power supply voltage line VIL can be arranged between the first corner non-display area CNA1 and the first corner display area CDA1, and between the first corner non-display area CNA1 and the prominent display area PDA. Each of the first power supply voltage line VDDL and the second power supply voltage line VIL can intersect with the scan line SL and the emission line EL.

[0152] The widths WCC1 of the first circuit region CCA1, WSS1 of the first side non-display region SNA1, and WCNA1 of the first corner non-display region CNA1 are different from each other. Similarly, the widths WCC2 of the second circuit region CCA2, WSS4 of the fourth side non-display region SNA4, and WCNA1 of the first corner non-display region CNA1 are different from each other. Therefore, each of the first power supply voltage line VDDL and the second power supply voltage line VIL, arranged between the display regions SDA1, SDA4, and PDA and the non-display regions SNA1, CCA1, CNA1, CCA2, and SNA4, can be bent multiple times.

[0153] Pixels PX used for displaying images can be arranged in the first corner display area CDA1 and the highlighted display area PDA. Pixels PX can be arranged in a matrix in a first direction (X-axis direction) and a second direction (Y-axis direction). Pixels PX can be related to the above reference... Figure 6A The descriptions are essentially the same; and therefore, any repeated detailed descriptions will be omitted.

[0154] The prominent display area PDA can protrude from the first corner display area CDA1. The recessed area can be defined by the first circuit area CCA1, the second circuit area CCA2, and the first corner non-display area CNA1. The prominent display area PDA can be surrounded by the recessed area.

[0155] In an embodiment, such as Figure 9A and Figure 9B As shown, the scan driver circuit SDC does not include a dummy scan level DST, and the transmit driver circuit EDC does not include a dummy transmit level DET. In such an embodiment, some of the scan levels SST and transmit levels EST are arranged in a first circuit region CCA1 between the first side non-display area SNA1 and the first corner non-display area CNA1. In such an embodiment, the remaining scan levels SST and transmit levels EST are arranged in a second circuit region CCA2 between the fourth side non-display area SNA4 and the first corner non-display area CNA1.

[0156] In this embodiment, a dummy scan level (DST) and a dummy emitter level (DET) are not provided, and a scan level (SST) and an emitter level (EST) are arranged in the first circuit region CCA1 and the second circuit region CCA2, thereby reducing the area of ​​the first corner non-display region CNA1. In this embodiment, the first corner non-display region CNA1 is reduced, and a prominent display region PDA is arranged or provided, thereby increasing the display area of ​​the first corner CS1.

[0157] Figure 10 It shows along Figure 9B A cross-sectional view of an embodiment of the display panel, taken by line I-I'. Figure 11 It shows along Figure 9B A cross-sectional view of an embodiment of the display panel, taken by line II-II'. Figure 12 It shows along Figure 9B A cross-sectional view of an embodiment of the display panel, taken by line III-III'.

[0158] Figure 10 The image shows a cross-section of the display panel, including the pixel PX portion. Figure 11 and Figure 12 Each of the figures shows a cross section of the display panel including the scan line SL and the emitter line EL that intersect with the first power supply voltage line VDDL and the second power supply voltage line VIL.

[0159] refer to Figures 10 to 12 The first buffer layer BF1 can be disposed on the first substrate SUB1.

[0160] The first substrate SUB1 may include, or be made of, an insulating material such as a polymer resin. For example, in one embodiment, the first substrate SUB1 may include polyimide (PI). The first substrate SUB1 may be a flexible substrate that can be bent, folded, or rolled.

[0161] The first buffer layer BF1 is a layer used to protect the thin-film transistor layer TFTL and the emitter layer 172 of the emitter material layer EML. Each of the first buffer layers BF1 may be composed of a plurality of inorganic layers sequentially stacked on top of each other. For example, in one embodiment, each of the first buffer layers BF1 may be defined or composed of a multilayer consisting of one or more inorganic layers (each layer including at least one selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide layers) stacked alternately on top of each other.

[0162] In an embodiment, a second substrate (not shown) may be disposed on the first buffer layer BF1, and the second buffer layer (not shown) may be further disposed on the second substrate. In an embodiment, a light-shielding layer (not shown) for blocking light incident on the first substrate SUB1 may be disposed on the first substrate SUB1.

[0163] The active layer ACT of the thin-film transistor ST can be disposed on the first buffer layer BF1. The active layer ACT of the thin-film transistor ST includes polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. In an embodiment, the exposed active layer ACT of the thin-film transistor ST, which is not covered by the gate insulating layer 130, can be doped with impurities or ions to become conductive. Therefore, the conductive source electrode S and drain electrode D of the thin-film transistor ST can be provided or defined by the impurity-doped portion of the active layer ACT.

[0164] The gate insulating layer 130 can be disposed on the active layer ACT of the thin-film transistor ST. The gate insulating layer 130 may include or be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0165] The gate electrode G and the first scan line SL1 of the thin-film transistor ST can be disposed on the gate insulating layer 130. The gate electrode G of the thin-film transistor ST can overlap with the active layer ACT in the third direction (Z-axis direction). The gate electrode G and the first scan line SL1 of the thin-film transistor ST can be defined or constituted by a single layer or multiple layers, each layer including at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0166] The first interlayer dielectric layer 141 can be disposed on the gate electrode G and the first scan line SL1 of the thin-film transistor ST. The first interlayer dielectric layer 141 may include or be formed of inorganic layers, such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide. The first interlayer dielectric layer 141 may have a multilayer structure comprising multiple inorganic layers stacked on top of each other.

[0167] The capacitor electrode CAE can be disposed on the first interlayer dielectric layer 141. The capacitor electrode CAE can overlap with the gate electrode G of the third thin-film transistor ST in the third direction (Z-axis direction). Since the first interlayer dielectric layer 141 has a predetermined dielectric constant, the capacitor can be formed by the capacitor electrode CAE, the gate electrode G, and the first interlayer dielectric layer 141 disposed between them. The capacitor electrode CAE can be composed of a single layer or multiple layers, each layer including at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0168] The second interlayer dielectric layer 142 can be disposed on the capacitor electrode CAE. The second interlayer dielectric layer 142 may include or be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer dielectric layer 142 may have a multilayer structure comprising multiple inorganic layers stacked on top of each other. The first interlayer dielectric layer 141 and the second interlayer dielectric layer 142 can be collectively referred to as interlayer dielectric layer 140.

[0169] In an embodiment, such as Figure 10 and Figure 11 As shown, the first anode connection electrode ANDE1, the first power supply voltage line VDDL, and the second power supply voltage line VIL can be disposed on the second interlayer dielectric layer 142. The first anode connection electrode ANDE1 can be connected to the drain electrode D of the thin-film transistor ST through the first anode contact hole ANCT1, which is defined by the first interlayer dielectric layer 141 and the second interlayer dielectric layer 142 to expose the drain electrode D of the thin-film transistor ST. The first anode connection electrode ANDE1, the first power supply voltage line VDDL, and the second power supply voltage line VIL can be defined or constituted by a single layer or multiple layers, each layer including at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0170] The first organic layer 160 may be disposed above the first anode connection electrode ANDE1, the first power supply voltage line VDDL, and the second power supply voltage line VIL to provide a flat surface. The first organic layer 160 may include or be formed as an organic layer comprising an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and PI resin.

[0171] The second anode connection electrode ANDE2 and the second scan line SL2 can be disposed on the first organic layer 160. The second anode connection electrode ANDE2 can be connected to the first anode connection electrode ANDE1 through a second anode contact hole ANCT2, which is defined by the first organic layer 160 to expose the first anode connection electrode ANDE1. The second scan line SL2 is disposed on the first organic layer 160 in the first corner non-display area CNA1. In an embodiment, as Figure 12 As shown, the second scan line SL2 can be arranged together with the first scan line SL1 on the gate insulating layer 130 in the highlighted display area PDA. The second anode connection electrode ANDE2 and the second scan line SL2 can be defined or constituted by a single layer or multiple layers, each layer including at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0172] The second organic layer 180 can be disposed on the second anode connection electrode ANDE2. The second organic layer 180 can be an organic layer comprising organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and PI resin.

[0173] Figure 10 The thin-film transistor ST shown can be an embodiment of the sixth transistor ST6 in Figure 6. Figure 10 In this embodiment, the thin-film transistor ST is implemented as a top-gate transistor in which the gate electrode G is located above the active layer ACT. However, it is to be understood that this disclosure is not limited thereto. Alternatively, the thin-film transistor ST may be implemented as a bottom-gate transistor in which the gate electrode G is located below the active layer ACT, or as a dual-gate transistor in which the gate electrode G is arranged above and below the active layer ACT.

[0174] The light-emitting element 170 and the embankment 190 can be arranged on the second organic layer 180. Each of the light-emitting elements 170 may include a first light-emitting electrode 171, an emitting layer 172, and a second light-emitting electrode 173.

[0175] The first light-emitting electrode 171 can be disposed on the second organic layer 180. The first light-emitting electrode 171 can be connected to the second anode connection electrode ANDE2 through the third anode contact hole ANCT3, which is defined by the second organic layer 180 to expose the second anode connection electrode ANDE2.

[0176] In an embodiment where the light-emitting element 170 is a top-emitting organic light-emitting diode from which light is emitted from the emitting layer 172 to the second light-emitting electrode 173, the first light-emitting electrode 171 may include or be made of a metal material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0177] A dam 190 may separate the first light-emitting electrode 171 on the second organic layer 180 to define the emission region EA. The dam 190 may be arranged to cover the edge of the first light-emitting electrode 171. The dam 190 may be an organic layer comprising organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and PI resin.

[0178] In the emission region EA, the first light-emitting electrode 171, the emission layer 172, and the second light-emitting electrode 173 are stacked sequentially on each other so that holes from the first light-emitting electrode 171 and electrons from the second light-emitting electrode 173 combine with each other in the emission layer 172 to emit light.

[0179] An emitting layer 172 is disposed on the first light-emitting electrode 171 and the embankment 190. The emitting layer 172 may include organic materials and emit light of a specific color. For example, in one embodiment, the emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0180] A second light-emitting electrode 173 is disposed on the emitting layer 172. The second light-emitting electrode 173 may be arranged to cover the emitting layer 172. The second light-emitting electrode 173 may be a common layer formed across all emitting regions EA. A capping layer may be disposed on the second light-emitting electrode 173.

[0181] In embodiments where the light-emitting element 170 is a top-emitting organic light-emitting diode, the second light-emitting electrode 173 can be formed of a transparent conductive material (TCP) such as indium tin oxide (ITO) and indium zinc oxide (IZO) that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or alloys of magnesium (Mg) and silver (Ag). In embodiments where the second light-emitting electrode 173 comprises or is formed of a semi-transmissive conductive material, light extraction efficiency can be improved by using a microcavity effect.

[0182] An encapsulation layer TFE can be disposed on the second light-emitting electrode 173. In an embodiment, the encapsulation layer TFE includes at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. In such an embodiment, the encapsulation layer TFE may further include at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust. For example, in one embodiment, the encapsulation layer TFE includes a first inorganic layer TFE1, an organic layer TFE2, and a second inorganic layer TFE3.

[0183] A first inorganic layer TFE1 can be disposed on the second light-emitting electrode 173, an organic layer TFE2 can be disposed on the first inorganic layer TFE1, and a second inorganic layer TFE3 can be disposed on the organic layer TFE2. The first inorganic layer TFE1 and the second inorganic layer TFE3 can be defined or constituted by a multilayer in which one or more inorganic layers, such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide layers, are alternately stacked. The organic layer TFE2 can include a monomer.

[0184] although Figures 10 to 12 The illustration shows an embodiment where the second scan line SL2 and the second emitter line EL2 are disposed on the first organic layer 160, but this disclosure is not limited thereto. Alternatively, the second scan line SL2 and the second emitter line EL2 may be disposed in the same layer as the capacitor electrode CAE. For example, in one embodiment, the second scan line SL2 and the second emitter line EL2 may be disposed on the first interlayer dielectric layer 141. Alternatively, the second scan line SL2 and the second emitter line EL2 may be disposed in the same layer as the first scan line SL1 and the first emitter line EL1. For example, in one embodiment, the second scan line SL2 and the second emitter line EL2 may be disposed on the gate insulating layer 130. Alternatively, the second scan line SL2 and the second emitter line EL2 may be disposed in the same layer as the first anode connection electrode ANDE1. For example, in one embodiment, the second scan line SL2 and the second emitter line EL2 may be disposed on the second interlayer dielectric layer 142.

[0185] although Figures 10 to 12The illustration shows an embodiment where the first scan line SL1 and the first emitter line EL1 are arranged on the gate insulating layer 130, but the present disclosure is not limited thereto. Alternatively, the first scan line SL1 and the first emitter line EL1 may be arranged on the first interlayer dielectric layer 141. Alternatively, the first scan line SL1 and the first emitter line EL1 may be arranged on the second interlayer dielectric layer 142. Alternatively, the first scan line SL1 and the first emitter line EL1 may be arranged on the first organic layer 160.

[0186] Figure 13A This is a diagram illustrating the layout of the first corner according to an alternative embodiment.

[0187] According to the embodiments, such as Figure 13A As shown, the first circuit region CCA1 is arranged between the first side non-display region SNA1 and the first corner non-display region CNA1, the second circuit region CCA2 is arranged between the fourth side non-display region SNA4 and the first corner non-display region CNA1, and the prominent display region PDA is arranged at a reduced position of the first corner non-display region CNA1, as shown in the reference above. Figure 9A and Figure 9B The described embodiments. However, Figure 13A Such an embodiment and Figure 9A and Figure 9B The difference in the embodiment is that each of the first circuit region CCA1 and the second circuit region CCA2 has a scan driver circuit SDC and a transmit driver circuit EDC, and the scan line SL of the second circuit region CCA2 extends along the first power supply voltage line VDDL and the second power supply voltage line VIL, and is connected to the pixel PX of the prominent display area PDA. For ease of description, the embodiment of FIG13 will be omitted or simplified below. Figure 9A and Figure 9B The embodiments are described in detail without any repetition of elements that are the same or similar to those in the embodiments.

[0188] refer to Figure 13A The first circuit region CCA1 and the second circuit region CCA2 include the scan driver circuit SDC and the transmit driver circuit EDC.

[0189] The scan driver circuit SDC can be arranged closer to the first corner display area CDA1 and the highlighted display area PDA than the transmit driver circuit EDC. In such an embodiment, the transmit driver circuit EDC can be arranged further away from the first corner display area CDA1 and the highlighted display area PDA than the scan driver circuit SDC.

[0190] The scan control line SCL can be positioned between the scan driver circuit SDC and the transmit driver circuit EDC. The transmit control line ECL can be positioned between the transmit driver circuit EDC and the edge of the display panel 100.

[0191] The scan driver circuit SDC includes scan levels SST. The scan level SST of the first circuit region CCA1 can be connected to the scan line SL connected to the pixel PX of the first side display region SDA1. The scan level SST of the second circuit region CCA2 can be connected to the scan line SL connected to the pixel PX of the fourth side display region SDA4 and the highlighted display region PDA.

[0192] The scan line SL of the scan level SST connected to the first circuit region CCA1 can be connected to the pixel PX of the first side display region SDA1 via the shortest path. In such an embodiment, the scan line SL of the scan level SST connected to the second circuit region CCA2 can extend along the first power supply voltage line VDDL and the second power supply voltage line VIL, and can then be connected to the pixel PX of the fourth side display region SDA4 and the prominent display region PDA.

[0193] Pixel PX arranged in the fourth side display area SDA4 is defined as a first pixel, and pixel PX arranged in the prominent display area PDA is defined as a second pixel. Furthermore, scan line SL connected to the first pixel is defined as a first scan line SL1, and scan line SL connected to the second pixel is defined as a second scan line SL2. Although both first scan line SL1 and second scan line SL2 extend along the first power supply voltage line VDDL, the length of the second scan line SL2 is greater than the length of the first scan line SL1. In an embodiment, the second scan line SL2 may bend more times than the first scan line SL1.

[0194] In one embodiment, the area overlapping the second scan line SL2 with the first power supply voltage line VDDL can be larger than the area overlapping the first scan line SL1 with the first power supply voltage line VDDL. Alternatively, both the first scan line SL1 and the second scan line SL2 extend along the second power supply voltage line VIL, and since the length of the second scan line SL2 is greater than the length of the first scan line SL1, the area overlapping the second scan line SL2 with the second power supply voltage line VIL can be larger than the area overlapping the first scan line SL1 with the second power supply voltage line VIL.

[0195] The width of the first circuit region CCA1 is different from the width of the first corner non-display region CNA1, and the width of the second circuit region CCA2 is different from the width of the first corner non-display region CNA1. Therefore, each of the first power supply voltage line VDDL and the second power supply voltage line VIL, arranged between the display regions SDA1, SDA4, and PDA and the non-display regions CCA1, CNA1, and CCA2, can be bent multiple times. Therefore, the scan line SL of the scan level SST connected to the second circuit region CCA2 can also be bent multiple times.

[0196] Each of the scan levels SST in the first circuit region CCA1 can generate a scan signal in response to a scan control signal from the scan control line SCL, and can output the scan signal to the scan line SL connected to the pixel PX of the first side display region SDA1. Each of the scan levels SST in the second circuit region CCA2 can generate a scan signal in response to a scan control signal from the scan control line SCL, and can output the scan signal to the scan line SL connected to the pixel PX of the fourth side display region SDA4 and the highlighted display region PDA.

[0197] The transmit driver circuit EDC includes a transmit stage EST. The transmit stage EST of the first circuit area CCA1 can be connected to the transmit line EL connected to the pixel PX of the first side display area SDA1. The transmit stage EST of the second circuit area CCA2 can be connected to the transmit line EL connected to the pixel PX of the fourth side display area SDA4 and the highlighted display area PDA.

[0198] The emitter line EL of the emitter stage EST connected to the first circuit region CCA1 can be connected to the pixel PX of the first side display region SDA1 via the shortest path. In such an embodiment, the emitter line EL of the emitter stage EST connected to the second circuit region CCA2 can extend along the first power supply voltage line VDDL and the second power supply voltage line VIL, and can then be connected to the pixel PX of the fourth side display region SDA4 and the prominent display region PDA.

[0199] The emitter line EL connected to the first pixel PX1 is defined as the first emitter line EL1, and the emitter line EL connected to the second pixel PX2 is defined as the second emitter line EL2. Although both the first emitter line EL1 and the second emitter line EL2 extend along the first power supply voltage line VDDL, the length of the second emitter line EL2 is greater than the length of the first emitter line EL1. In an embodiment, the second emitter line EL2 may be bent more times than the first emitter line EL1.

[0200] In one embodiment, the area where the second transmitting line EL2 overlaps with the first power supply voltage line VDDL can be larger than the area where the first transmitting line EL1 overlaps with the first power supply voltage line VDDL. Alternatively, both the first transmitting line EL1 and the second transmitting line EL2 extend along the second power supply voltage line VIL, and since the length of the second transmitting line EL2 is greater than the length of the first transmitting line EL1, the area where the second transmitting line EL2 overlaps with the second power supply voltage line VIL can be larger than the area where the first transmitting line EL1 overlaps with the second power supply voltage line VIL.

[0201] In an embodiment, such as Figure 13B As shown, the width WCC1 of the first circuit region CCA1 is different from the width WCNA1 of the first corner non-display region CNA1, and the width WCC2 of the second circuit region CCA2 is different from the width WCNA1 of the first corner non-display region CNA1. Therefore, each of the first power supply voltage line VDDL and the second power supply voltage line VIL arranged between the display regions SDA1, SDA4, and PDA and the non-display regions CCA1, CNA1, and CCA2 can be bent multiple times. Therefore, the transmitter line EL of the transmitter stage EST connected to the second circuit region CCA2 can also be bent multiple times.

[0202] Each of the transmitter stages EST in the first circuit region CCA1 can generate a transmitter signal in response to a transmitter control signal from the transmitter control line ECL, and can output the transmitter signal to the transmitter line EL connected to the pixel PX of the first side display region SDA1. Each of the transmitter stages EST in the second circuit region CCA2 can generate a transmitter signal in response to a transmitter control signal from the transmitter control line ECL, and can output the transmitter signal to the transmitter line EL connected to the pixel PX of the fourth side display region SDA4 and the prominent display region PDA.

[0203] In an embodiment, such as Figure 13A As shown, the scan driver circuit SDC does not include a dummy scan level DST, and the transmit driver circuit EDC does not include a dummy transmit level DET. In such an embodiment, some of the scan levels SST and transmit levels EST are arranged in a first circuit region CCA1 between the first side non-display area SNA1 and the first corner non-display area CNA1. In such an embodiment, the remaining scan levels SST and transmit levels EST are arranged in a second circuit region CCA2 between the fourth side non-display area SNA4 and the first corner non-display area CNA1.

[0204] In this embodiment, the dummy scan level (DST) and dummy emitter level (DET) are removed, and the scan level (SST) and emitter level (EST) are arranged in the first circuit region CCA1 and the second circuit region CCA2. Therefore, the area of ​​the first corner non-display area CNA1 can be reduced. In this embodiment, although the first corner non-display area CNA1 is reduced, the prominent display area PDA is arranged, and therefore, the display area of ​​the first corner CS1 can be increased.

[0205] Figure 14 It shows along Figure 13A A cross-sectional view of an embodiment of the display panel, taken by line IV-IV'.

[0206] Figure 14 The embodiments shown are the same as those referenced above. Figure 12 The described embodiments are essentially the same, except that the emitter line EL and scan line SL are arranged on the gate insulating layer 130. Therefore, the embodiments described above will be omitted in the following text. Figure 12 Any repeated detailed descriptions of elements that are the same as or similar to the described elements.

[0207] Figure 15 This is a diagram illustrating the layout of the first corner according to another alternative embodiment, wherein no pixels are arranged in the highlighted area.

[0208] Figure 15 Implementation examples and Figure 9A The embodiments are essentially the same, except that no pixels are arranged in the prominent display area of ​​the PDA; and therefore, the references above will be omitted. Figure 9A Any repeated detailed descriptions of elements that are the same as or similar to the described elements.

[0209] Figure 16 This is a diagram illustrating the layout of the first corner according to yet another alternative embodiment, wherein no pixels are arranged in the highlighted area.

[0210] Figure 16 Implementation examples and Figure 13A The embodiments are essentially the same, except that no pixels are arranged in the prominent display area of ​​the PDA; and therefore, the references above will be omitted. Figure 13A Any repeated detailed descriptions of elements that are the same as or similar to the described elements.

[0211] Figure 17 This is a diagram illustrating the layout of the first corner according to yet another alternative embodiment, wherein the non-displayed area is reduced from the first exemplary embodiment.

[0212] Figure 17 Implementation examples and Figure 9AThe embodiments are basically the same, except that the first corner non-display area CNA1 of the first corner CS1 is arranged adjacent to the first corner display area CDA1, and the first corner CS1 further includes a first idle space IDS1 arranged outside the first corner non-display area CNA1. For ease of description, references to the above will be omitted or simplified in the following text. Figure 9A Any repeated detailed descriptions of elements that are the same as or similar to the described elements.

[0213] refer to Figure 17 The first corner non-display area CNA1 is arranged outside the first corner display area CDA1. The first corner non-display area CNA1 is arranged between the first corner display area CDA1 and the first idle space IDS1.

[0214] The first scan control line SCL1, the second scan control line SCL2, the first emission control line ECL1, and the second emission control line ECL2 of the first corner non-display area CNA1 can be arranged closer to the first corner display area CDA1 than the edge of the display panel 100. In such an embodiment, the first power supply voltage line VDDL and the second power supply voltage line VIL can be arranged closer to the first corner display area CDA1 than the edge of the display panel 100.

[0215] The first vacant space IDS1 can be arranged outside the first corner non-display area CNA1. The first vacant space IDS1 can be the edge of the first corner CS1. No components of the display panel 100 can be arranged in the first vacant space IDS1. In addition, the substrate of the display panel 100 can be removed from the first vacant space IDS1.

[0216] In an embodiment, such as Figure 17 As shown, the non-display area CNA1 at the first corner is reduced in the first corner CS1 so that the first idle space IDS1 is confined in the first corner CS1. Therefore, since the light-blocking area of ​​the cover window arranged on the display panel 100 may not cover the first idle space IDS1, the non-display area of ​​the first corner CS1 that is recognized by the user can be reduced.

[0217] Figure 18 This is a diagram illustrating the layout of the first corner according to yet another alternative embodiment, wherein the non-displayed area is reduced from the second exemplary embodiment.

[0218] Figure 18 Implementation examples and Figure 13AThe embodiments are basically the same, except that the first corner non-display area CNA1 of the first corner CS1 is arranged adjacent to the first corner display area CDA1, and the first corner CS1 further includes a first idle space IDS1 arranged outside the first corner non-display area CNA1. For ease of description, references to the above will be omitted or simplified in the following text. Figure 13A Any repeated detailed descriptions of elements that are the same as or similar to the described elements.

[0219] refer to Figure 18 The first corner non-display area CNA1 is arranged outside the first corner display area CDA1. The first corner non-display area CNA1 is arranged between the first corner display area CDA1 and the first idle space IDS1.

[0220] The scan control line SCL and emission control line ECL of the first corner non-display area CNA1 can be arranged closer to the first corner display area CDA1 than the edge of the display panel 100. In such an embodiment, the first power supply voltage line VDDL and the second power supply voltage line VIL can be arranged closer to the first corner display area CDA1 than the edge of the display panel 100.

[0221] The first vacant space IDS1 can be arranged outside the first corner non-display area CNA1. The first vacant space IDS1 can be the edge of the first corner CS1. No components of the display panel 100 can be arranged in the first vacant space IDS1. In addition, the substrate of the display panel 100 can be removed from the first vacant space IDS1.

[0222] In an embodiment, such as Figure 18 As shown, the non-display area NDA1 at the first corner is reduced in the first corner CS1 so that the first idle space IDS1 is confined in the first corner CS1. Therefore, since the light-blocking area of ​​the cover window arranged on the display panel 100 may not cover the first idle space IDS1, the non-display area of ​​the first corner CS1 that is recognized by the user can be reduced.

[0223] Figure 19 This is a diagram illustrating the layout of a display device according to yet another alternative embodiment of the present disclosure. Figure 19 This is an unfolded view of a display device 10 according to yet another alternative embodiment of the present disclosure.

[0224] Figure 19 Implementation examples and Figure 4The embodiments are basically the same, except that the auxiliary display areas SAA1, SAA2, SAA3, SAA4, CAA1, CAA2, CAA3, and CAA4 are arranged between the display areas SDA1, SDA2, SDA3, SDA4, CDA1, CDA2, CDA3, and CDA4 of the display panel 100 and the non-display areas SNA1, SNA2, SNA3, SNA4, CNA1, CNA2, CNA3, and CNA4. The description will focus on the differences.

[0225] refer to Figure 19 The first side surface SS1 further includes a first side auxiliary display area SAA1 disposed between the first side display area SDA1 and the first side non-display area SNA1, and the second side surface SS2 further includes a second side auxiliary display area SAA2 disposed between the second side display area SDA2 and the second side non-display area SNA2. The third side surface SS3 further includes a third side auxiliary display area SAA3 disposed between the third side display area SDA3 and the third side non-display area SNA3, and the fourth side surface SS4 further includes a fourth side auxiliary display area SAA4 disposed between the fourth side display area SDA4 and the fourth side non-display area SNA4.

[0226] In such an embodiment, the first corner CS1 further includes a first corner auxiliary display area CAA1 disposed between the first corner display area CDA1 and the first corner non-display area CNA1, and the second corner CS2 further includes a second corner auxiliary display area CAA2 disposed between the second corner display area CDA2 and the second corner non-display area CNA2. The third corner CS3 further includes a third corner auxiliary display area CAA3 disposed between the third corner display area CDA3 and the third corner non-display area CNA3, and the fourth corner CS4 further includes a fourth corner auxiliary display area CAA4 disposed between the fourth corner display area CDA4 and the fourth corner non-display area CNA4.

[0227] Each of the side auxiliary display areas SAA1, SAA2, SAA3, and SAA4, and the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4, may include at least one selected from the scan driver circuit SDC, the transmit driver circuit EDC, the first power supply voltage line VDDL, the second power supply voltage line VIL, the scan control line SCL, and the transmit control line ECL. Therefore, compared to the area where pixel PX is arranged in each of the side auxiliary display areas SAA1, SAA2, SAA3, and SAA4, and the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4, the area where pixel PX is arranged can be reduced.

[0228] Therefore, the number of pixels (e.g., pixels per inch, PPI) per unit area in each of the side auxiliary display areas SAA1, SAA2, SAA3, and SAA4 can be less than the number of pixels per unit area in the front display area FDA, the side display areas SDA1, SDA2, SDA3, and SDA4, and the corner display areas CDA1, CDA2, CDA3, and CDA4. A unit area can be a predetermined area used to calculate the number of pixels, for example, an area equal to one inch in the first direction (X-axis direction) and one inch in the second direction (Y-axis direction). Additionally, the resolution of each of the side auxiliary display areas SAA1, SAA2, SAA3, and SAA4 and the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4 can be less than the resolution of the front display area FDA, the side display areas SDA1, SDA2, SDA3, and SDA4, and the corner display areas CDA1, CDA2, CDA3, and CDA4.

[0229] In an embodiment, such as Figure 19 As shown, due to the side auxiliary display areas SAA1, SAA2, SAA3 and SAA4 and the corner auxiliary display areas CAA1, CAA2, CAA3 and CAA4, the side non-display areas SNA1, SNA2, SNA3 and SNA4 and the corner non-display areas CNA1, CNA2, CNA3 and CNA4 can be reduced, and the display area of ​​the displayed image can be increased.

[0230] Figure 20 This is a diagram illustrating the layout of a display device according to yet another alternative embodiment of the present disclosure.

[0231] Figure 20 Implementation examples and Figure 19The embodiments are basically the same, except that the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4 are arranged only between the corner display areas CDA1, CDA2, CDA3, and CDA4 and the corner non-display areas CNA1, CNA2, CNA3, and CNA4. The description will focus on the differences.

[0232] refer to Figure 20 The first corner CS1 further includes a first corner auxiliary display area CAA1 disposed between the first corner display area CDA1 and the first corner non-display area CNA1, and the second corner CS2 further includes a second corner auxiliary display area CAA2 disposed between the second corner display area CDA2 and the second corner non-display area CNA2. The third corner CS3 further includes a third corner auxiliary display area CAA3 disposed between the third corner display area CDA3 and the third corner non-display area CNA3, and the fourth corner CS4 further includes a fourth corner auxiliary display area CAA4 disposed between the fourth corner display area CDA4 and the fourth corner non-display area CNA4.

[0233] Each of the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4 may include Figure 5A The scan driver circuit SDC, the transmit driver circuit EDC, the first power supply voltage line VDDL, the second drive voltage line VIL, the scan control line SCL, and the transmit control line ECL are included. Therefore, compared to the area where pixel PX is arranged in the front display area FDA, the side display areas SDA1, SDA2, SDA3, and SDA4, and the corner display areas CDA1, CDA2, CDA3, and CDA4, the area where pixel PX is arranged in each of the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4 can be reduced.

[0234] Therefore, the number of pixels (e.g., PPI) per unit area in each of the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4 can be less than the number of pixels per unit area in the front display area FDA, the side display areas SDA1, SDA2, SDA3, and SDA4, and the corner display areas CDA1, CDA2, CDA3, and CDA4. Additionally, the resolution of each of the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4 can also be less than the resolution of the front display area FDA, the side display areas SDA1, SDA2, SDA3, and SDA4, and the corner display areas CDA1, CDA2, CDA3, and CDA4.

[0235] In an embodiment, such as Figure 20As shown, the areas of the corner non-display areas CNA1, CNA2, CNA3, and CNA4 can be reduced due to the corner auxiliary display areas CAA1, CAA2, CAA3, and CAA4, and the area of ​​the display area for the displayed image can be increased. In such an embodiment, the minimum width of each of the corner non-display areas CNA1, CNA2, CNA3, and CNA4 can be smaller than the minimum width of each of the side non-display areas SNA1, SNA2, SNA3, and SNA4.

[0236] In an embodiment of the display device, dummy stages are removed from the circuit region where the intermediate stages are arranged, so that the non-display area can be reduced and the display area can be increased as much as the non-display area is reduced.

[0237] Furthermore, in embodiments of the display device, dummy stages are removed from the corners, and the stages are arranged within the circuit area. Therefore, the non-display area at the corner can be reduced, and the idle space at the corner can be defined as much as the non-display area is reduced. Thus, the light-shielding area of ​​the cover window arranged on the display panel may not cover the idle space, and therefore the non-display area identifiable by the user can be reduced.

[0238] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be exhaustive and comprehensive, and will fully convey the inventive concept to those skilled in the art.

[0239] Although the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: The display area including pixels; A non-display area adjacent to the display area, the non-display area including a circuit area located at a corner of the display device and a corner non-display area located between the circuit areas; Scan lines connected to the pixel; A first scan driver circuit is arranged in the circuit region of the non-display area, wherein the first scan driver circuit is connected to a first scan line among the scan lines; A second scan driver circuit is arranged in the circuit region of the non-display area, wherein the second scan driver circuit is connected to a second scan line among the scan lines; and The first and second transmitter driver circuits are arranged in the circuit region of the non-display area. The second scan driver circuit is arranged further away from the display area than the first scan driver circuit. The first transmit driver circuit and the second transmit driver circuit are arranged between the first scan driver circuit and the second scan driver circuit, and The first scan driver circuit, the second scan driver circuit, the first transmit driver circuit, and the second transmit driver circuit are not arranged in the corner non-display area.

2. The display device according to claim 1, wherein One of the second scan lines bends more times than one of the first scan lines.

3. The display device according to claim 1, further comprising: A first power supply voltage line is arranged between the first scan driver circuit and the display area, wherein a first power supply voltage is applied to the first power supply voltage line.

4. The display device according to claim 3, further comprising: A second power supply voltage line is arranged between the first scan driver circuit and the display area, wherein a second power supply voltage is applied to the second power supply voltage line.

5. The display device of claim 4, wherein, Each of the first scan line and the second scan line intersects the first power supply voltage line and the second power supply voltage line.

6. The display device according to claim 1, further comprising: The emission line connected to the pixel, The first transmit driver circuit is connected to the first transmit line in the transmit line and outputs the first transmit signal to the first transmit line. The second transmit driver circuit is connected to the second transmit line in the transmit line and outputs the second transmit signal to the second transmit line.

7. The display device according to claim 6, wherein, The second transmitter driver circuit is arranged further away from the display area than the first transmitter driver circuit.

8. The display device according to claim 7, wherein, One of the second transmission lines has more bends than one of the first transmission lines.

9. The display device according to claim 6, further comprising: The transmit control line is arranged between the first transmit driver circuit and the second transmit driver circuit. The transmit control line is connected to the first transmit driver circuit and the second transmit driver circuit.

10. The display device according to claim 6, further comprising: A first scan control line is arranged between the first scan driver circuit and the first transmit driver circuit, wherein the first scan control line is connected to the first scan driver circuit; and A second scan control line is arranged on one side of the second scan driver circuit, wherein the second scan control line is connected to the second scan driver circuit. The second transmit driver circuit is arranged on the side of the second scan driver circuit opposite to the side where the second scan control line is arranged.

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