Memory module and stacked memory device

Abstract

A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes an array of memory cells that store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address exchange operation in response to a power-on signal or a reset signal to randomly exchange a portion of bits of the access address to generate an exchanged address and enables a corresponding target word line among word lines in the array of memory cells in response to the access address, such that two or more of the semiconductor memory devices enable different target word lines.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0047233, filed on April 20, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments relate to memory devices, and more specifically, to memory modules and stacked memory devices. Background Technology

[0004] In memory devices, Dynamic Random Access Memory (DRAM) devices store data by storing charge in capacitors within memory cells. As the charge in the capacitors leaks over time, the DRAM device refreshes the memory cells. The memory controller can randomly access the addresses of the DRAM device, and more specifically, can access specific addresses frequently or intensively. Because DRAM, as a volatile memory device, has high access speeds, it is widely used as working memory, buffer memory, main memory, etc., in computing systems. For high capacity, multiple DRAMs can be configured as memory modules. Summary of the Invention

[0005] One aspect is to provide a memory module that can disperse interference caused by densely accessed addresses.

[0006] On the other hand, it provides a memory device that can distribute the interference caused by densely accessed addresses in a stack.

[0007] According to one aspect of an exemplary embodiment, a memory module is provided, the memory module including a plurality of semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each of the plurality of semiconductor memory devices includes a memory cell array for storing data. The control device receives commands and access addresses from an external device and provides the commands and access addresses to the plurality of semiconductor memory devices. Each of the plurality of semiconductor memory devices performs an address swapping operation in response to an energizing signal or a reset signal to randomly swap a portion of bits of the access address to generate a swapped address, and enables a corresponding target word line among a plurality of word lines in the memory cell array of the semiconductor memory device based on the same access address, such that at least two of the plurality of semiconductor memory devices enable different target word lines.

[0008] According to another aspect of an exemplary embodiment, a memory module is provided, comprising a plurality of semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each of the plurality of semiconductor memory devices includes a memory cell array for storing data. The control device receives a command and an access address from an external device, performs an address swapping operation in response to a power-on signal or a reset signal to randomly swap a portion of bits of the access address to generate a swapped address, and provides the command and the swapped address to the plurality of semiconductor memory devices. The plurality of semiconductor memory devices enable corresponding target word lines among a plurality of word lines in the memory cell array based on the same access address, such that at least two of the plurality of semiconductor memory devices enable different target word lines.

[0009] According to another aspect of an exemplary embodiment, a stacked memory device is provided, the stacked memory device including a buffer die, a plurality of memory dies stacked on the buffer die, and a plurality of through-silicon vias (TSVs) extending through the plurality of memory dies to connect to the buffer die. The buffer die receives commands and access addresses from an external device. The plurality of memory dies includes an array of memory cells storing data. Each of the plurality of memory dies receives an access address via a TSV, performs an address swapping operation in response to a power-on signal or a reset signal to randomly swap a portion of bits of the access address to generate a swapped address, and enables a corresponding target word line among the plurality of word lines in the memory cell array based on the same access address, such that at least two of the plurality of memory dies enable different target word lines. Attached Figure Description

[0010] The above and other aspects will be more clearly understood by referring to the detailed description of exemplary embodiments in the accompanying drawings, wherein:

[0011] Figure 1 This is a block diagram illustrating a memory system according to various exemplary embodiments;

[0012] Figure 2 This is a detailed illustration based on exemplary embodiments. Figure 1 A block diagram of the memory module of the memory system;

[0013] Figure 3 This illustrates various exemplary embodiments. Figure 2 A block diagram of one of the semiconductor memory devices in a memory module;

[0014] Figure 4 Illustrations based on various exemplary embodiments Figure 3 The first memory bank array of a semiconductor memory device;

[0015] Figure 5 This illustrates an exemplary embodiment. Figure 3 A block diagram of the address switching circuit in a semiconductor memory device;

[0016] Figure 6 This illustrates an exemplary embodiment. Figure 5 A block diagram of an example address switching circuit;

[0017] Figure 7 This is according to an exemplary embodiment. Figure 6 An example of a physically unclonable function (PUF) in an address-switching circuit;

[0018] Figure 8 This illustrates an exemplary embodiment. Figure 5 The circuit diagram of the address switching circuit, specifically the address switcher.

[0019] Figure 9 This illustrates an exemplary embodiment. Figure 5 A block diagram of another example of an address switching circuit;

[0020] Figure 10 Showing according to an exemplary embodiment Figure 2 An example of address swapping operations in a memory module;

[0021] Figure 11 This is a detailed illustration based on exemplary embodiments. Figure 1 A block diagram of another example of a memory module in a memory system;

[0022] Figure 12 This illustrates an exemplary embodiment. Figure 11 A block diagram illustrating an example of a control device in a memory module;

[0023] Figure 13 This illustrates an exemplary embodiment. Figure 12 A block diagram of an example address switching circuit block (ASB) in a control device;

[0024] Figure 14 This illustrates an exemplary embodiment. Figure 13 A block diagram of one of the address switching circuits of the ASB;

[0025] Figure 15 This illustrates various exemplary embodiments. Figure 11 A block diagram of one of the semiconductor memory devices in a memory module;

[0026] Figure 16 Showing according to an exemplary embodiment Figure 11 An example of address swapping operations in a memory module;

[0027] Figure 17A This illustrates an exemplary embodiment. Figure 1 A block diagram of another example of a memory module in a memory system;

[0028] Figure 17B This illustrates an exemplary embodiment. Figure 1 A block diagram of another example of a memory module in a memory system;

[0029] Figure 18 This is a block diagram illustrating an example of a stacked memory device according to an exemplary embodiment;

[0030] Figure 19 Showing according to an exemplary embodiment Figure 18 Examples of stacked memory devices;

[0031] Figure 20 This is a block diagram illustrating another example of a stacked memory device according to an exemplary embodiment;

[0032] Figure 21 This is a flowchart illustrating a method for operating a memory module according to an exemplary embodiment;

[0033] Figure 22 This is a diagram illustrating a semiconductor package including stacked memory devices according to an exemplary embodiment;

[0034] Figure 23 This is a block diagram illustrating a memory system having four columns of memory modules according to an exemplary embodiment; and

[0035] Figure 24 This is a block diagram illustrating a mobile system including a memory module according to an exemplary embodiment. Detailed Implementation

[0036] An exemplary embodiment provides a memory module capable of symmetrically transmitting address signals.

[0037] An exemplary embodiment also provides a method for operating a memory module capable of symmetrically transmitting address signals.

[0038] According to various exemplary embodiments, a memory module includes a plurality of semiconductor memory devices and a control device. The semiconductor memory devices or the control device can generate a swapped row address based on a row address in an access address. A row decoder in each of the semiconductor memory devices enables a different target word line in response to the swapped row address, such that at least two of the semiconductor memory devices enable different target word lines relative to the access address. Therefore, the semiconductor memory devices can disperse victim word lines that are interfered with by densely accessed addresses, and thus reduce the likelihood of failure due to unauthorized access.

[0039] In the following description, various exemplary embodiments will be described more fully with reference to the accompanying drawings. Throughout this application, the same reference numerals may refer to the same elements.

[0040] Figure 1 This is a block diagram illustrating a memory system according to various exemplary embodiments.

[0041] Reference Figure 1 The memory system 10 includes a host 20 and a memory module 100. The host 20 may include a memory controller 25.

[0042] The memory module 100 may include a control device 500, a plurality of semiconductor memory devices (DRAM) 200, a serial presence detection (SPD) chip 180, and a power management integrated circuit (PMIC) 185. In some exemplary embodiments, the control device 500 may be a registered clock driver (RCD).

[0043] The control device 500 can control the semiconductor memory device 200 and the PMIC 185 under the control of the memory controller 25. For example, the control device 500 can receive the address ADDR, command CMD, reset signal RST, and clock signal CK from the memory controller 25. In response to the received signals, the control device 500 can control the semiconductor memory device 200 via the first control signal CTL1 and control the PMIC 185 via the second control signal CTL2.

[0044] In response to the received signal, the control device 500 can control the semiconductor memory device 200 such that data received through the data signal DQ and the data strobe signal DQS is written into the semiconductor memory device 200, or that data stored in the semiconductor memory device 200 is output through the data signal DQ and the data strobe signal DQS.

[0045] For example, the control device 500 can send the address ADDR, command CMD, reset signal RST and clock signal CK as a first control signal CTL1 from the memory controller 25 to the semiconductor memory device 200.

[0046] The semiconductor memory device 200 can store data received via the data signal DQ and the data strobe signal DQS under the control of the control device 500. Alternatively, the semiconductor memory device 200 can output data written via the data signal DQ and the data strobe signal DQS under the control of the control device 500.

[0047] For example, semiconductor memory device 200 may include volatile memory devices such as dynamic random access memory (DRAM), static RAM (SRAM), or synchronous DRAM (SDRAM). For example, semiconductor memory device 200 may be a DRAM-based volatile memory device.

[0048] SPD chip 180 may be a programmable read-only memory (e.g., EEPROM). SPD chip 180 may include initial information or device information DI of memory module 100. In various exemplary embodiments, SPD chip 180 may include initial information or device information DI of memory module 100 such as model format, model configuration, storage capacity, model type, execution environment, etc.

[0049] When the memory system 10, including the memory module 100, is started, the host 20 can read device information DI from the SPD chip 180 and identify the memory module 100 based on the device information DI. The host 20 can control the memory module 100 based on the device information DI from the SPD chip 180. For example, the host 20 can identify the type of semiconductor memory device 200 included in the memory module 100 based on the device information DI from the SPD chip 180.

[0050] In various exemplary embodiments, the SPD chip 180 can communicate with the host 20 via a serial bus. For example, the host 20 can exchange signals with the SPD chip 180 via the serial bus. The SPD chip 180 can also communicate with the control device 500 via the serial bus. The serial bus may include at least one of the following: a 2-line serial bus for internal integrated circuits (I2C), a system management bus (SMBus), a power management bus (PMBus), an intelligent platform management interface (IPMI), and a management component transfer protocol (MCTP).

[0051] PMIC 185 receives an input voltage VIN, generates a power supply voltage VDD based on the input voltage VIN, and provides the power supply voltage VDD to the semiconductor memory device 200 and / or the control device 500. The semiconductor memory device 200 operates based on the power supply voltage VDD.

[0052] Figure 2 This illustrates an exemplary embodiment. Figure 1 A block diagram of an example memory module of a memory system.

[0053] Reference Figure 2 The memory module 100a includes a control device 500a disposed (or mounted) on a circuit board 101, a plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e, a plurality of data buffers (DBs) 141 to 145 and 151 to 155, module resistor units (MRUs) 160 and 170, an SPD chip 180 and a PMIC 185.

[0054] Here, the circuit board 101 (which is a printed circuit board) can extend between the first edge portion 103 and the second edge portion 105 in a second direction D2 perpendicular to the first direction D1. The first edge portion 103 and the second edge portion 105 can extend in the first direction D1.

[0055] In some exemplary embodiments, the control device 500a may be disposed at the center of the circuit board 101. A plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e may be arranged in multiple rows between the control device 500a and the first edge portion 103 and in multiple rows between the control device 500a and the second edge portion 105.

[0056] In this configuration, semiconductor memory devices 201a to 201e and 202a to 202e may be arranged in multiple rows between control device 500a and first edge portion 103. Semiconductor memory devices 203a to 203e and 204a to 204e may be arranged in multiple rows between control device 500a and second edge portion 105. A portion of semiconductor memory devices 201a to 201e and 202a to 202e may be error correction code (ECC) memory devices. ECC memory devices may perform ECC encoding operations to generate parity bits regarding data to be written into memory cells of the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e, and perform ECC decoding operations to correct errors occurring in data read from memory cells.

[0057] Each of the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e can be coupled to a corresponding data buffer among data buffers (DB) 141 to 145 and 151 to 155 via data transmission lines for receiving / transmitting data signals DQ and data strobe signals DQS.

[0058] Control device 500a can provide command / address signals (e.g., CA) to semiconductor memory devices 201a to 201e via command / address transmission line 161, and can provide command / address signals to semiconductor memory devices 202a to 202e via command / address transmission line 163. Additionally, control device 500a can provide command / address signals to semiconductor memory devices 203a to 203e via command / address transmission line 171, and can provide command / address signals to semiconductor memory devices 204a to 204e via command / address transmission line 173.

[0059] Command / address transmission lines 161 and 163 can be jointly connected to a module resistor unit (MRU) 160 located adjacent to the first edge portion 103, and command / address transmission lines 171 and 173 can be jointly connected to a module resistor unit (MRU) 170 located adjacent to the second edge portion 105. Each of the module resistor units (MRUs) 160 and 170 may include a terminating resistor Rtt / 2 connected to the termination voltage Vtt. In this case, the arrangement of the module resistor units (MRUs) 160 and 170 reduces the number of module resistor units and thus reduces the area where the terminating resistors are placed.

[0060] In addition, each of the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e may be a DDR5 SDRAM.

[0061] The SPD chip 180 may be positioned adjacent to the control device 500a, and the PMIC 185 may be positioned between the semiconductor memory device 203e and the second edge portion 105. The PMIC 185 may generate a power supply voltage VDD based on the input voltage VIN, and may provide the power supply voltage VDD to the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e.

[0062] Although Figure 2 The PMIC 185 is shown to be positioned adjacent to the second edge portion 105, but the exemplary embodiments are not limited thereto, and in some exemplary embodiments, the PMIC 185 may be positioned in the central portion of the circuit board 101, adjacent to the control device 500a.

[0063] Each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e may include an address switching circuit that performs an address switching operation in response to an energizing signal or a reset signal to randomly swap a portion of bits of the access address ADDR to generate a swapped address, and enables a corresponding target word line among multiple word lines in the memory cell array based on the same access address, such that at least two of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e enable different target word lines.

[0064] Each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e performs an address switching operation in response to a power-on signal and / or a reset signal, thereby outputting a random selection signal with different logic levels and switching a portion of the bits of the access address ADDR.

[0065] Therefore, when the access address ADDR is accessed intensively, that is, when the access address ADDR is accessed more frequently than the reference access count, the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e can disperse (i.e. distinguish) the victim word lines that are interfered with by the access address ADDR.

[0066] Here, the power-on signal can be a signal enabled by a logic high level, and during the power-on sequence in the initialization operation when power is applied to the memory module 100a from the host 20, it can be enabled in response to the power supply voltage VDD provided to each of the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e being equal to or greater than a reference voltage. The reset signal can be a signal applied to the memory module 100a by the memory controller 25 during normal operation of the memory module 100a. The memory module 100a can be reset in response to a reset signal enabled by a logic low level.

[0067] Figure 3 This illustrates various exemplary embodiments. Figure 2 A block diagram of one of the semiconductor memory devices in a memory module.

[0068] Reference Figure 3The semiconductor memory device 201a may include control logic circuitry 210, address register 220, memory bank control logic 230, row address multiplexer (RA MUX) 240, column address (CA) latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier 285, input / output gating circuit (I / O gating circuit) 290, data input / output (I / O) buffer 295, power-on signal generator (PUSG) 225, refresh counter 245, and ECC engine 297.

[0069] The memory cell array 300 may include a first memory array 310 through an eighth memory array 380. The memory cell array 300 may operate based on a power supply voltage VDD.

[0070] The row decoder 260 may include a first row decoder 260a to an eighth row decoder 260h respectively coupled to the first memory array 310 to the eighth memory array 380, the column decoder 270 may include a first column decoder 270a to an eighth column decoder 270h respectively coupled to the first memory array 310 to the eighth memory array 380, and the sense amplifier 285 may include a first sense amplifier 285a to an eighth sense amplifier 285h respectively coupled to the first memory array 310 to the eighth memory array 380.

[0071] The first memory array 310 to the eighth memory array 380, the first row decoder 260a to the eighth row decoder 260h, the first column decoder 270a to the eighth column decoder 270h, and the first sense amplifier 285a to the eighth sense amplifier 285h can form the first memory array to the eighth memory array. Each memory array in the first memory array 310 to the eighth memory array 380 may include multiple word lines WL, multiple bit lines BTL, and multiple memory cells MC formed at the intersection of word lines WL and bit lines BTL.

[0072] Although semiconductor memory device 201a in Figure 3 The diagram shows eight memory cells, but the semiconductor memory device 201a may include any number of memory cells.

[0073] Address register 220 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from control device 500. Address register 220 can provide the received bank address BANK_ADDR to bank control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0074] Address register 220 may include address switching circuitry (ASC) 400.

[0075] The address switching circuit 400 can randomly swap a portion of the bits of the row address ROW_ADDR in response to the power-on signal PUP or the reset signal RST, so as to output the swapped row address S_ROW_ADDR.

[0076] The memory bank control logic 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One row decoder from the first row decoder 260a to the eighth row decoder 260h, corresponding to the memory bank address BANK_ADDR, can be activated in response to the memory bank control signal, and one column decoder from the first column decoder 270a to the eighth column decoder 270h, corresponding to the memory bank address BANK_ADDR, can be activated in response to the memory bank control signal.

[0077] The row address multiplexer 240 can receive the swapped row address S_ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 can selectively output either the swapped row address S_ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 can be applied to the first memory bank row decoders 260a to the eighth memory bank row decoders 260h.

[0078] One of the first to eighth row decoders 260a is activated to decode the row address RA output from the row address multiplexer 240, and the word line WL corresponding to the row address RA is activated. For example, the activated bank row decoder can generate a word line drive voltage based on the power supply voltage VDD, and can apply the word line drive voltage to the word line WL corresponding to the row address RA.

[0079] Column address latch 250 can receive column address COL_ADDR from address register 220 and can temporarily store the received column address COL_ADDR. In various exemplary embodiments, in burst mode, column address latch 250 can generate a column address that is incremented relative to the received column address COL_ADDR. Column address latch 250 can apply the temporarily stored or generated column address to first bank column decoders 270a through eighth bank column decoders 270h.

[0080] One of the column decoders 270a to 270h, when activated, can decode the column address COL_ADDR output from the column address latch 250 and can control the I / O gate circuit 290 to output data corresponding to the column address COL_ADDR.

[0081] I / O gate circuit 290 may include circuitry for gating input / output data. I / O gate circuit 290 may also include a read data latch for storing data output from the first memory array 310 to the eighth memory array 380 and a write control device for writing data to the first memory array 310 to the eighth memory array 380.

[0082] Data read from one of the first memory arrays 310 to the eighth memory array 380 can be read out by a readout amplifier and stored in a readout data latch, the readout amplifier being coupled to the memory array from which the data will be read.

[0083] After ECC engine 297 performs ECC decoding on data (e.g., codeword CW), the data stored in the read data latch can be provided to memory controller 25 via data I / O buffer 295. Data to be written to one of the first memory arrays 310 to the eighth memory arrays 380 can be provided from memory controller 25 to data I / O buffer 295. ECC engine 297 can perform ECC encoding on the data provided to data I / O buffer 295, and ECC engine 297 can provide the encoded data (e.g., codeword CW) to I / O gate circuitry 290.

[0084] During a write operation, the data I / O buffer 295 provides the data signal DQ to the ECC engine 297. During a read operation, the data I / O buffer 295 receives the data signal DQ from the ECC engine 297 and provides the data signal DQ and the data strobe signal DQS to the memory controller 25.

[0085] The power-on signal generator (PUSG) 225 generates a power-on signal PUP in response to a power supply voltage VDD from the PMIC 185 being equal to or greater than a reference voltage. The power-on signal generator 225 provides the power-on signal PUP to the address switching circuit 400.

[0086] The power-on signal generator 225 may include a comparator. The comparator compares the supply voltage VDD with the level of a reference voltage and provides the address switching circuit 400 with a power-on signal PUP enabled in response to the supply voltage VDD being equal to or greater than the reference voltage.

[0087] When memory module 100a is powered on and PMIC 185 receives input voltage VIN from memory controller 25, PMIC 185 generates various voltages, including power supply voltage VDD, based on input voltage VIN. Semiconductor memory device 201a operates based on power supply voltage VDD and operates normally when power supply voltage VDD is equal to or greater than a certain voltage level.

[0088] The power-on signal generator 225 can be set to a specific voltage level as a reference voltage and provides the address switching circuit 400 with a power-on signal PUP that is enabled in response to the power supply voltage VDD being equal to or greater than the reference voltage, wherein the semiconductor memory device 201a operates normally at the specific voltage level. In response to receiving the power-on signal PUP, the address switching circuit 400 converts the access address ADDR into a switched address and provides the switched address to the row decoder 260.

[0089] Control logic circuit 210 can control the operation of semiconductor memory device 201a. For example, control logic circuit 210 can generate control signals for causing memory device 201a to perform write or read operations. Control logic circuit 210 may include command decoder 211 and mode register 212, wherein command decoder 211 decodes commands CMD received from memory controller 25 via control device 500a, and mode register 212 sets the operating mode of semiconductor memory device 201a.

[0090] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc.

[0091] Figure 4 Showing various exemplary embodiments Figure 3 The first memory bank array of a semiconductor memory device.

[0092] Reference Figure 4 The first memory bank array 310 includes multiple word lines WL1 to WL2m (where m is a natural number greater than two), multiple bit lines BTL1 to BTL2n (where n is a natural number greater than two), and multiple memory cells MC disposed near the intersections of the word lines WL1 to WL2m and the bit lines BTL1 to BTL2n. In an exemplary embodiment, each of the multiple memory cells MC may include a DRAM cell structure. The multiple word lines WL1 to WL2m to which the multiple memory cells MC are connected may be referred to as rows of the first memory bank array 310, and the multiple bit lines BTL1 to BTL2n to which the multiple memory cells MC are connected may be referred to as columns of the first memory bank array 310.

[0093] Figure 5 This illustrates an exemplary embodiment. Figure 3 A block diagram of the address switching circuit in a semiconductor memory device.

[0094] Reference Figure 5 The address switching circuit (ASC) 400 may include a random selection signal generator (RSSG) 410 and an address exchanger 430.

[0095] The random selection signal generator 410 can randomly generate a random selection signal RSS in response to a power-on signal PUP or a reset signal RST. The address exchanger 430 can exchange a portion of the bits of the row address ROW_ADDR in response to the random selection signal RSS to output the exchanged row address S_ROW_ADDR.

[0096] The random selection signal generator 410 may include circuit elements such as a physically unclonable function (PUF), a random number generator, an anti-fuse circuit, or a fuse circuit, which are triggered by an energizing signal PUP or a reset signal RST to randomly output a random selection signal RSS.

[0097] The random selection signal generator in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e is triggered by a power-on signal PUP or a reset signal RST and can generate a random selection signal RSS with different logic levels. The address exchange in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e can convert the row address ROW_ADDR into a different exchanged row address S_ROW_ADDR indicating different memory cell rows in response to the random selection signal RSS with different logic levels.

[0098] Figure 6 This illustrates an exemplary embodiment. Figure 5 A block diagram of an example address switching circuit.

[0099] Reference Figure 6 The address switching circuit 400a may include a random selection signal generator 410a and an address exchanger 430.

[0100] Address switching circuit 400a may include a Physically Unclonable Function (PUF) 410a, and PUF 410a may randomly generate a Random Select Signal RSS in response to a power-on signal PUP or a reset signal RST. Address switch 430 may swap a portion of the bits of the row address ROW_ADDR in response to the Random Select Signal RSS to output the swapped row address S_ROW_ADDR.

[0101] when Figure 5 The random selection signal generator 410 in the middle is composed of, for example, Figure 6 When the PUF 410a is implemented, the address switching circuit 400a can perform address switching operations while resisting unauthorized intrusion from outside the memory system.

[0102] Figure 7 This is according to an exemplary embodiment. Figure 6 An example of a physically unclonable function (PUF) in an address-switching circuit.

[0103] exist Figure 7 In this context, it is assumed that the random selection signal RSS includes a first random selection signal (bit) RSS1 and a second random selection signal (bit) RSS2, and that PUF 410a can swap a portion of bits RA0, RA1, RA2 and RA3 of the row address ROW_ADDR to output a portion of bits SRA0, SRA1, SRA2 and SRA3 of the swapped row address S_ROW_ADDR.

[0104] Reference Figure 7 When the first random selection signal RSS1 and the second random selection signal RSS2 correspond to '00', a portion of the row address ROW_ADDR bits RA0, RA1, RA2, and RA3 can be swapped with a portion of the swapped row address S_ROW_ADDR bits SRA0, SRA1, SRA2, and SRA3, respectively. When the first random selection signal RSS1 and the second random selection signal RSS2 correspond to '01', a portion of the row address ROW_ADDR bits RA0, RA1, RA2, and RA3 can be swapped with a portion of the swapped row address S_ROW_ADDR bits SRA1, SRA2, SRA3, and SRA0, respectively.

[0105] When the first random selection signal RSS1 and the second random selection signal RSS2 correspond to '10', a portion of the row address ROW_ADDR bits RA0, RA1, RA2, and RA3 can be swapped with a portion of the swapped row address S_ROW_ADDR bits SRA2, SRA3, SRA0, and SRA1, respectively. When the first random selection signal RSS1 and the second random selection signal RSS2 correspond to '11', a portion of the row address ROW_ADDR bits RA0, RA1, RA2, and RA3 can be swapped with a portion of the swapped row address S_ROW_ADDR bits SRA3, SRA0, SRA1, and SRA2, respectively.

[0106] Therefore, when Figure 5 When the random selection signal generator 410 is triggered by the power-on signal PUP or the reset signal RST, and the logic level of the random selection signal RSS is determined, the address exchange 430 can randomly exchange a portion of the bits of the row address ROW_ADDR based on the randomly determined logic level of the random selection signal RSS, so as to output the exchanged row address S_ROW_ADDR.

[0107] Figure 8 This illustrates an exemplary embodiment. Figure 5 The circuit diagram of the address switching circuit, specifically the address switcher.

[0108] exist Figure 8 In this context, it is assumed that the random selection signal RSS includes a first random selection signal RSS1 and a second random selection signal RSS2, and the address exchange 430 can exchange a portion of the row address ROW_ADDR bits RA0, RA1, RA2 and RA3 in response to the first random selection signal RSS1 and the second random selection signal RSS2, so as to output a portion of the row address S_ROW_ADDR bits SRA0, SRA1, SRA2 and SRA3 after the exchange.

[0109] Reference Figure 8 The address switch 430 may include multiple multiplexers 431, 433, 435 and 437.

[0110] Each of the multiplexers 431, 433, 435, and 437 receives a corresponding bit from the row address ROW_ADDR, namely RA0, RA1, RA2, and RA3, and outputs a corresponding bit from the row address S_ROW_ADDR, namely RA0, RA1, RA2, and RA3, based on a combination of the first random selection signal RSS1 and the second random selection signal RSS2, as a corresponding bit from the row address S_ROW_ADDR, namely SRA0, SRA1, SRA2, and SRA3.

[0111] For reference Figure 7 The description states that a subset of bits RA0, RA1, RA2, and RA3 in the row address ROW_ADDR can be swapped for one of the following subsets: (SRA0, SRA1, SRA2, and SRA3), (SRA1, SRA2, SRA3, and SRA0), (SRA2, SRA3, SRA0, and SRA1), and (SRA3, SRA0, SRA1, and SRA2).

[0112] Figure 8 The number of multiplexers in the address exchange 430 can vary depending on the number of bits to be exchanged. To exchange p bits of the row address ROW_ADDR, the address exchange 430 may include 2p multiplexers, and the random selection signal RSS includes p bits. Here, p is a natural number.

[0113] Figure 9 This illustrates an exemplary embodiment. Figure 5 A block diagram of another example of an address switching circuit.

[0114] Reference Figure 9 The address switching circuit 400b may include an antifuse circuit 410b and an address switch 430.

[0115] The logic levels of the first random selection signal RSS1 and the second random selection signal RSS2 can be programmed in the antifuse circuit 410b, and the antifuse circuit 410b can output the first random selection signal RSS1 and the second random selection signal RSS2 to the address exchange 430 in response to the power-on signal PUP or the reset signal RST. The address exchange 430 can swap a portion of the bits of the row address ROW_ADDR in response to the random selection signals RSS1 and RSS2 to output the swapped row address S_ROW_ADDR.

[0116] The logic levels of the first random selection signal RSS1 and the second random selection signal RSS2 can be programmed in different sequences in the antifuse circuit of each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e.

[0117] The first random selection signal RSS1 and the second random selection signal RSS2 can be programmed in the antifuse circuit of the first semiconductor memory device in the sequence of '00', in the antifuse circuit of the second semiconductor memory device in the sequence of '01', in the antifuse circuit of the third semiconductor memory device in the sequence of '10', and in the antifuse circuit of the fourth semiconductor memory device in the sequence of '11'.

[0118] In some exemplary embodiments, the random selection signal generator 410 may use a fuse circuit instead of the antifuse circuit 410b.

[0119] Figure 10 Showing according to an exemplary embodiment Figure 2 An example of address swapping operations for a memory module.

[0120] exist Figure 10 The diagram illustrates semiconductor memory devices 201a to 201e and control device 500a in semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e. It will be understood that the remaining semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e operate in a similar manner, and therefore, for the sake of brevity, their descriptions are omitted.

[0121] Reference Figure 10 The control device 500a receives the command CMD, the access address ADDR, and the reset signal RST, and relays the command CMD and the access address ADDR to the semiconductor memory devices 201a to 201e. Additionally, the control device 500a relays the reset signal RST to the semiconductor memory devices 201a to 201e.

[0122] Semiconductor memory device 201a includes memory cell array 300a, semiconductor memory device 201b includes memory cell array 300b, semiconductor memory device 201c includes memory cell array 300c, semiconductor memory device 201d includes memory cell array 300d, and semiconductor memory device 201e includes memory cell array 300e.

[0123] The address switching circuit in semiconductor memory device 201a converts the row address into a first-switched row address to enable the target word line WLa of memory cell array 300a. The address switching circuit in semiconductor memory device 201b converts the row address into a second-switched row address to enable the target word line WLb of memory cell array 300b. The address switching circuit in semiconductor memory device 201c converts the row address into a third-switched row address to enable the target word line WLc of memory cell array 300c. The address switching circuit in semiconductor memory device 201d converts the row address into a fourth-switched row address to enable the target word line WLd of memory cell array 300d. And the address switching circuit in semiconductor memory device 201e converts the row address into a fifth-switched row address to enable the target word line WLe of memory cell array 300e.

[0124] Therefore, semiconductor memory devices 201a to 201e enable different target word lines WLa, WLb, WLc, WLd, and WLe respectively in response to access address ADDR. Furthermore, if access address ADDR is accessed intensively, the victim word lines WLf, WLg, WLh, WLi, and WLj, dispersed by target word lines WLa, WLb, WLc, WLd, and WLe respectively in semiconductor memory devices 201a to 201e are different. Therefore, semiconductor memory devices 201a to 201e can disperse the victim word lines WLf, WLg, WLh, WLi, and WLj that are affected by access address interference with ADDR.

[0125] exist Figure 10 In this context, AWL indicates the aggressive word line corresponding to the target word lines WLa, WLb, WLc, WLd, and WLe, while VWL indicates the victim word line.

[0126] Figure 11 This is a detailed illustration of an exemplary embodiment. Figure 1 A block diagram of another example of a memory module in a memory system.

[0127] Reference Figure 11 The memory module 100b includes a control device 500b disposed in (or mounted on) a circuit board 101, a plurality of semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e and 208a to 208e, a plurality of data buffers (DBs) 141 to 145 and 151 to 155, module resistor units (MRUs) 160 and 170, an SPD chip 180 and a PMIC 185.

[0128] Figure 11 The memory module 100b and Figure 2 The memory module 100a differs in that: the control device 500b performs address switching and provides the switched addresses to the semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e and 208a to 208e, and the control device 500b receives the power supply voltage VDD.

[0129] Control device 500b receives command CMD, access address ADDR, clock signal CK, and reset signal RST. In response to the reset signal RST or a power-on signal, it randomly swaps a portion of the bits of access address ADDR to generate a swapped address, which is then provided to semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e, respectively. Control device 500b may include multiple address swapping circuits corresponding to the respective semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e.

[0130] Each of the semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e receives a corresponding one of the swapped addresses and enables a target word line corresponding to the corresponding one of the swapped addresses, such that two or more of the semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e enable different target word lines relative to the same access address ADDR.

[0131] Therefore, when access address ADDR is accessed intensively, semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e and 208a to 208e can disperse (i.e., distinguish) the victim word lines that are interfered with by access address ADDR.

[0132] Figure 12 This illustrates an exemplary embodiment. Figure 11 A block diagram illustrating an example of a control device in a memory module.

[0133] Reference Figure 12 The control device 500b may include a memory management circuit (MMU) 510 and an address switching circuit block (ASB) 520.

[0134] MMU 510 can relay command CMD and clock signal CK to semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e and 208a to 208e, and can provide access address ADDR to ASB 520.

[0135] MMU 510 may include control circuitry 511, command buffer C_BUF 513, clock buffer CK_BUF 515, and address buffer A_BUF 517. Control circuitry 511 controls the command buffer, clock buffer 515, and address buffer 517 to control the buffering time of command CMD, clock signal CK, and access address ADDR.

[0136] The ASB 520 can randomly swap a portion of the bits of the access address ADDR in response to a reset signal RST or a power-on signal based on the power supply voltage VDD, to generate swapped addresses SADDRa to SADDRk, and to provide the swapped addresses SADDRa to SADDRk to semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e and 208a to 208e, respectively.

[0137] The control circuit 511 can control the timing of providing the swapped addresses SADDRa to SADDRk and the timing of providing the command CMD and clock signal CK.

[0138] Figure 13 This illustrates an exemplary embodiment. Figure 12 A block diagram of an example address switching circuit block (ASB) in a control device.

[0139] Reference Figure 13 The ASB 520 includes a power signal generator PUSG 530 and multiple address switching circuits ASC1 540a to ASCk 540k.

[0140] Power-on signal generator 530 generates a power-on signal PUP in response to a power supply voltage VDD from PMIC 185 being equal to or greater than a reference voltage. Power-on signal generator 530 provides the power-on signal PUP to address switching circuits 540a to 540k.

[0141] Address switching circuits 540a to 540k can randomly swap a portion of the bits of the access address ADDR in response to a power-on signal PUP or a reset signal RST to generate swapped addresses SADDRa to SADDRk, and can provide the swapped addresses SADDRa to SADDRk to semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e and 208a to 208e, respectively.

[0142] The number of address switching circuits 540a to 540k may be equal to or less than the number of semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e. Control device 500b can control address switching circuits 540a to 540k to provide the switched addresses SADDRa to SADDRk to semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e, respectively.

[0143] Figure 14 This illustrates an exemplary embodiment. Figure 13 A block diagram of one of the address switching circuits in the address switching circuit block.

[0144] Figure 14 The configuration of address switching circuit 540a is shown in the diagram, and it will be understood that the configuration of each of the address switching circuits 540b to 540k is substantially the same as that of address switching circuit 540a, and therefore, for the sake of brevity, repeated descriptions of it are omitted.

[0145] Reference Figure 14 The address switching circuit 540a may include a random selection signal generator (RSSG) 541 and an address switcher 543.

[0146] The random selection signal generator 541 can randomly generate a random selection signal RSS in response to an energizing signal PUP or a reset signal RST. The address exchanger 543 can exchange a portion of the bits of the row address ROW_ADDR in response to the random selection signal RSS to output the exchanged row address S_ROW_ADDRa.

[0147] Address switch 543 may include circuit elements such as a physically unclonable function (PUF), a random number generator, an antifuse circuit, or a fuse circuit that are triggered by an energizing signal PUP or a reset signal RST to randomly output a random selection signal RSS.

[0148] The random selection signal generator in each of the address switching circuits 540a to 540k is triggered by a power-on signal PUP or a reset signal RST, and can generate random selection signals RSS with different logic levels. The address switcher in each of the address switching circuits 540a to 540k can convert the row address ROW_ADDR into different swapped row addresses S_ROW_ADDR indicating different memory cell rows in response to the random selection signals RSS with different logic levels.

[0149] Figure 15 This illustrates various exemplary embodiments. Figure 11 A block diagram of one of the semiconductor memory devices in a memory module.

[0150] Reference Figure 15 The semiconductor memory device 205a may include control logic circuitry 210, address register 220a, memory bank control logic 230, row address multiplexer (RA MUX) 240, column address (CA) latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier 285, input / output gating circuitry (I / O gating circuitry) 290, data input / output (I / O) buffer 295, refresh counter 245, and ECC engine 297.

[0151] The semiconductor memory device 205a differs from the semiconductor memory device 201a in that the semiconductor memory device 205a includes an address register 220a instead of an address register 220, and does not include a power-on signal generator 225.

[0152] Address register 220a can receive from control device 500b a swapped address SADDRa, which includes the bank address BANK_ADDR, the swapped row address S_ROW_ADDR, and the column address COL_ADDR. Address register 220a can provide the received bank address BANK_ADDR to the bank control logic 230, the received swapped row address S_ROW_ADDR to the row address multiplexer 240, and the received column address COL_ADDR to the column address latch 250.

[0153] Address register 220a does not perform address swapping operations.

[0154] Figure 16 An exemplary embodiment is shown. Figure 11 An example of address swapping operations for a memory module.

[0155] exist Figure 16 The diagram illustrates semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e, and control device 500b. It should be understood that the remaining semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e operate in a similar manner, and therefore, for the sake of brevity, their description is omitted.

[0156] Reference Figure 16The control device 500b receives the command CMD, the access address ADDR and the reset signal RST, receives the power supply voltage VDD from the PMIC 185, relays the command CMD to the semiconductor memory devices 205a to 205e, and provides the swapped addresses SADDRa to SADDRe to the semiconductor memory devices 205a to 205e respectively.

[0157] Semiconductor memory device 205a includes memory cell array 300a, semiconductor memory device 205b includes memory cell array 300b, semiconductor memory device 205c includes memory cell array 300c, semiconductor memory device 205d includes memory cell array 300d, and semiconductor memory device 205e includes memory cell array 300e.

[0158] The row decoder of semiconductor memory device 205a enables the target word line WLa1 of memory cell array 300a in response to the first swapped row address of the swapped address SADDRa, and the row decoder of semiconductor memory device 205b enables the target word line WLb1 of memory cell array 300b in response to the second swapped row address of the swapped address SADDRb.

[0159] The row decoder of semiconductor memory device 205c enables the target word line WLc1 of memory cell array 300c in response to the third swapped row address of the swapped address SADDRc; the row decoder of semiconductor memory device 205d enables the target word line WLd1 of memory cell array 300d in response to the fourth swapped row address of the swapped address SADDRd; and the row decoder of semiconductor memory device 205e enables the target word line WLe1 of memory cell array 300e in response to the fifth swapped row address of the swapped address SADDRe.

[0160] Therefore, when the memory controller 25 provides the access address ADDR, the semiconductor memory devices 205a to 205e respectively enable different target word lines WLa1, WLb1, WLc1, WLd1, and WLe1. Furthermore, if the access address ADDR is accessed intensively, the victim word lines WLf1, WLg1, WLh1, WLi1, and WLj1 in the semiconductor memory devices 205a to 205e that are interfered with by the target word lines WLa1, WLb1, WLc1, WLd1, and WLe1 are different. Therefore, the semiconductor memory devices 205a to 205e can disperse the victim word lines WLf1, WLg1, WLh1, WLi1, and WLj1 that are interfered with by the access address ADDR.

[0161] exist Figure 16In this context, AWL indicates the aggressive word lines corresponding to the target word lines WLa1, WLb1, WLc1, WLd1, and WLe1, while VWL indicates the victim word lines.

[0162] Figure 17A This illustrates an exemplary embodiment. Figure 1 A block diagram of another example of a memory module in a memory system.

[0163] Figure 17A The memory module 100c and Figure 2 The memory module 100c differs from the memory module 200a in that it does not include a data buffer (DB) for receiving data signals DQ and data strobe signals DQS from the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e, or for transmitting data signals DQ and data strobe signals DQS to the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e. The memory module 100c can receive data signals DQ and data strobe signals DQS from the memory controller 25 via the control device 500a, or transmit data signals DQ and data strobe signals DQS to the memory controller 25 via the control device 500a.

[0164] For reference Figure 2 As described, each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e may include an address switching circuit that performs an address switching operation in response to an energizing signal or a reset signal to randomly swap a portion of bits of the access address ADDR to generate a swapped address, and enables a corresponding target word line among a plurality of word lines in the memory cell array in response to the swapped address, such that at least two of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e enable different target word lines.

[0165] Figure 17B This illustrates an exemplary embodiment. Figure 1 A block diagram of another example of a memory module in a memory system.

[0166] Figure 17B The memory module 100d and Figure 11The memory module 100d differs from the memory module 100b in that it does not include a data buffer (DB) for receiving data signals DQ and DQS from the plurality of semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e, or for sending the data signals DQ and DQS to the plurality of semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e. The memory module 100d can receive data signals DQ and DQS from the memory controller 25 via the control device 500b, and can send the data signals DQ and DQS to the memory controller 25 via the control device 500b. The control device 500b receives a reset signal RST from the memory controller 25 and receives a power supply voltage VDD from the PMIC 185.

[0167] For reference Figure 11 As described, the control device 500b receives a command CMD, an access address ADDR, a clock signal CK, and a reset signal RST. In response to the reset signal RST or a power-on signal, it randomly swaps a portion of the bits in the access address ADDR to generate a swapped address, which is then provided to the specified addresses. Figure 17B The memory module 100d contains semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e. The control device 500b may include multiple address switching circuits corresponding to the respective semiconductor memory devices in the semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e.

[0168] Each of the semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e receives a corresponding swapped address from the swapped addresses and enables a target word line corresponding to the corresponding swapped address, such that two or more of the semiconductor memory devices 205a to 205e, 206a to 206e, 207a to 207e, and 208a to 208e enable different target word lines relative to the access address ADDR.

[0169] Figure 18 This is a block diagram illustrating an example of a stacked memory device according to an exemplary embodiment.

[0170] Reference Figure 18 The semiconductor memory device 600a may include a first set of dies 610 and a second set of dies 620 that provide a stacked chip structure.

[0171] The first set of dies 610 may include at least one buffer die 611. The second set of dies 620 may include a plurality of memory dies 620-1 to 620-s stacked on the at least one buffer die 611 and transmit data through a plurality of substrate through-hole (or silicon through-hole (TSV)) lines. Here, s is an integer greater than two.

[0172] Each of the memory dies 620-1 to 620-s may include a cell core 622 having an array of memory cells for storing data, an ECC engine 624, and an address switching circuit (ASC) 626. The address switching circuit 626 may employ... Figure 5 The address switching circuit 400. Therefore, the address switching circuit 626 can randomly swap a portion of the bits of the row address ROW_ADDR to generate a swapped row address, and can provide the swapped row address to the row decoder in the cell core. Therefore, the row decoders in the memory dies 620-1 to 620-s can enable different target word lines relative to the same access address from the memory controller.

[0173] Each memory die in memory dies 620-1 to 620-s can be used with Figure 3 It has a similar configuration to the semiconductor memory device 201a.

[0174] The buffer die 611 may include an interface circuit IFC 612 with an ECC engine 614 and an MMU 616.

[0175] ECC engine 614 may be referred to as a pass-through ECC engine, and can correct transmission errors in transmissions provided from at least one of the memory dies 620-1 to 620-s.

[0176] A data TSV line group 632 formed on a memory die 620-s may include multiple TSV lines L1 to Ls, and a parity TSV line group 634 may include multiple TSV lines L10 to Lt. The TSV lines L1 to Ls of the data TSV line group 632 and the parity TSV lines L10 to Lt of the parity TSV line group 634 may be connected to microbumps MCBs correspondingly formed between memory dies 620-1 to 620-s.

[0177] The stacked memory device 600a may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host via the data bus B10. The buffer die 611 may be connected to the memory controller via the data bus B10.

[0178] Figure 19 Showing according to an exemplary embodiment Figure 18 An example of a stacked memory device.

[0179] Reference Figure 19 The stacked memory device 600a may include a buffer die 611 and a plurality of memory dies 620a, 620b, 620c and 620d corresponding to memory dies 620-1 to 620-s.

[0180] Reference Figure 19 The buffer die 611 includes an internal command generator ICG 613 and an interface circuit IFC 612. The interface circuit IFC 612 includes an MMU 616. Internal commands ICMD from the internal command generator 613 are provided to memory dies 620a, 620b, 620c, and 620d via command silicon pass-throughs TSV_C formed independently for each channel.

[0181] The interface circuit 612 can provide data DQ and access address ADDR to the corresponding memory die during a write operation via the data silicon pass-through device TSV_D formed by the memory dies 620a, 620b, 620c and 620d, and can also provide data from the corresponding memory die to the outside.

[0182] Memory dies 620a, 620b, 620c, and 620d may each include: command decoders 621a to 621d, which output internal control signals by decoding internal commands; and address switching circuits 626a to 626d, which randomly swap a portion of the row address bits in the access address to output the swapped row address. Each of the address switching circuits 626a to 626d may employ... Figure 4 The address switching circuit 400 may include a random selection signal generator and an address switcher.

[0183] Address switching circuits 626a to 626d can enable different target word lines for different memory locations in memory dies 620a, 620b, 620c, and 620d relative to the same access address ADDR.

[0184] Figure 20 This is a block diagram illustrating another example of a stacked memory device according to an exemplary embodiment.

[0185] Reference Figure 20 The semiconductor memory device 600b may include a first set of dies 610-1 and a second set of dies 620-1 that provide a stacked chip structure.

[0186] The first set of dies 610-1 may include at least one buffer die 611-1. The second set of dies 620-1 may include a plurality of memory dies 620a-1 to 620a-s stacked on the at least one buffer die 611-1, and transmit data through a plurality of substrate through-hole (or silicon through-hole (TSV)) lines. Here, s is an integer greater than two.

[0187] Each of the memory dies 620a-1 to 620a-s may include a cell core 622 and an ECC engine 624, wherein the cell core 622 includes an array of memory cells for storing data.

[0188] Each memory die in the 620a-1 to 620a-s memory dies can be used with Figure 15 The configuration is similar to that of the semiconductor memory device 205a.

[0189] The buffer die 611-1 may have an interface circuit IFC 612a including an ECC engine 614 and an ASB 617.

[0190] ASB 617 can be adopted Figure 13 The ASB 520. Therefore, the ASB 617 may include a power signal generator and multiple address switching circuits.

[0191] The number of address switching circuits can be equal to or less than the number of memory dies 620a-1 to 620a-s.

[0192] A power-on signal generator generates a power-on signal in response to a power supply voltage equal to or greater than a reference voltage. The power-on signal generator provides this power-on signal to the address switching circuitry. The address switching circuitry can randomly swap a portion of the bits of the access address ADDR in response to either the power-on signal or the reset signal RST to generate a swapped address, and can provide the swapped address to memory dies 620a-1 to 620a-s respectively.

[0193] In each of the memory dies 620a-1 to 620a-s, the address register receives the corresponding swapped address and provides the swapped address to the row decoder. The row decoder can then enable the target word line in the memory cell array indicated by the swapped address.

[0194] Memory dies 620a-1 to 620a-s can enable different target word lines for different memory locations in memory dies 620a-1 to 620a-s relative to the same access address ADDR.

[0195] ECC engine 614 may be referred to as a pass-through ECC engine, and can correct transmission errors in at least one of the transmissions provided from memory dies 620a-1 to 620a-s.

[0196] A data TSV line group 632 formed on a memory die 620a-s may include multiple TSV lines L1 to Ls, and a parity TSV line group 634 may include multiple TSV lines L10 to Lt. The TSV lines L1 to Ls of the data TSV line group 632 and the parity TSV lines L10 to Lt of the parity TSV line group 634 may be connected to corresponding microbumps MCBs formed in the memory dies 620a-1 to 620a-s.

[0197] The stacked memory device 600b may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host via the data bus B10. The buffer die 611-1 may be connected to the memory controller via the data bus B10.

[0198] Figure 21 This is a flowchart illustrating a method for operating a memory module according to an exemplary embodiment.

[0199] Reference Figures 1 to 17B and Figure 21 A method is provided for operating a memory module 500a, which includes a control device 500a mounted on a circuit board and a plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e and 204a to 204e.

[0200] According to the method, the address switching circuit 400 in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e can randomly generate a random selection signal RSS (S110) based on the energizing signal PUP or the reset signal RST from the control device 500a. The address switching circuit 400 in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e can generate the random selection signal RSS in different sequences.

[0201] The address switching circuit 400 in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e can translate the access address into a switched address (S130). For example, the address switching circuit 400 in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e can switch a portion of the bits of the row address ROW_ADDR in response to the random selection signal RSS to generate the switched row address S_ROW_ADDR (S130).

[0202] The row decoder 260 in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e can enable different word lines in response to the corresponding swapped address (S150). For example, the row decoder 260 in each of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e can enable a target word line in response to the swapped row address S_ROW_ADDR, such that at least two or more of the semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e enable different target word lines.

[0203] Therefore, according to the method, if the access address ADDR is accessed intensively, the semiconductor memory devices 201a to 201e can disperse the victim word lines that are interfered with by the access address ADDR.

[0204] Figure 22 This is a diagram illustrating a semiconductor package including stacked memory devices according to an exemplary embodiment.

[0205] Reference Figure 22 The semiconductor package 700 may include one or more stacked memory devices 710 and graphics processing units (GPUs) 720.

[0206] The stacked memory device 710 and GPU 720 can be mounted on middleware 730, and the middleware with the stacked memory device 710 and GPU 720 mounted can be mounted on package substrate 740. Package substrate 740 is mounted on solder balls 750. GPU 720 can be... Figure 1 The memory controller 25 in the GPU 720 performs the same operation, or may include the memory controller 25. The GPU 720 may store data generated or used in graphics processing in the stacked memory device 710.

[0207] The stacked memory device 710 can be implemented in various forms, and the stacked memory device 710 can be a memory device in the form of high-bandwidth memory (HBM) in which multiple layers are stacked. In some exemplary embodiments, the stacked memory device 710 can adopt according to Figure 18 or Figure 20 The stacked memory device 710 may therefore include buffer dies and multiple memory dies. The buffer dies may include interface circuitry.

[0208] Each memory die may include a cell core, an ECC engine, and address switching circuitry, wherein the cell core includes a memory cell array.

[0209] Address switching circuits can use Figure 5 The address switching circuit 400. Therefore, the address switching circuit can randomly swap a portion of the bits of the row address to generate a swapped row address, and can provide the swapped row address to the row decoder in the cell core. Thus, the row decoder in the memory die can enable different target word lines relative to the same access address from the memory controller.

[0210] The buffer die may include an ASB. The ASB may be... Figure 13 The ASB (Address Switching Block) can therefore include an energizing signal generator and multiple address switching circuits. The address switching circuits can randomly swap a portion of the access address bits in response to an energizing signal or a reset signal to generate a swapped address, and can provide the swapped address to the memory die.

[0211] The plurality of stacked memory devices 710 may be mounted on middleware 730, and GPU 720 may communicate with the plurality of stacked memory devices 710. For example, each of the stacked memory devices 710 and GPU 720 may include a physical region, and communication between the stacked memory devices 710 and GPU 720 may be performed via the physical region.

[0212] Figure 23 This is a block diagram illustrating a memory system having quad-rank memory modules according to an exemplary embodiment.

[0213] Reference Figure 23 The memory system 800 may include a memory controller 810 and one or more memory modules 820 and 830. Figure 23 Two memory modules, 820 and 830, are shown, but this is just an example.

[0214] Memory controller 810 controls one or more memory modules 820 and 830 to execute commands supplied from a processor or host. Memory controller 810 may be implemented in a processor or host, or may be implemented using an application processor or a system-on-a-chip (SoC). For signal integrity, source termination may be implemented using a resistor RTT on bus 840 of memory controller 810. Resistor RTT may be coupled to a power supply voltage VDDQ. Memory controller 810 may include: a transmitter 811 for sending signals to one or more memory modules 820 and 830; and a receiver 813 for receiving signals from one or more memory modules 820 and 830.

[0215] One or more memory modules 820 and 830 may be referred to as a first memory module 820 and a second memory module 830. The first memory module 820 and the second memory module 830 may be coupled to a memory controller 810 via a bus 840. Each of the first memory module 820 and the second memory module 830 may correspond to... Figure 2 The memory module 100 or Figure 18 The memory module 100a. The first memory module 820 may include one or more memory columns RK1 and RK2, and the second memory module 830 may include one or more memory columns RK3 and RK4.

[0216] Each of the first memory module 820 and the second memory module 830 may include a control device disposed at the center of the circuit board, a first set of semiconductor memory devices disposed between the control device and a first edge portion of the circuit board, and a second set of semiconductor memory devices disposed between the control device and a second edge portion of the circuit board.

[0217] In an exemplary embodiment, each semiconductor memory device may include an address switching circuit that swaps a portion of bits of a row address to generate a swapped row address and applies the swapped row address to a row decoder. In an exemplary embodiment, a control device may include multiple address switching circuits corresponding to the semiconductor memory devices, which swap a portion of bits of a row address to generate a swapped row address and apply the swapped row address to the semiconductor memory devices. The row decoder in each semiconductor memory device may enable a different target word line in response to a corresponding swapped row address.

[0218] The semiconductor memory devices in the first memory module 820 and the second memory module 830 can enable different target word lines relative to the same access address to disperse the victim word lines that are interfered with by the access address.

[0219] Figure 24 This is a block diagram illustrating a mobile system including a memory module according to an exemplary embodiment.

[0220] Reference Figure 24 The mobile system 900 may include an application processor (AP) 910, a connectivity module 920, a memory module (MM) 950, a non-volatile memory device (NVM) 940, a user interface 930, and a power supply 970. The application processor 910 may include a memory controller (MCT) 911.

[0221] The application processor 910 can execute applications such as web browsers, games, and video players. The connectivity module 920 can perform wired or wireless communication with external devices.

[0222] Memory module 950 may store data processed by application processor 910 or operate as working memory. Memory module 950 may include a plurality of semiconductor memory devices (MDs) 951 to 95q (where q is a natural number greater than three) and control device 961. Each of the semiconductor memory devices 951 to 95q may include address switching circuitry that may swap a portion of bits of a row address to generate a swapped row address and apply the swapped row address to a row decoder. In some exemplary embodiments, control device 961 may include a plurality of address switching circuits corresponding to semiconductor memory devices 951 to 95q, which may swap a portion of bits of a row address to generate a swapped row address and apply the swapped row address to semiconductor memory devices 951 to 95q. The row decoder in each of the semiconductor memory devices 951 to 95q may enable a different target word line in response to a corresponding swapped row address.

[0223] Therefore, semiconductor memory devices 951 to 95q can enable different target word lines relative to the same access address to disperse victim word lines that are interfered with by the access address when the access address is accessed intensively.

[0224] The non-volatile memory device 940 can store a startup image for booting the mobile system 900. The user interface 30 may include at least one input device such as a keyboard or touch screen, and at least one output device such as a speaker or display device. The power supply 970 can supply operating voltage to the mobile system 900.

[0225] In various exemplary embodiments, the mobile system 900 and / or components of the mobile system 900 may be packaged in various forms.

[0226] The various exemplary embodiments described above can be applied to systems that use memory modules or stacked memory devices.

[0227] While various exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A memory module, comprising: A plurality of semiconductor memory devices mounted on a circuit board, each of the plurality of semiconductor memory devices comprising an array of memory cells for storing data; as well as A control device, mounted on the circuit board, is configured to receive commands and access addresses from external devices and to provide the commands and access addresses to the plurality of semiconductor memory devices. Each of the plurality of semiconductor memory devices is configured to: perform an address swapping operation in response to an energizing signal or a reset signal to randomly swap a portion of bits of the access address to generate a swapped address; and enable a corresponding target word line among multiple word lines in the memory cell array of each of the plurality of semiconductor memory devices based on the same access address, such that at least two of the plurality of semiconductor memory devices enable different target word lines.

2. The memory module according to claim 1, wherein: Each of the plurality of semiconductor memory devices includes an address switching circuit configured to perform the address switching operation on a row address in the access address.

3. The memory module according to claim 2, wherein, The address switching circuit includes: A random selection signal generator configured to randomly generate a random selection signal in response to the energizing signal or the reset signal; and An address exchanger is configured to swap a portion of the bits of the row address in response to the random selection signal to generate the swapped address, and to output the swapped address.

4. The memory module according to claim 3, in, The random selection signal generator includes a physically unclonable function configured to generate the random selection signal in response to the power-on signal or the reset signal.

5. The memory module according to claim 3, in, The random selection signal generator includes an antifuse circuit, wherein the random selection signal is randomly programmed, and the antifuse circuit is configured to output the random selection signal in response to the energizing signal or the reset signal. The random selection signals are programmed into the antifuse circuits of the plurality of semiconductor memory devices according to different sequences.

6. The memory module according to claim 3, in, The address switch includes a plurality of multiplexers configured to select bits that are different from the portion of bits of the row address in response to a combination of the random selection signal, in order to generate the switched address and output the switched address.

7. The memory module according to claim 1, wherein, Each of the plurality of semiconductor memory devices further includes: A row decoder, coupled to the memory cell array via the plurality of word lines, is configured to receive the swapped address; and An energizing signal generator is configured to generate the energizing signal in response to a power supply voltage being equal to or greater than a reference voltage.

8. The memory module according to claim 7, wherein, Each of the plurality of semiconductor memory devices further includes: An address register is configured to receive the access address and the power-on signal, and the address register includes an address switching circuit that performs the address switching operation.

9. The memory module according to claim 7, wherein, The line decoder is configured to enable one of the multiple word lines as the target word line in response to the swapped address.

10. The memory module according to claim 1, wherein, The plurality of semiconductor memory devices are configured to disperse victim word lines that are interfered with by the access address in response to the access address being accessed more frequently relative to a reference access number.

11. A memory module, comprising: A plurality of semiconductor memory devices mounted on a circuit board, each of the plurality of semiconductor memory devices comprising an array of memory cells for storing data; as well as A control device, mounted on the circuit board, is configured to: receive commands and access addresses from an external device; and, in response to a power-on signal or a reset signal, perform an address swapping operation to randomly swap a portion of the bits of the access address to generate a swapped address. And provide the command and the exchanged address to the plurality of semiconductor memory devices, The plurality of semiconductor memory devices are configured to enable corresponding target word lines among the multiple word lines in the memory cell array based on the same access address, such that at least two of the plurality of semiconductor memory devices enable different target word lines.

12. The memory module according to claim 11, wherein, The control device includes: A power-on signal generator configured to generate the power-on signal in response to a power supply voltage supplied to the control device being equal to or greater than a reference voltage; and Multiple address switching circuits, each corresponding to one of the multiple semiconductor memory devices, are configured to receive the power-on signal and perform the address switching operation on the row address in the access address.

13. The memory module according to claim 12, wherein, Each of the plurality of address switching circuits includes: A random selection signal generator configured to randomly generate a random selection signal in response to the energizing signal or the reset signal; and An address exchanger is configured to swap a portion of the bits of the row address in response to the random selection signal to produce a swapped address, and to output the swapped address.

14. The memory module according to claim 13, in, The random selection signal generator includes a physically unclonable function configured to generate the random selection signal in response to the power-on signal or the reset signal.

15. The memory module according to claim 13, in, The random selection signal generator includes an antifuse circuit in which the random selection signal is randomly programmed, and the antifuse circuit is configured to output the random selection signal in response to the energizing signal or the reset signal.

16. The memory module according to claim 13, in, The address switch includes a plurality of multiplexers configured to select bits that are different from the portion of bits of the row address in response to a combination of the random selection signal, in order to generate the switched address and output the switched address.

17. The memory module according to claim 13, wherein, Each of the plurality of semiconductor memory devices further includes a row decoder coupled to the memory cell array via the plurality of word lines, the row decoder being configured to receive the exchanged address, and The line decoder is configured to enable one of the multiple word lines as the target word line in response to the swapped address.

18. A stacked memory device, comprising: The buffer die is configured to receive commands and access addresses from external devices. Multiple memory dies are stacked on the buffer die, each of the multiple memory dies comprising an array of memory cells for storing data; as well as Multiple silicon through-holes extend through the multiple memory dies to connect to the buffer dies. Each of the plurality of memory dies is configured to: receive the access address through the plurality of silicon through-holes, perform an address swapping operation in response to a power-on signal or a reset signal to randomly swap a portion of the bits of the access address to generate a swapped address, and enable a corresponding target word line among the plurality of word lines in the memory cell array based on the same access address, such that at least two memory dies among the plurality of memory dies enable different target word lines.

19. The stacked memory device of claim 18, wherein, Each of the plurality of memory dies includes: An address switching circuit is configured to perform the address switching operation on the row address in the access address to generate the switched address; A row decoder, coupled to the memory cell array via the plurality of word lines, is configured to receive the swapped address; and An energizing signal generator is configured to generate the energizing signal in response to a power supply voltage being equal to or greater than a reference voltage.

20. The stacked memory device of claim 19, wherein, The address switching circuit includes: A random selection signal generator configured to randomly generate a random selection signal in response to the energizing signal or the reset signal; and An address exchanger is configured to swap a portion of the bits of the row address in response to the random selection signal to generate the swapped address, and to output the swapped address.

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