Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a dummy gate structure on the substrate; forming a sidewall layer on the sidewall of the dummy gate structure; forming an interlayer dielectric layer on the substrate to cover the sidewall of the sidewall layer; removing a portion of the height of the dummy gate structure and the sidewall layer, so that the interlayer dielectric layer and the remaining dummy gate structure and the sidewall layer form a groove; forming a protective layer covering the top surface of the sidewall layer on the sidewall of the groove; removing the remaining dummy gate structure, so that the protective layer, the sidewall layer and the substrate form a gate opening; forming a gate structure in the gate opening. The embodiments of the present invention are conducive to improving the performance of semiconductor structures.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control over the channel and can effectively suppress the short channel effect; and FinFETs have better compatibility with existing integrated circuit manufacturing than other devices.

[0004] In addition, in the field of semiconductor integrated circuit devices, as the size of transistors continues to shrink, high-K metal gate (HKMG) technology has gradually been widely used. At present, the process of forming HKMG structure transistors can be divided into the gate-first process and the gate-last process. Among them, the gate-last process is usually to form a metal gate after the drain / source region ion implantation operation and the subsequent high-temperature annealing step are completed on the silicon wafer, and generally before forming the metal gate, a dummy gate is first formed, and then the dummy gate is removed to form a metal gate. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to reducing the leakage current generated between the bottom of the gate structure and the source-drain doping layer when the device is working, thereby improving the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dummy gate structure on the substrate; forming a sidewall layer on the sidewall of the dummy gate structure; forming an interlayer dielectric layer covering the sidewall of the sidewall layer on the substrate; removing a portion of the height of the dummy gate structure and the sidewall layer so that the interlayer dielectric layer and the remaining dummy gate structure and the sidewall layer form a groove; forming a protective layer covering the top surface of the sidewall layer on the sidewall of the groove; removing the remaining dummy gate structure so that the protective layer, the sidewall layer and the substrate form a gate opening; and forming a gate structure in the gate opening.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; a sidewall structure layer covering the sidewall of the gate structure, including a sidewall layer and a protective layer located on the sidewall layer; an interlayer dielectric layer located on the substrate between the gate structures and covering the sidewall of the sidewall structure layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after the groove is formed, a protective layer covering the top surface of the sidewall layer is also formed on the sidewall of the groove; the protective layer can protect the top surface of the sidewall layer during the process of removing the remaining pseudo-gate structure, thereby helping to reduce the probability of damage to the top surface of the sidewall layer, and correspondingly helping to reduce the stress generated inside the sidewall layer. Moreover, the substrate usually also has a source-drain doping layer located on both sides of the pseudo-gate structure, and a gate oxide layer is usually formed between the pseudo-gate structure and the substrate. The probability of the sidewall layer being damaged and stress being generated inside the sidewall layer is relatively small, which helps to reduce the risk of the etching process causing damage to the source-drain doping layer and the gate oxide layer through the sidewall layer, and correspondingly helps to reduce the leakage current generated between the bottom of the gate structure and the source-drain doping layer when the device is working, and further helps to improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 5 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] There is a large leakage current in the semiconductor structure currently formed, resulting in poor performance of the device. The reasons for the poor performance of the device are now analyzed in combination with a method for forming a semiconductor structure.

[0013] refer to Figures 1 to 4 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 , providing a substrate 1; forming a dummy gate structure 2 on the substrate 1; forming a sidewall layer 3 on the sidewall of the dummy gate structure 2; forming a source-drain doped layer (not shown) in the substrate 1 on both sides of the dummy gate structure 2; forming an interlayer dielectric layer 4 covering the sidewall of the sidewall layer 3 on the substrate 1, and the interlayer dielectric layer 4 covers the source-drain doped layer.

[0015] refer to Figure 2 , remove part of the height of the dummy gate structure 2 and the spacer layer 3.

[0016] refer to Figure 3 , removing the remaining dummy gate structure 2 to form a gate opening 5 surrounded by the spacer layer 3 and the substrate 1 .

[0017] refer to Figure 4 , a gate structure 6 is formed in the gate opening 5 .

[0018] The inventors have found that a large leakage current exists in the semiconductor structure formed by the above-mentioned formation method. Specifically, a large leakage current exists between the bottom of the gate structure 6 and the source-drain doping layer.

[0019] Through further research by the inventors, it was found that the reason why there is a large leakage current in the semiconductor structure formed by the above-mentioned formation method is that after removing part of the height of the pseudo-gate structure 2 and the sidewall layer 3, in the semiconductor field, a dry etching process (for example, a plasma etching process) is usually used to remove the remaining pseudo-gate structure 2. In the process of removing the remaining pseudo-gate structure 2, the top surface of the sidewall layer 3 is exposed to the etching environment (for example, a plasma etching environment), which easily causes plasma to damage the top surface of the sidewall layer 3, and then easily generates a large stress inside the sidewall layer. Moreover, the pseudo-gate structure 2 usually also includes a gate oxide layer located on the substrate 1. The plasma is also easy to damage the source-drain doping layer and the gate oxide layer through the damage in the sidewall layer 3, thereby generating a plasma-damaged channel (Channel) in the sidewall layer 3, which causes a large leakage current generated between the bottom of the gate structure 6 and the source-drain doping layer when the device is working, resulting in poor performance of the formed semiconductor structure.

[0020] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a dummy gate structure on the substrate; forming a sidewall layer on the sidewall of the dummy gate structure; forming an interlayer dielectric layer covering the sidewall of the sidewall layer on the substrate; removing a portion of the height of the dummy gate structure and the sidewall layer so that the interlayer dielectric layer and the remaining dummy gate structure and the sidewall layer form a groove; forming a protective layer covering the top surface of the sidewall layer on the sidewall of the groove; removing the remaining dummy gate structure so that the protective layer, the sidewall layer and the substrate form a gate opening; and forming a gate structure in the gate opening.

[0021] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after the groove is formed, a protective layer covering the top surface of the sidewall layer is also formed on the sidewall of the groove; the protective layer can protect the top surface of the sidewall layer during the process of removing the remaining pseudo-gate structure, thereby helping to reduce the probability of damage to the top surface of the sidewall layer, and correspondingly helping to reduce the stress generated inside the sidewall layer. Moreover, the substrate usually also has a source-drain doping layer located on both sides of the pseudo-gate structure, and a gate oxide layer is usually formed between the pseudo-gate structure and the substrate. The probability of the sidewall layer being damaged and stress being generated inside the sidewall layer is relatively small, which helps to reduce the risk of the etching process causing damage to the source-drain doping layer and the gate oxide layer through the sidewall layer, and correspondingly helps to reduce the leakage current generated between the bottom of the gate structure and the source-drain doping layer when the device is working, and further helps to improve the performance of the semiconductor structure.

[0022] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figures 5 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0024] refer to Figure 5 , providing a substrate 100.

[0025] The substrate 100 provides a process platform for subsequent process steps.

[0026] In this embodiment, taking the semiconductor structure formed as a planar transistor as an example, the substrate 100 is a planar substrate, and the substrate 100 accordingly only includes a substrate. In other embodiments, when the semiconductor structure formed is a three-dimensional structure, for example, when a fin field effect transistor (FinFET) is formed, the substrate may accordingly include a substrate and a fin protruding from the substrate.

[0027] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0028] Continue to refer Figure 5 , a dummy gate structure 110 is formed on the substrate 100 .

[0029] The dummy gate structure 110 is used to occupy a space position for the subsequent formation of a gate structure. Specifically, the dummy gate structure 110 occupies a space position for the subsequent formation of a metal gate structure.

[0030] In this embodiment, the dummy gate structure 110 is a single-layer structure, and the dummy gate structure 110 only includes a dummy gate layer. In other embodiments, the dummy gate structure may also be a stacked-layer structure.

[0031] The material of the dummy gate structure 110 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride or amorphous carbon. In this embodiment, the material of the dummy gate structure 110 is polysilicon.

[0032] In this embodiment, in the step of forming the dummy gate structure 110 , a gate mask layer 120 is further formed on the top of the dummy gate structure 110 .

[0033] The gate mask layer 120 is used as an etching mask when forming the dummy gate structure 110. Therefore, the position, shape and number of the gate mask layer 120 correspond to the dummy gate structure 110. In this embodiment, the material of the gate mask layer 120 is silicon nitride.

[0034] It should be noted that, in this embodiment, before forming the dummy gate structure 110 , the method for forming the semiconductor structure further includes: forming a gate oxide layer 111 on the substrate 100 .

[0035] The gate oxide layer 111 can serve as a stop layer in the subsequent process of removing the dummy gate structure 110 , thereby reducing damage to the substrate 100 caused by the subsequent process of removing the dummy gate structure 110 .

[0036] The material of the gate oxide layer 111 includes silicon oxide or silicon oxynitride. In this embodiment, the material of the gate oxide layer 111 is silicon oxide.

[0037] Continue to refer Figure 5 , a spacer layer 115 is formed on the sidewall of the dummy gate structure 110 .

[0038] The spacer layer 115 is used to protect the sidewall of the dummy gate structure 110. The spacer layer 115 is also used to define the formation area of ​​the source and drain doping layers.

[0039] The sidewall layer 115 may be a single-layer or multi-layer structure, and the material of the sidewall layer 115 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the sidewall layer 115 is a single-layer structure, and the material of the sidewall layer 115 is silicon nitride.

[0040] In this embodiment, in the step of forming the spacer layer 115 , the spacer layer 115 also covers the sidewalls of the gate oxide layer 111 .

[0041] Subsequent steps further include: forming an interlayer dielectric layer 140 on the substrate 100 to cover the sidewalls of the spacer layer 115. In this embodiment, the method for forming the semiconductor structure further includes: forming a source-drain doping layer (not shown) in the substrate 100 on both sides of the dummy gate structure 110 and the spacer layer 115 after forming the spacer layer 115 and before forming the interlayer dielectric layer.

[0042] The source-drain doped layers are used to provide stress to the channel when the device is working, thereby improving the mobility of carriers.

[0043] In this embodiment, the source-drain doped layer is formed by epitaxy and doping process, and the source-drain doped layer includes a stress layer doped with ions. When forming a PMOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the stress layer are P-type ions; when forming an NMOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the stress layer are N-type ions.

[0044] Combined with reference Figures 5 to 8 An interlayer dielectric layer 140 (eg, Figure 7 shown).

[0045] The interlayer dielectric layer 140 is used to isolate adjacent devices.

[0046] In this embodiment, the top surface of the interlayer dielectric layer 140 is higher than the top surface of the dummy gate structure 110 , and a trench 20 is formed in the interlayer dielectric layer 140 to expose the top of the dummy gate structure 110 and the spacer layer 115 .

[0047] The trench 20 exposes the top of the dummy gate structure 110 and the spacer layer 115 , so as to facilitate the subsequent removal of a portion of the height of the dummy gate structure 110 and the spacer layer 115 .

[0048] In this embodiment, in the step of forming the interlayer dielectric layer 140 , the interlayer dielectric layer 140 covers the source-drain doped layer.

[0049] The material of the interlayer dielectric layer 140 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 140 is silicon oxide.

[0050] In this embodiment, in the step of forming the dummy gate structure 110, a gate mask layer 120 is also formed on the top of the dummy gate structure 110. The method for forming the semiconductor structure further includes: in the step of forming the interlayer dielectric layer 140, removing the gate mask layer 120.

[0051] By removing the gate mask layer 120 during the step of forming the interlayer dielectric layer 140 , the top of the dummy gate structure 110 is exposed, thereby preparing for the subsequent removal of a portion of the height of the dummy gate structure 110 , and facilitating the improvement of process integration and process compatibility.

[0052] The specific steps of forming the interlayer dielectric layer 140 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0053] like Figure 5 As shown, a first initial dielectric layer 125 is formed on the substrate 100 where the dummy gate structure 110 is exposed, and the first initial dielectric layer 125 covers the gate mask layer 120 and the spacer layer 115 .

[0054] The first initial dielectric layer 125 is used for subsequently forming an interlayer dielectric layer.

[0055] In this embodiment, the steps of forming the first initial dielectric layer 125 include: forming a dielectric material layer (not shown), the dielectric material layer covering the top of the pseudo gate structure 110; performing a second planarization treatment on the dielectric material layer; after the second planarization treatment, etching back a portion of the thickness of the dielectric material layer to form the first initial dielectric layer 125.

[0056] In this embodiment, the dielectric material layer is formed by a deposition process. Specifically, the deposition process may be a flow chemical vapor deposition (FCVD) process. The flow chemical vapor deposition process has good filling ability and is suitable for filling openings with high aspect ratios, which is beneficial to reducing the probability of forming defects such as voids in the dielectric material layer, and correspondingly is beneficial to improving the film quality of the subsequent interlayer dielectric layer.

[0057] In this embodiment, the second planarization process is performed by using a chemical mechanical polishing process.

[0058] In this embodiment, a dry etching process is used to etch back a portion of the dielectric material layer. The dry etching process has high etching accuracy and etching efficiency, which is conducive to accurately controlling the etching thickness of the dielectric material layer. Specifically, the dry etching process can be an inductively coupled plasma (ICP) etching process.

[0059] In this embodiment, in the process of etching back a dielectric material layer of a part of the thickness, the etching machine uses an electrostatic adsorption plate with a temperature control system Hydra. The Hydra system can compensate for the thickness difference of the film layer generated in the previous process, so that the top surface height consistency of the dielectric material layer after etching is better, which is conducive to improving the height consistency and top surface flatness of the first initial dielectric layer 125, and correspondingly helps to improve the top surface height consistency of the subsequent interlayer dielectric layer.

[0060] like Figure 6 As shown, a portion of the thickness of the first initial dielectric layer 125 is etched back to form a second initial dielectric layer 130 , and the second initial dielectric layer 130 exposes the top and a portion of the sidewall of the gate mask layer 120 .

[0061] The second initial dielectric layer 130 exposes the top and a portion of the sidewall of the gate mask layer 120 , so as to prepare for the subsequent step of removing the gate mask layer 120 .

[0062] In this embodiment, a Certas etching process is used to etch back a portion of the thickness of the first initial dielectric layer 125. The Certas etching process has good etching uniformity, is conducive to achieving a higher etching selectivity, is conducive to reducing the height difference of the top surface of the second initial dielectric layer 130, and reduces damage to other film layers, which is conducive to improving the etching accuracy.

[0063] like Figure 7 As shown, the gate mask layer 120 is removed to expose the top of the dummy gate structure 110 , and an initial trench 10 is formed in the second initial dielectric layer 130 .

[0064] The gate mask layer 120 is removed to expose the top of the dummy gate structure 110 , providing a process basis for subsequently removing a portion of the height of the dummy gate structure 110 .

[0065] In this embodiment, a plasma etching process is used to remove the gate mask layer 120. By using a plasma etching process to remove the gate mask layer 120, it is beneficial to improve the etching accuracy of removing the gate mask layer 120, reduce damage to other film layers, and also help improve etching efficiency.

[0066] like Figure 8As shown, the second initial dielectric layer 130 on the sidewall of the initial trench 10 is thinned to expose the top of the spacer layer 115 to form the trench 20 , and the remaining second initial dielectric layer 130 serves as the interlayer dielectric layer 140 .

[0067] By exposing the top of the spacer layer 115 , preparation is made for the subsequent removal of a portion of the height of the dummy gate structure 110 and the spacer layer 115 .

[0068] In this embodiment, an isotropic dry etching process is used to thin the second initial dielectric layer 130 on the side wall of the initial trench 10. The isotropic dry etching process has the characteristic of isotropic etching, so that the second initial dielectric layer 130 on the side wall of the initial trench 10 can be laterally etched along a direction perpendicular to the side wall of the initial trench 10 to achieve thinning of the second initial dielectric layer 130 on the side wall of the initial trench 10, and the dry etching process is conducive to achieving a large etching selectivity, so as to accurately control the thinning thickness of the second initial dielectric layer 130 on the side wall of the initial trench 10.

[0069] refer to Fig. 9 , partially removing the dummy gate structure 110 and the spacer layer 115 , so that the interlayer dielectric layer 140 and the remaining dummy gate structure 110 and the spacer layer 115 form a groove 30 .

[0070] By removing part of the height of the dummy gate structure 110 and the sidewall layer 115, the groove 20 forms the recess 30, thereby increasing the depth of the groove 20. That is, the depth of the recess 30 is greater, thereby reducing the height of the dummy gate structure 110, which is beneficial to reducing the difficulty of subsequent removal of the dummy gate structure 110.

[0071] Moreover, in this embodiment, a portion of the height of the dummy gate structure 110 and the spacer layer 115 is removed, and the remaining dummy gate structure 110 and the spacer layer 115 define the height of the subsequent gate structure.

[0072] In addition, the groove 30 is formed by removing a portion of the height of the dummy gate structure 110 and the spacer layer 115 , so that a protection layer covering the top surface of the spacer layer 115 can be formed on the sidewall of the groove 30 later.

[0073] As an example, the steps of removing a portion of the height of the dummy gate structure 110 and the spacer layer 115 in this embodiment are described in detail below with reference to the accompanying drawings.

[0074] like Fig. 9 As shown, a portion of the height of the dummy gate structure 110 is removed, so that the spacer layer 115 and the remaining dummy gate structure 110 form an initial groove (not shown).

[0075] The dummy gate structure 110 and the spacer layer 115 are made of different materials. By first removing a portion of the thickness of the dummy gate structure 110 , the sidewall of the initial groove is exposed to the spacer layer 115 , preparing for the subsequent removal of a portion of the height of the spacer layer 115 .

[0076] As an example, in this embodiment, the removal thickness of the dummy gate structure 110 is to

[0077] In this embodiment, a dry etching process is used to remove a portion of the thickness of the dummy gate structure 110. The dry etching process has high etching profile controllability and etching accuracy, which is conducive to accurately controlling the removal thickness of the dummy gate structure 110.

[0078] Specifically, in this embodiment, a chemical downstream etch (CDE) process can be used to remove a portion of the thickness of the pseudo gate structure 110. The chemical downstream etching process uses a downstream plasma source system to generate plasma in a reaction chamber, and then filters out ions that are likely to cause damage to the wafer surface, retaining the active groups and then transmitting them to the wafer surface. The wafer and the plasma that may cause damage are separated, which is beneficial to improve the etching selectivity and etching accuracy while reducing damage to the wafer.

[0079] By selecting a chemical downstream etching process, it is advantageous to further precisely control the removal thickness of the dummy gate structure 110 and improve the etching selectivity to reduce damage to other film layer structures.

[0080] In this embodiment, the material of the dummy gate structure 110 is polysilicon, and the etching gas used in the chemical downstream etching process may include NF3 and H2.

[0081] like Fig. 9 As shown, the spacer layer 115 on the sidewall of the initial groove is removed, so that the interlayer dielectric layer 140 , the remaining top of the spacer layer 115 and the remaining top of the dummy gate structure 110 form the groove 30 .

[0082] Removing the sidewall layer 115 from the sidewall of the initial groove, on the one hand, reserves space for the protective layer subsequently formed on the sidewall of the groove 30 and covering the top surface of the sidewall layer 115; on the other hand, by removing the sidewall layer 115 from the sidewall of the initial groove, the bottom of the groove 30 is made to be a flat and highly consistent surface, which is beneficial to reducing the difficulty of the subsequent process of forming the protective layer and improving the film formation quality of the protective layer, which is correspondingly beneficial to improving the protective effect of the protective layer on the top surface of the sidewall layer 115.

[0083] In this embodiment, an isotropic dry etching process is used to remove the sidewall layer 115 of the sidewall of the initial groove. The isotropic dry etching process can lateral-etch the sidewall layer 115 along a direction perpendicular to the sidewall of the initial groove, thereby facilitating an increase in the etching rate of the sidewall layer 115 for removing the sidewall of the initial groove, and the use of the dry etching process is conducive to achieving a larger etching selectivity, thereby improving the etching accuracy and preventing damage to other film layers.

[0084] In this embodiment, the material of the sidewall layer 115 is silicon nitride, and the etching gas used in the dry etching process includes CH 3 F and O 2 .

[0085] In this embodiment, a dry etching process is used to remove a portion of the thickness of the dummy gate structure 110. The dry etching process has high controllability of the etching profile and etching accuracy, thereby improving the depth uniformity of the initial groove. Accordingly, in the step of removing the sidewall layer 115 of the sidewall of the initial groove, the removal height uniformity of the sidewall layer 115 is also high, which is conducive to improving the height uniformity of the remaining sidewall layer 115.

[0086] refer to Figures 10 to 12 A protection layer 150 is formed on the sidewall of the groove 30 to cover the top surface of the spacer layer 115 .

[0087] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the groove 30, a protective layer 150 covering the top surface of the sidewall layer 115 is formed on the sidewall of the groove 30; the protective layer 150 can protect the top surface of the sidewall layer 115 during the process of removing the remaining pseudo gate structure 110, thereby helping to reduce the probability of damage to the top surface of the sidewall layer 115, and correspondingly helping to reduce the stress generated inside the sidewall layer 115. Moreover, the substrate 100 also has source and drain doping layers located on both sides of the pseudo gate structure 110, and a gate oxide layer 111 is usually formed between the pseudo gate structure 110 and the substrate 100. The probability of the sidewall layer 115 being damaged and stress being generated inside the sidewall layer 115 is relatively small, which helps to reduce the risk of the etching process causing damage to the source and drain doping layers and the gate oxide layer 111 through the sidewall layer 115, and correspondingly helps to reduce the leakage current generated between the bottom of the gate structure and the source and drain doping layers when the device is working, thereby helping to improve the performance of the semiconductor structure.

[0088] In this embodiment, the steps of forming the protective layer 150 include:

[0089] like Fig.10 As shown, a liner layer 145 is formed to conformally cover the bottom and sidewalls of the groove 30 and the top surface of the interlayer dielectric layer 140 .

[0090] The material of the liner layer 145 includes silicon nitride or silicon carbide.

[0091] The liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 is subsequently removed, and the liner layer 145 located at the sidewall of the groove 30 is used as the protective layer, so the material of the protective layer includes silicon nitride or silicon carbide. Silicon nitride or silicon carbide has a high etching selectivity with polysilicon, which is conducive to improving the etching selectivity ratio of the process of removing the remaining dummy gate structure 110 to the dummy gate structure 110 and the protective layer, and correspondingly helps to improve the protective effect of the protective layer on the sidewall layer 115.

[0092] Specifically, in this embodiment, the material of the liner layer 145 is silicon nitride.

[0093] In this embodiment, the liner layer 145 is formed by an atomic layer deposition (ALD) process. The atomic layer deposition process is a self-limiting reaction process based on the atomic layer deposition process. The deposited thin film can reach the thickness of a single layer of atoms. Because the atomic layer deposition process can accurately deposit one atomic layer in each cycle, the deposition process can be controlled at the nanoscale, which is conducive to accurately controlling the thickness of the liner layer 145 and improving the thickness consistency of the liner layer 145. Moreover, the step coverage ability of the atomic layer deposition process is strong, which is conducive to improving the conformal ability of the liner layer 145 at the bottom and sidewall of the groove 30, thereby improving the morphology quality of the liner layer 145. In addition, the thin film prepared by the atomic layer deposition process also has the characteristics of good bonding strength, high density, good composition uniformity, etc. In summary, the formation of the liner layer 145 by the atomic layer deposition process is conducive to improving the quality of the subsequent formation of the protective layer, and correspondingly conducive to improving the protective effect of the protective layer on the top surface of the sidewall layer 115.

[0094] like Figure 11 to Figure 12 As shown, the liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 is removed, and the liner layer 145 located at the sidewall of the groove 30 is used as the protection layer 150 .

[0095] As an example, in this embodiment, the step of removing the liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 includes performing one or more modification removal processes, and the modification removal process includes: Fig.11 As shown, the liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 is modified to reduce the etching resistance of the liner layer 145; Fig.12 As shown, the modified liner layer 145 is removed.

[0096] In this embodiment, the liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 is removed by performing one or more modification and removal treatments. By first performing the modification treatment, it is suitable to reduce the etching resistance of the liner layer 145, and then removing the modified liner layer 145, which is beneficial to improve the etching selectivity ratio of the modified liner layer 145 and the unmodified liner layer 145, thereby helping to reduce the process difficulty of removing the liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140, and the process of removing the liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 has little effect on the liner layer 145 located at the side wall of the groove 30, which is beneficial to ensure that the protective layer 150 has a high formation quality. The corresponding protective layer 150 can protect the top surface of the sidewall layer 115 during the subsequent removal of the remaining pseudo gate structure 110.

[0097] Moreover, compared with the conventional dry etching process for removing the liner layer 145 at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140, in the present embodiment, the liner layer 145 at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 is removed by performing one or more modified removal processes, which is beneficial to reducing the difference in removal rate of the liner layer 145 at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 in areas with different pattern densities (for example, pattern-dense areas and pattern-sparse areas), and is also beneficial to reducing the probability of causing mis-etching to other film layers (for example, the interlayer dielectric layer 140 or the sidewall layer 115).

[0098] As an example, in this embodiment, the step of performing the modification treatment includes: performing plasma treatment on the liner layer 145 located at the bottom of the groove 30 and the top surface of the interlayer dielectric layer 140 .

[0099] As an example, in this embodiment, the material of the liner layer 145 includes silicon nitride, and the ions used in the plasma treatment include hydrogen ions or helium ions.

[0100] By using hydrogen ions to perform plasma treatment on the pad layer 145, Si-H bonds and NH bonds can be introduced into the pad layer 145. These two chemical bonds can improve the process reaction efficiency and rate of the pad layer 145 after subsequent removal and modification, and can also increase the probability of forming hydrogen-containing volatile compounds, thereby reducing the etching resistance of the pad layer 145.

[0101] By performing plasma treatment on the liner layer 145 using helium ions, Si—N bonds in the material of the liner layer 145 can be reduced, thereby reducing the etching resistance of the liner layer 145 .

[0102] In other embodiments, the material of the liner layer includes silicon carbide, and the ions used in the plasma treatment include nitrogen ions. By using nitrogen ions to perform plasma treatment on the silicon carbide material, -N bonds can be introduced into the silicon carbide material, so that the silicon carbide material is converted into a material similar to silicon carbonitride, which is easier to remove than silicon nitride, and the etching resistance of the liner layer can be reduced accordingly.

[0103] In this embodiment, the parameters of the plasma treatment include: a bias voltage of 10V to 500V.

[0104] The bias voltage is used to control the directionality of plasma. By setting the bias voltage of the plasma processing within a range of 10V to 500V, the anisotropy of the plasma is increased, thereby reducing the probability of the plasma contacting the liner layer 145 located on the sidewall of the groove 30 .

[0105] In this embodiment, the process of removing the modified liner layer 145 includes a wet etching process, and the etching solution used in the wet etching process is a hydrofluoric acid solution.

[0106] In other embodiments, the process of removing the modified liner layer includes a dry etching process, and the etching gas of the dry etching process includes: CH2F2 and C4F6.

[0107] The modification and removal treatment time should not be too short, otherwise the modification and removal treatment is used to reduce the etching resistance of the liner layer 145 and improve the removal efficiency of the modified liner layer 145. The modification and removal treatment time should not be too long, otherwise it is easy to waste working hours and thus easy to reduce production capacity. For this reason, in this embodiment, the modification and removal treatment time is 5 seconds to 30 seconds.

[0108] In actual processes, one or more modification removal processes can be performed according to process requirements. For example, when multiple modification removal processes are performed, it is beneficial to further reduce the difference in removal rate of the liner layer at the bottom of the groove and the top surface of the interlayer dielectric layer in different pattern density areas.

[0109] refer to Fig.13 , the remaining dummy gate structure 110 is removed, so that the protection layer 150 , the spacer layer 115 and the substrate 100 form a gate opening 40 .

[0110] The gate opening 40 is used to provide a space for forming a gate structure.

[0111] The embodiment of the present invention also forms a protective layer 150 covering the top surface of the sidewall layer 115 on the sidewall of the groove 30. Therefore, in the process of removing the remaining dummy gate structure 110, the protective layer 150 can protect the top surface of the sidewall layer 115, which is beneficial to reduce the probability of the process of removing the remaining dummy gate structure 110 causing damage to the top surface of the sidewall layer 115, which is correspondingly beneficial to reducing the stress generated inside the sidewall layer 115, and it is also beneficial to reduce the risk of the etching process causing damage to the source-drain doping layer and the gate oxide layer 111 through the sidewall layer 115, which is correspondingly beneficial to reducing the leakage current generated between the bottom of the gate structure and the source-drain doping layer when the device is working, and further beneficial to improving the performance of the semiconductor structure.

[0112] In this embodiment, the bottom of the gate opening 40 exposes the gate oxide layer 111 , and therefore, the gate opening 40 is surrounded by the gate oxide layer 111 , the protection layer 150 , and the spacer layer 11 .

[0113] In this embodiment, the process of removing the remaining dummy gate structure 110 includes a wet etching process. Compared with a dry etching process (e.g., a plasma etching process), no plasma is formed in the wet etching process environment, which is beneficial to further reduce the probability of the process of removing the remaining dummy gate structure 110 causing damage to the top surface of the sidewall layer 115. Specifically, the etching solution used in the wet etching process includes a TMAH solution or an Ammonia solution.

[0114] refer to Fig.14 , a gate structure 160 is formed in the gate opening 40 .

[0115] When the device is operating, the gate structure 160 is used to control the opening or closing of the conductive channel.

[0116] In this embodiment, the gate structure 160 is a metal gate structure, and includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the gate opening 40.

[0117] Specifically, the material of the high-k gate dielectric layer is a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer can also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0118] The work function layer is used to adjust the work function of the device, thereby adjusting the threshold voltage of the formed transistor. When forming a PMOS, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. When forming an NMOS, the work function layer is an N-type work function layer, and the material of the P-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0119] The gate electrode layer is used as an electrode to electrically connect the gate structure 160 to other interconnect structures or external circuits. In this embodiment, the material of the gate electrode layer is W. In other embodiments, the material of the gate electrode layer can also be Al, Cu, Ag, Au, Pt, Ni or Ti.

[0120] In this embodiment, the step of forming the gate structure 160 includes: forming a gate material layer filling the gate opening 40 on the interlayer dielectric layer 140; removing the gate material layer higher than the interlayer dielectric layer 140, and retaining the gate material layer located in the gate opening 40 as the gate structure 160.

[0121] In this embodiment, a planarization process is used to remove the gate material layer higher than the interlayer dielectric layer 140. Specifically, the planarization process includes a chemical mechanical polishing process.

[0122] In this embodiment, the sidewall layer 115 and the protection layer 150 located on the top surface of the sidewall layer 115 constitute a sidewall structure layer 170 .

[0123] Combined with reference Fig.15 In this embodiment, after forming the gate structure 160 , the method for forming the semiconductor structure further includes: removing the protection layer 150 , and the interlayer dielectric layer 140 higher than the spacer layer 115 and the gate structure 160 .

[0124] In this embodiment, the protective layer 150, the interlayer dielectric layer 140 higher than the spacer layer 115, and the gate structure 160 are removed. That is, the required height of the gate structure 160 is defined by the height of the spacer layer 115. Compared with the solution of defining the height of the gate structure 160 by the top surface height of the interlayer dielectric layer 140, the interlayer dielectric layer 140 in different pattern density regions occupies different areas. In the process of forming the interlayer dielectric layer 140 and the gate structure 160, the removal rate of the interlayer dielectric layer 140 in different pattern density regions is different, resulting in poor consistency of the top surface height of the interlayer dielectric layer 140, making it difficult to control the height of the gate structure 160 by controlling the top surface height of the interlayer dielectric layer 140. In this embodiment, a part of the height of the spacer layer 115 is first removed, and the remaining The sidewall layer 115 is used to define the required height of the gate structure 160. From the above analysis, it can be seen that the height uniformity of the remaining sidewall layer 115 is good, which is correspondingly beneficial to improving the height uniformity of the gate structure 160, and the difference in the width of the sidewall layer 115 in areas with different pattern densities is small. In the process of removing part of the height of the sidewall layer 115, the difference in the removal rate of the sidewall layer 115 in areas with different pattern densities is small, so that the height consistency of the remaining sidewall layer 115 is high, which is correspondingly beneficial to ensure that the gate structure 160 has a high height consistency.

[0125] In this embodiment, the steps of removing the protective layer 150, the interlayer dielectric layer 140 higher than the spacer layer 115, and the gate structure 160 include: removing the protective layer 150; after removing the protective layer 150, removing the interlayer dielectric layer 140 and the gate structure 160 higher than the spacer layer 115.

[0126] In this embodiment, a dry etching process is used to remove the protective layer. Specifically, the protective layer 150 can be removed by using an isotropic dry etching process.

[0127] In this embodiment, the step of removing the interlayer dielectric layer 140 and the gate structure 160 that are higher than the spacer layer 115 includes: taking the top surface of the spacer layer 115 as the stop position, and performing a planarization process on the interlayer dielectric layer 140 and the gate structure 160 .

[0128] In this embodiment, the process of removing the interlayer dielectric layer 140 and the gate structure 160 that are higher than the spacer layer 115 includes a chemical mechanical polishing process.

[0129] Accordingly, the present invention also provides a semiconductor structure. Fig.14 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0130] The semiconductor structure includes: a substrate 100; a gate structure 110, located on the substrate 100; a sidewall structure layer 170, covering the sidewall of the gate structure 110, including a sidewall layer 115 and a protective layer 150 located on the sidewall layer 115; an interlayer dielectric layer 140, located on the substrate 100 between the gate structures 110 and covering the sidewall of the sidewall structure layer 170.

[0131] The sidewall structure layer 170 in the semiconductor structure provided by the embodiment of the present invention includes a sidewall layer 115 and a protective layer 150 located on the sidewall layer 115; forming a gate structure 160 includes removing a dummy gate structure to form a gate opening, and forming the gate structure 160 in the gate opening. The protective layer 150 can protect the top surface of the sidewall layer 115 during the process of removing the dummy gate structure, thereby reducing the probability of causing damage to the top surface of the sidewall layer 115, and correspondingly reducing the stress generated inside the sidewall layer 115. In addition, the semiconductor structure The conductor structure usually also includes a source-drain doped layer formed in the substrate 100 on both sides of the gate structure 160, and a gate oxide layer 111 located between the gate structure 160 and the substrate 100. The probability of the sidewall layer 115 being damaged and stress being generated inside the sidewall layer 115 is small, which is beneficial to reducing the risk of the etching process causing damage to the source-drain doped layer and the gate oxide layer 111 through the sidewall layer 115, and correspondingly beneficial to reducing the leakage current generated between the bottom of the gate structure 160 and the source-drain doped layer when the device is working, thereby helping to improve the performance of the semiconductor structure.

[0132] The substrate 100 provides a process platform for the process.

[0133] In this embodiment, taking the semiconductor structure formed as a planar transistor as an example, the substrate 100 is a planar substrate, and the substrate 100 accordingly only includes a substrate. In other embodiments, when the semiconductor structure formed is a three-dimensional structure, for example, when a fin field effect transistor (FinFET) is formed, the substrate may accordingly include a substrate and a fin protruding from the substrate.

[0134] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0135] When the device is operating, the gate structure 160 is used to control the opening or closing of the conductive channel.

[0136] In this embodiment, the gate structure 160 is a metal gate structure, and includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the gate opening 40.

[0137] Specifically, the material of the high-k gate dielectric layer is a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer can also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0138] The work function layer is used to adjust the work function of the device, thereby adjusting the threshold voltage of the formed transistor. When forming a PMOS, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. When forming an NMOS, the work function layer is an N-type work function layer, and the material of the P-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0139] The gate electrode layer is used as an electrode to electrically connect the gate structure 160 to other interconnect structures or external circuits. In this embodiment, the material of the gate electrode layer is W. In other embodiments, the material of the gate electrode layer can also be Al, Cu, Ag, Au, Pt, Ni or Ti.

[0140] In this embodiment, the semiconductor structure further includes: a gate oxide layer 111 located between the gate structure 160 and the substrate 100 .

[0141] The gate oxide layer 111 can serve as a stop layer in the process of removing the dummy gate structure to form a gate opening, thereby reducing damage to the substrate 100. The gate oxide layer 111 and the high-k gate dielectric layer also realize electrical isolation between the work function layer or gate electrode layer and the substrate 100.

[0142] The material of the gate oxide layer 111 includes silicon oxide or silicon oxynitride. In this embodiment, the material of the gate oxide layer 111 is silicon oxide.

[0143] The spacer layer 115 is used to protect the sidewall of the dummy gate structure 110. The spacer layer 115 is also used to define the formation area of ​​the source and drain doping layers.

[0144] In this embodiment, the protection layer 150 , the interlayer dielectric layer 140 and the gate structure 160 that are higher than the spacer layer 115 will be removed later. Therefore, the spacer layer 115 is also used to define the height of the final gate structure 160 .

[0145] The spacer layer 115 may be a single-layer or multi-layer structure, and the material of the spacer layer 115 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0146] In this embodiment, the spacer layer 115 is a single-layer structure, and the material of the spacer layer 115 is silicon nitride.

[0147] In this embodiment, the spacer layer 115 also covers the sidewalls of the gate oxide layer 111 .

[0148] The protection layer 150 is used to protect the top surface of the sidewall layer 115 .

[0149] The material of the protective layer 150 includes silicon nitride or silicon carbide. The material of the dummy gate structure is usually polysilicon, and silicon nitride or silicon carbide has a high etching selectivity with polysilicon, which is beneficial to improve the etching selectivity ratio of the process of removing the dummy gate structure to the dummy gate structure and the protective layer 150, and further helps to improve the protective effect of the protective layer 150 on the top surface of the sidewall layer 115.

[0150] In this embodiment, the semiconductor structure further includes: source-drain doping layers (not shown) located in the substrate 100 on both sides of the gate structure 160. Specifically, the source-drain doping layers are located in the substrate 100 on both sides of the gate structure 150 and the spacer structure layer 170.

[0151] The source-drain doped layers are used to provide stress to the channel when the device is working, thereby improving the mobility of carriers.

[0152] In this embodiment, the source-drain doped layer is formed by epitaxy and doping process, and the source-drain doped layer includes a stress layer doped with ions. When forming a PMOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the stress layer are P-type ions; when forming an NMOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the stress layer are N-type ions.

[0153] The interlayer dielectric layer 140 is used to isolate adjacent devices.

[0154] In this embodiment, the interlayer dielectric layer 140 covers the source-drain doping layer.

[0155] The material of the interlayer dielectric layer 140 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 140 is silicon oxide.

[0156] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0157] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dummy gate structure on the substrate; forming a spacer layer on the sidewall of the dummy gate structure; forming an interlayer dielectric layer on the substrate to cover the sidewalls of the spacer layer; Removing a portion of the height of the dummy gate structure and the spacer layer, so that the interlayer dielectric layer and the remaining dummy gate structure and the spacer layer form a groove; A protective layer covering the top surface of the sidewall layer is formed on the sidewall of the groove, and the side surface of the protective layer is flush with the side surface of the sidewall layer. The step of forming the protective layer includes: forming a liner layer conformally covering the bottom and sidewall of the groove and the top surface of the interlayer dielectric layer; removing the liner layer located at the bottom of the groove and the top surface of the interlayer dielectric layer, and the liner layer located at the sidewall of the groove and flush with the side surface of the sidewall layer is used as the protective layer; the step of removing the liner layer located at the bottom of the groove and the top surface of the interlayer dielectric layer includes performing one or more modification and removal treatments on the liner layer located at the bottom of the groove and the top surface of the interlayer dielectric layer, and the protective layer covers the sidewall of the interlayer dielectric layer; Removing the remaining dummy gate structure, so that the protection layer, the sidewall layer and the substrate form a gate opening; forming a gate structure in the gate opening; Performing a modification treatment on the liner layer located at the bottom of the groove and the top surface of the interlayer dielectric layer, which is suitable for reducing the etching resistance of the liner layer; removing the modified liner layer; The step of performing the modification treatment includes: performing plasma treatment on the liner layer located at the bottom of the groove and the top surface of the interlayer dielectric layer; The material of the liner layer includes silicon carbide, and the ions used in the plasma treatment include nitrogen ions; the process of removing the modified liner layer includes a dry etching process, and the etching gas of the dry etching process includes CH2F2 and C4F6.

2. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the plasma treatment include: a bias voltage of 10V to 500V.

3. The method for forming a semiconductor structure according to claim 1, wherein: The modification and removal treatment lasts for 5 seconds to 30 seconds.

4. The method for forming a semiconductor structure according to claim 1, wherein: The sidewall layer is a single-layer or multi-layer structure, and the material of the sidewall layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

5. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing a portion of the height of the dummy gate structure and the spacer layer comprises: removing a portion of the height of the dummy gate structure so that the spacer layer and the remaining dummy gate structure form an initial groove; The sidewall spacer layer of the sidewall of the initial groove is removed, so that the interlayer dielectric layer, the remaining top of the sidewall spacer layer and the remaining top of the dummy gate structure form the groove.

6. The method for forming a semiconductor structure according to claim 5, wherein: An isotropic dry etching process is adopted to remove the sidewall layer of the sidewall of the initial groove.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the remaining dummy gate structure includes a wet etching process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the semiconductor structure further comprises: after forming the spacer layer and before forming the interlayer dielectric layer, forming a source-drain doping layer in the substrate on both sides of the dummy gate structure and the spacer layer; In the step of forming the interlayer dielectric layer, the interlayer dielectric layer covers the source-drain doped layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: After forming the gate structure, the method for forming the semiconductor structure further includes: removing the protection layer, the interlayer dielectric layer higher than the spacer layer, and the gate structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: The protective layer is removed by using a dry etching process.

11. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing the interlayer dielectric layer and the gate structure higher than the spacer layer includes a chemical mechanical polishing process.

12. A semiconductor structure, characterized in that: A method for forming a semiconductor structure according to any one of claims 1 to 11, comprising: substrate; A gate structure, located on the substrate; A sidewall structure layer, covering the sidewall of the gate structure, comprising a sidewall layer and a protective layer located on the sidewall layer, wherein the protective layer covers the top surface of the sidewall layer, the protective layer covers the sidewall of the interlayer dielectric layer, and the side surface of the protective layer is flush with the side surface of the sidewall layer; An interlayer dielectric layer is located on the substrate between the gate structures and covers the sidewalls of the spacer structure layer.

13. The semiconductor structure according to claim 12, wherein: The material of the protection layer includes silicon nitride or silicon carbide.

14. The semiconductor structure according to claim 12, wherein: The semiconductor structure further includes: source-drain doping layers located in the substrate on both sides of the gate structure; The interlayer dielectric layer covers the source-drain doping layer.

15. The semiconductor structure according to claim 12, wherein: The sidewall layer is a single-layer or multi-layer structure, and the material of the sidewall layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

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