Power amplifier module comprising a top-side cooling interface and method of manufacturing the same

Abstract

A power amplifier module (PAM) having a top-side cooling interface is disclosed, as well as a method for manufacturing such a PAM. In embodiments, the method includes attaching an RF power die to a die support surface of a module substrate. The RF power die is attached to the module substrate in an inverted orientation such that a front side of the RF power die faces the module substrate. A front side input / output interface of the RF power die is electrically coupled to a corresponding substrate interconnect feature of the module substrate when the RF power die is attached to the module substrate. The method additionally includes providing a primary heat extraction path that extends from a transistor channel of the RF power die to a top-side cooling interface of the PAM in a direction opposite the module substrate.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to microelectronics, and more specifically, to power amplifier modules and methods for manufacturing power amplifier modules having a top-side cooling interface. Background Technology

[0002] A power amplifier module (PAM) typically includes a module substrate and at least one radio frequency (RF) power die mounted to the module substrate in a non-inverted orientation. The module substrate can be, for example, a printed circuit board (PCB), a ceramic substrate, or another substrate with conductive wiring features that electrically interconnects with the RF power die. A given PAM can contain a single RF power die or multiple RF power dies, along with any number of other microelectronic components, such as discretely placed capacitors and resistors. One or more RF power dies within a PAM can easily generate excess heat during operation, especially when operating at higher RF frequencies (e.g., frequencies approaching or exceeding 3 GHz) or when manufactured using power-dense die technologies such as layered gallium nitride die structures. Without adequate heat dissipation, such excess heat can accumulate within the PAM and limit the performance of the RF power dies contained therein. Traditionally, such excess heat is dissipated from the region adjacent to the RF power die, for example, by providing a thermal path extending from the rear side of the given RF power die through the module substrate and to a component-level heatsink outside the PAM using a bottom-side heat dissipation structure. However, this bottom-side heat dissipation structure is usually limited in its heat dissipation capacity and often has various drawbacks, such as high manufacturing costs and overly complex wiring schemes. Summary of the Invention

[0003] According to one aspect of the present invention, a method for manufacturing a power amplifier module (PAM) is provided, the method comprising:

[0004] A radio frequency (RF) power die is obtained, the RF power die including a front side, a rear side, and a front input / output (I / O) interface on the front side of the RF power die;

[0005] The RF power die is attached to the die support surface of the module substrate, and the RF power die is attached to the module substrate in an inverted orientation such that the front side of the RF power die faces the module substrate.

[0006] When the RF power die is attached to the module substrate, the front I / O interface of the RF power die is electrically coupled to the corresponding interconnect features of the module substrate; and

[0007] A primary heat extraction path is provided, which extends from the rear side of the RF power die to the top cooling interface of the PAM in a direction opposite to the module substrate.

[0008] According to one or more embodiments, it further includes bonding a top-side thermal extension to the rear side of the RF power die, the main heat extraction path extending through the top-side thermal extension.

[0009] According to one or more embodiments, the top-side thermal extension includes a prefabricated body having a thermal conductivity of more than 100 watts per meter Kelvin; and wherein bonding includes bonding the top-side thermal extension to the rear side of the RF power die using a thermally conductive bonding material.

[0010] According to one or more embodiments, it further includes a molded module body that encapsulates the RF power die, surrounds the top thermal extension, and contacts the module substrate.

[0011] According to one or more embodiments, the molded module body has an upper surface opposite to the module substrate; and wherein the method further includes forming the molded module body such that the top-side thermal extension extends from a position adjacent to the rear side of the RF power die to terminate at a position substantially coplanar with the upper surface of the molded module body.

[0012] According to one or more embodiments, forming includes: initially forming the molding module body to have a thickness sufficient to cover the upper surface of the top-side thermal extension; and after initially forming the molding module body, back-side grinding the molding module body to expose the upper surface of the top-side thermal extension and define the top-side thermal extension.

[0013] According to one or more embodiments, the RF power die includes at least one transistor having transistor contacts; and the method further includes electrically coupling the transistor contacts to the top thermal extension.

[0014] According to one or more embodiments, the at least one transistor includes a field-effect transistor having a source contact; and the method further includes electrically coupling the source contact of the field-effect transistor to the top-side thermal extension.

[0015] According to one or more embodiments, the method further includes forming a conductive path from the transistor contact through the top thermal extension and to an interconnect feature on the module substrate.

[0016] According to one or more embodiments, the top-side cooling interface is further included in being formed such that its length and width are equal to or greater than the length and width of the RF power die, respectively.

[0017] According to one or more embodiments, the RF power includes a field-effect transistor having a drain manifold, a gate manifold, an array of interdigitated contact lines between the drain manifold and the gate manifold, and a plurality of source contacts adjacent to the interdigitated contact line array; wherein the method further includes electrically coupling each of the drain manifold, the gate manifold, and the plurality of source contacts to a terminal disposed in the front-side I / O interface of the RF power die.

[0018] According to a second aspect of the invention, a method for manufacturing a plurality of power amplifier modules (PAMs) is provided, the method comprising: bonding the rear side of a radio frequency (RF) power die to a thermal extension panel comprising a plurality of interconnects on a top side thermal extension; after bonding, separating the thermal extension panel to produce partially manufactured PAMs, each PAM comprising at least one RF power die bonded to the separated top side thermal extension; after separating the thermal extension panel, attaching the partially manufactured PAMs to a substrate panel comprising a plurality of interconnect module substrates such that each module substrate has at least one partially manufactured PAM attached thereto; when attaching the RF power die to the substrate panel, electrically coupling a front-side input / output (I / O) interface of the RF power die to a corresponding substrate interconnect feature of the plurality of interconnect module substrates; and after attaching the partially manufactured PAMs to the substrate panel, further separating the substrate panel to produce a plurality of PAMs, each PAM comprising at least one RF power die, a separated module substrate electrically coupled to the at least one RF power die, and a separated top side thermal extension opposite to the module substrate.

[0019] According to one or more embodiments, the method further includes: after attaching the partially manufactured PAM to the substrate panel and before further separating the substrate panel, overmolding the partially manufactured PAM to form a molded panel encapsulating the RF power die and the separated top-side thermal extension; and simultaneously separating the molded panel from the substrate panel to separate the molded panel into a plurality of molded package bodies, each molded package body including at least one RF power die and having a top surface through which the separated top-side thermal extension is exposed.

[0020] According to one or more embodiments, overmolding includes forming the molded panel to have a thickness sufficient to cover the upper surface of the separated top-side thermal extension; and wherein the method further includes back-grinding the molded panel to remove material therefrom and expose the upper surface of the separated top-side thermal extension before separating the molded panel.

[0021] According to another aspect of the present invention, a power amplifier module (PAM) is provided, comprising:

[0022] Top side;

[0023] The bottom side, as shown along a centerline extending through the power amplifier module, is opposite to the top side;

[0024] A radio frequency (RF) power die is located between the top side and the bottom side as shown along the center line, the RF power die having a front side, a rear side, and a front input / output (I / O) interface on the front side;

[0025] A module substrate, wherein the RF power die is mounted to the RF module substrate in an inverted orientation such that the front side of the RF power die faces the module substrate, and the module substrate has substrate interconnect features electrically coupled to the I / O interface of the RF power die;

[0026] A top-side cooling interface, which is substantially coplanar with the top side of the PAM; and

[0027] The main heat extraction path extends from the rear side of the RF power die to the top cooling interface of the PAM in a direction opposite to the module substrate.

[0028] According to one or more embodiments, a top-side thermal extension is further included, the top-side thermal extension having an upper surface that at least partially defines the top-side cooling interface of the PAM, and a lower surface that is in direct thermal contact with the rear side of the RF power die.

[0029] According to one or more embodiments, a molded module body is further included surrounding the RF power die, peripherally surrounding the top thermal extension and contacting the module substrate; wherein the top thermal extension extends from a position adjacent to the RF power die in a direction opposite to the module substrate to disrupt the upper surface of the molded module body.

[0030] According to one or more embodiments, the RF power die further includes a field-effect transistor having a source terminal having a conductive interconnect feature electrically coupled to the module substrate through the top-side thermal extension.

[0031] According to one or more embodiments, the RF power die further includes a field-effect transistor having a drain manifold, a gate manifold, an interdigitated contact line array located between the drain manifold and the gate manifold, and a plurality of source contacts adjacent to the interdigitated contact line array; wherein the drain manifold, the gate manifold, and the plurality of source contacts are each coupled to an end disposed in the front-side I / O interface of the RF power die.

[0032] According to one or more embodiments, the gate manifold of the field-effect transistor is divided into a plurality of spaced-apart manifold portions, which are staggered with the source contacts. Attached Figure Description

[0033] At least one example of the invention will be described below with reference to the accompanying drawings, wherein like reference numerals denote like elements, and:

[0034] Figure 1 This is a simplified cross-sectional view of a power amplifier module (PAM) as shown in an exemplary embodiment of the present disclosure, the PAM including a top-side cooling interface, a module substrate, and at least one radio frequency (RF) power die mounted to the module substrate in an inverted orientation;

[0035] Figure 2 This is a simplified cross-sectional view of a larger electronic component (partially shown). Figure 1 The example PAM shown can be incorporated therein, while the top-side cooling interface is thermally coupled to a component-level heatsink outside the PAM;

[0036] Figure 3 and Figure 4 These are first and second planar schematic diagrams of a transistor layout (here, a field-effect transistor structure) as shown in the example embodiment, which may be integrated into... Figure 1 The PAM shown contains the RF power die;

[0037] Figure 5 It is a flowchart of the overall process, including the processes used for manufacturing and Figure 1 The first example sub-process of multiple PAMs that are similar or identical to PAMs and the method for integrating one or more of the completed PAMs into a PAM such as Figure 2 The second example subprocess in the electronic component shown;

[0038] Figures 6 to 10 It shows the completion and according to Figure 5 The illustrated PAM manufacturing subprocess is used to manufacture a finite number of PAMs, including different stages of a top-side cooling interface.

[0039] Figure 11 It shows according to Figures 5 to 10The PAM manufactured in the example PAM manufacturing subprocess described can be based on Figure 5 The example further elaborates on one way in which the PAM integration subprocess is installed within an electronic component;

[0040] Figure 12 and Figure 13 These are, respectively, isometric and exploded views of a partially manufactured PAM module, which includes a top-side thermal extension in the form of a conductive clip. In other embodiments, this top-side thermal extension may provide an electrical interconnection with the module substrate.

[0041] Figure 14 In additional embodiments of this disclosure, it is suitable to incorporate, for example... Figures 1 to 4 and Figures 6 to 13 The diagram shows a plan view of a multi-stage power amplifier integrated circuit in a PAM with a top-side cooling interface, such as any PAM.

[0042] For the sake of simplicity and clarity, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the following detailed description. It should be further understood that, unless otherwise stated, features or elements appearing in the drawings are not necessarily drawn to scale. For example, the dimensions of certain elements or regions in the drawings may be enlarged relative to other elements or regions to improve understanding of the embodiments of the invention. Detailed Implementation

[0043] The embodiments of this disclosure are illustrated in the accompanying drawings, which have been briefly described above. Various modifications to the exemplary embodiments will be apparent to those skilled in the art without departing from the scope of the invention as set forth in the appended claims.

[0044] definition

[0045] The following definitions apply throughout this document. Terms not explicitly defined herein or elsewhere in this document have their general meaning in the relevant technical field.

[0046] Rear side - the side (outer main surface) of the die that is opposite to the front side of the die along an axis orthogonal to the front side of the die (defined below).

[0047] Bottom side - The side (outer main surface) of the module substrate containing the power amplifier module or PAM (defined below) that is closest to the module substrate on which one or more radio frequency (RF) power dies are mounted.

[0048] The front side - the side of the die (outer main surface) on which the bonding pad is located, either alone or in the majority.

[0049] Metal – a material which is composed primarily of one or more metallic components by weight percentage.

[0050] Power Amplifier Module (PAM) - A modular electronic component containing at least one radio frequency (RF) power die for power or signal amplification purposes.

[0051] Radio frequency (RF) power die - a semiconductor die with an integrated circuit (IC) that contains at least one transistor for RF power or signal amplification purposes.

[0052] Thermal conductivity - thermal conductivity exceeds 10 watts per meter Kelvin (W / mK).

[0053] Top side - the side (outer main surface) of the PAM (as defined above) opposite the bottom side of the PAM, as shown along an axis orthogonal to the top side of the PAM.

[0054] summary

[0055] The following describes a power amplifier (PAM) with enhanced heat dissipation capabilities, at least largely due to the provision of a unique top-side cooling interface. As illustrated herein, the term "top-side cooling interface" refers to an externally accessible interface exposed along the top side of the PAM through which heat can be easily extracted from the body of the PAM, specifically from locations adjacent to one or more RF power dies (and possibly other heat-generating components) contained within the PAM. When the PAM is mounted within a larger electronic assembly or system, the top-side cooling interface may be exposed (uncovered) to allow convective heat transfer to the surrounding environment. However, more effectively, when the PAM is mounted within a larger electronic assembly, the top-side cooling interface can be thermally coupled to a component-level heat sink to further facilitate the outflow of excess heat from the PAM and dissipate it into the surrounding environment. Such a component-level heat sink can be, for example, an array of heat sinks, a metal chassis, or another thermally conductive structure adapted to absorb excess heat extracted from the PAM and convectively transfer it to the surrounding environment. Electrical connections are further formed between the PAM's input / output (I / O) interface and a component-level substrate, such as a motherboard, to mount the PAM onto the component-level substrate when it is installed in a larger electronic component or system.

[0056] The PAM includes a module substrate in which one or more microelectronic components, including at least one RF power die, are mounted. The module substrate can be any support structure to which at least one RF power die is suitably mounted, and the support structure includes conductive features (hereinafter, “wiring” or “interconnection” features) for interconnection with the PAM’s I / O interface. The PAM’s I / O interface is formed at least on the bottom side of the PAM at a location opposite the top-side cooling interface, as shown along the centerline of the PAM. Furthermore, the PAM includes at least one RF power die mounted in an inverted orientation to the upper surface or “die support surface” of the module substrate; that is, such that the front side of the RF power die faces the die support surface of the module substrate. A primary heat extraction path extends from the rear side of the inverted RF power die to the top-side thermal interface of the PAM. The primary heat extraction path extends away from (and thus around) the module substrate, and further avoids extending through any area of ​​the PAM made of a material with low thermal conductivity. In this way, the primary heat extraction path provides a direct and efficient route for extracting excess heat generated by the inverted RF power die, passing it through the rear side of the RF power die, and ultimately through the top-side cooling interface of the PAM. Furthermore, in embodiments, the size of the top-side cooling interface can be configured such that its planar dimensions (e.g., length and width) are substantially equal to (if not exceeding) the planar dimensions (e.g., length and width) of the inverted RF power die, to provide a relatively large-volume heat extraction conduit and maximize the surface area of ​​the top-side cooling interface, thereby further enhancing the heat dissipation capabilities of the host PAM.

[0057] In some embodiments, the PAM includes at least one top-side thermal extension; that is, a thermally conductive structure bonded to the rear side of the inverted RF power die and extending from the RF power die toward the top-side cooling interface. The top-side thermal extension can be deposited directly on the rear side of the RF power die by, for example, electroplating a relatively thick layer of metal (e.g., Cu) onto the rear side of the die during PAM fabrication. Alternatively, the top-side thermal extension can be provided as a preform or part bonded to the rear side of the RF power die using a thermally conductive bonding material. In the latter case, the top-side thermal extension can be formed of various metallic and non-metallic materials having relatively high thermal conductivity; for example, in embodiments, the top-side thermal extension can be made of a material having a thermal conductivity exceeding 100 W / mK and possibly exceeding 200 W / mK. When present, the top-side thermal extension can extend from a location adjacent to the rear side of the RF power die to a location adjacent to the top-side thermal interface of the PAM or sharing an end with the top-side thermal interface of the PAM. In the latter aspect, in at least some embodiments, the upper surface of the top-side thermal extension (i.e., the surface opposite the RF power die) can be exposed from the top side of the PAM to define or help define the top-side cooling interface. As a more specific example, in embodiments where the PAM further includes a molded module body encapsulating an inverted RF power die, the upper end of the top-side thermal extension may terminate at a position substantially coplanar with the outer main surface of the molded module body to define the top-side thermal interface.

[0058] When provided, the top-side thermal extension may or may not be electrically active; that is, it may be used for electrical power or signal transmission purposes. In embodiments where the top-side thermal extension is not electrically active, the inverted RF power die may be designed such that the I / O interfaces of the RF power die are entirely located on the front side of the die. Therefore, in such embodiments, all I / O terminals of the transistor IC carried by the RF power die may be included in the front-side I / O for direct connection to the module substrate. In embodiments where at least one field-effect transistor (FET) is integrated into the RF power die, the source, drain, and ground contacts of the FET may be electrically coupled to corresponding terminals located in the front-side I / O of the inverted RF power die. The following is in conjunction with... Figure 3 and Figure 4This paper discusses unique FET designs or layouts that facilitate such front-side dedicated interconnect schemes. In other embodiments, the top-side thermal extension may be electrically active and used for signal or power routing purposes. Again, considering an example embodiment where at least one FET is integrated into a given RF power die contained in a PAM, the source contacts of the FET can be electrically coupled to the top-side thermal extension via the rear side of the RF power die. For example, by forming a conductive path extending from the outer peripheral portion of the top-side thermal extension to the die support surface of the module substrate, the top-side thermal extension can be sequentially electrically coupled to a corresponding interconnect feature on the module substrate (e.g., a trace terminating in a bonding pad). In various embodiments, this can be achieved by determining the dimensions of the top-side thermal extension to extend beyond the underlying RF power die in at least one planar dimension, thereby creating a peripheral protrusion. To complete the required electrical path, one or more vertically extending contacts (e.g., one or more solder balls or discretely placed metal blocks) are provided at the junction between the interconnect feature and the peripheral protrusion, or by further providing a top-side thermal extension, such that one or more outer peripheral walls extend downward toward the module substrate (thus side one or more surfaces of the mandrel) to electrically interconnect with the module substrate, and the peripheral protrusion can be electrically coupled to the corresponding interconnect feature of the module substrate.

[0059] The PAM embodiments described herein offer additional benefits beyond enhanced thermal performance. For example, in some embodiments, the PAM described below has a unique architecture that physically separates the PAM's electrical ground return path and primary heat extraction path. As a more specific example, and as briefly mentioned above, PAM embodiments include an RF power die with I / O interfaces fully formed on the front side of the die. As previously stated, when the RF power die is mounted to the module substrate in an inverted orientation, the front-side I / O interface of the RF power die interconnects with conductive interconnect features of the module substrate. In such embodiments, providing an electrical ground connection through the rear side of the die may become unnecessary, potentially reducing costs by enabling the elimination or reduction of conductive vias (e.g., through-substrate vias (TSVs)) formed through the RF power die. Furthermore, such front-side I / O interconnect schemes between RF power dies and module substrates allow the use of surface mount techniques (e.g., solder bumps or solder balls) when interconnecting RF power dies, thereby avoiding or reducing reliance on the formation of bonding wires, which can complicate PAM and potentially degrade its electrical performance at higher operating frequencies. Additionally, further cost savings can be achieved by eliminating wire bonding and associated materials, such as gold (Au) bonding pads. Despite these advantages, further details are provided below. Figure 12 and Figure 13 As further discussed, in other embodiments, additional electrical interconnections (e.g., grounding) may be provided via the back side of the die.

[0060] Efficient and cost-effective manufacturing processes for manufacturing the PAMs described herein are also provided. In one such manufacturing process, a partially manufactured PAM is first manufactured in the initial manufacturing stage by, for example, bonding the back side of at least one RF power die to a top-side thermal extension, such as a metal (e.g., copper) block or other conductive material. To improve process efficiency, partially manufactured PAMs can be produced simultaneously with multiple other PAMs by bonding each PAM to a corresponding top-side thermal extension, while the top-side thermal extensions remain interconnected in a panel form. The thermal extension panels can then be separated to produce multiple discrete units, which are mounted (physically attached and electrically interconnected) to a module substrate. The module substrate can be a PCB, a coreless substrate, a ceramic substrate, or other wiring substrate, which are also interconnected in a panel form. Overmolding is then performed to form a molded panel with excessive thickness or surface coverage, which completely covers the upper surface of the top-side thermal extension of the partially completed PAM. Subsequently, the molded panel can be thinned (e.g., by back-grinding) to expose the corresponding top side of the thermal extension, thereby defining the top-side cooling interface of the PAM. Subsequently, a second separation process can be performed to separate the panel assemblies (i.e., the molded panel and the module substrate panel) into multiple complete PAMs with top-side cooling interfaces. The following section combines... Figures 5 to 11 An example of such a manufacturing process is further described. Other manufacturing processes for manufacturing PAM with top-side cooling interfaces are also possible and conceivable, as will become apparent from the following description taken in conjunction with the accompanying drawings.

[0061] Now we will combine Figures 1 to 4 , Figure 12 and Figure 13 An example embodiment of a PAM with a top-side cooling interface is described below, and the following is combined with Figures 5 to 11 The following section further discusses example methods for manufacturing such PAMs using panel-level manufacturing processes. For ease of explanation, PAMs with relatively simple constructions are described first; for example, the following section combines... Figures 1 to 11 , Figure 12 and Figure 13 The example PAMs discussed may each contain a single RF power die (or two dies) enclosed within a molded module body. However, as discussed below... Figure 14Furthermore, embodiments of the PAM can vary in complexity and can include any actual number of RF power dies and other microelectronic components distributed on the module substrate, including, for example, any number of surface mount devices (SMDs), embedded wiring structures, or other IC bearing semiconductor dies. Additionally, alternative embodiments may not include a molded die encapsulation body, or may differ from the PAM described below in other respects, provided that each PAM includes at least one top-side cooling interface that helps to extract excess heat generated by one or more RF power dies during the use of the PAM.

[0062] General discussion of power amplifier modules including top-side cooling interfaces

[0063] Figure 1 This is a simplified cross-sectional view of a PAM 18 having a top-side cooling interface 20, and is illustrated according to an exemplary embodiment of this disclosure. In addition to the top-side cooling interface 20, the PAM 18 also includes at least one RF power die 22, a module substrate 24, a molded module body 26, and a top-side thermal extension 28. The RF power die 22 is mounted to the upper front side or die support surface 30 of the module substrate 24, such as a PCB, ceramic substrate, coreless substrate, or another wiring structure suitable for supporting the RF power die 22 and providing electrical interconnection thereto. The RF power die 22 is mounted to the module substrate 24 in an inverted orientation such that the front side 32 of the die 22 faces the die support surface 30. The molded module body 26 encloses the RF power die 22, contacts the die support surface 30 of the module substrate 24, and surrounds (i.e., extends around) the top-side thermal extension 28. The upper main surface 34 of the top-side thermal extension 28 is substantially coplanar or flush with the outer main surface 36 of the molded module body 26. The upper main surface 34 of the top thermal extension 28 and the upper main surface 36 of the molded module body 26 together define the outer main surfaces of the top sides 34, 36 of the PAM 18. In other embodiments, and depending on the manufacturing method of the PAM 18, the top thermal extension 28 may be recessed relative to the top sides 34, 36 or protrude above said top sides, provided that the upper main surface 34 of the top thermal extension 28 is exposed outward along the PAM top sides 34, 36, to subsequently provide the option of thermal coupling to a component-level heat sink when the PAM 18 is mounted within a larger electronic system or assembly, as described below. Figure 2 Further description.

[0064] RF power die 22 includes, for example, along the centerline of PAM 18 or the vertical axis (parallel to) Figure 1The rear side 40, opposite the front side 32, is shown on the Z-axis of the coordinate diagram 42. At least one RF power transistor (here, FET 44) is formed within and above the die body 48; the term "above" is used in a relative sense to indicate the vertical overlap shown along a vertical axis extending orthogonally to the front side 32 and rear side 40 of the RF power die 22. The die body 48 is at least partially composed of a body or layer of semiconductor material in which the channel of the FET 44 is formed. In some embodiments, when the RF power die 22 is fabricated, for example, using a discrete wafer of a bulk silicon (Si) wafer, the die body 48 may be entirely composed of such semiconductor material. In other cases, the die body 48 may have a more complex layered structure. This may be because, for example, when the RF power die 22 is fabricated using a layered die technique that achieves a relatively high transistor power density, the transistor power density tends to generate a relatively high concentration of excess heat and is therefore well-suited for integration into the high thermal performance PAM described herein. An example of this type of power-intensive die technology is a layered GaN structure, in which one or more layers of GaN material (i.e., semiconductor material containing GaN as its main component by weight) are formed over one or more substrate layers of another material, such as silicon carbide (SiC). Therefore, the term "die" as used herein includes the semiconductor material comprising the die body as well as the layers formed on the die body during wafer-level processes.

[0065] Regardless of the specific die technology employed, the transistor channel is formed along or slightly below the main surface of the semiconductor material bulk or layer within the RF power die 22. During transistor fabrication, selected regions of the semiconductor material bulk are doped to define the source and drain regions of the FET 44. Multiple front-side layers 50 are then built or sequentially fabricated above this surface to define the contact portions of the transistor; for example, in the case of the FET 44, gate contact fingers, gate manifold, drain line, and drain manifold. Specifically, as described below... Figure 3 and Figure 4 Further described, a first patterned metal layer (typically referred to as the "M1" layer) can be formed over the semiconductor material body to define such features. Additional patterned metal layers and intermediate dielectric layers can then be formed to create the desired interconnects or integrated wiring structure of the RF power die 22. As... Figure 1As shown, the final metal layer is also typically patterned to create a plurality of bonding pads 54, 56, and 58. In an embodiment, the front layer 50 may terminate at an external passivation layer, which may define or help define the front side 32 of the RF power die 22. In general, the bonding pads 54, 56, and 58 serve as the front-side I / O interface of the RF power die 22. In an embodiment, the rear side 40 of the RF power die 22 may be further used as an I / O terminal (e.g., a ground terminal or a source terminal), while in other embodiments of PAM 18, the rear side 40 may be electrically inert, such that the I / O of the RF power die 22 is formed only on the front side 32.

[0066] Therefore, a front-side I / O interface is formed on the front side 50 of the RF power die 22, the front-side I / O interface including at least first, second, and third bonding pads 54, 56, and 58. In the illustrated embodiment where the FET 44 is formed in the RF power die 22, as a non-limiting example, the first pad 54 (or the first set of bonding pads) can be used as an input terminal of the RF power die 22 electrically coupled to the gate terminal of the FET 44; the second bonding pad 56 (or the second set of bonding pads) can be used as an output terminal of the die 22 electrically coupled to the drain terminal of the FET 44; and the third bonding pad 58 (or the third set of bonding pads) can be used as a ground (or other reference voltage) terminal of the die 22 electrically coupled to the source terminal of the FET 44. In one method, increased isolation between the gate signal and the drain signal is achieved by positioning the ground terminal (bonding pad 56) between the source terminal (one of the bonding pads 54 and 58) and the drain terminal (the other of the bonding pads 54 and 58). Various conductive interconnect features 62 (vias and substrate interconnects) formed in or on the module substrate 24 are used to provide corresponding I / O interfaces on the die support surface 30 of the module substrate 24 to electrically couple the interconnect interfaces formed on the die support surface 30 to the component-level interfaces formed on the outer main surface of the module substrate 24 (corresponding to the bottom side 38 of the PAM in the illustrated example). Therefore, the conductive interconnect features 62 may include first, second, and third interconnects 64, 66, and 68 formed in the body of a dielectric material 70 (e.g., a ceramic layer or laminate of a PCB), which is electrically coupled to die bonding pads 54, 56, and 58 respectively during the manufacture of the PAM 18. Depending on the manufacturing method of the PAM 18, the die bonding pads 54, 56, and 58 may be electrically coupled to the bonding pads and interconnects 64, 66, and 68 of the module substrate 24 via multiple lower contact extensions 72, such as multiple solder balls or solder bumps. However, alternative implementations may employ other interconnect structures or solutions for providing the required electrical connection between the front I / O interface of the RF power die 22 and the module substrate 24. For example, in other implementations, the RF power die 22 may be directly mounted to the module substrate 24 without providing contact extensions, thereby undergoing the manufacturing process used to produce PAM 18.

[0067] Continue to refer to Figure 1 The rear side 40 of the RF power die 22 is bonded to the interior or lower main surface 46 of the top thermal extension 28 via a thermally conductive bonding layer 52. The thermally conductive bonding layer 52 may be made of any material suitable for mechanically bonding the RF power die 22 to the top thermal extension 28, while having a relatively high thermal conductivity; for example, in embodiments, the thermal conductivity of the bonding layer 52 may exceed 30 W / mK and possibly exceed 100 W / mK. Suitable materials include metal-filled (e.g., copper (Cu), gold (Au), and silver (Ag) filled) epoxy resins, solder materials (e.g., deposited solder paste and solder topcoat applied to the top thermal extension 28), and thermally conductive die attachment materials comprising metal-metal (e.g., tin-copper) transition liquid phase systems. Furthermore, in some embodiments, the thermally conductive bonding layer 52 may be made of a sintered metal material; that is, a material formed from sintered metal particles and primarily composed of one or more metal components by weight. When formed from such sintered materials, the thermally conductive bonding layer 52 may consist primarily of Cu, Ag, Au, or mixtures thereof by weight. Furthermore, in such cases, the thermally conductive bonding layer 52 may or may not contain organic materials, such as epoxy resin added for reinforcement purposes. If desired, the rear side 40 of the RF power die 22 may be metallized to form a robust metallurgical bond with the thermally conductive bonding layer 52 when made of sintered metal material. For example, in embodiments, a back metal layer (e.g., a relatively thick Cu layer) may be electroplated or otherwise deposited on the rear side 40 of the RF power die 22. Similarly, in embodiments, the lower surface 46 of the top thermal extension 28 may also be electroplated, intentionally roughened, or otherwise treated to promote bonding with the thermally conductive bonding layer 52.

[0068] The top-side thermal extension 28 can be created by depositing conductive material onto the rear side 40 of the RF power die 22, for example by electroplating one or more layers of a metal-containing material onto the rear side 40 of the die. Alternatively, as Figure 1As indicated, the top-side thermal extension 28 can be provided as a preform or part, positioned above and bonded to the RF power die 22 via a thermally conductive bonding layer 52. In embodiments, the top-side thermal extension 28 may be in the form of a metal block primarily composed of metallic materials such as Cu, Au, Ag, aluminum (Al), or nickel (Ni) and their alloys by weight. In other embodiments, the top-side thermal extension 28 may be made of composite or non-metallic materials with relatively high thermal conductivity. Such materials include, but are not limited to, diamond polycarbonate materials, diamond metal composites (e.g., diamond Au, diamond Ag, and diamond Cu), Cu graphite, pyrolytic graphite, and materials containing carbon allotropes, such as graphene and carbon nanotube-filled materials. Regardless of its specific configuration, the top-side thermal extension 28 is ideally chosen to have a relatively high thermal conductivity, particularly in the vertical direction (parallel to the Z-axis of coordinate diagram 42), along which heat is conducted upwards from the RF power die 22 and the module substrate 24 during the operation of PAM 18. Therefore, in embodiments, as shown in a cross-section along the main heat extraction path extending through the thermal extension 28 in a direction away from the module substrate 24, the top-side thermal extension 28 can have a thermal conductivity exceeding 100 W / mK, and possibly exceeding 200 W / mK.

[0069] If measured along the vertical axis or centerline (corresponding to the Z-axis in coordinate diagram 42) and as... Figure 1 As indicated (not drawn to scale), the thickness of the top thermal extension 28 may be greater than the thickness of the RF power die 22 in this embodiment. In other embodiments, the thickness of the top thermal extension 28 may be less than or substantially equal to the thickness of the RF power die 22. As measured along the X and Y axes of coordinate diagram 42, respectively, the planar dimensions (length and width) of the top thermal extension 28 may be substantially equal to or greater than the planar dimensions (length and width) of the RF power die 22. When the two quantities differ by less than 10%, as shown in this document, the two quantities are considered “substantially equal.” Determining the size of the top thermal extension 28 in this manner expands the area of ​​the lower surface 46 that contacts the rear side 40 of the RF power die 22 to facilitate heat flow from the RF power die 22, through the bonding layer 52, and to the top thermal extension 28. In other embodiments, the shape of the top-side thermal extension 28 may allow the length and / or width of the extension 28 to increase with increasing distance from the RF power die 22 (e.g., fanning out in a continuous or stepped manner), to further increase the surface area of ​​the top-side thermal extension 28 relative to the die rear side 40. This possibility is only indicated by the dashed area 47. Figure 1 and Figure 2The dashed line on the upper right shows that the top-side thermal extension 28 can be given an inverted conical geometry, the width of which increases with increasing distance from the RF power die 22 and from the top-side cooling interface 20. Figure 1 As further indicated, in embodiments, the top thermal extension 28 is typically centered above the RF power die 22, as obtained along a vertical axis or centerline extending through PAM 18 (again, parallel to the Z-axis of coordinate diagram 42) and intersecting the thermal extension 28 and die 22. In other embodiments, the top thermal extension 28 may have different positioning relative to the RF power die 22, provided that the top thermal extension 28 is thermally coupled to the rear side 40 of the RF power die 22. In many cases, the top thermal extension 28 will be positioned directly above the RF power die 22; for example, the top thermal extension 28 may be positioned to at least overlap a large portion, or if not, as obtained along a vertical axis or centerline, the entire RF power die 22 extends through the thermal extension 28 and die 22 and is orthogonal to the rear side 40 of the RF power die 22.

[0070] With the structural arrangement described above, a high thermal conductivity, dimensionally stable heat extraction path is created, extending from the rear side 40 of the inverted RF power die 22, through the thermally conductive bonding layer 52, through the top thermal extension 28, and reaching the top cooling interface 20 of the PAM 18. Furthermore, in this embodiment, a straight line can be drawn from the rear side 40 of the RF power die 22 to the top cooling interface 20 along the main heat dissipation path, and no portion of this line extends through a material region having a thermal conductivity of less than 30 W / mK or possibly less than 100 W / mK. Figure 1 Arrow 74 indicates this primary heat extraction path and provides an efficient, direct (non-twisting), volumetrically robust heat conduction path for transferring excess heat from the RF power die 22 to a component-level heatsink outside the PAM 18 when the PAM 18 is ultimately mounted within a larger electronic assembly containing such a component-level heatsink. This can be seen by referring to... Figure 2 To further understand, a portion of the electronic component 76 on which the PAM 18 can be mounted in an embodiment is shown in a simplified cross-section. It can be seen that the electronic component 76 includes an assembly-level substrate 78, such as a motherboard, on which the PAM 18 is mounted. Any suitable interconnect technology, such as a solder ball array 80, can be used to electrically couple the I / O interfaces of the PAM 18 to corresponding interconnect features (e.g., bonding pads and traces) on the upper surface of the component-level substrate 78. In other embodiments, the PAM 18 can be mounted onto the component-level substrate 78 and electrically interconnected with the component-level substrate using a patterned solder layer, a planar grid array (LGA), a pin grid array (PGA), or various ball gate arrays (BGA). Furthermore, for clarity, Figure 2 Only a limited portion of the component-level substrate 78 is shown. Various other components may be distributed on the portion of the component-level substrate 78 not shown, possibly including other PAMs having a top-side cooling interface similar to the top-side cooling interface 20 of PAM18, to form the desired circuit structure.

[0071] like Figure 2 As shown, in one embodiment, the component-level heat sink 82 can be directly mounted to the top sides 34, 36 of the PAM 18 and bonded to the top-side cooling interface 20 using, for example, a thermally conductive bonding layer 84. The thermally conductive bonding layer 84 can be made of any thermally conductive bonding material, including those discussed above in conjunction with the thermally conductive bonding layer 52. In other embodiments, the component-level heat sink 82 can be thermally coupled to the top-side cooling interface 20 in a less direct manner. For example, in other cases, the component-level heat sink 82 can be spatially separated from the PAM 18, and heat pipes, such as metal bodies or elongated heat pipes, can be thermally coupled between the heat sink 82 and the top-side cooling interface 20. Regardless of its specific location relative to the PAM 18, the component-level heat sink 82 can be any thermally conductive structure or device suitable for absorbing excess heat extracted from the PAM 18 through the top-side cooling interface 20. For example, in one embodiment, the component-level heat sink 82 can be a metal chassis, a heat sink structure (e.g., a pin-heat sink array), or another thermally conductive body external to the PAM 18. The component-level heat sink 82 typically, but need not, have a volume exceeding that of the top-side thermal extension 28. The component-level heat sink 82 can be convectively cooled by releasing heat to the surrounding environment; and, in some embodiments, heat sink fins can direct airflow toward the component-level heat sink 82 to promote convective heat transfer into impinging airflow. In embodiments, a liquid coolant can also be used to effectively cool the component-level heat sink 82. Generally, the component-level heat sink 82 can then take different forms and configurations depending on the characteristics of the electronic component 76. It is also possible to mount the PAM 18 within a larger electronic system or component, and if such an arrangement provides sufficient heat dissipation for the PAM 18 in certain applications, the top-side cooling interface 20 remains exposed (and therefore not directly thermally coupled to the heat sink).

[0072] As described above, in addition to improving thermal performance by providing a top-side cooling interface 20, embodiments of the PAM 18 can also achieve other benefits through a front-side I / O interface formed by the bonding pads 54, 56, and 58 of the RF power die 22. To support such a front-side I / O interface, the various terminals or contacts of the transistor IC carried by the RF power die 22 are also formed as a front side 32 facing the RF power die 22, defined by a front-side layer 52 constructed above the die body 48 as previously discussed. Specific transistor designs or layouts can be used to allow for such front-side I / O interfaces for the RF power die, as discussed below. Figure 3 and Figure 4 Two examples are described. In the following description, for illustrative purposes, a transistor IC comprising a single FET is discussed. In other embodiments, other types of transistors (e.g., bipolar transistors) may be formed on the RF power die 22 and / or more complex transistor ICs may be employed, such as multi-level transistor ICs comprising multiple transistors formed on a single RF power die. In this regard, embodiments of this disclosure can be used with a variety of different die technologies, transistor types, and transistor layouts. For example, when one or more transistors carried by the RF power die 22 employ FETs (e.g., Figure 1 When the FET is in the form of FET44 (generally shown in the diagram), any of the following die technologies can be used to implement the FET: silicon-based FETs (e.g., laterally diffused metal-oxide-semiconductor FETs or LDMOS FETs) or III-V group FETs (e.g., GaN FETs, gallium arsenide (GaAs) FETs, gallium phosphide (GaP) FETs, indium phosphide (InP) FETs, or indium antimonide (InSb) FETs or another type of III-V group transistor). The embodiments of this disclosure may be particularly useful when one or more RF power dies included in a PAM (e.g., RF power die 22 included in PAM 18) are prone to generating excess heat during operation, for example when RF power die 22 uses power-intensive (e.g., GaN) die technology and / or when RF power die 22 operates at higher RF frequencies, such as those approaching or exceeding 3 GHz.

[0073] Turn now Figure 3 and Figure 4 This illustrates two possible FET layouts or structures 86 and 88 with front-side I / O interfaces. First, refer to FET structure 86 (…). Figure 3 The FET structure 86 is formed in and above the body of the semiconductor material 90, which can be formed into Figure 1Part or all of the die body 48 shown. Certain regions of the semiconductor material 90 are doped to define the source and drain regions of the FET structure 86; for example, as shown by looking down at the main surface of the semiconductor region forming the channel of the FET structure 86, each source region may be located between or bounded by two drain lines and two lower drain regions, which in turn are located between or bounded by two gate contact fingers. A patterned metal layer (hereinafter referred to as the "M1 layer") is initially formed over the upper surface 92 of the semiconductor material body 90 to define the contact features of the FET 86. The FET contact features include a drain manifold 94, a plurality of gate manifold portions 96, and a plurality of source contact portions 98. As shown along the X-axis of coordinate diagram 42 (in this example along the axis of the elongated FET 86), the gate manifold portions 96 and the source contact portions 98 are staggered. Within the central interdigitated contact line array 100, multiple drain lines extending from the drain manifold 94 are interleaved with multiple gate contact fingers extending from the gate manifold portion 96. The gate manifold portion 96, the source contact portion 98, and the drain manifold 94 are located adjacent to or bordering the interdigitated contact line array 100 to provide a relatively compact transistor layout, wherein all transistor ends face the front side of the RF power die. The FET 86 may be configured to include various other contact features, such as the gate bias contact 102, as needed. Since the drain manifold 94, the gate manifold 96, and the source contact portion 98 are coplanar with the first patterned metal layer 104, an additional patterned metal layer formed in the front layer 50 may be constructed over the illustrated structure to define the wiring architecture of the RF power die 22 and ultimately electrically connect the transistor contact features 94, 96, 98 to bonding pads 54, 56, 58 present on the front side 32 of the RF power die 22.

[0074] Similarly, in Figure 4 In the example, another possible FET structure 88 supporting the front-side I / O interface is presented. Similarly, the FET structure 88 includes a drain manifold 106, a gate manifold 108, and two source contact portions 110. As before, multiple elongated fingers or lines extend from the manifolds 106, 108 to create a central interdigitated transistor finger or line region 112. All the aforementioned features can be formed by patterning an M1 layer 114, which is deposited on the front side or upper main surface 116 of the semiconductor material body 118. Additional conductive features, such as gate bias contacts 120, can also be formed by patterning the M1 layer 114. Before depositing the M1 layer 114, appropriate regions of the semiconductor material body 118 are doped in a manner similar to those previously described to define the source and drain regions of the FET structure 88. Finally, various additional patterned metal layers are subsequently constructed over the surface 116 and the first patterned metal layer 114 to generate the front-side layer 50. Figure 1The wiring structure of the RF power die 22 is completed. Therefore, the source contact 110 is located adjacent to the interdigitated transistor line region 112 along with the gate and drain manifolds 106, 108. As previously described, the end result is a relatively compact FET layout where all transistor ends face the front side of the RF power die to form a front-side I / O interface. Various other FET layouts also exist in other embodiments. Additionally, in other embodiments, at least one electrically active region (e.g., the source region) of the FET structure 88 can be electrically coupled through the rear side 40 of the RF power die 22, in which case the top thermal extension 28 can be electrically active and serve as the end of the PAM 18.

[0075] Further details Figure 1 The PAM 18 FET structure shown is 86 ( Figure 3 ) and FET structure 88 ( Figure 4 The contacts or terminals of FET structures 86 and 88 are electrically coupled to one or more of bonding pads 54, 56, and 58. Specifically, FET structure 86 is formed in RF power die 22. Figure 3 In an example embodiment, gate contact 96 is electrically coupled to a first of bonding pads 54, 56, and 58; source contact 98 is electrically coupled to a second of bonding pads 54, 56, and 58; and drain manifold 94 is electrically coupled to a third of bonding pads 54, 56, and 58. Similarly, a FET structure 88 is formed in the RF power die 22. Figure 3 In an example embodiment, gate manifold 108 is electrically coupled to a first of bonding pads 54, 56, 58; source contact 110 is electrically coupled to a second of bonding pads 54, 56, 58; and drain manifold 106 is electrically coupled to a third of bonding pads 54, 56, 58. Electrical interconnections between the contacts or terminals of FET structures 86, 88 (or another FET structure formed in the RF power die 22) and bonding pads 54, 56, 58 are provided by conductive features formed in the front layer 50, which are constructed above the surface of the die body 48 along which the transistor is formed (and...). Figure 1 (This corresponds to the FET 44 generally shown in the diagram). Similarly, appropriate doping and other processes can be performed during wafer-level processes to generate, for example, FETs in… Figure 3 and Figure 4 Following a desired FET structure such as FET structure 86 or FET structure 88 shown, such a front-side layer 50 is formed. In other embodiments, as discussed below, for example, in embodiments where one or more FETs are integrated into the RF power die 22 for grounding purposes, one or more transistors integrated into the RF power die 22 may have different structures or layouts, including (e.g., via one or more TSVs) structures or layouts that provide electrical connections to the rear side 40 of the RF power die 22.

[0076] Then proceed to Figure 5 It shows the use of PAM 18 ( Figure 1 A plurality of similar or identical PAMs and an overall process 122 for mounting one or more of the resulting PAMs in an electronic assembly. Process 122 includes a plurality of process steps 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, described sequentially below. Depending on the specific manner in which process 122 is implemented, Figure 5 Each step typically shown may be accompanied by a single process or multiple sub-processes. Furthermore, Figure 5 The steps shown and described below are provided as non-limiting examples only. In alternative embodiments of process 122, additional process steps may be performed, certain steps may be omitted, and / or the process steps shown may be performed in a different order. The overall process 122 is divided into two sub-processes: PAM manufacturing sub-process 144 and PAM installation sub-process 146. In embodiments, a single manufacturer or entity may perform both sub-processes 144, 146 at least in their substantial parts. However, more commonly, a first entity (e.g., a supplier) will perform PAM manufacturing sub-process 144, while a second entity (e.g., a customer or buyer) will perform PAM installation sub-process 146. It is also possible that multiple entities perform various other combinations of steps included in the overall process 122 and other related processes; for example, a third entity (e.g., a chip manufacturer) may initially manufacture the RF power die integrated into the PAM generated according to sub-process 144. Figures 5 to 11 Describe the overall process 122, and use as needed from... Figure 1 and Figure 2 The accompanying figure references. Although for illustrative purposes, they are combined with example PAM 18 ( Figure 1 and 2 The overall process 122, specifically the PAM manufacturing subprocess 144, can be used for PAMs that differ in various respects from PAM18.

[0077] Also refer to Figures 5 to 11 Overall process 122 ( Figure 5 The process begins at step 124 of the PAM manufacturing subprocess 144. During this step, one or more RF power dies 22 are obtained through independent manufacturing, purchase from a supplier, or otherwise. The RF power dies 22 have been manufactured using wafer fabrication processes to define the above-described process. Figure 1The features described include, for example, the desired transistor IC already formed in each of the RF power dies 22, a front-side layer 50 already constructed on the die body 48 of each RF power die 22, and multiple bonding pads 54, 56, 58 formed to create the front-side I / O of each die 22. The RF power dies 22 may or may not be fabricated to provide additional I / O connections (e.g., ground) through the back-side 40. During step 124 of example subprocess 144, the top-side thermal extension 28 is bonded to the back-side 40 of the RF power die 22. As described above, in embodiments, the top-side thermal extension 28 can be generated by electroplating or otherwise directly depositing a thermally conductive material on the back-side 40 of the RF power die 22. Alternatively, the top-side thermal extension 28 may be provided as a prefabricated structure that is bonded to the back-side 40 of the RF power die 22 during step 124 of the PAM fabrication subprocess 144. Therefore, in one possible approach to improving manufacturing efficiency by employing panel-level components, a thermally extended panel 148 comprising multiple interconnected top-side thermally extended portions 28 can be obtained. A limited portion of such a panel 148 is as follows: Figure 6 As shown, it includes four top-side thermal extensions 28 interconnected by posts or tie rods 150. The tie rods 150 physically interconnect the top-side thermal extensions 28 while having a reduced thickness relative to them to facilitate subsequent separation from the thermal extension panel 148, for example by sawing, as described below in conjunction with step 128.

[0078] In the illustrated process flow, the RF power die 22 is bonded to the lower surface 46 of the top thermal extension 28, while the top thermal extension 28 remains interconnected with the thermal extension panel 148. For example... Figure 6As shown in the top right quadrant of the exploded view, each RF power die 22 can be bonded to the lower surface 46 of its corresponding top-side thermal extension 28 using a layer of bonding material 52. As previously described, the thermally conductive bonding material 52 can take any form suitable for mechanically attaching each die 22 to its corresponding top-side thermal extension 28, while also having a relatively high thermal conductivity exceeding, for example, 30 W / mK or possibly exceeding 100 W / mK. In embodiments, the thermally conductive bonding layer 52 can be applied as a stand-alone film, applied to the rear side 40 of each RF power die 22 before placing the thermally conductive bonding layer above the lower surface 46 of the top-side thermal extension 28; or, alternatively, the thermally conductive bonding layer can be applied to the lower surface 46 of the top-side thermal extension 28 before placing the RF power die 22 above the lower surface of the top-side thermal extension. In a latter aspect, in an embodiment, the thermally conductive bonding layer 52 can be applied as a panel-level film across panel 148 to improve process efficiency. In this case, the individual bonding layers 52 can be separated during the separation process described below. In other cases, the thermally conductive bonding layer 52 can be formed in another manner, for example, by applying a sintering precursor material (e.g., a material containing metal particles and other components, such as a liquid carrier), followed by heat treatment of the sintering precursor material to form a sintered bonding layer. In such embodiments, the rear side 40 of the RF power die 22 can be electroplated with a back metal layer and / or a selected surface of the top thermal extension 28 with an electroplatable material (e.g., a nickel-pale gold (NiPdAu) alloy) to facilitate the formation of a robust, highly thermally conductive metallurgical bond at the respective interface. In other embodiments, the thermally conductive bonding layer 52 may be made of solder material; for example, a solder topcoat may be applied to the lower surface 46 of the top thermal extension 28, or solder paste may be applied to the lower surface 46 of the top thermal extension 28 or the rear side 40 of the RF power die 22 before the die is placed on top of the panel 148. A solder reflow process may then be performed to form the thermally conductive bonding layer 52.

[0079] Continue to PAM manufacturing subprocess 144 ( Figure 5 In step 126, a contact extension is then formed over the bonding pads 54, 56, and 58 of each RF power die 22. For example... Figure 7 As shown, one or more contact extensions 72, such as solder bumps or solder balls, can be formed to contact each bonding pad 54, 56, 58. In some embodiments, an overmolding process can be performed before depositing the contact extensions 72 to form a molded body encapsulating the RF power die 22. In this case, the molded body can initially be deposited as a front-side I / O interface with an excessive thickness or surface covering of the RF power die 22 (here, bonding pads 54, 56, 58). Then, before depositing the contact extensions 72, a process similar to that described below can be performed. Figure 10The molded panel is thinned (e.g., back-grinding) in the manner described in step 134 of PAM manufacturing subprocess 144 to expose bonding pads 54, 56, and 58. Following this, PAM manufacturing subprocess 144 proceeds to step 128, during which the thermally extended panel 148 is separated, for example by sawing, water jetting, or laser cutting, to produce multiple partially manufactured PAMs 18'; the basic symbol (`) appended to reference numeral 18 indicates that the PAM at this joint is still in an incomplete or partially manufactured state as part of the manufacturing process. The resulting structure in Figure 8 Described in the text.

[0080] refer to Figure 8 This illustrates the four-part PAM 18' manufactured following the separation process performed at step 128 of PAM manufacturing subprocess 144. Next, as... Figure 8 As shown, a partially manufactured PAM 18' is attached to a module panel 152 composed of multiple interconnect module substrates 24 (to increase visual clarity). Figure 8 The boundaries between them are shown. Here, it can be seen that the module substrate 24 includes interconnect features 154 (e.g., bonding pads and associated interconnect lines or traces) for electrical connection to solder contacts 72 or other contact extensions previously established in step 126 ( Figure 7 During this process, bonding pads 54, 56, and 58 of each partially manufactured PAM 18' are deposited. Therefore, during step 130, the partially manufactured PAM 18' are attached to the module substrate panel 152 in a manner that mechanically bonds at least one of the PAM 18' to one of the interconnect module substrates 24, while providing the desired electrical connection between the solder contacts 72 and corresponding contact features 154 disposed on the corresponding front side or die support surface 30 of the module substrate 24. Conveniently, this can be achieved by using a pick-and-place tool to position each partially manufactured PAM 18' appropriately above the module substrate panel 152. Subsequently, a solder reflow process can be performed to physically attach and electrically interconnect the PAM 18' to the module substrate 24, simultaneously interconnecting them as panel 152.

[0081] like Figure 9 As shown, proceed to PAM manufacturing subprocess 144 ( Figure 5 In step 132, the partially manufactured PAM 18' is overmolded to produce molded panel 156. Molded panel 156 encapsulates all the partially manufactured PAM 18' previously attached to panel 152 during step 130 of subprocess 144. For visual clarity, the boundaries between the partially manufactured PAM 18' are typically defined by… Figure 9The dotted line 157 indicates this. The molded panel 156 is formed with an excessive thickness or surface cover that completely encloses the PAM 18' to cover the upper surface 34 of the top-side thermal extension 28. Subsequently, the molded panel 156 is thinned by removing material from the front side 158 of the panel during step 134 of the PAM manufacturing subprocess 144. For this purpose, a back-grinding process can be used; the term back-grinding includes various grinding and polishing processes suitable for controlling the removal of material from the molded panel 156. The upper main surface or front side 158 of the molded panel 156, and thus the molded module body 26 currently joined as the panel 156, is back-grinded to expose the corresponding upper surface 34 of the top-side thermal extension 28, resulting in a structure as shown... Figure 10 As shown. This produces a plurality of molded bodies 26 having an upper surface or front side 36, which is substantially coplanar with the exposed surface 34 of the top-side thermal extension 28 and defines a top-side cooling interface 20. Finally, in step 136, the molded panel 156 and the module panel 152 are separated to produce a plurality of PAMs 18 and complete the PAM manufacturing subprocess 144.

[0082] In some embodiments, such as Figure 5 As indicated in step 142, additional steps can also be performed to advance the PAM manufacturing subprocess 144. For example, in at least some embodiments, a thermally conductive bonding layer can be applied over the corresponding top-side cooling interface 20 of the PAM 18 to facilitate customer connectivity of the component-level heat sink in the embodiments. Such steps can be performed after panel separation at step 136 of subprocess 144; or, alternatively, before panel separation to improve process efficiency. In one approach, the thermally conductive bonding layer is applied together with a sheet-like removable backing before separating panels 152, 156, and then each bonding layer and its corresponding backing are separated during the separation process. In another approach, the thermally conductive bonding layer can be applied to the top-side cooling interface 20, for example, by a different method such as jet deposition.

[0083] At a certain junction after PAM manufacturing, a given PAM18 generated according to subprocess 144 can be installed in a larger electronic component or system. Proceed to PAM installation subprocess 146, in which... Figure 5 During step 138, the given PAM18 can be mounted to a component-level substrate, such as a motherboard. An example of such a component-level substrate is the one previously combined with... Figure 2 The substrate 78. Before, after, or simultaneously with mounting the PAM 18 to the component-level substrate 78, the top-side cooling interface 20 is thermally coupled to, for example... Figure 2 The heatsink 82 shown is an external component-level heatsink of PAM 18 (step 140, Figure 5Then, additional steps are performed as needed to complete the manufacturing of the electronic component to complete subprocess 146; the electronic component is, for example, an additional PAM that can be mounted on a motherboard, can form any other electrical interconnect, can be tested, can perform other such steps, other semiconductor dies or other microelectronic components (e.g., SMD).

[0084] Figure 11 This is an exploded view of the electronic component 76 illustrating the performance of steps 138 and 140 in the embodiment. Here, it can be seen that in subprocess 146 ( Figure 5 During step 140 of subprocess 146, a layer of thermally conductive material 84 can be used to attach the component-level heat sink 82 to the top sides 34, 36 of the PAM, and thus to the top-side cooling interface 20. The thermally conductive bonding layer 84 may be made of an adapted thermally conductive material to allow conformal contact along the interface between the component-level heat sink 82 and the top sides 34, 36 of the PAM, to accommodate any non-uniform or non-planar surface topology. Before or after heat sink attachment, during step 138 of subprocess 146, the external end or contact on the bottom side of the PAM 18 is interconnected with a corresponding contact (e.g., bonding pad) on the front side or module support surface 160 of the component-level substrate 78. As described above, any interconnection technology can be used to interconnect the I / O interface on the bottom side of the PAM 18 to the module support surface 160 of the component-level substrate 78; for example, such as... Figure 11 As shown, the PAM 170 can be mounted to the module support surface 160 using a BGA 80, while providing the necessary electrical interconnects. Therefore, this structural arrangement allows heat generated by the RF power die 22 to be efficiently dissipated from within the PAM 18 along the main heat extraction path extending generally upwards from the rear side of the inverted RF power die 22, through the bonding layer 52, through the top thermal extension 28, through the top cooling interface 20, and finally to the component-level heat sink 82. Simultaneously, signal and power transmission (potentially including grounding one or more FETs carried by the RF power die 22) routes downwards from the RF power die 22, through the module substrate 24, and finally to the interconnect features disposed on the component-level substrate 78.

[0085] Additional example PAM with an electrically active top-side thermal extension

[0086] As previously indicated, embodiments of the PAM may or may not include a top-side thermal extension. When a top-side thermal extension is absent, the rear side of the RF power die (or multiple RF power dies) included in the PAM can be directly exposed through the top side of the PAM (e.g., as described above in conjunction with...). Figure 10The top-side cooling interface of the PAM is defined by back-grinding the molded panel. When a top-side thermal extension is included, it may or may not be electrically active; that is, for electrical signal or power conduction purposes during PAM operation. Various benefits can be achieved by not using a top-side thermal extension for power or signal conduction, but instead forming the I / O interface of the RF power die only on the front side of the die. Such benefits have been discussed above and may include cost reduction by eliminating TSVs within the RF power die, eliminating any need for Au bonding pads, and simplifying the process as described above. Figure 3 and Figure 4 The wiring scheme supported by unique transistor designs such as the FET layout discussed. Nevertheless, in alternative embodiments, electrical connections can be expected to be provided via the rear side of the RF power die and any top-side thermal extensions bonded thereto. For this reason, reference will now be made to... Figure 1 , Figure 2 and Figure 12 , Figure 13 Additional description of an embodiment in which the top-side thermal extension is used for signal or power (e.g., grounding) purposes.

[0087] Brief reference again Figure 1 and Figure 2 An example manner for forming a conductive path extending from the top-side thermal extension 28 to the module substrate 24 is depicted. In this example, the dimensions of the top-side thermal extension 28 are enlarged such that the top-side thermal extension 28 includes a peripheral protrusion 164 (shown in dashed lines) that protrudes beyond the RF power die 22 by at least one planar dimension (here, as shown along the X-axis of coordinate diagram 42). For clarity, the peripheral protrusion 164 is shown as protruding beyond... Figure 1 and Figure 2 One side of the RF power die 22 (the left side depicted). However, as shown along the X-axis of coordinate diagram 42, the dimensions of the top thermal extension 28 can also extend to the opposite side of the RF power die 22; and / or, as shown along the Y-axis of coordinate diagram 42, to other sides of the RF power die 22. As further indicated by dashed lines, at least one discrete, vertically extending contact 166 can be positioned at the peripheral protrusion 164 and one or more interconnect features 168 of the module substrate 24. Figure 1The vertically extending contact 166 has sufficient height to span the vertical gap between the underside of the peripheral protrusion 164 and the vertically aligned bonding or joining pads included in the interconnect feature 168; again, the term "vertical" refers to a direction parallel to the centerline of PAM 18 and the Z-axis of coordinate diagram 42. The vertically extending contact 166 can be, for example, a relatively large solder ball or a discretely placed conductive element, such as a metal (e.g., Cu) block or pillar. When in the form of a discrete conductive element, the vertically extending contact 166 can be bonded to the peripheral protrusion 164 and the aligned bonding pads using any suitable conductive bonding material and process, such as solder paste, solder topcoat provided on the Cu block, epoxy resin containing metal particles, or conductive die attachment material. In other embodiments, different interconnect technologies can be used to electrically couple the peripheral protrusion 164 to one or more interconnect features on the module substrate 24, the interconnect features including, for example, wire bonding; for example, this can be implemented when the top thermal extension 28 is formed to include recessed bonding pads protruding from one or more sides of the extension 28.

[0088] The above-described structural configuration enables the provision of a wider conductive path starting from the die rear side 40, passing through the bonding layer 52 (here, formed of conductive material), through the top thermal extension 28, through the vertically extending contact 166, and reaching the module substrate 24. In embodiments where the RF power die 22 includes at least one FET, such as FET 44, the source terminal of the FET can be electrically coupled to wiring features 168 on the module substrate 24 through the die rear side 40, through the bonding layer 52, through the top thermal extension 28, and through the vertically extending contact 166. When PAM 18 is mounted, for example... Figure 2 In larger components such as component 76 shown, a reference voltage (e.g., electrically grounded) can be further electrically coupled to the source terminal of the FET via the electrical path described above. In other embodiments, different terminals of one or more FETs (or another transistor type) formed in the RF power die 22 can be electrically coupled to corresponding interconnect features on the module substrate 24 via the top-side thermal extension 28 in this manner. In yet another case, such electrical (e.g., grounded) connections through the top-side thermal extension 28 and reaching the rear side 40 of the RF power die 22 can be provided via component-level, component-level heat sink 82.

[0089] Figure 12 and Figure 13 These are isometric and exploded views of a portion of PAM 170, including a top-side thermal extension in the form of a conductive clip 172, as shown in other exemplary embodiments according to this disclosure. PAM 170 is manufactured as follows: Figure 12 and Figure 13 The intermediate manufacturing stages shown illustrate its relationship with... Figure 8The manufacturing stages shown in the figures correspond to those described above in conjunction with the manufacturing of PAM 18. Following the manufacturing stages shown in these figures, PAM 170 may undergo overmolding (similar to...). Figure 9 The process shown), backside grinding to expose the upper surface 174 of clamp 172 (similar to...) Figure 10 (The process shown above) involves panel separation to produce a complete PAM with a top-side thermal interface. In many respects, the PAM 170, if not combined with the above... Figures 1 to 11 If it is similar to PAM 18, then it is similar to it. For example, PAM 170 includes a rear side 178 ( Figure 13 The RF power die 176 (hidden in the view) is located on the opposite front side. Multiple conductive contacts, such as a printed solder paste layer or solder ball array 184, electrically couple bonding pads on the front side of the RF power die 176 to corresponding conductive interconnect features 180 disposed on a module substrate 182, such as a PCB. Similarly, a thermally conductive bonding layer 186 (…) is used… Figure 13 The rear side 178 of the RF power die 176 is bonded to the underside of the top thermal extension (here referred to as the conductive clip 172). In this particular example, the thermally conductive bonding layer 186 is made of a material that is conductive and thermally conductive to allow a signal or power to start from the rear side 178 of the die, pass through the bonding layer 186, pass through the conductive clip 172 and reach the module substrate 188.

[0090] With PAM 18 ( Figures 1 to 11 In contrast to the top thermal extension 28, the conductive clip 172 includes a body 188 and two sidewalls 190 extending downward from the body portion 188 to the upper surface 192 of the module substrate 188. Furthermore, in the illustrated example, the lower edge portion of the sidewalls 190 is grooved or serrated to define a plurality of fingers 194 staggered with a plurality of openings 196. Using a patterned bonding layer 200, the fingers 194 are further bonded to and electrically coupled to additional interconnect features 198 disposed on the upper surface 912 of the module substrate 188. The patterned bonding layer 200 may be composed of solder paste, solder topcoat formed at least on the lower surface of the fingers 194, conductive die attachment material, sintering material, or another conductive bonding material. The solder ball 184 extends through the opening 196 (or at least immediately below the opening) to maintain electrical isolation between the interconnect feature 180, the conductive clip 172, and the interconnect feature 198, thereby providing contact between the conductive interconnect feature 180 (e.g., a trace) and the front I / O interface of the RF power die 176. In this way, a conductive (e.g., ground) path extending from the rear side of the die is again provided.

[0091] The conductive clip 172 can be made of various conductive materials, including Cu, Al, Ni, Al-SiC, and other metallic and non-metallic materials. For example... Figure 12 and Figure 13 As shown, although having a specific shape, the shape of the conductive clip 172 can vary between embodiments; for example, in other embodiments, the conductive clip 172 may have a box-like or cup-like shape including four lower sidewalls that completely surround the lateral extension of the RF power die 176 to enclose the die 176. The specific manner in which the conductive clip 172 is manufactured will vary based on the configuration and shape of the clip 172. However, for example, the conductive clip 172 can be formed by extruding an elongated rod of material having the desired shape and then separating the material rod to form the clip 172. The toothed structure defined by the finger 194 and the opening 196 can then be created using a suitable material removal process such as stamping, laser cutting, or water jetting. In other cases, the conductive clip 172 can be formed in parallel with multiple similar clips using sheet metal processes. Forging, pressing, or similar techniques can be used to bend such sheet metal into Figure 12 and Figure 13 The desired three-dimensional geometry is shown. In other embodiments, the serrated or slotted edges of the conductive clip 172 (or another top-side thermal extension) may not be provided, where the necessary electrical isolation is provided by routing appropriate signal or power paths through the open side of the clip 172 or by routing signals to a lower level (e.g., an inner layer or rear side of the module substrate) of the module substrate as needed. Similarly, in embodiments where the top-side thermal extension included in the PAM is electrically inert and there is no risk of bridging separate signal or power paths, such routing schemes may also become unnecessary or simplified.

[0092] Alternative embodiments of high thermal performance PAM and manufacturing methods

[0093] Therefore, the foregoing describes a method for manufacturing a high thermal performance PAM including a top-side cooling interface in a streamlined and cost-effective manner. In other embodiments, various other manufacturing methods are also possible. For example, in another method, after the module substrate is filled with RF power dies and any other microelectronic components included in a given PAM, a top-side thermal extension can be attached to the rear side of the RF power die. In such embodiments, as previously described, the top-side thermal extension can be bonded to multiple RF power dies while the top-side thermal extension remains interconnected in a panel-like manner. Then, it can be combined as described above... Figure 9 The aforementioned process involves encapsulation molding. Subsequently, the process is combined with the above... Figure 10 and Figure 11The separation process described above is similar to a separation process used to separate various panels into discrete PAMs with top-side cooling interfaces. Other manufacturing methods are also possible without performing overmolding. For example, in such alternative embodiments, different types of module housings (e.g., covered housings) can be used to enclose the RF power die and any other microelectronic components contained within a given PAM, while top-side thermal extensions (if present) can be exposed from the outside of the housing (e.g., the thermal extensions can protrude through an opening in the covered housing) to provide the required top-side cooling interfaces. It is also possible to keep the RF power die (or multiple RF power dies) contained within a given PAM unenclosed (not housed within a molded body or covered housing), which may, in some cases, increase heat dissipation from the RF power die to some extent. However, forming a housing surrounding the die, such as the molded module body 26 described above, provides mechanical protection and structural integrity to the PAM. Additionally, this housing can provide a generally planar top side to facilitate manipulation using vacuum tools, such as pick-and-place tools.

[0094] In the example described above, PAM 18 takes a relatively simple form and includes a single RF power die (RF power die 22) shown. In other embodiments, the PAM generated according to the teachings of the present invention can be quite complex, provided that the PAM includes at least one RF power die and a top-side cooling interface through which heat generated by the die (and any number of other microelectronic components within the PAM) can be extracted. For example, in some embodiments, PAM 18 may include both peaked dies and carrier dies used in Dougherty power amplifier ICs, which are attached to a massively multi-input multiple-output (MIMO) substrate. To further emphasize this point, Figure 12 This is a top-down or plan view of a two-stage power amplifier IC 202 suitable for integration into a PAM of the type described herein. In this example, the two-stage power amplifier IC 202 includes a primary transistor stage 204, a secondary transistor stage 206, and various other electronic components (some of which are labeled for clarity), such as parallel capacitors and bias circuitry. These circuit components are formed in or mounted on a module substrate, such as a PCB 210. One or more top-side thermal extensions (in...) Figure 12(Hidden in the view, but generally indicated by dashed line 212) has been previously bonded to the rear side of one or two RF power dies included in transistor stages 204, 206. One or more top-side thermal extensions 212 can be thermally coupled to the RF power dies via PCB 210, or openings can be provided in PCB 210 through which the top-side thermal extensions protrude to directly attach to one or both of the RF power dies. In the illustrated example, specifically, a single top-side thermal extension 212 is shown positioned above the RF power die 214 included in the primary transistor stage 204; for example, this die 214 may be particularly prone to generating and accumulating excess heat, and therefore, the objective is to enhance heat dissipation through the top-side thermal extension 212.

[0095] To integrate the dual-stage power amplifier IC 202 into a PAM with a front-side thermal interface, various contact extensions 216 (e.g., solder bumps or solder balls) can be deposited above the appropriate ends or contacts of the dual-stage power amplifier IC 202; to name just a few, these include drain pads, parallel -L pads, first and second stage source pads, first stage gate pads, bias pads, and parallel capacitors. Particularly regarding parallel capacitors, when the dual-stage power amplifier IC 202 is integrated into the PAM and ultimately mounted in a larger electronic system or component, the uppermost metal end or "top plate" can be connected to ground via such contact extensions 216. Figure 12 The manufacturing stage shown above can be started from the beginning, and the above-mentioned combination can be performed. Figures 7 to 10 The process described is to complete the production of a PAM containing a dual-stage power amplifier IC 202. For example, the dual-stage power amplifier IC 202 can be inverted and mounted (physically connected and electrically interconnected) with a module substrate such as a second PCB; a molding assembly can then be overlaid to form a molded module body with excessive thickness that completely covers the top-side thermal extension 212; the molded module body can then be thinned by back-side grinding to expose the upper surface of the top-side thermal extension 212 on the top side of the PAM; and any additional steps can then be performed as needed to complete the manufacturing of the resulting PAM.

[0096] in conclusion

[0097] Therefore, a PAM with a top-side cooling interface has been provided, which facilitates thermal coupling between the top-side cooling interface and the component-level heat sink when the PAM is mounted in an electronic assembly. In this way, the PAM can effectively extract excess heat generated by at least one RF power die included in the PAM through its top side. Simultaneously, embodiments of the PAM route the electrical signals and power supplied to the RF power die downwards through the module substrate to which the RF power die is mounted, and any number of additional components. The RF power die is mounted to the module substrate in an inverted orientation such that the front side (front side) of the RF power die faces the die support surface of the substrate. In addition to providing enhanced thermal performance, embodiments of the PAM are suitable for low-cost, streamlined manufacturing using, for example, panel-level manufacturing and component-level processes. In embodiments, cost reduction can also be achieved by eliminating wire bonding connections and / or TSVs formed through the RF power die, particularly when the rear and top thermal extensions (if present) of the RF power die are not charged. After production, PAM can be distributed to customers, who can then integrate PAM into various electronic systems or components by forming the required electrical interconnects with the component-level substrate (e.g., PCB) and by thermally coupling component-level heat sinks, such as chassis, heat sink arrays, or other convection cooling structures, to the top-side cooling interface of the PAM (e.g., using thermally conductive bonding materials).

[0098] In an embodiment, a method for manufacturing a PAM includes independently manufacturing, purchasing, or otherwise obtaining an RF power die, the RF power die including a front side, a rear side, and a front I / O interface on the front side of the RF power die. The RF power die is attached to a die support surface of a module substrate. The RF power die is attached to the module substrate in an inverted orientation such that the front side of the RF power die faces the module substrate. When the RF power die is attached to the module substrate, the front I / O interface of the RF power die is electrically coupled to or interconnected with a corresponding interconnect feature of the module substrate. A primary heat extraction path is further formed to extend from the rear side of the RF power die to a top-side cooling interface of the PAM in a direction opposite to the module substrate.

[0099] In other embodiments, a method for manufacturing a plurality of PAMs includes the following steps or processes: (i) bonding the rear side of an RF power die to a thermal extension panel comprising a plurality of interconnects on a top-side thermal extension; (ii) after bonding, separating the thermal extension panel to produce partially manufactured PAMs, each PAM comprising at least one RF power die bonded to the separated top-side thermal extension; (iii) after separating the thermal extension panel, attaching the partially manufactured PAMs to a substrate panel comprising a plurality of interconnect module substrates such that each module substrate has at least one partially manufactured PAM attached thereto; (iv) when attaching the RF power die to the substrate panel, electrically coupling the front-side I / O interface of the RF power die to a corresponding substrate interconnect feature of the plurality of interconnect module substrates; and (v) after attaching the partially manufactured PAMs to the substrate panel, further separating the substrate panel to produce a plurality of PAMs, each PAM comprising at least one RF power die, a separated module substrate electrically coupled to the at least one RF power die, and a separated top-side thermal extension opposite to the module substrate. In some embodiments, the method further includes: after attaching the partially manufactured PAM to the substrate panel, and before further separating the substrate panel, overmolding the partially manufactured PAM to form a molded panel encapsulating the RF power die and the thermal extension. The molded panel is then simultaneously separated from the substrate panel to separate the molded panel into a plurality of molded package bodies, each molded package body containing at least one RF power die and having a top surface through which the separated top-side thermal extension is exposed.

[0100] The alternative embodiment of the PAM includes a top side, a bottom side opposite to the top side as shown along a centerline extending through the power amplifier module, and an RF power die located between the top and bottom sides as shown along the centerline. The RF power die has a front side, a rear side, and a front I / O interface on its front side. The PAM further includes a module substrate to which the RF power die is attached with an inverted orientation block such that the front side of the RF power die faces the module substrate. The module substrate includes substrate interconnect features electrically coupled to the I / O interfaces of the RF power die. The top-side cooling interface is substantially coplanar with the top side of the PAM, while the primary heat extraction path extends from the rear side of the RF power die to the top-side cooling interface of the PAM in a direction opposite to the module substrate. In some cases, the PAM further includes a top-side thermal extension having an upper surface that at least partially defines the top-side cooling interface of the PAM, and a lower surface that is in direct thermal contact with the rear side of the RF power die. Additionally, in this embodiment, the PAM may further include a molded module body surrounding the RF power die, peripherally surrounding the top thermal extension, and contacting the module substrate. In the latter case, the top thermal extension may extend from a position adjacent to the RF power die in a direction opposite to the module substrate to disrupt the upper surface of the molded module body.

[0101] Although at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the invention in any way. In fact, the foregoing detailed descriptions will provide those skilled in the art with a convenient guide for implementing exemplary embodiments of the invention, and it should be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of the invention as set forth in the appended claims. Numerical identifiers such as “first,” “second,” “third,” etc., have been used according to the order in which certain elements (e.g., package leads, transistors, and dies carrying transistors) are introduced in the foregoing embodiments. Such numerical identifiers may also be used in subsequent claims to indicate the order of introduction in the claims. Therefore, such numerical identifiers may vary between embodiments and subsequent claims to reflect differences in the order of introduction of elements.

Claims

1. A method for manufacturing a power amplifier module, characterized in that, The method includes: An RF power die is obtained, the RF power die including a front side, a rear side, and a front input / output interface on the front side of the RF power die; The RF power die is attached to the die support surface of the module substrate, and the RF power die is attached to the module substrate in an inverted orientation such that the front side of the RF power die faces the module substrate. When the RF power die is attached to the module substrate, the front input / output interface of the RF power die is electrically coupled to the corresponding interconnect feature of the module substrate; Bond the top thermal extension to the rear side of the RF power die; and A primary heat extraction path is provided, extending from the rear side of the RF power die to the top cooling interface of the power amplifier module in a direction opposite to the module substrate. The radio frequency power die includes at least one transistor with transistor contacts. The method further includes electrically coupling the transistor contacts to the top thermal extension.

2. The method according to claim 1, characterized in that, The top-side thermal extension includes a prefabricated body with a thermal conductivity exceeding 100 watts per meter Kelvin; and The bonding process includes using a thermally conductive bonding material to bond the top thermal extension to the rear side of the RF power die.

3. The method according to claim 1, characterized in that, Additionally, it includes a molded module body that encapsulates the RF power die, surrounds the top thermal extension portion, and contacts the module substrate.

4. A power amplifier module, characterized in that, include: Top side; The bottom side, as shown along a centerline extending through the power amplifier module, is opposite to the top side; An RF power die is located between the top side and the bottom side as shown along the center line, the RF power die having a front side, a rear side, and a front input / output interface on the front side; A module substrate, wherein the RF power die is mounted to the RF module substrate in an inverted orientation such that the front side of the RF power die faces the module substrate, and the module substrate has substrate interconnect features electrically coupled to the input / output interface of the RF power die; The top-side cooling interface is substantially coplanar with the top side of the power amplifier module; The main heat extraction path extends from the rear side of the RF power die to the top cooling interface of the power amplifier module in a direction opposite to the module substrate. as well as A top-side thermal extension has an upper surface that at least partially defines the top-side cooling interface of the power amplifier module, and a lower surface that is in direct thermal contact with the rear side of the RF power die. The radio frequency power die includes at least one transistor having transistor contacts electrically coupled to the top thermal extension.

5. The power amplifier module according to claim 4, characterized in that, Additionally, a molded module body is included, surrounding the RF power die, with the top thermal extension portion surrounding the periphery and contacting the module substrate; The top thermal extension extends from a position adjacent to the RF power die in a direction opposite to the module substrate to disrupt the upper surface of the molded module body.

6. The power amplifier module according to claim 4, characterized in that, The transistor is a field-effect transistor, and the transistor contact is the source end of a conductive interconnect feature electrically coupled to the module substrate through the top thermal extension.

7. The power amplifier module according to claim 4, characterized in that, The RF power die further includes a field-effect transistor, the field-effect transistor having a drain manifold, a gate manifold, an interdigitated contact line array located between the drain manifold and the gate manifold, and a plurality of source contacts adjacent to the interdigitated contact line array. The drain manifold, the gate manifold, and the plurality of source contacts are each coupled to a terminal in the front input / output interface of the RF power die.

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