Semiconductor device and method of manufacturing the same

Abstract

This invention provides a semiconductor device and a method for manufacturing the same, which can eliminate damage to the periphery of the adjustment element during adjustment by testing in the manufacturing process, thereby improving quality. The method includes the following steps: forming a fusible resistor (3) inside or above a semiconductor substrate (1); forming an insulating film (4) on the fusible resistor (3); forming a first wiring (6a) on the insulating film (4) and connecting it to one end of the fusible resistor (3) via a first contact area (5a) penetrating the insulating film (4); forming a second wiring (6b) on the insulating film (4) and connecting it to the other end of the fusible resistor (3) via a second contact area (5b) penetrating the insulating film (4); adjusting the fusible resistor (3); and after the adjustment step, testing the insulation state between the semiconductor substrate (1) and the first wiring (6a) or the second wiring (6b).

Description

Technical Field

[0001] This invention relates to a semiconductor device with a trimming circuit and a method for manufacturing the same. Background Technology

[0002] In the switching of functions and adjustment of characteristics of semiconductor integrated circuits (ICs), tuning circuits are used (see Patent Documents 1-4). During tuning, electrical stress is applied externally to the tuning element in the tuning circuit, causing the logic of the tuning element to reverse. For example, when the tuning element is a fusible resistor, the fusible resistor is melted, changing the terminals of the fusible resistor from a short circuit state to an open circuit state. When the tuning element is a Zener zap diode, an avalanche current is used to cause a short circuit at the pn junction, thereby changing the terminals of the Zener zap diode from an open circuit state to a short circuit state.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-110326

[0006] Patent Document 2: International Publication No. 2009 / 104343

[0007] Patent Document 3: Japanese Patent Application Publication No. 2011-222691

[0008] Patent Document 4: Japanese Patent Application Publication No. 2008-288280 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] When adjusting components, electrical stress is applied, potentially damaging the periphery of the component. In cases where the damage is so severe that the IC immediately becomes inoperable, it can be detected during testing in subsequent manufacturing processes, allowing defective products to be eliminated. However, in cases where the damage is at a potential level, such as being normal for IC operation, it cannot be detected during testing in subsequent manufacturing processes. This potential damage to the periphery of the adjusting component may manifest during use in the market, leading to a decrease in quality.

[0011] In view of the above problems, the object of the present invention is to provide a semiconductor device and a method thereof that can eliminate damage to the periphery of the adjustment element during adjustment in a test during the manufacturing process, thereby improving the quality.

[0012] Solution for solving the problem

[0013] One aspect of the present invention is a semiconductor device comprising: (a) a trimming element disposed inside or above a semiconductor substrate; (b) an insulating film disposed on the trimming element; (c) a first wiring disposed on the insulating film and connected to one end of the trimming element via a first contact area penetrating the insulating film; (d) a second wiring disposed on the insulating film and connected to the other end of the trimming element via a second contact area penetrating the insulating film; and (e) an auxiliary wiring disposed on the insulating film at a position overlapping the central portion of the trimming element.

[0014] Other aspects of the present invention relate to a semiconductor device comprising: (a) a trimming element disposed inside or above a semiconductor substrate; (b) an insulating film disposed on the trimming element; (c) a first wiring disposed on the insulating film and connected to one end of the trimming element via a first contact area penetrating the insulating film; (d) a second wiring disposed on the insulating film and connected to the other end of the trimming element via a second contact area penetrating the insulating film; and (e) an inspection pad connected to the semiconductor substrate.

[0015] Another aspect of the present invention relates to a method for manufacturing a semiconductor device, comprising the following steps: (a) forming a trimming element inside or above a semiconductor substrate; (b) forming an insulating film on the trimming element; (c) forming a first wiring on the insulating film that is connected to one end of the trimming element via a first contact area penetrating the insulating film; (d) forming a second wiring on the insulating film that is connected to the other end of the trimming element via a second contact area penetrating the insulating film; (e) trimming the trimming element; and (f) after the trimming step, performing a test on the insulation state between the semiconductor substrate and the first wiring or the second wiring.

[0016] The effects of the invention

[0017] According to the present invention, a semiconductor device and a method thereof are provided that can eliminate damage to the periphery of the adjustment element during adjustment in a test during the manufacturing process, thereby improving the quality. Attached Figure Description

[0018] Figure 1 This is a top view of a semiconductor device according to the first embodiment of the present invention.

[0019] Figure 2 This is a circuit diagram of the adjustment circuit involved in the first embodiment.

[0020] Figure 3 This is a top view of the semiconductor device according to the first embodiment before adjustment.

[0021] Figure 4 This is a cross-sectional view of the semiconductor device according to the first embodiment before adjustment.

[0022] Figure 5 This is a modified cross-sectional view of the semiconductor device according to the first embodiment.

[0023] Figure 6 It is a cross-sectional image of the semiconductor device according to the first embodiment, in which the adjustment element is not damaged after adjustment.

[0024] Figure 7 It is a cross-sectional image of the semiconductor device according to the first embodiment, in the case where the surrounding area of ​​the adjustment element is damaged after adjustment.

[0025] Figure 8 This is a cross-sectional view of the semiconductor device according to the first embodiment when determining the adjustment abnormality.

[0026] Figure 9 These are other cross-sectional views when determining the adjustment anomaly of the semiconductor device according to the first embodiment.

[0027] Figure 10 This is a flowchart of the adjustment process of the semiconductor device manufacturing method according to the first embodiment.

[0028] Figure 11 This is a flowchart of the adjustment anomaly determination process in the semiconductor device manufacturing method according to the first embodiment.

[0029] Figure 12 This is a cross-sectional view of the semiconductor device according to the second embodiment before adjustment.

[0030] Figure 13 This is a cross-sectional view of the semiconductor device according to the second embodiment when determining the adjustment abnormality.

[0031] Figure 14 These are other cross-sectional views when determining the adjustment anomaly of the semiconductor device according to the second embodiment.

[0032] Figure 15 This is a cross-sectional view of the semiconductor device according to the third embodiment before adjustment.

[0033] Figure 16 This is a cross-sectional view of the semiconductor device according to the third embodiment when determining the adjustment abnormality.

[0034] Figure 17 These are other cross-sectional views when determining the adjustment anomaly of the semiconductor device according to the third embodiment.

[0035] Figure 18This is a circuit diagram of the adjustment circuit of the semiconductor device according to the fourth embodiment.

[0036] Figure 19 This is a cross-sectional view of the semiconductor device according to the fourth embodiment before adjustment.

[0037] Figure 20 This is a modified cross-sectional view of the semiconductor device according to the fourth embodiment.

[0038] Figure 21 This is a cross-sectional view of the semiconductor device according to the fourth embodiment when determining the adjustment abnormality.

[0039] Figure 22 These are other cross-sectional views when determining the adjustment anomaly of the semiconductor device according to the fourth embodiment.

[0040] Figure 23 This is a cross-sectional view of the semiconductor device according to the fifth embodiment before adjustment.

[0041] Figure 24 This is a cross-sectional view of the semiconductor device according to the fifth embodiment when determining the adjustment abnormality.

[0042] Figure 25 These are other cross-sectional views when determining the adjustment anomaly of the semiconductor device according to the fifth embodiment.

[0043] Figure 26 This is a cross-sectional view of the semiconductor device according to the sixth embodiment before adjustment.

[0044] Figure 27 This is a cross-sectional view of the semiconductor device according to the sixth embodiment when determining the adjustment abnormality.

[0045] Figure 28 These are other cross-sectional views of the semiconductor device according to the sixth embodiment when determining adjustment abnormalities.

[0046] Explanation of reference numerals in the attached figures

[0047] 1: Semiconductor substrate; 2: Insulating film (field insulating film); 3: Adjustment element (fuse resistor); 3a: Gap; 4: Insulating film (interlayer insulating film); 5a: First contact area; 5b: Second contact area; 6a: First wiring; 6b: Second wiring; 6c: Auxiliary wiring; 7: Insulating film (protective insulating film); 11: Semiconductor substrate; 12: Semiconductor region; 21: Semiconductor substrate; 22: First semiconductor region; 23: Second semiconductor region; 24: Insulating film (field insulating film); 25a: First contact area; 25b: Second contact area; 26a: First wiring; 26b: Second wiring; 26c: Auxiliary wiring; 28: Metal; 31: Semiconductor substrate; 32: First semiconductor region; 33: Second semiconductor region; 101: Semiconductor device; 102: Internal circuit; 103: Adjustment circuit; 200: Adjustment pad; 201: Power terminal; 202: Output terminal; 203: Ground terminal; 204: Pad terminal; 205: Substrate terminal; R1: Protection resistor; R2: Protection resistor; D0: Adjustment element (Zener breakdown diode); D1: Protection diode. Detailed Implementation

[0048] The first to sixth embodiments of the present invention will now be described with reference to the accompanying drawings. In the drawings, identical or similar parts are labeled with the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may sometimes differ from actual conditions. Furthermore, the drawings may include parts with different dimensional relationships or ratios. Additionally, the first to sixth embodiments shown below are illustrative of apparatuses and methods for embodying the technical concept of the present invention; the technical concept of the present invention does not specify the material, shape, structure, or arrangement of structural components as described below.

[0049] Furthermore, the definitions of directions such as up and down in the following description are merely for ease of explanation and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° and observed, the term "up and down" becomes "left and right," and if the object is rotated 180° and observed, the term "up and down" will be reversed, which is perfectly reasonable.

[0050] Furthermore, in the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type is illustrated illustratively. However, the conductivity types can also be chosen in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Additionally, the "+" and "-" notations attached to "n" and "p" indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without "+" and "-" notations, respectively. However, even semiconductor regions labeled with the same "n" and "n" do not necessarily mean that the impurity concentrations of each semiconductor region are strictly the same. Furthermore, in the following description, unless otherwise explicitly stated, components and regions defined by "first conductivity type" and "second conductivity type" refer to components and regions made of semiconductor material, which is obvious both technically and logically.

[0051] (First Implementation)

[0052] Semiconductor Devices

[0053] like Figure 1 As shown, the semiconductor device 101 according to the first embodiment has an internal circuit 102 and a tuning circuit 103 connected to the internal circuit 102 on the same substrate. The internal circuit 102 may have, for example, a vertical transistor such as an insulated gate bipolar transistor (IGBT) and a control circuit for controlling the vertical transistor. The tuning circuit 103 adjusts for variations in the circuit characteristics of the internal circuit 102.

[0054] like Figure 2 As shown, the adjustment circuit 103 includes a fusible resistor 3 that constitutes the adjustment element. For example, a polysilicon resistor made of a polysilicon film can be used as the fusible resistor 3. One end of the fusible resistor 3 is connected to the adjustment pad 200, one end of the protection resistor R1, and one end of the protection resistor R2, respectively.

[0055] The other end of the protection resistor R1 is connected to the power supply terminal 201. An internal power supply or similar source applies a first potential (power supply potential) VDD to the power supply terminal 201. The resistance value of the protection resistor R1 is higher than that of the protection resistor R2. Alternatively, a depletion-mode (normally open) MOS transistor can be used instead of the protection resistor R1.

[0056] The other end of the fusible resistor 3 is connected to the anode side of the protection diode D1 and the ground terminal 203. A second potential (ground potential) GND is applied to the ground terminal 203. The protection diode D1 is a Zener diode. The breakdown voltage Vz of the protection diode D1 is, for example, approximately 5V. The cathode side of the protection diode D1 is connected to the other end of the protection resistor R2 and the output terminal 202. The output value OUT is output to the outside from the output terminal 202.

[0057] Before adjustment of the fuse resistor 3, the terminals of the fuse resistor 3 are in a short-circuit state, and the output value OUT of the adjustment circuit 103 is a low (L) level (e.g., 0V). During adjustment, the adjustment potential is applied to the adjustment pad 200 from an external power supply, etc., and the fuse resistor 3 is melted by Joule heating. After adjustment of the fuse resistor 3, the terminals of the fuse resistor 3 change from a short-circuit state to an open-circuit state. The output value OUT of the adjustment circuit 103 is logically inverted, and a high (H) level (e.g., 5V) is output.

[0058] Figure 3 Shown in Figure 2 The top view of the peripheral portion of the fuse resistor 3 shown in the figure. Figure 4 Showing from Figure 3 The cross-sectional view obtained by observing along the AA direction. For example... Figure 3 and Figure 4 As shown, the semiconductor device according to the first embodiment includes a semiconductor substrate 1 of the first conductivity type (n-type), an insulating film (field insulating film) 2 disposed on the semiconductor substrate 1, and a fusible resistor 3 disposed on the field insulating film 2.

[0059] The semiconductor substrate 1 is connected to a substrate terminal 205 to which a third potential (reference potential) Vcc (e.g., around 13V) is applied. The semiconductor substrate 1 can be, for example, a semiconductor wafer made of silicon (Si) as the base material. Furthermore, in addition to the fusible resistor 3, a structure formed on the inside and above the semiconductor substrate 1 is also formed. Figure 1 The internal circuit 102 and the adjustment circuit 103 are shown in the figure, including various components such as IGBTs, MOS transistors, and diodes, but the figures are omitted.

[0060] like Figure 3 As shown, the central portion of the fusible resistor 3 has a narrower width than its two ends, and is the part that is melted during adjustment. The fusible resistor 3 in... Figure 3 The fuse resistor 3 has a symmetrical planar pattern, but it can also have an asymmetrical planar pattern. The planar pattern of the fuse resistor 3 is not particularly limited.

[0061] like Figure 3 and Figure 4 As shown, an insulating film (interlayer insulating film) 4 is disposed on the fusible resistor 3. A first wiring 6a is disposed on the interlayer insulating film 4, overlapping one end of the fusible resistor 3. The first wiring 6a is electrically connected to one end of the fusible resistor 3 via a first contact area 5a penetrating the interlayer insulating film 4. The first wiring 6a is connected to a pad terminal 204. The pad terminal 204 and... Figure 2 The repair pad 200 shown is connected, and voltage PAD is applied to the pad terminal 204 via the repair pad 200.

[0062] A second wiring 6b is disposed on the interlayer insulating film 4, overlapping the other end of the fusible resistor 3. The second wiring 6b is electrically connected to the other end of the fusible resistor 3 via a second contact area 5b penetrating the interlayer insulating film 4. The second wiring 6b is connected to a ground terminal 203 to which a ground potential GND is applied. An insulating film (protective insulating film) 7 is disposed on the first wiring 6a and the second wiring 6b. Furthermore, Figure 4 The text omits the part in the middle. Figure 3 The illustration shows the protective insulating film 7.

[0063] The material used for the fusible resistor 3 can be, for example, polycrystalline silicon with a high concentration of added impurities, polycrystalline silicon-metal silicide, or a metal. Examples of structures that constitute the polycrystalline silicon-metal silicide include titanium silicide (TiSi2), cobalt silicide (CoSi2), and tungsten silicide (WSi2). Furthermore, tantalum silicide (TaSi2), molybdenum silicide (MoSi), and nickel silicide (NiSi) can also be used as the polycrystalline silicon-metal silicide. In addition to aluminum (Al), gold (Au), and copper (Cu), high-melting-point metals such as platinum (Pt), titanium (Ti), and tungsten (W) can also be used as metals.

[0064] The materials used for the first wiring 6a, the second wiring 6b, the first contact area 5a, and the second contact area 5b can be metals such as aluminum (Al), copper (Cu), and tungsten (W). The materials of the first wiring 6a and the second wiring 6b can be the same as or different from the materials of the first contact area 5a and the second contact area 5b. There are no particular limitations on the number or arrangement of the first contact area 5a and the second contact area 5b.

[0065] Materials used for the field insulating film 2, the interlayer insulating film 4, and the protective insulating film 7 include, for example, silicon oxide film (SiO2 film), silicon nitride film (Si3N4 film), insulating film (TEOS film) formed by chemical vapor deposition (CVD) using tetraethyl orthosilicate (TEOS) gas of organosilicon compounds, silicon oxide film (SiO2 film) that does not contain phosphorus (P) and boron (B) and is called "NSG film", silicon oxide film with added phosphorus (PSG film), silicon oxide film with added boron (BSG film), silicon oxide film with added phosphorus and boron (BPSG film), or composite film obtained by combining multiple single-layer films selected from these single-layer films.

[0066] like Figure 5As shown, during the adjustment of the fusible resistor 3, an adjustment voltage, which is a voltage PAD, is applied from an external power source via the adjustment pad 200 and pad terminal 204. Joule heating is used to melt the central part of the fusible resistor 3, forming a gap 3a in the central part of the fusible resistor 3. The terminals of the fusible resistor 3 change from a short circuit state to an open circuit state.

[0067] After adjusting the fuse resistor 3, confirm whether the terminals of the fuse resistor 3 have become an open circuit. Specifically, by applying a check voltage lower than the adjustment voltage as a potential PAD to the adjustment pad 200 and pad terminal 204, it is confirmed that there is no current flowing between the pad terminal 204 and the ground terminal 205, thereby confirming that the terminals of the fuse resistor 3 have become an open circuit.

[0068] However, even when it can be confirmed that the terminals of the fusible resistor 3 are in an open circuit state, there are times when the periphery of the fusible resistor 3 is potentially damaged. For example, there may be cases where a portion of the polysilicon constituting the fusible resistor 3 is exposed on the upper surface of the interlayer insulating film 4, or where the field insulating film 2 develops cracks, causing the fusible resistor 3 to short circuit with the semiconductor substrate 1.

[0069] Figure 6 This is a cross-sectional image showing the adjusted fusible resistor 3 of the semiconductor device according to the first embodiment, with no damage around its periphery. On the other hand, Figure 7 This is a cross-sectional image showing damage around the adjusted fuse resistor 3 in the semiconductor device according to the first embodiment. Figure 7 As shown, when there is damage around the fusible resistor 3, sometimes a portion of the polysilicon constituting the fusible resistor 3 is exposed from the upper surface of the interlayer insulating film or short-circuited with the semiconductor substrate 1.

[0070] Potential damage to the periphery of the fusible resistor 3 may affect subsequent operation and durability, reducing long-term reliability. Therefore, in the first embodiment, potential damage to the periphery of the fusible resistor 3 is detected.

[0071] As a method for detecting potential damage around the fusible resistor 3, such as Figure 8As shown, a voltage is applied between the substrate terminal 205 and the pad terminal 204, and a galvanometer (not shown) or the like is used to measure the leakage current between the substrate terminal 205 and the pad terminal 204, thereby testing the insulation state between the substrate terminal 205 and the pad terminal 204. When no current flows between the substrate terminal 205 and the pad terminal 204, the semiconductor device is judged to be a qualified product (normal). On the other hand, when current flows between the substrate terminal 205 and the pad terminal 204, it is because the field insulation film 2 on the pad terminal 204 side has cracks or other damages, resulting in a short circuit between one end of the fuse resistor 3 on the pad terminal 204 side and the semiconductor substrate 1, so the semiconductor device is judged to be unqualified (abnormal).

[0072] And, as Figure 9 shown, a voltage is applied between the substrate terminal 205 and the ground terminal 203, and the leakage current between the substrate terminal 205 and the ground terminal 203 is measured, thereby testing the insulation state between the substrate terminal 205 and the ground terminal 203. When no current flows between the substrate terminal 205 and the ground terminal 203, the semiconductor device is judged to be a qualified product (normal). On the other hand, when current flows between the substrate terminal 205 and the ground terminal 203, it is because the field insulation film 2 on the ground terminal 203 side has cracks or other damages, resulting in a short circuit between the other end of the fuse resistor 3 on the ground terminal 203 side and the semiconductor substrate 1, so the semiconductor device is judged to be unqualified (abnormal).

[0073] <Manufacturing Method of Semiconductor Device>

[0074] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described. First, the internal circuit 102 and the trimming circuit 103 shown in Figure 1 are formed using a conventional semiconductor process. When forming the trimming circuit 103, as Figure 4 shown, a field insulation film 2 is formed on the semiconductor substrate 1 by thermal oxidation or chemical vapor deposition (CVD) method or the like. Then, a polysilicon film is deposited by CVD method or the like, and a part of the polysilicon film is selectively removed using photolithography technology and etching technology, thereby forming a fuse resistor 3 on the field insulation film 2.

[0075] Next, an interlayer insulating film 4 is formed on the fusible resistor 3 using CVD or similar methods, and through-holes are formed in the interlayer insulating film 4 using photolithography and etching techniques. Then, the through-holes in the interlayer insulating film 4 are filled using a metal film via sputtering or vapor deposition. Next, a portion of the metal film is removed using photolithography and etching techniques, thereby forming a first contact region 5a and a second contact region 5b filled in the through-holes in the interlayer insulating film 4, and a first wiring 6a and a second wiring 6b are formed on the interlayer insulating film 4. At this time, a portion of the metal film may also be formed... Figure 2 The repair pad 200 is shown in the diagram. Then, a protective insulating film 7 is deposited on the first wiring 6a and the second wiring 6b using methods such as CVD. Thus, Figure 3 as well as Figure 4 The construction of the semiconductor device according to the first embodiment shown is completed before adjustment.

[0076] Next, the adjustment process is carried out. (Refer to...) Figure 10 The flowchart below illustrates the detailed steps of the adjustment process. In step S1, it is confirmed whether the initial characteristics of the internal circuit 102 meet a predetermined threshold. In step S2, based on the confirmation result of the initial characteristics of the internal circuit 102, it is decided whether adjustment is required. If the initial characteristics of the internal circuit 102 meet the predetermined threshold, and therefore adjustment is deemed unnecessary, the process proceeds to step S8 to the next step. Conversely, if in step S2 the initial characteristics of the internal circuit 102 do not meet the predetermined threshold, and therefore adjustment is deemed necessary, the process proceeds to step S3.

[0077] In step S3, the fuse resistor 3 is adjusted. For example, an adjustment voltage, which is a voltage PAD, is applied from an external power source via the adjustment pad 200 and pad terminal 204, and the central part of the fuse resistor 3 is melted by Joule heating to form a gap 3a. The terminals of the fuse resistor 3 change from a short circuit state to an open circuit state.

[0078] In step S4, the characteristic value of the internal circuit 102 after adjusting the fuse resistor 3 is confirmed. In step S5, if the characteristic value of the internal circuit 102 does not meet the threshold, it is determined to be a defective product, and the process proceeds to step S6 to exclude it. On the other hand, in step S5, if the characteristic value of the internal circuit 102 meets the threshold, it is determined to be a qualified product, and the process proceeds to step S7 to determine whether there is any adjustment abnormality.

[0079] Reference Figure 11The flowchart below illustrates the detailed process of determining whether there is an adjustment anomaly in step S7. First, in step S71, a check voltage lower than the voltage during adjustment is applied as a voltage PAD from an external power source via the adjustment pad 200 and pad terminal 204. The current between the pad terminal 204 and the ground terminal 203 is measured to determine whether the terminals of the fusible resistor 3 are in an open-circuit state. If there is current flowing between the pad terminal 204 and the ground terminal 203, indicating that the terminals of the fusible resistor 3 are not in an open-circuit state, it is determined to be a defective product, and the process proceeds to step S6 to remove it. On the other hand, if in step S71 there is no current flowing between the pad terminal 204 and the ground terminal 203, indicating that the terminals of the fusible resistor 3 are in an open-circuit state, the process proceeds to step S72.

[0080] In step S72, potential damage around the fusible resistor 3 is detected. Specifically, such as... Figure 8 As shown, a test voltage lower than the repair voltage is applied between the substrate terminal 205 and the pad terminal 204, and the leakage current between the substrate terminal 205 and the pad terminal 204 is measured, thereby testing the insulation state between the substrate terminal 205 and the pad terminal 204. Furthermore, as... Figure 9 As shown, a voltage is applied between the substrate terminal 205 and the ground terminal 203, and the leakage current between the substrate terminal 205 and the ground terminal 203 is measured to test the insulation state between the substrate terminal 205 and the ground terminal 203. If there is no current flow between the substrate terminal 205 and the pad terminal 204, and between the substrate terminal 205 and the ground terminal 203, the semiconductor device is determined to be a qualified product (normal), and the process proceeds to step S8 to enter the next process.

[0081] On the other hand, in step S72, if there is current flowing between at least one of the substrate terminal 205 and the pad terminal 204 and between the substrate terminal 205 and the ground terminal 203, damage such as cracks in the field insulating film 2 causes a short circuit between the fusible resistor 3 and the semiconductor substrate 1. Therefore, the semiconductor device is determined to be defective (abnormal), and the process proceeds to step S6 to eliminate it.

[0082] According to the first embodiment, after adjusting the fuse resistor 3, the following steps are performed: Figure 8 The test of the insulation state between the substrate terminal 205 and the pad terminal 204 shown, and Figure 9 The insulation state test between the substrate terminal 205 and the ground terminal 203 shown can eliminate potential damage to the periphery of the fusible resistor 3 due to adjustment during the manufacturing process, thereby improving quality.

[0083] In addition, for implementation Figure 8The test of the insulation state between the substrate terminal 205 and the pad terminal 204 shown, and Figure 9 The test of the insulation state between the substrate terminal 205 and the ground terminal 203 shown has been described, but it is also possible to perform only one of these tests. Figure 8 The test of the insulation state between the substrate terminal 205 and the pad terminal 204 shown, and Figure 9 One of the tests on the insulation state between the substrate terminal 205 and the ground terminal 203 shown.

[0084] (Second Implementation)

[0085] Semiconductor Devices

[0086] The semiconductor device involved in the second embodiment and Figure 4 The difference between the semiconductor device involved in the first embodiment shown is that, as Figure 12 As shown, the interlayer insulating film 4 also has auxiliary wiring 6c arranged in a manner that overlaps with the central part of the fusible resistor 3.

[0087] The auxiliary wiring 6c is connected to the inspection pad 206 provided on the semiconductor substrate 1. During the adjusted test, an inspection potential V1 is applied to the inspection pad 206. The auxiliary wiring 6c can be made of the same material as the first wiring 6a and the second wiring 6b, or it can be made of a different material. Other structures of the semiconductor device according to the second embodiment are similar to... Figure 4 The semiconductor device involved in the first embodiment shown is the same, so repeated descriptions are omitted.

[0088] The semiconductor device according to the second embodiment, after adjustment of the fusible resistor 3, is able to... Figure 8 Similarly, in the test of the semiconductor device according to the first embodiment shown, a voltage is applied between the substrate terminal 205 and the pad terminal 204 to test the insulation state between the substrate terminal 205 and the pad terminal 204. Furthermore, it is possible to... Figure 9 Similarly, in the test of the semiconductor device according to the first embodiment shown, a voltage is applied between the substrate terminal 205 and the ground terminal 203 to perform a test of the insulation state between the substrate terminal 205 and the ground terminal 203.

[0089] Furthermore, in the semiconductor device according to the second embodiment, after adjusting the fusible resistor 3, as... Figure 13As shown, a voltage is applied between the grounding terminal 203 and the inspection pad 206 to test the insulation state between them. If no current flows between the grounding terminal 203 and the inspection pad 206, the semiconductor device according to the second embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the grounding terminal 203 and the inspection pad 206, it indicates damage such as cracks in the interlayer insulating film 4 on the grounding terminal 203 side, causing a short circuit between the auxiliary wiring 6c and the fusible resistor 3. Therefore, the semiconductor device according to the second embodiment is determined to be a defective product (abnormal).

[0090] And, as Figure 14 As shown, a voltage is applied between the pad terminal 204 and the inspection pad 206 to test the insulation state between them. If no current flows between the pad terminal 204 and the inspection pad 206, the semiconductor device according to the second embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the pad terminal 204 and the inspection pad 206, it indicates damage such as cracks in the interlayer insulating film 4 on the pad terminal 204 side, causing a short circuit between the auxiliary wiring 6c and the fusible resistor 3. Therefore, the semiconductor device according to the second embodiment is determined to be a defective product (abnormal).

[0091] In the semiconductor device manufacturing method according to the second embodiment, during the formation Figure 12 The first wiring 6a and the second wiring 6b shown also form an auxiliary wiring 6c, which is then connected to the inspection pad 206. Furthermore, in Figure 11 In step S72 of the adjustment anomaly determination shown, in addition to performing tests on the insulation state between the substrate terminal 205 and the pad terminal 204 and the insulation state between the substrate terminal 205 and the ground terminal 203, further steps are performed... Figure 13 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 14 The insulation condition between the pad 206 and the grounding terminal 203 shown in the figure can be tested.

[0092] Furthermore, in step S72, it is also possible that the implementation is not carried out. Figure 13 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 14 The test shown is for checking the insulation condition between the pad 206 and the grounding terminal 203, but only the two methods are performed. Figure 13 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 14The test shown is one of the tests for the insulation condition between the pad 206 and the ground terminal 203. Alternatively, one or both of the tests for the insulation condition between the substrate terminal 205 and the pad terminal 204 and the insulation condition between the substrate terminal 205 and the ground terminal 203 may not be performed.

[0093] According to the second embodiment, after adjusting the fuse resistor 3, the following steps are performed: Figure 13 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 14 The test shown examines the insulation condition between the solder pad 206 and the grounding terminal 203. This allows for the elimination of damage to the periphery of the fusible resistor 3 due to adjustments during the manufacturing process, thereby improving quality.

[0094] (Third Implementation)

[0095] Semiconductor Devices

[0096] The semiconductor device involved in the third embodiment and Figure 4 The difference between the semiconductor device involved in the first embodiment shown is that, as Figure 15 As shown, a semiconductor substrate 11 of the second conductivity type (p-type) is used. The semiconductor substrate 11 is connected to a substrate terminal 205 to which a third potential (ground potential) GND is applied. A semiconductor region 12 of the first conductivity type (n-type) is provided on the upper part of the semiconductor substrate 11. The n-type semiconductor region 12 is positioned directly below the fusible resistor 3.

[0097] Semiconductor region 12 is connected to inspection pad 207 provided on semiconductor substrate 11. During the adjusted test, an inspection potential V2 is applied to the inspection pad 207. Other structures of the semiconductor device according to the third embodiment are similar to... Figure 4 The semiconductor device involved in the first embodiment shown is the same, so repeated descriptions are omitted.

[0098] In the semiconductor device according to the third embodiment, such as Figure 16As shown, after adjusting the fusible resistor 3, a voltage is applied between the inspection pad 207 and the ground terminal 203 to test the insulation state between them. If no current flows between the inspection pad 207 and the ground terminal 203, the semiconductor device according to the third embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the inspection pad 207 and the ground terminal 203, it indicates damage such as cracks in the field insulating film 2 on the ground terminal 203 side, causing a short circuit between the fusible resistor 3 and the semiconductor region 12. Therefore, the semiconductor device according to the third embodiment is determined to be a defective product (abnormal).

[0099] And, as Figure 17 As shown, a voltage is applied between the pad terminal 204 and the inspection pad 207 to test the insulation state between them. If no current flows between the pad terminal 204 and the inspection pad 207, the semiconductor device according to the third embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the pad terminal 204 and the inspection pad 207, it indicates damage such as cracks in the field insulating film 2 on the pad terminal 204 side, causing a short circuit between the fusible resistor 3 and the semiconductor region 12. Therefore, the semiconductor device according to the third embodiment is determined to be a defective product (abnormal).

[0100] In the semiconductor device manufacturing method according to the third embodiment, in Figure 11 In step S72 shown, the implementation is performed. Figure 16 The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 17 The insulation condition between the pad terminal 204 and the inspection pad 207 shown can be tested.

[0101] According to the third embodiment, after adjusting the fuse resistor 3, the following steps are performed: Figure 16 The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 17 The test of the insulation state between the pad terminal 204 and the inspection pad 207 shown can eliminate the possibility of damage to the periphery of the fusible resistor 3 due to adjustment during the manufacturing process, thereby improving quality.

[0102] Furthermore, in the third embodiment, the implementation... Figure 16 The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 17 The test for the insulation condition between the pad terminal 204 and the inspection pad 207 has been described, but it is also possible to perform only one of the following: Figure 16The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 17 One of the tests for the insulation status between the pad terminal 204 and the inspection pad 207 shown.

[0103] (Fourth Implementation)

[0104] Semiconductor Devices

[0105] The semiconductor device involved in the fourth embodiment and Figure 2 The difference between the semiconductor device involved in the first embodiment shown is that, as Figure 18 As shown, the adjustment circuit 103 is a Zener breakdown adjustment circuit.

[0106] The adjustment circuit 103 has an adjustment element consisting of a Zener breakdown diode D0. The cathode side of the Zener breakdown diode D0 is connected to the adjustment pad 200 and one end of the protection resistor R1, respectively. The other end of the protection resistor R1 is connected to one end of the protection resistor R2, the output terminal 202, and the cathode side of the protection diode D1.

[0107] The other end of the protection resistor R2 is connected to the power supply terminal 201, where the first potential (power supply potential) VDD is applied. The resistance value of the protection resistor R2 is higher than that of the protection resistor R1. Alternatively, a depletion-mode (normally open) MOS transistor can be used instead of the protection resistor R2.

[0108] The anode side of the Zener breakdown diode D0 is connected to the anode side of the protection diode D1 and the ground terminal 203. A second potential (ground potential) GND is applied to the ground terminal 203. The protection diode D1 is composed of a Zener diode. The breakdown voltage Vz of the protection diode D1 is, for example, approximately 5V.

[0109] Before adjustment of the Zener diode D0, the cathode and anode of the Zener diode D0 are in an open-circuit state. An L level (e.g., 0V) is output from the output terminal 202 of the adjustment circuit 103 as the OUT output value. During adjustment, the adjustment voltage is applied from the adjustment pad 200, thereby using avalanche current to cause a short circuit at the pn junction of the Zener diode D0, changing the open-circuit state between the cathode and anode of the Zener diode D0 to a short circuit state. The output value OUT from the output terminal 202 of the adjustment circuit 103 is logically inverted, outputting an H level (e.g., 5V).

[0110] Figure 19 Shown in Figure 18 The diagram shows a cross-sectional view of the peripheral portion of the Zener breakdown diode D0. (See diagram for reference.) Figure 19As shown, the semiconductor device according to the fourth embodiment includes a semiconductor substrate 21 of a first conductivity type (n-type), a first semiconductor region 22 of a second conductivity type (p-type) disposed on the upper part of the semiconductor substrate 21, and a first conductivity type (n-type) region disposed on the upper part of the first semiconductor region 22. + The second semiconductor region 23 (of type p). It is composed of the first semiconductor region 22 of type p and n. + The second semiconductor region 23 of the type constitutes the Zener breakdown diode D0.

[0111] The semiconductor substrate 21 is connected to a substrate terminal 205 to which a third potential (reference potential) Vcc (e.g., around 13V) is applied. An insulating film (field insulating film) 24 is disposed on the semiconductor substrate 21. A first wiring 26a is disposed on the field insulating film 24, overlapping with the second semiconductor region 23. The first wiring 26a is electrically connected to the second semiconductor region 23 via a first contact region 25a penetrating the field insulating film 24. The first wiring 26a is connected to a pad terminal 204. The pad terminal 204 and... Figure 18 The repair pad 200 is connected and a potential is applied to the PAD.

[0112] A second wiring 26b is disposed on the field insulating film 24, overlapping the first semiconductor region 22. The second wiring 26b is electrically connected to the first semiconductor region 22 via a second contact region 25b penetrating the field insulating film 24. The second wiring 26b is connected to a ground terminal 203 to which a ground potential GND is applied. An insulating film (interlayer insulating film) 27 is disposed on the first wiring 26a and the second wiring 26b. Other structures of the semiconductor device according to the fourth embodiment are similar to those described in the previous embodiment. Figure 4 The semiconductor device involved in the first embodiment shown is the same, so repeated descriptions are omitted.

[0113] like Figure 20 As shown, during the adjustment of the Zener breakdown diode D0, a adjustment voltage PAD is applied from the pad terminal 204 to the ground terminal 203. Due to avalanche current, the pn junction of the Zener breakdown diode D0 short-circuits and is destroyed. The metal 28 constituting the wiring of the first contact area 25a and the second contact area 25b melts and enters the surface layer of the semiconductor substrate 21. The anode and cathode of the Zener breakdown diode D0 change from an open circuit state to a short circuit state. After the Zener breakdown diode D0 is adjusted, a check voltage lower than the adjustment voltage is applied from the pad terminal 204 to the ground terminal 203 to confirm whether the anode and cathode of the Zener breakdown diode D0 have become short-circuited.

[0114] However, even if it can be confirmed that the anode and cathode of the Zener breakdown diode D0 are in a short-circuit state, sometimes the area around the Zener breakdown diode D0 is potentially damaged. Therefore, in the fourth embodiment, potential damage around the Zener breakdown diode D0 is detected.

[0115] like Figure 21 As shown, after adjusting the Zener breakdown diode D0, a voltage is applied between the substrate terminal 205 and the pad terminal 204 to test the insulation state between the substrate terminal 205 and the pad terminal 204. If no current flows between the substrate terminal 205 and the pad terminal 204, the semiconductor device according to the fourth embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the substrate terminal 205 and the pad terminal 204, it indicates that the Zener breakdown diode D0 has been damaged, causing a short circuit between the substrate terminal 205 and the pad terminal 204; therefore, the semiconductor device according to the fourth embodiment is determined to be a defective product (abnormal).

[0116] And, as Figure 22 As shown, after adjusting the Zener breakdown diode D0, a voltage is applied between the substrate terminal 205 and the ground terminal 203 to test the insulation state between the substrate terminal 205 and the ground terminal 203. If no current flows between the substrate terminal 205 and the ground terminal 203, the semiconductor device according to the fourth embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the substrate terminal 205 and the ground terminal 203, it indicates that the Zener breakdown diode D0 has been damaged, resulting in a short circuit between the substrate terminal 205 and the ground terminal 203; therefore, the semiconductor device according to the fourth embodiment is determined to be a defective product (abnormal).

[0117] As a method for manufacturing a semiconductor device according to the fourth embodiment, preparation Figure 19 The n-type semiconductor substrate 21 is shown. Then, a p-type first semiconductor region 22 and an n-type semiconductor region 23 are formed on the semiconductor substrate 21 by ion implantation and heat treatment, etc. + The second semiconductor region 23 of the type is formed, thereby forming the Zener breakdown diode D0.

[0118] Subsequently, similar to the first embodiment, a field insulating film 24 is formed on the semiconductor substrate 21. Then, a first contact region 25a and a second contact region 25b are buried in the through-holes of the field insulating film 24, and a first wiring 26a and a second wiring 26b are formed on the field insulating film 24. Subsequently, an interlayer insulating film 27 is formed on the first wiring 26a and the second wiring 26b.

[0119] Moreover, in Figure 11 In step S72 of the adjustment anomaly determination shown, the implementation is as follows: Figure 21 The test of the insulation state between the substrate terminal 205 and the pad terminal 204 shown, and Figure 22 The insulation state between the substrate terminal 205 and the ground terminal 203 shown can be tested. Other processes in the semiconductor device manufacturing method according to the fourth embodiment are... Figure 10 as well as Figure 11 The manufacturing process of the semiconductor device involved in the first embodiment shown is the same.

[0120] According to the fourth embodiment, after adjusting the Zener breakdown diode D0, the following steps are performed: Figure 21 The test of the insulation state between the substrate terminal 205 and the pad terminal 204 shown, and Figure 22 The insulation state test between the substrate terminal 205 and the ground terminal 203 shown can eliminate the possibility of damage to the periphery of the Zener breakdown diode D0 due to adjustment during the manufacturing process, thereby improving quality.

[0121] In addition, for implementation Figure 21 The test of the insulation state between the substrate terminal 205 and the pad terminal 204 shown, and Figure 22 The test of the insulation state between the substrate terminal 205 and the ground terminal 203 shown has been described, but it is also possible to perform only one of these tests. Figure 21 The test of the insulation state between the substrate terminal 205 and the pad terminal 204 shown, and Figure 22 One of the tests on the insulation state between the substrate terminal 205 and the ground terminal 203 shown.

[0122] (Fifth Implementation)

[0123] Semiconductor Devices

[0124] The semiconductor device involved in the fifth embodiment and Figure 19 The difference between the semiconductor device involved in the fourth embodiment shown is that, as Figure 23 As shown, it also includes auxiliary wiring 26c disposed on the field insulating film 24.

[0125] The auxiliary wiring 26c is arranged to overlap with the pn junctions of the first semiconductor region 22 and the second semiconductor region 23. The auxiliary wiring 26c is connected to the inspection pad 206. During the adjusted test, an inspection potential V1 is applied to the inspection pad 206. The auxiliary wiring 26c may be made of the same material as the first wiring 26a and the second wiring 26b, or it may be made of a different material. Other structures of the semiconductor device according to the fifth embodiment are... Figure 19The semiconductor device involved in the fourth embodiment shown is the same, so repeated descriptions are omitted.

[0126] The semiconductor device according to the fifth embodiment, after adjustment of the Zener breakdown diode D0, is able to... Figure 21 Similarly, in the test of the semiconductor device according to the fourth embodiment shown, a voltage is applied between the substrate terminal 205 and the pad terminal 204 to test the insulation state between the substrate terminal 205 and the pad terminal 204. Furthermore, it is possible to... Figure 22 Similarly, in the test of the semiconductor device according to the fourth embodiment shown, a voltage is applied between the substrate terminal 205 and the ground terminal 203 to perform a test of the insulation state between the substrate terminal 205 and the ground terminal 203.

[0127] Furthermore, in the semiconductor device according to the fifth embodiment, after adjusting the Zener breakdown diode D0, as... Figure 24 As shown, a voltage is applied between the grounding terminal 203 and the inspection pad 206 to test the insulation state between them. If no current flows between the grounding terminal 203 and the inspection pad 206, the semiconductor device according to the fifth embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the grounding terminal 203 and the inspection pad 206, the field insulating film 24 is damaged, causing a short circuit between the auxiliary wiring 26c and the Zener breakdown diode D0. Therefore, the semiconductor device according to the fifth embodiment is determined to be a defective product (abnormal).

[0128] And, as Figure 25 As shown, a voltage is applied between the pad terminal 204 and the inspection pad 206 to test the insulation state between them. If no current flows between the pad terminal 204 and the inspection pad 206, the semiconductor device according to the fifth embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the pad terminal 204 and the inspection pad 206, the field insulating film 24 is damaged, causing a short circuit between the auxiliary wiring 26c and the Zener breakdown diode D0. Therefore, the semiconductor device according to the fifth embodiment is determined to be a defective product (abnormal).

[0129] In the semiconductor device manufacturing method according to the fifth embodiment, in Figure 11 In step S72 shown, further implementation is also performed. Figure 24 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 25The insulation condition between the pad 206 and the grounding terminal 203 shown in the diagram can be tested. Other processes in the semiconductor device manufacturing method according to the fifth embodiment are the same as those in the semiconductor device manufacturing method according to the fourth embodiment.

[0130] According to the fifth embodiment, after adjusting the Zener breakdown diode D0, the following steps are performed: Figure 24 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 25 The test shown examines the insulation condition between the pad 206 and the ground terminal 203. This allows for the elimination of damage to the periphery of the Zener breakdown diode D0 due to adjustment during the manufacturing process, thereby improving quality.

[0131] Furthermore, in the fifth embodiment, the implementation... Figure 24 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 25 The test demonstrating the insulation condition between the pad 206 and the grounding terminal 203 has been described, but it may also be performed using only one of these methods. Figure 24 The test shown is for the insulation condition between pad 206 and pad terminal 204. Figure 25 The test shown is one of the tests for the insulation state between the pad 206 and the ground terminal 203. Alternatively, one or both of the tests for the insulation state between the substrate terminal 205 and the pad terminal 204, and between the substrate terminal 205 and the ground terminal 203, may not be performed.

[0132] (Sixth Implementation Method)

[0133] Semiconductor Devices

[0134] The semiconductor device involved in the sixth embodiment and Figure 19 The difference between the semiconductor device involved in the fourth embodiment shown is that, as Figure 26 As shown, a semiconductor substrate 31 using a second conductivity type (p-type) is employed. A first semiconductor region 32 of a first conductivity type (n-type) and a second conductivity type (p-type) region disposed on the upper part of the semiconductor substrate 31 are provided. + The second semiconductor region 33 (of type n). It is composed of the first semiconductor region 32 of type n and p... + The second semiconductor region 33 of the type constitutes the Zener breakdown diode D0.

[0135] The first wiring 26a is electrically connected to the first semiconductor region 32 via the first contact area 25a. The second wiring 26b is electrically connected to the second semiconductor region 33 via the second contact area 25b. The first semiconductor region 32 is connected to an inspection pad 207 disposed on the semiconductor substrate 31. During the adjusted test, an inspection potential V1 is applied to the inspection pad 207. Other structures of the semiconductor device according to the sixth embodiment are similar to those described in the sixth embodiment. Figure 19 The semiconductor device involved in the fourth embodiment shown is the same, so repeated descriptions are omitted.

[0136] In the semiconductor device according to the sixth embodiment, such as Figure 27 As shown, after adjusting the Zener breakdown diode D0, a voltage is applied between the test pad 207 and the ground terminal 203 to test the insulation state between them. If no current flows between the test pad 207 and the ground terminal 203, the semiconductor device according to the sixth embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the test pad 207 and the ground terminal 203, it indicates that the periphery of the Zener breakdown diode D0 is damaged, causing a short circuit between the Zener breakdown diode D0 and the first semiconductor region 32. Therefore, the semiconductor device according to the sixth embodiment is determined to be a defective product (abnormal).

[0137] And, as Figure 28 As shown, a voltage is applied between the pad terminal 204 and the inspection pad 207 to test the insulation state between them. If no current flows between the pad terminal 204 and the inspection pad 207, the semiconductor device according to the sixth embodiment is determined to be a qualified product (normal). On the other hand, if current flows between the pad terminal 204 and the inspection pad 207, the Zener breakdown diode D0 is damaged, causing a short circuit between the Zener breakdown diode D0 and the first semiconductor region 32. Therefore, the semiconductor device according to the sixth embodiment is determined to be a defective product (abnormal).

[0138] In the semiconductor device manufacturing method according to the sixth embodiment, in Figure 11 In step S72 shown, the implementation is performed. Figure 27 The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 28 The insulation state between the pad terminal 204 and the inspection pad 207 shown can be tested. Other processes in the semiconductor device manufacturing method according to the sixth embodiment are the same as those in the semiconductor device manufacturing method according to the fourth embodiment.

[0139] According to the sixth embodiment, after adjusting the Zener breakdown diode D0, the following steps are performed: Figure 27 The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 28 The test of the insulation state between the pad terminal 204 and the inspection pad 207 shown can eliminate the possibility of damage to the periphery of the Zener breakdown diode D0 due to adjustment during the manufacturing process, thereby improving quality.

[0140] Furthermore, in the sixth embodiment, the implementation... Figure 27 The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 28 The test for the insulation condition between the pad terminal 204 and the inspection pad 207 has been described, but it is also possible to perform only one of the following: Figure 27 The test shown is for inspecting the insulation condition between the solder pad 207 and the grounding terminal 203, and Figure 28 One of the tests for the insulation status between the pad terminal 204 and the inspection pad 207 shown.

[0141] (Other implementation methods)

[0142] As described above, the present invention has been described through the first to sixth embodiments, but it should not be construed as limiting the invention by the discussion and drawings that constitute a part of this disclosure. Based on this disclosure, those skilled in the art will recognize various alternative embodiments, examples, and application techniques.

[0143] For example, the first to sixth embodiments can be appropriately combined. For example, in Figure 15 In the third embodiment shown, it can be with Figure 12 Similarly, in the second embodiment shown, auxiliary wiring is provided on the interlayer insulating film 4, and the auxiliary wiring is connected to the inspection pad. In this case, it is possible to perform tests on the insulation state between the inspection pad and the pad terminal 204, as well as tests on the insulation state between the inspection pad and the ground terminal 203.

[0144] In addition, Figure 26 In the sixth embodiment shown, it can be combined with Figure 23 Similarly, in the fifth embodiment shown, auxiliary wiring is provided on the field insulating film 24, and the auxiliary wiring is connected to the inspection pad. In this case, it is possible to perform tests on the insulation state between the inspection pad and the pad terminal 204, as well as tests on the insulation state between the inspection pad and the ground terminal 203.

[0145] In addition, in the first to third embodiments, the method for adjusting the fuse resistor 3 constituting the adjusting element is to apply a voltage between the terminals of the fuse resistor 3 to fuse it using Joule heating. However, laser adjustment that cuts the fuse resistor by laser irradiation can also be used.

[0146] Thus, once the spirit of the technical content disclosed in the above embodiments is understood, those skilled in the art will realize that the present invention can include various alternative embodiments, examples, and application techniques. Furthermore, it is self-evident that the present invention includes various embodiments not described herein, such as structures obtained by arbitrarily applying the structures described in the above embodiments and variations. Therefore, the technical scope of the present invention is determined solely by the inventive features covered by the appropriate claims based on the illustrative descriptions above.

Claims

1. A semiconductor device, characterized by comprising: have: Adjustment elements are disposed inside or above a semiconductor substrate; An insulating film disposed on the adjustment element; A first wiring is disposed on the insulating film and connected to one end of the adjustment element via a first contact area penetrating the insulating film; A second wiring is disposed on the insulating film and connected to the other end of the adjustment element via a second contact area penetrating the insulating film; as well as An auxiliary wiring is disposed on the insulating film at a position overlapping the central portion of the adjustment element, and the auxiliary wiring is connected to only one inspection pad.

2. The semiconductor device according to claim 1, characterized in that, After the adjustment element is adjusted, an insulation test is performed between the auxiliary wiring and the first wiring or the second wiring.

3. The semiconductor device according to claim 1 or 2, characterized in that, The adjustment element is composed of a fusible resistor disposed above the semiconductor substrate through an insulating film.

4. The semiconductor device according to claim 1 or 2, characterized in that, The adjustment element is composed of a Zener diode disposed inside the semiconductor substrate.

5. A method for manufacturing a semiconductor device, characterized by The process includes the following steps: Adjustment elements are formed inside or on top of a semiconductor substrate; An insulating film is formed on the adjustment element; A first wiring is formed on the insulating film to connect to one end of the adjustment element via a first contact area penetrating the insulating film; A second wiring is formed on the insulating film to connect to the other end of the adjustment element via a second contact area penetrating the insulating film; The adjustment element is adjusted; as well as After the adjustment process, an insulation test is performed between the semiconductor substrate and the first wiring or the second wiring. In the process of conducting the insulation state test, the insulation state test is performed between the substrate terminal connected to the lower surface of the semiconductor substrate and the first wiring or the second wiring.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, In the process of conducting the insulation state test, the insulation state between the inspection pad connected to the upper surface of the semiconductor substrate and the first wiring or the second wiring is tested.

7. The method for manufacturing a semiconductor device according to claim 5 or 6, wherein It also includes the following processes: An auxiliary wiring is formed on the insulating film at a position overlapping with the central portion of the adjustment element; as well as After the adjustment process, an insulation test is performed between the auxiliary wiring and the first wiring or the second wiring.

8. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that, The adjustment element is composed of a fusible resistor disposed above the semiconductor substrate through an insulating film.

9. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that, The adjustment element is composed of a Zener diode disposed inside the semiconductor substrate.

10. A method of manufacturing a semiconductor device, characterized by The process includes the following steps: Adjustment elements are formed inside or on top of a semiconductor substrate; An insulating film is formed on the adjustment element; A first wiring is formed on the insulating film to connect to one end of the adjustment element via a first contact area penetrating the insulating film; A second wiring is formed on the insulating film to connect to the other end of the adjustment element via a second contact area penetrating the insulating film; The adjustment element is adjusted; as well as After the adjustment process, an insulation test is performed between the semiconductor substrate and the first wiring or the second wiring. The manufacturing method further includes the following steps: An auxiliary wiring is formed on the insulating film at a position overlapping with the central portion of the adjustment element; as well as After the adjustment process, an insulation test is performed between the auxiliary wiring and the first wiring or the second wiring.

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