Semiconductor device package and semiconductor device package alignment inspection method

Abstract

A semiconductor device package is provided. The semiconductor device package includes a substrate having a central region and a periphery surrounding the central region, and an electronic component disposed on the substrate. The substrate includes a plurality of test contacts disposed within the periphery and spaced apart from one another. The electronic component includes a dummy pad. The dummy pad covers two of the plurality of test contacts and is laterally spaced apart from other ones of the plurality of test contacts. A semiconductor device package alignment inspection method is also provided.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device package and a method for checking the alignment of semiconductor device packages. Background Technology

[0002] Conductive pillars (e.g., copper (Cu) pads, pillars, or bumps) are commonly used as interconnects in semiconductor structures. As the spacing of conductive pads decreases further to accommodate the increasing number of I / Os, checking interconnect alignment becomes more challenging. Summary of the Invention

[0003] In one or more embodiments, this disclosure provides a semiconductor device package. The semiconductor device package includes: a substrate having a central region and a periphery surrounding the central region; and an electronic component disposed on the substrate. The substrate includes a plurality of test contacts disposed within the periphery and spaced apart from each other. The electronic component includes dummy pads. The dummy pads cover two of the plurality of test contacts and are laterally spaced from the other test contacts.

[0004] In one or more embodiments, this disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate having a central region and a periphery surrounding the central region. The semiconductor device package further includes a first test contact, a second test contact, and a third test contact, the first test contact, the second test contact, and the third test contact being disposed within the periphery of the first substrate and spaced apart from each other. The semiconductor device package further includes a second substrate and a first dummy pad, the second substrate being disposed on the first substrate, the first dummy pad being exposed from a surface of the second substrate. The first dummy pad contacts the first test contact and the second test contact and is laterally spaced from the third test contact.

[0005] In one or more embodiments, this disclosure provides a method for aligning semiconductor device packages. The method includes providing a first substrate and a second substrate. The first substrate includes a first dummy pad and a second dummy pad, and the second substrate includes a first set of test contacts adjacent to the first dummy pad and a second set of test contacts adjacent to the second dummy pad. The method further includes obtaining first electrical information between the first set of test contacts and obtaining second electrical information between the second set of test contacts. The method further includes determining the relative position between the first substrate and the second substrate based on the first electrical information and the second electrical information. Attached Figure Description

[0006] When with attachment Figure 1When reading the following detailed description, various aspects of this disclosure can be readily understood. It should be noted that the various features may not necessarily be drawn to scale. For clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a cross-sectional view of a substrate and electronic components according to embodiments of the present disclosure.

[0008] Figure 2A This is a cross-sectional view of a semiconductor device package according to an embodiment of the present disclosure.

[0009] Figure 2B This is a cross-sectional view of a substrate and electronic components according to embodiments of the present disclosure.

[0010] Figure 3A This is a top view of an electronic component according to an embodiment of the present disclosure.

[0011] Figure 3B This is a top view of a substrate according to an embodiment of the present disclosure.

[0012] Figure 4 This is a perspective top view of a portion of a semiconductor device package according to an embodiment of the present disclosure.

[0013] Figure 5A This is a perspective top view of a portion of a semiconductor device package according to an embodiment of the present disclosure.

[0014] Figure 5B This is a cross-sectional view of a portion of a semiconductor device package according to an embodiment of the present disclosure.

[0015] Figure 6 This is a flowchart of a semiconductor device package alignment inspection method according to some embodiments of the present disclosure.

[0016] Figure 7 This is a table showing the predetermined relative positions of a substrate and electronic components based on the electrical state of test contacts according to some embodiments of this disclosure.

[0017] Figure 8A One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present disclosure are shown.

[0018] Figure 8B One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present disclosure are shown.

[0019] Figure 8C One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present disclosure are shown.

[0020] Throughout the accompanying drawings and detailed description, common reference numerals are used to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0023] Figure 1 This is a cross-sectional view of the substrate 10 and electronic component 11 according to an embodiment of the present disclosure. Figure 2A A cross-sectional view is shown after the electronic component 11 is bonded to the substrate 10 to form the semiconductor device package 1.

[0024] In some embodiments, substrate 10 may be, for example, a semiconductor substrate, such as a silicon substrate or another suitable semiconductor substrate. In some embodiments, substrate 10 may be a semiconductor wafer, such as a silicon wafer, and may contain a plurality of semiconductor chips.

[0025] Substrate 10 includes a surface 101 and a surface 102 opposite to surface 101. In some embodiments, surface 101 is an active surface and surface 102 is a passive surface or a back-side surface. Conductive element 10c and a plurality of test contacts p1 to p6 (collectively referred to as test contacts 10p1 and 10p2) may be close to, adjacent to, embedded in, and / or partially exposed from surface 101. Test contacts 10p2 (which have a plurality of test contacts) may be positioned diagonally or oppositely to test contacts 10p1. For example, test contacts 10p1 and 10p2 may be positioned at opposite corners of substrate 10. For simplicity, each test contact in test contacts 10p2 is not labeled in the figures.

[0026] The substrate 10 includes an inner region (or central region, conductive region) r1 and an outer region (or periphery, test region) r2 surrounding the inner region r1. A conductive element 10c is disposed in or within the inner region r1. Test contacts 10p1 and 10p2 are disposed in or within the outer region r2.

[0027] In other words, the conductive element 10c is placed in a space made of Figure 1 The area defined or enclosed by the dashed lines. The conductive element 10c is surrounded by test contacts 10p1 and 10p2.

[0028] Conductive element 10c is insulated from test contacts 10p1 and 10p2 by, for example, one or more organic materials (such as welding masks, polyimide (PI), epoxy resin, Ajinomoto laminate (ABF), polypropylene (PP), and bismaleimide triazine (BT)), one or more inorganic materials (such as silicon dioxide (SiO2)). x ), silicon nitride (SiN) x ), tantalum oxide (TaO) x ( ), silicon, glass, ceramics and quartz, or a combination of two or more of them.

[0029] Each of the conductive element 10c and the test contacts 10p1 and 10p2 can be a conductive pad, a conductive trace, or a conductive post. Each of the conductive element 10c and the test contacts 10p1 and 10p2 can contain, for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), palladium (Pd), another metal, a solder alloy, or a combination of two or more of these.

[0030] Electronic component 11 may be a chip or die, and the electronic component includes a semiconductor substrate, one or more integrated circuit devices and one or more overlay interconnect structures thereon.

[0031] Electronic component 11 includes a surface 111 facing the substrate 10 and a surface 112 opposite to the surface 111. In some embodiments, surface 111 is an active surface and surface 112 is a passive surface or a back-side surface. Conductive elements 11c and dummy pads 11p1 and 11p2 may be close to, adjacent to, embedded in, and / or partially exposed from the surface 111. Dummy pad 11p1 corresponds to the placement of test contact 10p1. Dummy pad 11p2 corresponds to the placement of test contact 10p2. Dummy pad 11p1 may be positioned diagonally or oppositely to dummy pad 11p2. For example, dummy pads 11p1 and dummy pad 11p2 may be positioned at opposite corners of electronic component 11.

[0032] Similarly, electronic component 11 includes an inner region (or central region, conductive region) r1 and an outer region (or periphery, test region) r2 surrounding the inner region r1. Conductive elements 11c are disposed in or within the inner region r1. Dummy pads 11p1 and 11p2 are disposed in or within the outer region r2. In some embodiments, electronic component 11 may be a semiconductor wafer, such as a silicon wafer, and includes multiple semiconductor chips. In such embodiments, dummy pads 11p1 and 11p2 are disposed on the periphery of the semiconductor wafer.

[0033] In other words, the conductive element 11c is placed in a space made of Figure 1 Within the area defined or enclosed by the dashed lines, conductive element 11c is surrounded by dummy pads 11p1 and 11p2. Conductive element 11c is insulated from dummy pads 11p1 and 11p2.

[0034] Each of the conductive element 11c and the dummy pads 11p1 and 11p2 can be a conductive pad, a conductive trace, or a conductive post. Each of the conductive element 11c and the dummy pads 11p1 and 11p2 can contain the materials listed above for the conductive element 10c and the test contacts 10p1 and 10p2.

[0035] like Figure 1 As shown, conductive elements 10c and 11c to be connected are aligned. After alignment, electronic component 11 is bonded to or mounted on substrate 10, thereby forming as shown. Figure 2A The semiconductor device package 1 shown.

[0036] exist Figure 2A In this configuration, the substrate 10 and electronic components 11 (e.g., conductive elements 10c and 11c) are aligned and connected to each other. For example, the relative positions between the substrate 10 and electronic components 11 are within design specifications. In other words, the relative displacement (e.g., rotation or offset) between the substrate 10 and electronic components 11 is within design specifications.

[0037] The alignment between substrate 10 and electronic component 11 (e.g., alignment between conductive element 10c and conductive element 11c) can be checked by measuring the conductivity (e.g., open circuit or short circuit) between dummy pad 11p1 (or dummy pad 11p2) and one of test contacts p1 to p6; and / or by measuring the conductivity of two test contacts among test contacts p1 to p6. (The remaining text appears to be unrelated and likely refers to further details about alignment.) Figure 6 and Figure 7 Describe the detailed operation and standards of alignment checking methods.

[0038] like Figure 2AAs shown, when the relative position between the substrate 10 and the electronic component 11 is within the design specifications, the dummy pad 11p1 of the electronic component 11 contacts the test contacts p1 and p2 of the substrate 10, but does not contact the test contacts p3 to p6. For example, the dummy pad 11p1 may conduct electricity with the test contacts p1 and p2 but insulate against the test contacts p3 to p6. For example, the dummy pad 11p1 may be short-circuited with the test contacts p1 and p2 but form an open circuit with the test contacts p3 to p6. For example, the test contacts p3 to p6 may be floating.

[0039] For example, dummy pad 11p1 covers or overlaps with test contacts p1 and p2 (see reference). Figure 4 For example, dummy pad 11p1 is laterally spaced from test contacts p3 to p6. For example, dummy pad 11p1 is not connected to test contacts p3 to p6.

[0040] Similarly, the dummy pad 11p2 of the electronic component 11 contacts two of the test contacts 10p2 of the substrate 10 but does not contact the other test contacts 10p2.

[0041] X-ray or optical microscopes are well-known tools for alignment checks, but they require sample preparation, which is time-consuming, and have limited resolution, which may affect the accuracy of displacement information.

[0042] The purpose of this disclosure is to provide a method that allows for accurate alignment checks and displacement determination. This disclosure eliminates the need for sample preparation, and electrical conductivity (e.g., open or short circuit) can represent the relative displacement between the substrate and the electronic component. Furthermore, the methods used in this disclosure are not limited by package size and can detect displacements at the micrometer or nanometer scale.

[0043] Figure 3A This is a top view of electronic component 11 according to an embodiment of the present disclosure. Figure 3B This is a top view of substrate 10 according to an embodiment of the present disclosure. Figure 4 A perspective top view is shown after the electronic component 11 has been bonded to the substrate 10. Figure 2A The semiconductor device package 1 in the text can be Figure 4 A cross-sectional view of a semiconductor device package.

[0044] like Figure 4 As shown, test contacts (such as test contacts p1 to p6) are disposed in the periphery of the surface 101 of the substrate 10. Dummy pads 11p1 and 11p2 (located diagonally on the surface 111 of the electronic component 11) cover two of the test contacts (such as test contacts p1 and p2).

[0045] Test contact p1 has a portion p1b covered by dummy pad 11p1 and a portion p1a connected to portion p1b. Portion p1a is exposed from the projection area of ​​electronic component 11. Similarly, test contact p2 has a portion p2b covered by dummy pad 11p1 and a portion p2a connected to portion p2b. Portion p2a is exposed from electronic component 11. If portions p1b and p2b are in contact with dummy pad 11p1, they can form a short circuit. If at least one portion of portions p1b and p2b is not in contact with dummy pad 11p1, they can form an open circuit. In some embodiments, portions p1a and p2a can be energized to determine whether portions p1b and p2b are conductive.

[0046] Test contacts p3 to p6 are spaced apart from dummy pad 11p1. Test contacts p3 to p6 surround dummy pad 11p1. Test contacts p3 to p6 are positioned adjacent to the corners of dummy pad 11p1. Test contacts p3 to p6 follow the contour of the side of dummy pad 11p1. Each test contact p3 to p6 has a portion close to dummy pad 11p1 and a portion away from dummy pad 11p1. Taking test contact p3 as an example, test contact p3 has a portion p3b and a portion p3a connected to portion p3b. Portion p3b overlaps with the projected area of ​​electronic component 11. Portion p3a is exposed from the projected area of ​​electronic component 11.

[0047] If any two test contacts p3 to p6 come into contact with the dummy pad 11p1, then the two test contacts can form a short circuit. Similarly, a portion exposed from the projected area of ​​the electronic component 11 (such as portion p3a) can be energized to determine whether any two test contacts p3 to p6 are conductive.

[0048] In some embodiments, the projected area of ​​the dummy pad 11p1 may differ from the projected area of ​​the test contacts p1, p2, p3, p4, p5, and / or p6. In some embodiments, the projected area of ​​a portion of test contact p1a may be substantially similar to the projected area of ​​a portion of test contact p1b. Similarly, the projected area of ​​a portion of test contact p2a may be substantially similar to the projected area of ​​a portion of test contact p2b. In some embodiments, the projected area of ​​a portion of test contact p3a (or a portion of test contact p4a, a portion of test contact p5a, or a portion of test contact p6a) may be substantially similar to the projected area of ​​a portion of test contact p3b (or a portion of test contact p4b, a portion of test contact p5b, or a portion of test contact p6b). In some embodiments, the projected areas may be substantially parallel to the surface 101 of the substrate 10.

[0049] In some embodiments, the interval (or shortest distance) between the dummy pad 11p1 and one of the test contacts p1 to p6 may differ from the interval (or shortest distance) between the dummy pad 11p1 and the other of the test contacts p1 to p6. For example, the interval between the dummy pad 11p1 and a portion p3b of the test contact p3 may differ from the interval between the dummy pad 11p1 and a portion p4b of the test contact p4. In some embodiments, the aforementioned interval may be measured in a direction substantially parallel to the surface 101 of the substrate 10.

[0050] In some embodiments, the semiconductor device package according to this disclosure may have any number of dummy pads and test contacts, depending on design requirements, and is not limited to the specific embodiments shown in the figures. For example, the number of test contacts may be N, where N is an integer greater than 1.

[0051] In addition, the projected area and shape of dummy pads and test contacts (such as...) Figure 7 The squares or circles shown, the spacing and positioning can be modified according to design requirements and are not limited to the specific embodiments shown in the figures.

[0052] Figure 5A This is a perspective top view of a portion of a semiconductor device package 2 according to an embodiment of the present disclosure. Figure 5B The semiconductor device package 2 in the middle can be Figure 5A A cross-sectional view of semiconductor device package 2 in the image. Figure 5A and 5B Semiconductor device package 2 in the middle is similar to Figure 2A The semiconductor device package 1 is described below, and the differences therebetween are also described below.

[0053] In semiconductor device package 2, portions p1a and p1b of test contacts p1 are connected by a trace p1w disposed at a height position different from that of portions p1a and p1b. In some embodiments, the trace p1w may be part of a redistribution layer (RDL) or may be formed together with the RDL. In some embodiments, the yield of the manufacturing process of semiconductor device package 2 is higher than that of the manufacturing process of semiconductor device package 1.

[0054] Return to reference Figure 2B , Figure 2B A cross-sectional view of a semiconductor device package 1' according to some embodiments of the present disclosure is shown. Figure 2B Semiconductor device package 1' is similar to Figure 2A The semiconductor device package 1 is described below, and the differences therebetween are also described below.

[0055] like Figure 2B As shown, surface 102 of substrate 10 (which may be a passive surface or a back surface) faces surface 111 of electronic component 11 (which may be an active surface). Test contacts 10p1 and 10p2 are positioned close to surface 102, adjacent to surface 102, embedded in surface 102, and / or partially exposed from surface 102.

[0056] The substrate 10 includes conductive vias 10v1 and 10v2 electrically connected between conductive element 10c and conductive element 11c.

[0057] Using the structure of semiconductor device package 1' (where substrate 10 faces down), more than two substrates (or electronic components, wafers, or combinations thereof) can be stacked together. In some embodiments, test contacts and dummy pads can be formed in a structure where more than two substrates (or electronic components, wafers, or combinations thereof) are stacked together, and each substrate can be in a face-down or face-up configuration, depending on design specifications. Additionally, the test contacts and dummy pads in each substrate can be positioned close to either the passive or active surface.

[0058] Figure 6 This is a flowchart of a semiconductor device package alignment inspection method according to some embodiments of the present disclosure. Figure 7 This is a table showing the predetermined relative positions of a substrate and electronic components according to the electrical state of test contacts, based on some embodiments of this disclosure.

[0059] refer to Figure 6 In operation S60, the electronic component is connected to (or bonded to) the substrate (e.g., bonding electronic component 11 to substrate 10, such as...). Figure 1(As shown). In some embodiments, the method can be performed on other structures, such as electronic components on another electronic component, electronic components on a wafer, substrates on a substrate, or other combinations thereof.

[0060] Then, the method proceeds to operation s61, determining whether the dummy pad 11p1 of the electronic component 11 is conductive (or in contact) with the test contacts p1 and p2 of the substrate 10. In some embodiments, this determination can be made, for example, by energizing the test contacts p1 and p2 and detecting electrical information (such as voltage and / or resistance) and / or electrical states (e.g., conductivity, such as short circuit or open circuit). For example, a short circuit between test contacts p1 and p2 can indicate conductivity between test contacts p1 and p2 through the dummy pad 11p1, and therefore it can be determined that the dummy pad 11p1 is conductive with the test contacts p1 and p2.

[0061] Referring to operation s62, it is detected whether the dummy pad 11p1 is insulated from one or more sets of test contacts of the substrate 10 to obtain one or more electrical information. In some embodiments, it can be detected whether the dummy pad 11p1 is insulated from one or more sets of test contacts of the substrate 10 located adjacent to the corner of the dummy pad 11p1. For example, it is detected whether the dummy pad 11p1 of the electronic component 11 is insulated from the set of test contacts p6 and p5 of the substrate 10 (e.g., insulated from portions of p6b and p5b). In some embodiments, this can be determined and detected, for example, by energizing the test contacts p6 and p5 and detecting the electrical information (e.g., voltage and / or resistance) and / or electrical state (e.g., conductivity, such as short circuit or open circuit). An open circuit between test contacts p6 and p5 means that the dummy pad 11p1 is insulated from the set of test contacts p6 and p5. A short circuit between test contact p6 and test contact p5 means that the dummy pad 11p1 is conductive (or in contact) with the set of test contacts p6 and p5.

[0062] Similar operations can be performed on other groups of test contacts. For example, it can be detected whether the dummy pad 11p1 of electronic component 11 is insulated from the "test contact groups p5 and p4", "test contact groups p4 and p3", and "test contact groups p3 and p6" of substrate 10. For example, it can be detected whether the dummy pad 11p1 of electronic component 11 is insulated from the "partial p5b and p4b", "partial p4b and p3b", and "partial p3b and p6b" of substrate 10. In some embodiments, detection can be performed between the dummy pad 11p1 of electronic component 11 and four groups of test contacts of substrate 10. In other embodiments, detection can be performed between the dummy pad 11p1 of electronic component 11 and N groups of test contacts, where N is an integer equal to or greater than 1, depending on different design specifications.

[0063] In some embodiments, similar operations to those performed on dummy pads 11p1 as shown in operations s61 and s62 are performed on dummy pads 11p2 of electronic component 11 to obtain one or more electrical information.

[0064] Referring to operation s63, the relative position between the electronic component 11 and the substrate 10 is determined (or obtained) based on the electrical information between the dummy pads 11p1 and 11p2 of the electronic component 11 and the set of test contacts of the substrate 10.

[0065] In some embodiments, if an open circuit is detected between test contacts (such as test contacts p3 to p6) in all groups of dummy pads 11p1 and 11p2, it is determined that there is no offset or rotation between electronic component 11 and substrate 10, or that the offset or rotation between electronic component 11 and substrate 10 is within a predetermined value or within the design specifications.

[0066] In some embodiments, such as Figure 7 As shown, the electronic component 11 is determined to be offset upwards by approximately 5 micrometers (μm) relative to the substrate 10 under the following conditions: an open circuit is detected between test contact groups "test contact p6 and test contact p5", between test contact groups "test contact p4 and test contact p3", and between test contact groups "test contact p3 and test contact p6" of dummy pads 11p1 and 11p2, and a short circuit is detected between test contact groups "test contact p5 and test contact p4" of dummy pads 11p1 and 11p2.

[0067] In some embodiments, the electronic component 11 is determined to be offset by approximately 5 μm relative to the substrate 10 at the upper right corner if: an open circuit is detected between test contact groups “test contact p6 and test contact p5” and “test contact p3 and test contact p6” of dummy pads 11p1 and 11p2, and a short circuit is detected between test contact groups “test contact p5 and test contact p4” and “test contact p4 and test contact p3” of dummy pads 11p1 and 11p2.

[0068] In some embodiments, an electronic component 11 is determined to have rotated approximately 0.15 degrees clockwise relative to the substrate 10 if: an open circuit is detected between test contact groups "test contact p6 and test contact p5" and "test contact p3 and test contact p6" of dummy pad 11p1, and between test contact groups "test contact p5 and test contact p4" and "test contact p4 and test contact p3" of dummy pad 11p2; and a short circuit is detected between test contact groups "test contact p5 and test contact p4" and "test contact p4 and test contact p3" of dummy pad 11p1, and between test contact groups "test contact p6 and test contact p5" and "test contact p3 and test contact p6" of dummy pad 11p2. In some embodiments, it can be determined that the electronic component 11 is rotated about 0.15 degrees clockwise relative to the substrate 10 and offset about 5 μm to the lower right corner relative to the substrate 10.

[0069] In some embodiments, an electronic component 11 is determined to have rotated approximately 0.15 degrees counterclockwise relative to the substrate 10 if: an open circuit is detected between test contact groups "test contact p5 and test contact p4" and "test contact p4 and test contact p3" of dummy pad 11p1, and between test contact groups "test contact p6 and test contact p5" and "test contact p3 and test contact p6" of dummy pad 11p2, and a short circuit is detected between the aforementioned groups "test contact p6 and test contact p5" and "test contact p3 and test contact p6" of dummy pad 11p1, and between test contact groups "test contact p5 and test contact p4" and "test contact p4 and test contact p3" of dummy pad 11p2. In some embodiments, it can be determined that the electronic component 11 is rotated about 0.15 degrees counterclockwise relative to the substrate 10 and offset about 5 μm to the lower right corner relative to the substrate 10.

[0070] Regarding the relative position between electronic component 11 and substrate 10 when the dummy pads 11p1 and 11p2 are circular, please refer to... Figure 7 .

[0071] In some embodiments, the micron- or nanometer-level relative displacement of an electronic component relative to a substrate (e.g., up / down offset, angular offset, clockwise / counterclockwise rotation) can be detected using the methods used in this disclosure. It should be noted that, for the sake of simplicity, Figure 7 Some relative displacements are omitted from the table, and this disclosure is not limited to... Figure 7 The table shows the specific relative displacements.

[0072] Figure 8A , Figure 8B and Figure 8C These are cross-sectional views of a semiconductor device packaged according to some embodiments of the present disclosure at various manufacturing stages. At least some of these figures have been simplified to provide a better understanding of aspects of the present disclosure.

[0073] refer to Figure 8A A substrate 10 is provided. The substrate 10 includes conductive elements 10c1 disposed adjacent to and at least partially exposed from said surface. In embodiments of the invention, the substrate 10 may include a plurality of units, one of which can be separated from another unit by a dicing groove. Since each unit in the unit undergoes similar or identical processes in the manufacturing method, for convenience, only exemplary units are shown and described in the following description.

[0074] refer to Figure 8B A dielectric layer 10d1 is disposed on substrate 10 to cover such Figure 8A The conductive element 10c1 is shown. The dielectric layer 10d1 can be disposed by, for example, coating, lamination, chemical vapor deposition (CVD) or other suitable processes. The dielectric layer 10d1 can be patterned by, for example, lithography techniques using a photoresist film (or mask) to expose, as... Figure 8A This is a portion of the conductive element 10c1 shown. Conductive material can be deposited on the exposed portion of the conductive element 10c1 by, for example, sputtering, chemical plating, printing, or other suitable processes, thereby forming a conductive element as shown. Figure 8B The conductive element 10c2 is shown. In some embodiments, after the conductive material is placed, a planarization operation, such as a chemical-mechanical polishing (CMP) operation, may be performed. In some embodiments, the conductive element 10c2 may be an RDL. Figure 8B As shown, the conductive element 10c2 is placed in the inner region (or central region, conductive region) r1 surrounded by the dashed line.

[0075] refer to Figure 8C A dielectric layer 10d2 is placed on dielectric layer 10d1 to cover such... Figure 8B The conductive element 10c2 is shown. A similar operation can be performed to pattern the dielectric layer 10d2 and form the conductive element 10c and test contacts p1 to p6. The test contacts p1 to p6 are insulated from the conductive element 10c through the dielectric layer 10d2.

[0076] In some embodiments, a single-cut operation (e.g., using a cutting saw, laser, punch press, or other suitable cutting technique) can be performed to remove, for example, Figure 1 Discrete substrates are shown.

[0077] In some embodiments, similar operations can be performed on electronic component 11, such as... Figure 1 As shown, dummy pads 11p1 and 11p2 are formed.

[0078] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0079] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may refer to two surfaces located along the same plane whose positional difference is within several micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, and ±0.5% of the average of said values.

[0080] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device package comprising: A substrate (10) having an active surface (101) and a passive surface (102), wherein the substrate has a first conductive element (10c) disposed in a central region (r1) of the active surface (101) and a first set of test contacts (10p1) and a second set of test contacts (10p2) disposed in the periphery (r2) of the passive surface (102); and An electronic component (11) is disposed on the substrate and has an active surface (111) facing the passive surface (102) of the substrate. The electronic component includes a first dummy pad (11p1) and a second dummy pad (11p2), wherein the first dummy pad and the second dummy pad are disposed at opposite angles to the active surface (111) of the electronic component, and wherein the electronic component includes a second conductive element (11c), which is disposed in the central region (r1) of the active surface (111) of the electronic component and is connected to the first conductive element (10c) through a conductive via (10v1) through the substrate (10). When the relative positions between the substrate and the electronic component are within the design specifications, the first dummy pad (11p1) covers the first test contact (p1) and the second test contact (p2) in the first group of test contacts (10p1) and forms an open circuit with the other test contacts (p3~p6) in the first group of test contacts (10p1), and the second dummy pad (11p2) covers the first test contact and the second test contact in the second group of test contacts (10p2) and forms an open circuit with the other test contacts in the second group of test contacts (10p2); The other test contacts (p3~p6) in the first group of test contacts (10p1) include a third test contact, which includes a first portion close to the first dummy pad (11p1) and a second portion away from the first dummy pad (11p1) and connected to the first portion; and The other test contacts (p3~p6) in the first group of test contacts (10p1) surround the first dummy pad (11p1) such that the other test contacts (p3~p6) in the first group of test contacts (10p1) are arranged angularly adjacent to the first dummy pad (11p1).

2. The semiconductor device package according to claim 1, wherein the projected area of ​​the first dummy pad on the substrate is square, and the other test contacts in the first group of test contacts have contours corresponding to the contours of the first dummy pad, wherein when a short circuit is detected between the first dummy pad (11p1) and the other test contacts (p3~p6) in the first group of test contacts (10p1), and when a short circuit is detected between the second dummy pad (11p2) and the other test contacts in the second group of test contacts (10p2), the combination of short-circuited contacts determines an offset and / or rotation.

3. The semiconductor device package according to claim 1, wherein the first test contact (p1) of the first group of test contacts (10p1) includes a first inner portion covered by the first dummy pad (11p1) and a first outer portion exposed from the projected area of ​​the electronic component (11); the second test contact (p2) of the first group of test contacts (10p1) includes a second inner portion covered by the first dummy pad (11p1) and a second outer portion exposed from the projected area of ​​the electronic component (11); the other test contacts (p3~p6) of the first group of test contacts (10p1) respectively include portions overlapping with and close to the projected area of ​​the electronic component (11). The inner portion of the first dummy pad (11p1) and the outer portion exposed from the projected area of ​​the electronic component (11); wherein the other test contacts (p3~p6) in the first group of test contacts (10p1) are arranged along the side profile of the first dummy pad (11p1), and when the relative position between the substrate and the electronic component is within the design specifications, the first test contact (p1) and the second test contact (p2) in the first group of test contacts (10p1) form a short circuit through the first dummy pad (11p1), while the other test contacts (p3~p6) in the first group of test contacts (10p1) are all laterally spaced from the first dummy pad (11p1).

4. The semiconductor device package of claim 3, wherein the inner portion and the outer portion of at least one of the first set of test contacts (10p1) are connected to each other by a trace, the trace being disposed at a height position relative to the substrate (10) different from the height positions of the inner portion and the outer portion relative to the substrate, and the trace being part of or formed together with the redistribution layer (RDL).

5. The semiconductor device package of claim 1, wherein the first test contact (p1) of the first set of test contacts (10p1) comprises a first portion (p1b) covered by the first dummy pad and a second portion (p1a) exposed from the electronic component (11) and connected to the first portion, the second test contact of the first set of test contacts (10p1) comprises a first portion (p2b) and a second portion (p2a) connected to the first portion, and the width of the first portion of the first test contact of the first set of test contacts (10p1) is different from the width of the second portion of the first test contact of the first set of test contacts (10p1).

6. The semiconductor device package of claim 5, wherein the second portion of the first test contact in the first set of test contacts (10p1) is configured to perform an energizing operation to determine whether the first portion (p1b) of the first test contact and the first portion (p2b) of the second test contact are connected.

7. The semiconductor device package of claim 5, wherein the first portion and the second portion of the first test contact in the first set of test contacts (10p1) are connected by a trace (p1w) having different contact areas with the first portion and the second portion, and wherein, when viewed from a top view, the trace passes between two of the other test contacts in the first set of test contacts (10p1).

8. A semiconductor device package comprising: A first substrate (10) having a central region (r1) and a periphery (r2) surrounding the central region; A first test contact (p1), a second test contact (p2), a third test contact (p5), and a fourth test contact (p4) are disposed within the periphery of the first substrate and spaced apart from each other. A second substrate (11) is disposed on the first substrate and has a first side surface and a second side surface adjacent to the first side surface; as well as The first dummy pad (11p1) is exposed from the surface of the second substrate. When the relative positions between the first substrate (10) and the second substrate (11) are within the design specifications, the first dummy pad contacts the first test contact and the second test contact and is laterally spaced from the third test contact and the fourth test contact. The first test contact is exposed on the first side of the second substrate, and the second test contact is exposed on the second side of the second substrate. The first test contact includes a first part (p1b) and a second part (p1a) connected by a trace (p1w), wherein the height position of the trace (p1w) relative to the first substrate (10) is different from the height positions of the first part and the second part relative to the first substrate (10); When viewed from above, the trace (p1w) passes between the third test contact (p5) and the fourth test contact (p4); The third test contact includes a first portion close to the first dummy pad (11p1) and a second portion away from the first dummy pad (11p1) and connected to the first portion; and The third test contact (p5) and the fourth test contact (p4) surround the first dummy pad (11p1) such that the third test contact (p5) and the fourth test contact (p4) are arranged angularly adjacent to the first dummy pad (11p1).

9. The semiconductor device package of claim 8, wherein the third test contact surrounds a portion of the first dummy pad and the third test contact is exposed on the second side of the second substrate.

10. The semiconductor device package of claim 8, wherein when the relative positions between the first substrate and the second substrate (11) are within design specifications, the first portion of the third test contact does not coincide with the first dummy pad in the vertical direction, and the second portion of the third test contact is at least partially exposed from the projected area of ​​the second substrate.

11. The semiconductor device package of claim 8, further comprising a fifth test contact and a sixth test contact, wherein the third test contact, the fourth test contact, the fifth test contact and the sixth test contact are spaced apart from each other, wherein when the relative positions between the first substrate and the second substrate (11) are within design specifications, the first dummy pad is laterally spaced apart from the third test contact, the fourth test contact, the fifth test contact and the sixth test contact, wherein the first dummy pad forms an open circuit with the third test contact, the fourth test contact, the fifth test contact and the sixth test contact.

12. The semiconductor device package of claim 11, wherein the third test contact, the fourth test contact, the fifth test contact and the sixth test contact surround the first dummy pad, wherein each of the third test contact, the fourth test contact, the fifth test contact and the sixth test contact is disposed at a corner of the first dummy pad and each has a profile corresponding to the profile of the first dummy pad.

13. The semiconductor device package of claim 8, wherein the second portion of the first test contact is at least partially exposed from the projected area of ​​the second substrate.

14. The semiconductor device package of claim 8, further comprising a second dummy pad (11p2) exposed from the surface of the second substrate, wherein the first dummy pad and the second dummy pad are disposed diagonally on the second substrate and coplanar with the surface of the second substrate.

15. The semiconductor device package of claim 8, further comprising a conductive element (10c) disposed in the central region of the first substrate, wherein the conductive element is insulated from the first test contact, wherein the first test contact, the second test contact and the third test contact are disposed on the passive surface (102) of the first substrate.

16. The semiconductor device package of claim 15, wherein the active surface (111) of the second substrate directly contacts the passive surface of the first substrate.

17. A method for checking alignment of a semiconductor device package, the method comprising: A substrate (10) is provided having an active surface (101) and a passive surface (102), and the substrate has a first conductive element (10c) disposed in the central region (r1) of the active surface (101) and a first set of test contacts (10p1) and a second set of test contacts (10p2) disposed in the periphery (r2) of the passive surface (102). An electronic component (11) is connected to the substrate (10), wherein the electronic component (11) has an active surface (111) facing the passive surface (102) of the substrate, the electronic component includes a first dummy pad (11p1) and a second dummy pad (11p2), wherein the first dummy pad and the second dummy pad are disposed at opposite angles to the active surface (111) of the electronic component, and wherein the electronic component includes a second conductive element (11c), which is disposed in the central region (r1) of the active surface (111) of the electronic component, and is connected to the first conductive element (10c) through a conductive via (10v1) through the substrate (10); Obtain the first electrical information between the first group of test contacts; Obtain the second electrical information between the second set of test contacts; as well as Based on the first electrical information and the second electrical information, the relative position between the substrate (10) and the electronic component (11) is determined. When the first dummy pad is short-circuited with the first test contact (p1) and the second test contact (p2) in the first group of test contacts, and forms an open circuit with the third test contact (p3) in the first group of test contacts, it is determined that the relative position between the substrate (10) and the electronic component (11) is within the design specifications. The third test contact includes a first portion close to the first dummy pad (11p1) and a second portion away from the first dummy pad (11p1) and connected to the first portion; and The first group of test contacts (10p1) includes other test contacts (p3~p6), and the other test contacts (p3~p6) include a third test contact (p3). The other test contacts (p3~p6) surround the first dummy pad (11p1) such that the other test contacts (p3~p6) in the first group of test contacts (10p1) are arranged adjacent to the corner of the first dummy pad (11p1).

18. The method of claim 17, wherein when the first dummy pad (11p1) is shorted to the third test contact (p3), it is determined that the offset and / or rotation between the substrate (10) and the electronic component (11) exceeds a predetermined value.

19. The method of claim 18, wherein when the first test contact (p1) is shorted to the third test contact (p3), it is determined that the offset and / or rotation between the substrate (10) and the electronic component (11) exceeds a predetermined value.

20. The method according to claim 18, wherein when the first test contact (p1) and the second test contact (p2) are shorted through the first dummy pad, it is determined that the relative position between the substrate (10) and the electronic component (11) is within the design specifications.

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