Memory devices, semiconductor devices and methods of manufacturing the same

Abstract

This disclosure provides a semiconductor device including first, second, and third transistors. The first transistor includes a first active region, a first gate dielectric layer, a first concentration of a dipole layer material, and a first gate structure on the first active region, situated on the first gate dielectric layer. The second transistor includes a second active region, a second gate dielectric layer, a second concentration of a dipole layer material, and a second gate structure on the second active region, situated on the second gate dielectric layer. The third transistor includes a third active region, a third gate dielectric layer, a third concentration of a dipole layer material, and a third gate structure on the third active region, situated on the third gate dielectric layer. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration, and the second concentration is greater than the third concentration.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device having different critical voltage values. Background Technology

[0002] The integrated circuit (IC) industry is experiencing rapid growth. In the evolution of ICs, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest possible layout (or wire) that a process can create) has shrunk. This shrinking process, in principle, offers some advantages by increasing process efficiency and reducing associated costs. However, this shrinking process also comes with more complex designs and processes for devices that incorporate these ICs, and similar advancements in device manufacturing processes are needed to make these advancements possible.

[0003] As the geometry of IC devices continues to shrink, forming features in the desired shape becomes increasingly challenging. For example, in gate-last processes, a dummy gate stack is first formed as a placeholder, allowing the subsequently formed metal gate stack to undergo substantial processing, and then it is removed and replaced with a functional metal gate stack. To replace the dummy gate stack, it is first removed to form a gate trench, and multiple layers are deposited in the gate trench to form the functional metal gate stack. In some cases, additional dipole layers or dielectric layers may be deposited on the gate dielectric layer to provide transistors with different threshold voltages. Because the shrinking geometry also reduces the size of the gate trench, these additional dipole and dielectric layers may shrink the process window for satisfactorily depositing multiple layers in the functional metal gate structure. The process window may shrink further when the gate trench is not straight. Therefore, while existing gate-last processes meet their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] In one embodiment, this disclosure provides a semiconductor device including a first transistor, a second transistor, and a third transistor. The first transistor includes a first active region and a first gate dielectric layer. On the first active region, the first gate dielectric layer includes a first concentration of a dipole layer material and a first gate structure, disposed on the first gate dielectric layer. The second transistor includes a second active region and a second gate dielectric layer. On the second active region, the second gate dielectric layer includes a second concentration of a dipole layer material and a second gate structure, disposed on the second gate dielectric layer. The third transistor includes a third active region and a third gate dielectric layer. On the third active region, the third gate dielectric layer includes a third concentration of a dipole layer material and a third gate structure, disposed on the third gate dielectric layer. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration, and the second concentration is greater than the third concentration.

[0005] In another embodiment, this disclosure provides a method for manufacturing a semiconductor device, comprising providing a workpiece, the workpiece including a first device region, a second device region, and a third device region; forming a first gate trench in the first device region, a second gate trench in the second device region, and a third gate trench in the third device region; depositing a gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench; depositing a first dipole layer on the gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench; selectively removing the first dipole layer in the second gate trench; depositing a second dipole layer on the first dipole layer in the first gate trench, the gate dielectric layer in the second gate trench, and the first dipole layer in the third gate trench; selectively removing the first dipole layer and the second dipole layer in the third gate trench; and annealing the workpiece.

[0006] In another embodiment, this disclosure provides a method for manufacturing a semiconductor device, comprising providing a workpiece including a first device region, a second device region, a third device region, and a fourth device region; forming a first gate trench in the first device region; forming a second gate trench in the second device region; forming a third gate trench in the third device region; and forming a fourth gate trench in the fourth device region; depositing a gate dielectric layer; depositing a first dipole layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench; and depositing the first dipole layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench. On the gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench, the first dipole layer in the third gate trench and the fourth gate trench is selectively removed. A first annealing process is performed on the workpiece to remove the first dipole layer in the first gate trench and the second gate trench. After removing the first dipole layer, a second dipole layer is deposited on the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench. A second dipole layer in the second gate trench and the fourth gate trench is selectively removed. A second annealing process is performed on the workpiece, and the second dipole layer is removed from the workpiece. Attached Figure Description

[0007] The various aspects of this disclosure will be best understood when read in conjunction with the accompanying illustrations and the following description of the embodiments. It should be emphasized that, in accordance with industry standard practice, many features are not depicted to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily increased or decreased.

[0008] Figure 1 A flowchart of a method for forming a semiconductor device is depicted according to some embodiments of the present disclosure.

[0009] Figures 2-15 According to some embodiments of this disclosure, for Figure 1 The method is to obtain partial cross-sectional views of the workpiece during each process operation.

[0010] Figure 16 A flowchart of another method for forming a semiconductor device is depicted according to some embodiments of the present disclosure.

[0011] Figures 17-27 , Figure 28A ,as well as Figure 28B According to some embodiments of this disclosure, for Figure 16 A partial cross-sectional view of a workpiece during various manufacturing processes.

[0012] Figure 29 According to some embodiments of this disclosure, a circuit diagram of an 8-transistor (8T) static random access memory (SRAM) cell is provided.

[0013] Figure 30 According to some embodiments of this disclosure, for Figure 29 Layout diagram of the 8T SRAM cell.

[0014] Figure 31 According to some embodiments of this disclosure, a circuit diagram of a 10-transistor (10T) SRAM cell is provided.

[0015] Figure 32 According to some embodiments of this disclosure, for Figure 31 Layout diagram of the 10T SRAM cell.

[0016] The reference numerals in the attached figures are explained as follows:

[0017] 100, 500: Method

[0018] 102-122, 502-526: Boxes

[0019] 10: Passage Area

[0020] 20: Source / Drain Region

[0021] 200: Workpiece / Semiconductor Device

[0022] 202: Substrate

[0023] 204, 905, 1005: Active Zone

[0024] 205: Dummy gate dielectric layer

[0025] 207: Dummy Gate Electrode

[0026] 208: Dummy Gate Stack

[0027] 210: Gate spacer layer

[0028] 212: Source / Drain Characteristics

[0029] 214: Contact Etching Stop Layer

[0030] 216: Dielectric layer

[0031] 218: Gate trench

[0032] 220: Interface Layer

[0033] 222: Gate dielectric layer

[0034] 224: First Dipole Layer

[0035] 226, 232, 242: Hard mask layer

[0036] 228, 234, 244: Bottom anti-reflective coating layer

[0037] 230, 240: Second dipole layer

[0038] 236: Functional Metal Gate Stack

[0039] 300: Annealing process

[0040] 410, 810: First transistor

[0041] 420, 820: Second transistor

[0042] 430, 830: Third transistor

[0043] 600: First annealing process

[0044] 700: Second annealing process

[0045] 840: Fourth Transistor

[0046] 900: 8-Transistor SRAM Cell

[0047] 902, 1002: First-channel gate transistor

[0048] 904, 1004: Second-channel gate transistor

[0049] 906, 1006: First pull-up transistor

[0050] 908, 1008: Second pull-up transistor

[0051] 910, 1010: First pull-down transistor

[0052] 912, 1012: Second pull-down transistor

[0053] 914: Reading the pull-down transistor

[0054] 916: Read Channel Gate Transistor

[0055] 918: Reader

[0056] 920, 1026: Virtual grounding

[0057] 922, 1028: Retaining transistors

[0058] 924, 1030: Power gate transistor

[0059] 903, 1003: Gate structure

[0060] 903-1, 1003-1: First gate structure

[0061] 903-2, 1003-2: Second gate structure

[0062] 1000: 10-Transistor SRAM Cell

[0063] 1014: First Read End

[0064] 1016: Second Reading End

[0065] 1018: First read pull-down transistor

[0066] 1020: First read channel gate transistor

[0067] 1022: Second read pull-down transistor

[0068] 1024: Second read channel gate transistor

[0069] 1100, 3100: First device area

[0070] 1200, 3200: Second device area

[0071] 1300, 3300: Third Device Area

[0072] 2221, 2231: First gate dielectric layer

[0073] 2222, 2232: Second gate dielectric layer

[0074] 2233: Third gate dielectric layer

[0075] 3400: Fourth Device Area

[0076] BL: Bitline

[0077] BLB: Complementary Bit Line

[0078] I: Region

[0079] Q: First data storage node

[0080] QB: Second data storage node

[0081] RBL: Read Bit Line

[0082] RBLB: Read complementary bit line

[0083] RWL: Read character lines

[0084] WL: Character Line Detailed Implementation

[0085] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0086] In addition, the formation of a feature above, connected to, and / or coupled to another feature in this disclosure may include embodiments in which the features are formed in direct contact, and may also include formation embodiments in which additional features can be inserted so that the features may not be in direct contact. Furthermore, spatially relative terms, such as “lower,” “upper,” “above,” “above,” “below,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontal,” “downward,” “upward,” etc.), are used to facilitate the description of the relationship between one feature and another. Spatially relative terms are intended to cover not only the orientation of the device as depicted in the drawings, but also different orientations of the device in operation or use.

[0087] Furthermore, when a number or range of numbers is described using terms such as "approximately," "about," or similar, the purpose of this vocabulary is to encompass other numbers within a reasonable range that includes the stated number, such as within + / - 10% of the stated number, or other values ​​that would be understood by a person skilled in the art. For example, the term "approximately 5nm" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0088] Metal gate stacks, common in modern transistors, can be formed using either a gate-first or gate-last process. In the former, the functional metal gate stack is formed before other features (such as source / drain features and interlayer dielectric layers). In the latter, a non-functional dummy gate stack is first formed as a placeholder for the subsequent metal gate stack, followed by the fabrication of source / drain features and the interlayer. The dummy gate stack is then removed and replaced with a functional metal gate stack. To replace the dummy gate stack, it is first removed to form a gate trench, and then multiple layers are deposited in the gate trench to form the functional metal gate stack. In some cases, one or more dipole layers can be deposited on the gate dielectric layer to provide transistors with different threshold voltages. Based on the difference in oxygen atom density, interface dipoles may form at the interface between the dipole layer and the underlying silicon oxide interface layer. Depending on the polarity of the interface dipole, it may increase or decrease the threshold voltage of the transistor it belongs to. While dipole layers can be used to modulate the critical voltage, additional dipole layers can further reduce the process window for satisfactorily depositing multiple layers in a functional metal gate stack. In cases where the gate trench is not straight, the process window can be further reduced. For example, the two sides of the layers can be joined and the trench opening closed before all the multiple layers are deposited in the gate trench to form the functional metal gate stack, preventing subsequent layers from being deposited in the gate trench.

[0089] To mitigate the aforementioned problems, this disclosure provides a method for forming a semiconductor device. In some embodiments of this disclosure, the method includes depositing a gate dielectric layer on gate trenches in a first device region, a second device region, and a third device region on a workpiece. Next, a first dipole layer is deposited on the gate dielectric layer in the gate trenches in the first, second, and third device regions. The first dipole layer on the gate trench in the second device region is selectively removed, while the first dipole layer still covers the gate dielectric layer in the first and third device regions. Next, a second dipole layer is deposited on the first dipole layer in the gate trenches in the first and third device regions and on the gate dielectric layer in the second device region. Next, the first and second dipole layers on the gate dielectric layer in the third device region are removed. The workpiece is then annealed at a temperature between approximately 500°C and approximately 900°C, allowing the ingredients of the first and second dipole layers to thermally diffuse to the gate dielectric layer to alter the threshold voltage. Next, the first and second dipole layers are removed from the gate trench of the workpiece, and substantially identical gate structures are formed in the gate trenches of the first, second, and third device regions to form a first transistor in the first device region, a second transistor in the second device region, and a third transistor in the third device region. The first transistor in the first device region, the second transistor in the second device region, and the third transistor in the third device region have different threshold voltages. Since the dipole layer is not included in the gate trench but only serves as a vehicle for the diffused dopant, the process window for forming the functional metal gate stack is not reduced. This disclosure also provides an embodiment with four device regions.

[0090] Figure 1 A flowchart of a method 100 for forming a semiconductor device is depicted according to some embodiments of the present disclosure. Figures 2-15 for Figure 1 The method 100 provides partial cross-sectional views of the workpiece at various process stages. Additional operations may be provided before, during, and after method 100, and some of these operations may be moved, replaced, or removed for additional embodiments of method 100. Additional features may be added to... Figures 2-15 The contact structure shown below, and some of the features described below, are in Figures 2-15 In other embodiments of the illustrated interconnect structure, it may be replaced, modified, or removed.

[0091] refer to Figure 1 as well as Figure 2Method 100 includes block 102, wherein block 102 receives workpiece 200. Upon completion of method 100, workpiece 200 may be processed to become semiconductor device 200. In this sense, workpiece 200 may also be referred to as semiconductor device 200 in a suitable context. Semiconductor device 200 may be included in processors, memory, and / or other integrated circuit (IC) devices. In some embodiments, semiconductor device 200 is part of an integrated circuit (IC) chip, a system-on-chip (SoC), or a portion thereof, and includes a variety of passive electronic devices and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS), bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Transistors can be planar transistors or multi-gate transistors, such as FinFETs or gate-all-around (GAA) transistors.

[0092] like Figure 2As depicted, the semiconductor device 200 includes a substrate (wafer) 202. In the illustrated embodiment, the substrate 202 comprises silicon. The substrate 202 may alternatively or additionally comprise another elemental semiconductor, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or combinations thereof. In some embodiments, the substrate 202 comprises one or more group III-V materials, one or more group II-IV materials, or combinations thereof. In some embodiments, substrate 202 is a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the semiconductor device 200, substrate 202 may include various doped regions (not shown), such as p-type doped regions, n-type doped regions, or combinations thereof. N-type doped regions (e.g., p-type wells) contain p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof. N-type doped regions (e.g., n-type wells) contain n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments, the substrate 202 includes doped regions formed by a combination of p-type and n-type dopants. Numerous doped regions can be formed directly in or on the substrate 202, for example, providing p-well structures, n-well structures, dual-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the numerous doped regions.

[0093] Semiconductor device 200 includes an active region 204 on substrate 202. The active region 204 may be a fin-shaped semiconductor feature or a vertically stacked nanostructure. For example... Figure 2 As shown, the active region 204 extends laterally along the X direction and longitudinally along the Z direction of the substrate 202. In some embodiments, the active region 204 may be a part of the substrate 202 (e.g., a part of a material layer of the substrate 202). For example, the active region 204 of silicon may be formed from the silicon substrate 202. Alternatively, in some embodiments, the active region 204 is defined in a material layer, such as forming one or more semiconductor material layers on the substrate 202. For example, the active region 204 may comprise a semiconductor layer stack having a plurality of semiconductor layers (e.g., a heterostructure) deposited on the substrate 202. The semiconductor layers may comprise any suitable material, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers may comprise the same or different materials, etch rates, atomic percentages, weight percentages, thicknesses, and / or configurations according to the design requirements of the semiconductor device 200. In some embodiments, the semiconductor layer stack comprises alternating semiconductor layers, such as a plurality of semiconductor layers composed of a first material and a plurality of semiconductor layers composed of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon germanium layers (e.g., from bottom to top, silicon germanium (SiGe) / silicon (Si) / silicon germanium (SiGe) / silicon (Si) / silicon germanium (SiGe) / silicon (Si)). In some embodiments, the semiconductor layer stack comprises semiconductor layers of the same material but with alternating atomic percentages, such as semiconductor layers with a first atomic percentage component and semiconductor layers with a second atomic percentage component. For example, the semiconductor layer stack comprises silicon germanium layers having alternating silicon and / or germanium atomic percentages (e.g., from bottom to top, Si). a Ge b / Si c Ge d / Si a Ge b / Si c Ge d / Si a Ge b / Si c Ge d, where a and c are silicon with different atomic percentages and b and d are germanium with different atomic percentages.

[0094] The active region 204 can be formed on the substrate 202 using any suitable process. In some embodiments, a combination of deposition, lithography, and / or etching processes is performed to define the active region 204. Figure 2The active region 204 is depicted. For example, forming the active region 204 includes performing a lithography process to form a patterned resist layer on a substrate 202 (or a material layer deposited on the substrate 202, such as a heterostructure) and performing an etching process to transfer a pattern defined in the patterned resist layer to the substrate 202 (or a material layer deposited on the substrate 202, such as a heterostructure)). The lithography process may include forming a resist layer on the substrate 202 (e.g., spin coating), performing a pre-exposure baking process, performing an exposure process with a mask, performing a post-exposure baking process, and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (such as ultraviolet light, UV light, deep UV, DUV, or extreme UV, EUV). A mask, depending on its pattern and / or type (e.g., binary mask, phase-shift mask, or EUV mask), blocks, transmits, and / or reflects this radiation to the resist layer, causing an image corresponding to the mask pattern to be projected onto the resist layer. Because the resist layer is sensitive to radiant energy, the exposed portions of the resist layer undergo chemical changes, and depending on the characteristics of the resist layer and the developer used in the development process, the exposed (or unexposed) portions of the resist layer dissolve during development. After development, the patterned resist layer contains a photoresist pattern corresponding to the mask. The etching process utilizes the patterned resist layer as an etching mask to remove portions of the substrate 202 (or a material layer deposited on the substrate 202). The etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching, other suitable etching processes, or a combination thereof. After the etching process, for example, a patterned resist layer is removed from the substrate 202 by a resist stripping process.Alternatively, the active region 204 may be formed using multiple patterning processes, such as double patterning lithography (DPL) processes (e.g., lithography-etch-lithography-etch (LELE) processes, self-aligned double patterning (SADP) processes, spacer-is-dielectric (SID) SADP processes, other double patterning processes, or combinations thereof), triple patterning processes (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) processes, self-aligned triple patterning (SATP) processes, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) processes), or combinations thereof. In some embodiments, directed self-assembly (DSA) technology is implemented when forming the active region 204. Furthermore, in some embodiments, in order to pattern the resist layer and / or other thin layers, the exposure process may implement maskless lithography, electron beam writing, ion beam writing, and / or nanoimprinting techniques.

[0095] Isolation features (not shown) are formed on and / or within substrate 202 to separate regions, such as the various device regions of semiconductor device 200. For example, isolation features separate and isolate active region 204 from adjacent active regions. In some embodiments, isolation features may surround a bottom portion of active region 204 and expose a top portion of active region 204. Isolation features may comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., comprising silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. Isolation features may comprise different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. In some embodiments, the STI feature may be formed by etching trenches in the substrate 202 (e.g., using dry etching and / or wet etching processes) and filling the trenches with an insulating material (e.g., chemical vapor deposition or spin-on-glass process). A chemical mechanical polishing (CMP) process may be performed to remove excess insulating material and / or planarize the top surface of the isolation feature. In some embodiments, the STI feature may be formed by depositing an insulating material on the substrate 202 after forming the active region 204 (in some embodiments, such that an insulating material layer fills the gaps (trenches) between the active region 204 and adjacent active regions) and etching back the insulating material layer to form the isolation feature. In some embodiments, the isolation feature comprises a multilayer structure filling trenches, such as a bulk dielectric layer disposed on a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer comprise materials according to design requirements (e.g., the bulk dielectric layer comprises materials disposed on a thermal oxide layer). Silicon nitride on the pad dielectric layer of oxide.

[0096] exist Figure 2In the depicted embodiment, workpiece 200 includes a dummy gate stack 208 above and surrounding channel region 10 in active region 204. Each dummy gate stack 208 may include a dummy gate dielectric layer 205 and a dummy gate electrode 207. Figure 2 In the represented embodiment, the dummy gate stack 208 includes a dummy gate dielectric layer 205 on the active region 204 and a dummy gate electrode 207 above the dummy gate dielectric layer 205. In some embodiments, the dummy gate dielectric layer 205 may be formed of silicon oxide, and the dummy gate electrode 207 may be formed of polysilicon. The gate spacer layer 210 may be formed along the sidewalls of the dummy gate stack 208 using any suitable process and includes a dielectric material. The dielectric material of the gate spacer layer 210 may comprise silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some embodiments, the gate spacer layer 210 may comprise a multilayer structure, such as a first spacer layer comprising silicon nitride and a second spacer layer comprising silicon oxide. In some embodiments, the gate spacer layer 210 may comprise more than one set of spacers formed adjacent to the gate stack, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers. Notably, Figure 2 The cross-sectional view depicts a section taken along the X direction of the top surface of the active region 204. For example, when the active region 204 is a fin-shaped active region (or a single fin), Figure 2 The dummy gate stack 208 is shown as being disposed on the top surface of the fin.

[0097] The workpiece 200 may further include source / drain features 212 formed in the source / drain region 20 adjacent to the channel region 10. For example... Figure 2As shown, the source / drain feature 212 is disposed adjacent to the dummy gate stack 208. In some embodiments, the source / drain feature 212 is formed on the source / drain region 20 of the active region 204 using an epitaxial process. The epitaxial process may implement chemical vapor deposition (CVD) deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure chemical vapor deposition (LPCVD), and / or plasma-assisted chemical vapor deposition (PECVD)), molecular beam epitaxy, other suitable selective film growth (SEG) processes, or combinations thereof. The source / drain feature 212 may be doped with n-type dopant or p-type dopant. In some embodiments, when the transistor is configured as an n-type device (e.g., having an n-channel), the source / drain feature 212 may be an epitaxial layer comprising silicon or a silicon-carbon epitaxial layer doped with phosphorus, other n-type dopants, or combinations thereof (e.g., forming a silicon:phosphorus (Si:P) epitaxial layer or a silicon:carbon:phosphorus (Si:C:P) epitaxial layer). In some embodiments, when the transistor is configured as a p-type device (e.g., having a p-channel), the source / drain feature 212 may be an epitaxial layer comprising silicon and germanium, doped with boron, other p-type dopants, or combinations thereof (e.g., forming a silicon:germanium:boron (Si:Ge:B) epitaxial layer). In some embodiments, an annealing process is performed to activate the dopants in the source / drain feature 212 of the semiconductor device 200.

[0098] Workpiece 200 may include a contact etch stop layer (CESL) 214 deposited on the source / drain feature 212. In some cases, CESL 214 may also be deposited on the side surface of the gate spacer layer 210. In some embodiments, CESL 214 may also be formed of silicon nitride, silicon oxynitride, or silicon carbonitride, and may be compliantly formed using atomic layer deposition (ALD). Dielectric layer 216, also referred to as interlayer dielectric (ILD) layer 216, is deposited on CESL 214. Dielectric layer 216 may be formed using a flowable chemical vapor deposition (FCVD) process. In some embodiments, after using the FCVD process, the deposited dielectric layer 216 may be cured by incident ultraviolet (UV) radiation, annealing, or both. In some embodiments, the dielectric layer 216 may comprise a dielectric material, including, for example, silicon oxide, oxides formed from tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Examples of low-k dielectric materials include (FSG), (carbon) (silicon oxide), and black... (Applied Materials of Santa Clara, California)), Xerogel, Aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (Dow Chemical, Midland, Michigan)), polyimide, other low dielectric dielectrics, or combinations thereof.

[0099] refer to Figure 1 as well as Figure 3Method 100 includes block 104, wherein a dummy gate stack 208 is removed to form a gate trench 218. In some embodiments, the dummy gate stack 208 may be removed to form the gate trench 218 using a suitable combination of dry and wet etching processes. The gate trench 218 exposes the channel region 10 of the active region 204. While the dummy gate stack 208 and the gate trench 218 are depicted as having straight sidewalls along the Z direction, in some embodiments they may also be non-straight and may include a necking profile. The necking profile may reduce the process window for depositing multiple thin layers in the gate trench 218 to form a functional metal gate stack.

[0100] refer to Figure 1 as well as Figure 4 Method 100 includes block 106, wherein an interface layer 220 is deposited in a gate trench 218. In some embodiments, the interface layer 220 may be formed of silicon oxide.

[0101] refer to Figure 1 as well as Figure 5 Method 100 includes block 108, wherein a gate dielectric layer 222 is deposited on interface layer 220. Gate dielectric layer 222 may comprise a dielectric material with a high dielectric constant, such as a dielectric constant higher than that of silicon oxide (k≈3.9). Examples of high-k dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable compositions, or combinations thereof. In some embodiments, the gate dielectric layer 222 may comprise a high dielectric constant dielectric material, including, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium dioxide (ZrO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), other suitable high dielectric constant dielectric materials, or combinations thereof.

[0102] As described below, workpiece 200 may include multiple device regions (e.g., three device regions, four device regions, or more device regions) of transistors with different threshold voltages, and... Figures 2-5 The structure shown may span and repeat across the multiple device regions, but the repeated structure has been omitted, and instead... Figures 2-5 The ellipsis (“…”) shown is used to represent this. The operation of method 100, which differs for different device areas, will be related to… Figures 6-15 The following description is provided. For the sake of simplicity and clarity, Figures 6-14 A partial cross-sectional view of region "I" in different device areas.

[0103] refer to Figure 1 as well as Figure 6 Method 100 includes block 110, wherein a first dipole layer 224 is deposited on the gate dielectric layer 222. Figures 6-15 In some of the depicted embodiments, workpiece 200 includes three device regions—a first device region 1100, a second device region 1200, and a third device region 1300. As described above, Figure 6 A partial cross-sectional view depicting region "I" in the first device region 1100, the second device region 1200, and the third device region 1300 is shown. A first dipole layer 224 is deposited on the gate dielectric layer 222 in the gate trenches of the first device region 1100, the second device region 1200, and the third device region 1300. In some embodiments, the first dipole layer 224 may be formed of lanthanum oxide, yttrium oxide, or aluminum oxide, and may be deposited using atomic layer deposition (ALD). In some embodiments, the ALD process used to form the first dipole layer 224 may comprise between approximately 2 and approximately 10 cycles. In the embodiment described, the first dipole layer 224 may have approximately up to approximately The thickness is between [a certain value]. In one embodiment, the first dipole layer 224 may be formed of lanthanum oxide.

[0104] refer to Figure 1 , Figure 7 , Figure 8 ,as well as Figure 9 Method 100 includes block 112, wherein a first dipole layer 224 is selectively removed from the second device region 1200. In some embodiments, lithography and etching techniques may be used to perform the operation of block 112. Example processes are described in... Figures 7-9 Demonstration. First, refer to... Figure 7First, a hard mask layer 226 is formed on the first dipole layer 224, and a bottom antireflective coating (BARC) layer 228 is deposited on the hard mask layer 226. In some cases, the hard mask layer 226 may be a single layer or multiple layers. When the hard mask layer 226 is a single thin layer, it may contain silicon oxide, silicon nitride, or silicon oxynitride. When the hard mask layer 226 is a multiple layer, it may contain a thin silicon layer and a thin silicon nitride layer on the silicon layer. The BARC layer 228 may contain silicon oxynitride, a polymer, or a suitable material. To pattern the BARC layer 228 and the hard mask layer 226, a photoresist layer can be blanket-deposited on the workpiece 200, including the BARC layer 228 in the first device region 1100, the second device region 1200, and the third device region 1300. The photoresist layer can be a single thin layer or multiple layers, such as three layers. The photoresist layer is then exposed to radiation that penetrates the mask or is reflected from the mask, baked in a post-baking process, and developed in a developer to form a patterned photoresist mask. The BARC layer 228 and the hard mask layer 226 are then patterned using the patterned photoresist mask to form an etch mask with an opening above the second device region 1200. Then, in an etching process, the first dipole layer 224 in the gate trench in the second device region 1200 is selectively etched away using the etch mask, such as... Figure 8 The etching process can be dry etching, wet etching, or a suitable etching process. (See reference.) Figure 9 After the first dipole layer 224 is selectively etched away from the gate trench in the second device region 1200, the hard mask layer 226 and the BARC layer 228 in the first device region 1100 and the third device region 1300 are removed using a suitable etching process.

[0105] refer to Figure 1 as well as Figure 10 Method 100 includes block 114, wherein a second dipole layer 230 is deposited on workpiece 200. For example... Figure 10As shown, the second dipole layer 230 is deposited on the first dipole layer 224 in the gate trenches of the first device region 1100 and the third device region 1300, and on the gate dielectric layer 222 in the gate trench of the second device region 1200. In some embodiments, the second dipole layer 230 and the first dipole layer 224 may have the same composition. Similar to the first dipole layer 224, the second dipole layer 230 may also be formed of lanthanum oxide, yttrium oxide, or aluminum oxide, and may be deposited using atomic layer deposition (ALD). In some embodiments, the ALD process used to deposit the second dipole layer 230 may include approximately 2 to approximately 10 cycles. In some embodiments, the second dipole layer 230 may have approximately up to approximately Between the thicknesses. In one embodiment, the second dipole layer 230 may be formed of lanthanum oxide.

[0106] refer to Figure 1 , Figure 11 , Figure 12 ,as well as Figure 13 Method 100 includes block 116, in which the second dipole layer 230 is selectively removed from the third device region 1300. Similar to the operation in block 112, the operation in block 116 can also be performed using lithography and etching techniques. For example, as... Figure 11 As shown, a hard mask layer 232 and a bottom antireflective coating (BARC) layer 234 can be formed on the second dipole layer 230. Since the hard mask layer 232 is similar to the hard mask layer 226 and the BARC layer 234 is similar to the BARC layer 228, detailed descriptions of the hard mask layer 232 and the BARC layer 234 are omitted for brevity. Following this, a resist layer can be deposited on the BARC layer 234. The resist layer, BARC layer 234, and hard mask layer 232 are then patterned in a manner similar to that described in the corresponding box 112 and are not repeated here. The patterned hard mask layer 232 allows for the selective removal of the first dipole layer 224 and the second dipole layer 230 in the gate trench of the third device region 1300, thereby exposing the gate dielectric layer 222 in the gate trench of the third device region 1300. Figure 12As depicted, at this moment, the gate trench in the first device region 1100 includes the first dipole layer 224 and the second dipole layer 230 described above; the gate trench in the second device region 1200 includes the second dipole layer 230 described above; and the gate trench in the third device region 1300 does not have the first dipole layer 224 and the second dipole layer 230. In other words, the total thickness (along the Z direction) of the first dipole layer 224 and the second dipole layer 230 in the gate trench of the first device region 1100 is greater than the total thickness of the second dipole layer 230 in the gate trench of the second device region 1200, while the gate trench in the third device region 1300 has no dipole layer. After selectively removing the first dipole layer 224 and the second dipole layer 230 from the gate trench in the third device region 1300, as... Figure 13 As depicted, the hard mask layer 232 and the BARC layer 234 can then be removed from the first device area 1100 and the second device area 1200.

[0107] refer to Figure 1 as well as Figure 13 Method 100 includes block 118, wherein workpiece 200 is annealed in annealing process 300. In block 118, the annealing process 300 thermally drives elements in the first dipole layer 224 and / or the second dipole layer 230 to the gate dielectric layer 222 in the gate trenches of the first device region 1100 and the second device region 1200. The first dipole layer 224 and the second dipole layer 230 serve as diffusion doping carriers to directly contact the gate dielectric layer 222 with the elements. Annealing process 300 may be a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. In some embodiments, the annealing process 300 includes a high annealing temperature between approximately 500°C and approximately 900°C, allowing lanthanum, yttrium, or aluminum in the first dipole layer 224 and / or the second dipole layer 230 to diffuse into the gate dielectric layer 222 in the gate trenches of the first device region 1100 and the second device region 1200. Since there are no dipole layers in the gate trenches of the third device region 1300, the annealing process 300 in block 118 does not cause any dipole layer material to diffuse into the gate dielectric layer 222 in the third device region 1300. In some embodiments, the annealing process 300 may last between approximately 5 seconds and approximately 20 seconds.

[0108] refer to Figure 1 as well as Figure 14Method 100 includes block 120, wherein a first dipole layer 224 and a second dipole layer 230 are removed from a workpiece 200. After thermally driving elements of the first dipole layer 224 and the second dipole layer 230 to the gate dielectric layer 222 in block 118, the first dipole layer 224 and the second dipole layer 230 are removed from a gate trench in a first device region 1100, and the second dipole layer 230 is removed from a gate trench in a second device region 1200. The operation of block 120 can be performed by a dry etching process, a wet etching process, or a suitable etching process. Figure 14 As shown, the annealing process 300 in block 118 creates a first gate dielectric layer 2221 in the gate trench of the first device region 1100 and a second gate dielectric layer 2222 in the gate trench of the second device region 1200. Due to the lack of any dipole layer, the gate dielectric layer 222 in the gate trench of the third device region 1300 remains substantially unchanged.

[0109] It was also observed that a thicker dipole layer contributes to a higher doping concentration of the dipole layer material in the gate dielectric layer 222. For example, when the gate dielectric layer 222 is formed of hafnium oxide and the first dipole layer 224 / second dipole layer 230 is formed of lanthanum oxide, the operation in block 118 can result in a first lanthanum concentration in the first gate dielectric layer 2221 in the gate trench of the first device region 1100, and a second lanthanum concentration in the second gate dielectric layer 2222 in the gate trench of the second device region 1200. Since there is no dipole layer in the gate trench of the third device region 1300, the gate dielectric layer 222 in the gate trench of the third device region 1300 contains a zero concentration of third lanthanum. Since the gate trench in the first device region 1100 includes both a first dipole layer 224 and a second dipole layer 230, the first lanthanum concentration is greater than the second lanthanum concentration, and greater than the zero concentration of the third lanthanum. The respective first, second, and third lanthanum concentrations can be represented by the ratio of lanthanum concentration (i.e., the [lanthanum] or [La] in the first dipole layer 224 / second dipole layer 230) to hafnium concentration (i.e., the [hafnium] or [Hf] in the gate dielectric layer 222). In the example above, the first lanthanum concentration (i.e., the ratio of the first lanthanum to hafnium) can be approximately 0.4 ([La] / [Hf]) and the second lanthanum concentration (i.e., the ratio of the second lanthanum to hafnium) can be approximately 0.2 ([La] / [Hf]) and the third lanthanum concentration (i.e., the ratio of the third lanthanum to hafnium) is zero. The preceding description generally applies to other dipole layer materials, such as yttrium and aluminum, as well as other gate dielectric materials, such as hafnium oxide (HfSiO), hafnium oxysilicon (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium dioxide (ZrO2), titanium dioxide (TiO2), and tantalum pentoxide (Ta2O5), provided that different dipole layer materials can have different diffusivity and different dipole layer materials can have different solid solubility in different gate dielectric layers.

[0110] refer to Figure 1 as well as Figure 15 Method 100 includes block 122, wherein further processes are performed to form a first transistor 410 in a first device region 1100, a second transistor 420 in a second device region 1200, and a third transistor 430 in a third device region 1300. As... Figure 15 As shown, the first transistor 410 includes a first gate dielectric layer 2221, the second transistor 420 includes a second gate dielectric layer 2222, and the third transistor 430 includes a gate dielectric layer 222. Each of the first transistor 410, second transistor 420, and third transistor 430 includes an interface layer 220 and a first gate dielectric layer 2221 / second gate dielectric layer 2222 / gate dielectric layer 222, as well as a functional metal gate stack 236. Since the first gate dielectric layer 2221 in the first transistor 410, the second gate dielectric layer 2222 in the second transistor 420, and the gate dielectric layer 222 in the third transistor 430 differ only in composition, not in size, the functional metal gate stacks 236 in all different device regions 1100, 1200, and 1300 are structurally and dimensionally identical.

[0111] The functional metal gate stack 236 may include one or more work function layers and a metal fill layer. N-type devices and p-type devices may have different work function layers. In some embodiments, while the n-type device region and the p-type device region may share a specific common work function layer, the n-type device region may include one or more work function layers not located in the p-type device region. Similarly, in another embodiment, the p-type device region may include one or more work function layers not located in the n-type device region. The p-type work function layer may contain any suitable p-type work function material, such as titanium nitride (TiN), tantalum nitride (TaN), silicon tantalum nitride (TaSN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), tungsten carbide (WCN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), other p-type work function materials, or combinations thereof. The N-type work function layer can contain any suitable n-type work function material, such as titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum carbide (TiAlSiC), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminide (TaAl), tantalum aluminum carbide (TaAlC), tantalum aluminum carbide (TaSiAlC), titanium aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof. It is important to note that the p-type work function layer is not limited to use in p-type device regions, and the n-type work function layer is not limited to use in n-type device regions. Both p-type and n-type work function layers can be applied to both n-type and p-type device regions to achieve the desired threshold voltage. Metal filler layers can be deposited on both the n-type and p-type device regions to fill any remaining portions of the gate trenches in the different device regions. The metal filler layer may contain suitable conductive materials such as aluminum (Al), tungsten (W), ruthenium (Ru), and / or copper (Cu). The metal filler layer may additionally or entirely contain other metals, metal nitrides, other suitable materials, or combinations thereof.

[0112] Due to the different interface dipoles created by the use of the first gate dielectric layer 2221, the second gate dielectric layer 2222, and the gate dielectric layer 222, the first transistor 410 in the first device region 1100, the second transistor 420 in the second device region 1200, and the third transistor 430 in the third device region 1300 have different threshold voltages. Different metal oxides have different oxygen atom areal densities. For example, the oxygen atom areal densities in lanthanum oxide and yttrium oxide are greater than those in silicon oxide, while the oxygen atom areal densities in aluminum oxide and hafnium oxide are greater than those in silicon oxide. Among these metal oxides, aluminum oxide has the highest oxygen atom areal density. In embodiments where the gate dielectric layer 222 essentially comprises hafnium oxide and the interface layer 220 essentially comprises silicon oxide, an interface dipole toward the gate dielectric layer 222 may be formed. When lanthanum or yttrium (having a smaller areal density of oxygen atoms than silicon oxide) in the first dipole layer 224 and the second dipole layer 230 is allowed to diffuse into the gate dielectric layer 222, the interface dipole toward the gate dielectric layer may be reduced or reversed. When aluminum (having a larger areal density of oxygen atoms than silicon oxide) in the first dipole layer 224 and the second dipole layer 230 is allowed to diffuse into the gate dielectric layer 222, the interface dipole toward the gate dielectric layer may be increased.

[0113] In an embodiment where the first gate dielectric layer 2221 has a first lanthanum concentration (i.e., the ratio of the first lanthanum to hafnium) of approximately 0.4 ([La] / [Hf]), the second gate dielectric layer 2222 has a second lanthanum concentration (i.e., the ratio of the second lanthanum to hafnium) of approximately 0.2 ([La] / [Hf]), and the gate dielectric layer 222 has a third lanthanum concentration of zero (i.e., the ratio of the third lanthanum to hafnium) of approximately zero ([La] / [Hf]), the first transistor 410 has a first threshold voltage (Vt1), the second transistor 420 has a second threshold voltage (Vt2), and the third transistor 430 has a third threshold voltage (Vt3). When the first transistor 410, the second transistor 420, and the third transistor 430 are n-type transistors, Vt1 can be approximately 150 mV smaller than Vt3, and Vt2 can be approximately 50 mV smaller than Vt3. When the first transistor 410, the second transistor 420, and the third transistor 430 are p-type transistors, Vt1 can be approximately 150 mV larger than Vt3, and Vt2 can be approximately 50 mV larger than Vt2.

[0114] The first transistor 410, the second transistor 420, and the third transistor 430 may be implemented in a static random access memory (SRAM) cell to improve the signal-to-noise margin (SNM) and write margin (WM) of the SRAM cell. For example, the first transistor 410, the second transistor 420, and the third transistor 430 may be implemented in... Figure 29 as well as Figure 30 The 8-transistor (8T) SRAM cell 900 shown is... Figure 31 as well as Figure 32 The 10-transistor (10T) SRAM cell 1000 is shown.

[0115] First refer to Figure 29The circuit diagram of the 8T SRAM cell 900 is shown. WL represents the word line, BL represents the bit line, BLB represents the complementary bit line, RWL represents the read word line, and RBL represents the read bit line. The 8T SRAM cell 900 includes a first pull-up transistor (PU1) 906 and a first pull-down transistor (PD1) 910 forming a first inverter, a second pull-up transistor (PU2) 908 and a second pull-down transistor (PD2) 912 forming a second inverter cross-coupled with the first inverter, and a first channel gate transistor (PG1) 902 and a second channel gate transistor (PG2) 904 configured to write data stored by the cross-coupled first inverter and second inverter. The 8T SRAM cell 900 further includes a read pull-down transistor (RPD) 914 and a read pass-gate transistor (RPG) 916, which form a read port (RP) 918 to access the data stored by the cross-coupled first inverter and second inverter. The drain electrodes of the first pull-up transistor (PU1) 906, the first pull-down transistor (PD1) 910, and the first channel gate transistor (PG1) 902 are electrically connected to the first data storage node Q. The drain electrodes of the second pull-up transistor (PU2) 908, the second pull-down transistor (PD2) 912, and the second channel gate transistor (PG2) 904 are electrically connected to the second data storage node QB. The gate electrodes of the second pull-up transistor (PU2) 908 and the second pull-down transistor (PD2) 912 are electrically connected to the drain electrodes of the first pull-down transistor (PD1) 910, the first channel gate transistor (PG1) 902, and the first pull-up transistor (PU1) 906 via the first data storage node Q. The gate electrodes of the first pull-up transistor (PU1) 906 and the first pull-down transistor (PD1) 910 are electrically connected to the drain electrodes of the second pull-down transistor (PD2) 912, the second channel gate transistor (PG2) 904, and the second pull-up transistor (PU2) 908 via the second data storage node QB. The source electrodes of the first pull-down transistor (PD1) 910, the second pull-down transistor (PD2) 912, and the read pull-down transistor (RPD) 914 are connected to the first power supply node Vss. The source electrodes of the first pull-up transistor (PU1) 906 and the second pull-up transistor (PU2) 908 are connected to the second power supply node Vdd. According to one embodiment, the first power supply node Vss is electrically connected to the virtual ground 920, while the second power supply node Vdd is electrically connected to a positive potential supplied by the power supply circuit of the SRAM (not shown).In some embodiments, the virtual ground 920 includes a hold transistor 922 and a power gate transistor 924.

[0116] Figure 29 The circuit diagram can be found in Figure 30 The layout diagram of the 8T SRAM cell 900 shown is implemented. In some embodiments, each of the first channel gate transistor (PG1) 902, the second channel gate transistor (PG2) 904, the first pull-down transistor (PD1) 910, the second pull-down transistor (PD2) 912, the read pull-down transistor (RPD) 914, and the read pass-gate transistor (RPG) 916 includes a gate structure 903 disposed on two active regions 905. Each of the first pull-up transistor (PU1) 906 and the second pull-up transistor (PU2) 908 includes a gate structure 903 disposed on a single active region 905 (including a first gate structure 903-1 and a second gate structure 903-2). When the active region is fin-shaped, the former can be referred to as a dual-fin device and the latter as a single-fin device.

[0117] In one embodiment, the power gate transistor 924 may be the first transistor 410. Since the first transistor 410 has the highest threshold voltage (first threshold voltage, Vt1) among the first transistor 410, second transistor 420, and third transistor 430, the first transistor 410 has the lowest leakage current and can reduce leakage current in the power gate transistor 924. In the same embodiment, the read port (RP) 918 may be formed by the third transistor 430. Since the third transistor 430 has the lowest threshold voltage (third threshold voltage, Vt3) among the first transistor 410, second transistor 420, and third transistor 430, the third transistor 430 has the highest switching rate and can improve the read rate of the 8T SRAM cell 900. In the same embodiment, a second transistor 420 with a median threshold voltage level (second threshold voltage, Vt2) can be applied to each of the first channel gate transistor (PG1) 902, the second channel gate transistor (PG2) 904, the first pull-down transistor (PD1) 910, and the second pull-down transistor (PD2) 912 to obtain balanced signal-noise margins (SNMs). Since the first pull-down transistor (PD1) 910, the second channel gate transistor (PG2) 904, and the read pass-gate transistor (RPG) 916 share the first gate structure 903-1, the two second transistors 420 (implemented with PD1 and PG1) and a third transistor 430 (implemented with RPG) share the first gate structure 903-1. Similarly, since the first channel gate transistor (PG1) 902, the second pull-down transistor (PD2) 912, and the read pull-down transistor (RPD) 914 share the second gate structure 903-2, the two second transistors 420 (implemented as PD2 and PG2) and a third transistor 430 (implemented as RPD) also share the second gate structure 903-2. As used herein, the gate structure is referred to as being shared by multiple transistors because the functional metal gate of this gate structure extends above the transistors. Reference Figure 15 Although the first transistor 410, the second transistor 420, and the third transistor 430 have different gate dielectric layers, the transistors may have a common functional metal gate stack 236. The common functional metal gate stack 236 allows the transistors of this disclosure to be shared with more than one transistor.

[0118] Please refer to the following: Figure 31The circuit diagram shown is for a 10T SRAM cell 1000. WL represents a word line, BL a bit line, BLB a complementary bit line, RWL a read word line, RBL a read bit line, and RBLB a read complementary bit line. The 10T SRAM cell 1000 includes a first pull-up transistor (PU1) 1006 and a first pull-down transistor (PD1) 1010 forming a first inverter, a second pull-up transistor (PU2) 1008 and a second pull-down transistor (PD2) 1012 forming a second inverter cross-coupled with the first inverter, and a first channel gate transistor (PG1) 1002 and a second channel gate transistor (PG2) 1004 configured to write data stored by the cross-coupled first and second inverters. The 10T SRAM cell 1000 further includes a first read port (RP1) 1014 and a second read port (RP2) 1016 for accessing data stored by the cross-coupled first and second inverters. The first read terminal 1014 includes a first read pull-down transistor (RPD1) 1018 and a first read pass-gate transistor (RPG1) 1020, while the second read terminal 1016 includes a second read pull-down transistor (RPD2) 1022 and a second read pass-gate transistor (RPG2) 1024. The drain electrodes of the first pull-up transistor (PU1) 1006, the first pull-down transistor (PD1) 1010, and the first pass-gate transistor (PG1) 1002 are electrically connected to the first data storage node Q. The drain electrodes of the second pull-up transistor (PU2) 1008, the second pull-down transistor (PD2) 1012, and the second pass-gate transistor (PG2) 1004 are electrically connected to the second data storage node QB. The gate electrodes of the second pull-up transistor (PU2) 1008 and the second pull-down transistor (PD2) 1012 are electrically connected to the drain electrodes of the first pull-down transistor (PD1) 1010, the first channel gate transistor (PG1) 1002, and the first pull-up transistor (PU1) 1006 through the first data storage node Q. The gate electrodes of the first pull-up transistor (PU1) 1006 and the first pull-down transistor (PD1) 1010 are electrically connected to the drain electrodes of the second pull-down transistor (PD2) 1012, the second channel gate transistor (PG2) 1004, and the second pull-up transistor (PU2) 1008 through the second data storage node QB.The source electrodes of the first pull-down transistor (PD1) 1010, the second pull-down transistor (PD2) 1012, the first read pull-down transistor (RPD1) 1018, and the second read pull-down transistor (RPD2) 1022 are connected to the first power supply node Vss, while the source electrodes of the first pull-up transistor (PU1) 1006 and the second pull-up transistor (PU2) 1008 are connected to the second power supply node Vdd. According to one embodiment, the first power supply node Vss is electrically connected to a virtual ground 1026, while the second power supply node Vdd is electrically connected to a positive potential supplied by the SRAM's power supply circuitry (not shown). In some embodiments, the virtual ground 1026 includes a hold transistor 1028 and a power gate transistor 1030.

[0119] Figure 31 The circuit diagram can be found in Figure 32 The layout diagram of the 10T SRAM cell 1000 shown is implemented. In some embodiments, each of the first channel gate transistor (PG1) 1002, the second channel gate transistor (PG2) 1004, the first pull-down transistor (PD1) 1010, the second pull-down transistor (PD2) 1012, the first read pull-down transistor (RPD1) 1018, the first read pass-gate transistor (RPG1) 1020, the second read pull-down transistor (RPD2) 1022, and the second read pass-gate transistor (RPG2) 1024 includes a gate structure 1003 disposed on two active regions 1005. Each of the first pull-up transistor (PU1) 1006 and the second pull-up transistor (PU2) 1008 includes a gate structure 1003 disposed on a single active region 1005 (including a first gate structure 1003-1 and a second gate structure 1003-2). When the active region is fin-shaped, the former can be called a double-fin device and the latter can be called a single-fin device.

[0120] In one embodiment, the power gate transistor 1030 may be a first transistor 410. Since the first transistor 410 has the highest threshold voltage (first threshold voltage, Vt1) among the first transistor 410, second transistor 420, and third transistor 430, the first transistor 410 has the lowest leakage current and can reduce leakage current in the power gate transistor 1030. In the same embodiment, the first read port (RP1) 1014 and the second read port (RP2) 1016 may be formed by the third transistor 430. Since the third transistor 430 has the lowest threshold voltage (third threshold voltage, Vt3) among the first transistor 410, second transistor 420, and third transistor 430, the third transistor 430 has the highest switching rate and can improve the read rate of the 10T SRAM cell 1000. In the same embodiment, a second transistor 420 with a median threshold voltage level (second threshold voltage, Vt2) can be applied to each of the first channel gate transistor (PG1) 1002, the second channel gate transistor (PG2) 1004, the first pull-down transistor (PD1) 1010, and the second pull-down transistor (PD2) 1012 to obtain balanced signal-noise margins (SNMs). Since the first read pull-down transistor (RPD1) 1018, the first pull-down transistor (PD1) 1010, the second channel gate transistor (PG2) 1004, and the second read pass-gate transistor (RPG2) 1024 share the first gate structure 1003-1, the two second transistors 420 (implemented with PD1 and PG1) and the two third transistors 430 (implemented with RPD1 and RPG2) share the first gate structure 1003-1. Similarly, since the first read pass-gate (RPG1) 1020, the first channel gate transistor (PG1) 1002, the second pull-down transistor (PD2) 1012, and the second read pull-down transistor (RPD2) 1022 share the second gate structure 1003-2, the two second transistors 420 (implemented as PD2 and PG2) and the two third transistors 430 (implemented as RPG1 and RPD2) also share the second gate structure 1003-2. As mentioned above, the gate structure is referred to as being shared with multiple transistors because the functional metal gate of this gate structure extends above the transistors. Reference Figure 28A as well as Figure 28BAlthough the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 have different gate dielectric layers, the transistors may have a common functional metal gate stack 236. The common functional metal gate stack 236 allows the transistors of this disclosure to be shared with more than one transistor.

[0121] Figure 16 A flowchart of a method 500 for forming a semiconductor device is depicted according to some embodiments of the present disclosure. Figures 2-5 , Figures 17-27 , Figure 28A ,as well as Figure 28B for Figure 16 A partial cross-sectional view of workpiece 200 during the various processes of method 500. Additional operations may be provided before, during, or after method 500, and some operations of additional embodiments of the described method 500 may be moved, replaced, or removed. Figures 2-5 , Figures 17-27 , Figure 28A ,as well as Figure 28B Additional features are added to the described contact structure, and these features can be moved, replaced, or removed. Figures 2-5 , Figures 17-27 , Figure 28A ,as well as Figure 28B Some of the features described below are from other embodiments of the interconnect structure shown.

[0122] refer to Figure 16 as well as Figure 2 Method 500 includes block 502, where block 502 receives workpiece 200. Since the operation in block 502 is similar to that in block 102 described above, it will not be repeated here. Furthermore, the detailed description of workpiece 200 and its many features have already been described above and are omitted here for brevity.

[0123] refer to Figure 16 as well as Figure 3 Method 500 includes block 504, in which a dummy gate stack 208 is removed to form a gate trench 218. Since the operation in block 504 is similar to that in block 104 described above, it will not be repeated here. Furthermore, the detailed description of the dummy gate stack 208 and the gate trench 218 has already been described above and is omitted here for brevity.

[0124] refer to Figure 16 as well as Figure 4Method 500 includes block 506, in which an interface layer 220 is deposited in a gate trench 218. Since the operation in block 506 is similar to that in block 106 described above, it will not be repeated here. Furthermore, a detailed description of the interface layer 220 has already been described above and is omitted here for brevity.

[0125] refer to Figure 16 as well as Figure 5 Method 500 includes block 508, in which a gate dielectric layer 222 is deposited on interface layer 220. Since the operation in block 508 is similar to that in block 108 described above, it will not be repeated here. Furthermore, a detailed description of the gate dielectric layer 222 has already been described above and is omitted here for brevity.

[0126] As described below, workpiece 200 may include multiple device regions (e.g., three device regions, four device regions, or more device regions) of transistors with different threshold voltages, and... Figures 2-5 The structure shown may span and repeat across the multiple device regions, but the repeated structure has been omitted, and instead... Figures 2-5 The ellipsis (“…”) shown is used to represent this. The operation of method 500, which differs for different device areas, will be related to… Figures 17-27 , Figure 28A ,as well as Figure 28B The following description is provided. For the sake of simplicity and clarity, Figures 17-27 A partial cross-sectional view of region "I" in different device areas.

[0127] refer to Figure 16 as well as Figure 6 Method 500 includes block 510, wherein a first dipole layer 224 is deposited on gate dielectric layer 222. Figures 17-27 , Figure 28A ,as well as Figure 28B In some of the depicted embodiments, workpiece 200 includes four device regions—a first device region 3100, a second device region 3200, a third device region 3300, and a fourth device region 3400. As described above, Figure 17A partial cross-sectional view depicting region "I" in the first device region 1100, the second device region 1200, the third device region 1300, and the fourth device region 3400. A first dipole layer 224 is deposited on the gate dielectric layer 222 in the gate trenches of the first device region 1100, the second device region 1200, the third device region 1300, and the fourth device region 3400. In some embodiments, the first dipole layer 224 may be formed of lanthanum oxide, yttrium oxide, or aluminum oxide, and may be deposited using atomic layer deposition (ALD). In some embodiments, the ALD process used to form the first dipole layer 224 may comprise between approximately 2 and approximately 10 cycles. In the embodiment described, the first dipole layer 224 may have approximately up to approximately The thickness is between [a certain value]. In one embodiment, the first dipole layer 224 may be formed of lanthanum oxide.

[0128] refer to Figure 16 , Figure 18 , Figure 19 ,as well as Figure 20 Method 500 includes block 512, wherein the first dipole layer 224 is selectively removed from the third device region 3300 and the fourth device region 3400. In some embodiments, lithography and etching techniques may be used to perform the operation of block 512. An example process is described in... Figures 18-20 Demonstration. First, refer to... Figure 18 First, a hard mask layer 226 is formed on the first dipole layer 224, and a bottom antireflective coating layer 228 is deposited on the hard mask layer 226. In some cases, the hard mask layer 226 may be a single thin layer or multiple layers. When the hard mask layer 226 is a single thin layer, it may comprise silicon oxide, silicon nitride, or silicon oxynitride. When the hard mask layer 226 is multiple layers, it may comprise a thin silicon layer and a thin silicon nitride layer on top of the silicon layer. The BARC layer 228 may comprise silicon oxynitride, a polymer, or a suitable material. To pattern the BARC layer 228 and the hard mask layer 226, a photoresist layer may be blanket-deposited on the workpiece 200, including the BARC layer 228 in the first device region 1100, the second device region 1200, and the third device region 1300. The photoresist layer may be a single thin layer or multiple layers, such as three layers. The photoresist layer is then exposed to radiation that penetrates or is reflected from the mask, baked in a post-baking process, and developed in a developer to form a patterned photoresist mask. The BARC layer 228 and the hard mask layer 226 are then patterned using the patterned photoresist mask to form an etch mask with openings above the third device region 3300 and the fourth device region 3400. The first dipole layer 224 in the gate trenches of the third device region 3300 and the fourth device region 3400 is then selectively etched away in the etch process using the etch mask, such as... Figure 19The etching process can be dry etching, wet etching, or a suitable etching process. (See reference.) Figure 20 After the first dipole layer 224 is selectively etched away from the gate trenches in the third device region 3300 and the fourth device region 3400, the hard mask layer 226 and the BARC layer 228 in the first device region 3100 and the second device region 3200 are removed using a suitable etching process.

[0129] refer to Figure 16 as well as Figure 21 Method 500 includes block 514, wherein workpiece 200 is annealed in a first annealing process 600. In block 514, the first annealing process 600 thermally drives elements in a first dipole layer 224 to a gate dielectric layer 222 in a gate trench in a first device region 3100 and a second device region 3200. The first dipole layer 224 serves as a diffusion doping carrier to directly contact the gate dielectric layer 222 in the first device region 3100 and the second device region 3200 with the elements. The first annealing process 600 may be a rapid thermal annealing process, a laser tip annealing process, a rapid annealing process, or a furnace annealing process. In some embodiments, the first annealing process 600 includes a high annealing temperature between approximately 500°C and approximately 900°C, such that lanthanum, yttrium, or aluminum in the first dipole layer 224 diffuses to the gate dielectric layer 222 in the gate trench in the first device region 3100 and the second device region 3200. Since the gate trenches in the third device region 3300 and the fourth device region 3400 do not have a first dipole layer 224, the first annealing process 600 in block 514 does not cause any dipole layer material to diffuse into the gate dielectric layer 222 in the third device region 3300 and the fourth device region 3400. In some embodiments, the first annealing process 600 may last between approximately 5 seconds and approximately 20 seconds. Figure 22 As shown, after the first annealing process 600 in block 514, the elements in the first dipole layer 224 diffuse to the gate dielectric layer 222 to form the second gate dielectric layer 2232 in the gate trenches in the first device region 3100 and the second device region 3200.

[0130] refer to Figure 16 as well as Figure 22Method 500 includes block 516, wherein a first dipole layer 224 is selectively removed from workpiece 200. In some embodiments, lithography and etching techniques may be used at block 516 to avoid damaging the gate dielectric layer 222 in the third device region 3300 and the fourth device region 3400. For example, a hard mask, a bottom anti-reflective coating layer, and a photoresist layer may be deposited on workpiece 200. The hard mask, BARC layer, and photoresist layer are then patterned to form an etch mask that exposes the first dipole layer 224 in the gate trenches in the first device region 3100 and the second device region 3200. The first dipole layer 224 is then etched using the etch mask with a dry etching process, a wet etching process, or a suitable etching process. The etch mask formed by the hard mask and the BARC layer is then removed. At the end of block 516, the second gate dielectric layer 2232 in the gate trenches of the first device region 3100 and the second device region 3200 is exposed, and the gate dielectric layer 222 in the gate trenches of the third device region 3300 and the fourth device region 3400 is exposed.

[0131] refer to Figure 16 as well as Figure 23 Method 500 includes block 518, wherein a second dipole layer 240 is deposited on workpiece 200. For example... Figure 23 As shown, the second dipole layer 240 is deposited on the second gate dielectric layer 2232 in the gate trenches of the first device region 3100 and the second device region 3200, and on the gate dielectric layer 222 in the gate trenches of the third device region 3300 and the fourth device region 3400. In some embodiments, the second dipole layer 240 and the first dipole layer 224 may have the same composition. Similar to the first dipole layer 224, the second dipole layer 240 may also be formed of lanthanum oxide, yttrium oxide, or aluminum oxide, and may be deposited using atomic layer deposition (ALD). In some embodiments, the ALD process used to deposit the second dipole layer 240 may include approximately 2 to approximately 5 cycles. In some embodiments, the second dipole layer 240 may have approximately up to approximately Between the thicknesses. In one embodiment, the second dipole layer 240 may be formed of lanthanum oxide. The difference between the second dipole layer 230 and the embodiment depicted in Figures 2-15 is that... Figures 17-27 , Figure 28A ,as well as Figure 28B The second dipole layer 240 in the depicted embodiment is relatively thin. It has approximately... up to approximately The thickness of the second dipole layer 240 is approximately [missing information - likely a number]. up to approximately The first dipole layer 224 is still thinner than the first dipole layer between the thicknesses.

[0132] refer to Figure 16 , Figure 24 , Figure 25 ,as well as Figure 26 Method 500 includes block 520, in which the second dipole layer 240 is selectively removed from the gate trenches in the second device region 3200 and the fourth device region 3400. Similar to the operation in block 112 of method 100, the operation in block 520 can also be performed using lithography and etching techniques. For example, as... Figure 24 As shown, a hard mask layer 242 and a bottom antireflective coating (BARC) layer 244 can be formed on the second dipole layer 240. Since the hard mask layer 242 can be similar to the hard mask layer 226, and the BARC layer 244 can be similar to the BARC layer 228, detailed descriptions of the hard mask layer 242 and the BARC layer 244 are omitted for brevity. Following this, a photoresist layer can be deposited on the BARC layer 244. The photoresist layer, BARC layer 244, and hard mask layer 242 are then patterned in a manner similar to that described in block 112 of the corresponding method 100, and will not be repeated here. The patterned hard mask layer 242 allows for the selective removal of the second dipole layer 240 in the gate trenches of the second device region 3200 and the fourth device region 3400, exposing the second gate dielectric layer 2232 in the second device region 3200 and the gate dielectric layer 222 in the fourth device region 3400. Figure 25 As depicted, at this moment, the gate trench in the first device region 3100 includes the second gate dielectric layer 2232 and the second dipole layer 240 described above; the gate trench in the second device region 3200 includes the second gate dielectric layer 2232 described above; the gate trench in the third device region 3300 includes the second dipole layer 240 described above; and the gate trench in the fourth device region 3400 is not covered by any dipole layer. After selectively removing the second dipole layer 240 from the gate trenches in the second device region 3200 and the fourth device region 3400, as... Figure 26 As depicted, the hard mask layer 242 and the BARC layer 244 can then be removed from the first device area 3100 and the third device area 3300.

[0133] refer to Figure 16 as well as Figure 26Method 500 includes block 522, wherein workpiece 200 is annealed in a second annealing process 700. In block 522, the second annealing process 700 thermally drives elements in the second dipole layer 240 to the second gate dielectric layer 2232 in the gate trench of the first device region 3100 and the gate dielectric layer 222 in the gate trench of the third device region 3300. The second dipole layer 240 serves as a diffusion doping carrier to directly contact the second gate dielectric layer 2232 and the gate dielectric layer 222 with the elements. The second annealing process 700 may be a rapid thermal annealing process, a laser tip annealing process, a rapid annealing process, or a furnace annealing process. In some embodiments, the second annealing process 700 includes a high annealing temperature between approximately 500°C and approximately 900°C, allowing lanthanum, yttrium, or aluminum in the second dipole layer 240 to diffuse into the second gate dielectric layer 2232 in the gate trench of the first device region 3100 and the gate dielectric layer 222 in the gate trench of the third device region 3300. Since there is no dipole layer in the gate trench of the fourth device region 3400, the annealing process 700 at block 522 does not cause any dipole layer material to diffuse into the gate dielectric layer 222 in the fourth device region 3400. In some embodiments, the second annealing process 700 may last between approximately 5 seconds and approximately 20 seconds.

[0134] refer to Figure 16 as well as Figure 27 Method 100 includes block 524, in which a second dipole layer 240 is removed from workpiece 200. The operation of block 524 can be performed by a dry etching process, a wet etching process, or a suitable etching process. Next, elements in the second dipole layer 240 are thermally driven to a second gate dielectric layer 2232 in the first device region 3100 and a gate dielectric layer 222 in the third device region 3300. In block 524, the second dipole layer 240 is removed from gate trenches in the first device region 3100 and the third device region 3300. Due to the second annealing process in block 522, a first gate dielectric layer 2231 is formed on the gate trench in the first device region 3100, and a third gate dielectric layer 2233 is formed on the gate trench in the third device region 3300. In summary, the first dipole layer 224 driven in annealing process 600 and the second dipole layer 240 driven in annealing process 700 form the first gate dielectric layer 2231 in the first device region 3100; the first dipole layer 224 driven in annealing process 600 forms the second gate dielectric layer 2232 in the second device region 3200; the second dipole layer 240 driven in annealing process 700 forms the third gate dielectric layer 2233 in the third device region 3300, while the gate dielectric layer 222 in the fourth device region 3400 has no element diffusion of any dipole layer.

[0135] It was also observed that a thicker dipole layer and an enhanced annealing process contribute to a higher doping concentration of the dipole layer material in the gate dielectric layer 222. For example, when the gate dielectric layer 222 is formed of hafnium oxide and the first dipole layer 224 / second dipole layer 240 is formed of lanthanum oxide, the operation in block 526 can result in a first lanthanum concentration in the first gate dielectric layer 2231 in the first device region 3100, a second lanthanum concentration in the second gate dielectric layer 2232 in the second device region 3200, a third lanthanum concentration in the third device region 3300, and a fourth lanthanum concentration in the fourth device region 3400. The first lanthanum concentration is greater than the second lanthanum concentration, the second lanthanum concentration is greater than the third lanthanum concentration, and the third lanthanum concentration is greater than the fourth lanthanum concentration. Since there is no dipole layer in the gate trench in the fourth device region 3400, the fourth lanthanum concentration is zero. The first, second, third, and fourth lanthanum concentrations can be represented by the ratio of lanthanum concentration (i.e., the ratio of [lanthanum] or [La] in the first dipole layer 224 / second dipole layer 240) to hafnium concentration (i.e., the ratio of [hafnium] or [Hf] in the gate dielectric layer 222). In the example above, the first lanthanum concentration (i.e., the ratio of the first lanthanum to hafnium) can be approximately 0.6 ([lanthanum (La)] / [hafnium (Hf)]), the second lanthanum concentration (i.e., the ratio of the second lanthanum to hafnium) can be approximately 0.4 ([lanthanum (La)] / [hafnium (Hf)]), the third lanthanum concentration (i.e., the ratio of the third lanthanum to hafnium) can be approximately 0.2 ([lanthanum (La)] / [hafnium (Hf)]), and the fourth lanthanum concentration (i.e., the ratio of the fourth lanthanum to hafnium) is zero. The preceding description generally applies to other dipole layer materials, such as yttrium and aluminum, as well as other gate dielectric materials, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium dioxide (ZrO2), titanium dioxide (TiO2), and tantalum pentoxide (Ta2O5), provided that different dipole layer materials can have different diffusivity and different dipole layer materials can have different solid solubility in different gate dielectric layers.

[0136] refer to Figure 16 , Figure 28A as well as Figure 28B Method 500 includes block 526, wherein further processes are performed to form a first transistor 810 in a first device region 3100, a second transistor 820 in a second device region 3200, a third transistor 830 in a third device region 3300, and a fourth transistor 840 in a fourth device region 3400. Figure 28A as well as Figure 28BAs shown, the first transistor 810 includes a first gate dielectric layer 2231, the second transistor 820 includes a second gate dielectric layer 2232, the third transistor 830 includes a third gate dielectric layer 2233, and the fourth transistor 840 includes a gate dielectric layer 222. Each of the first transistor 810, second transistor 820, third transistor 830, and fourth transistor 840 includes an interface layer 220 and the first / second / third / second / gate dielectric layers 2231 / 2232 / 3233 / 222, as well as a functional metal gate stack 236. Since the first gate dielectric layer 2231 in the first transistor 810, the second gate dielectric layer 2232 in the second transistor 820, the third gate dielectric layer 2233 in the third transistor 830, and the gate dielectric layer 222 in the fourth transistor 840 are only different in composition rather than in size, the functional metal gate stacks 236 of all different device regions 3100, 3200, 3300, and 3400 are structurally and dimensionally uniform.

[0137] The functional metal gate stack 236 may include one or more work function layers and a metal fill layer. N-type devices and p-type devices may have different work function layers. In some embodiments, while the n-type device region and the p-type device region may share a specific common work function layer, the n-type device region may include one or more work function layers not located in the p-type device region. Similarly, in another embodiment, the p-type device region may include one or more work function layers not located in the n-type device region. The p-type work function layer may contain any suitable p-type work function material, such as titanium nitride (TiN), tantalum nitride (TaN), silicon tantalum nitride (TaSN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), tungsten carbide (WCN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), other p-type work function materials, or combinations thereof. The N-type work function layer can contain any suitable n-type work function material, such as titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum carbide (TiAlSiC), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminide (TaAl), tantalum aluminum carbide (TaAlC), tantalum aluminum carbide (TaSiAlC), titanium aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof. It is important to note that the p-type work function layer is not limited to use in p-type device regions, and the n-type work function layer is not limited to use in n-type device regions. Both p-type and n-type work function layers can be applied to both n-type and p-type device regions to achieve the desired threshold voltage. Metal filler layers can be deposited on both the n-type and p-type device regions to fill any remaining portions of the gate trenches in the different device regions. The metal filler layer may contain suitable conductive materials such as aluminum (Al), tungsten (W), ruthenium (Ru), and / or copper (Cu). The metal filler layer may additionally or entirely contain other metals, metal nitrides, other suitable materials, or combinations thereof.

[0138] Due to the different interface dipoles created by the use of the first gate dielectric layer 2231, the second gate dielectric layer 2232, the third gate dielectric layer 2233, and the gate dielectric layer 222, the first transistor 810 in the first device region 3100, the second transistor 820 in the second device region 3200, the third transistor 830 in the third device region 3300, and the fourth transistor 840 in the fourth device region 3400 have different threshold voltages. Different metal oxides have different oxygen atom areal densities. For example, the areal density of oxygen atoms in lanthanum oxide and yttrium oxide is greater than that in silicon oxide, while the areal density of oxygen atoms in aluminum oxide and hafnium oxide is greater than that in silicon oxide. Among these metal oxides, aluminum oxide has the largest oxygen atom areal density. In embodiments where the gate dielectric layer 222 essentially comprises hafnium oxide and the interface layer 220 essentially comprises silicon oxide, an interface dipole toward the gate dielectric layer 222 can be formed. When lanthanum or yttrium (with a smaller areal density of oxygen atoms than silicon oxide) in the first dipole layer 224 and the second dipole layer 240 are allowed to diffuse into the gate dielectric layer 222, the interface dipoles toward the gate dielectric layer can be reduced or reversed. When aluminum (with a larger areal density of oxygen atoms than silicon oxide) in the first dipole layer 224 and the second dipole layer 240 is allowed to diffuse into the gate dielectric layer 222, the interface dipoles toward the gate dielectric layer can be increased.

[0139] The first gate dielectric layer 2231 has a first lanthanum concentration (i.e., the ratio of first lanthanum to hafnium) of approximately 0.6 ([lanthanum (La)] / [hafnium (Hf)]), the second gate dielectric layer 2232 has a second lanthanum concentration (i.e., the ratio of second lanthanum to hafnium) of approximately 0.4 ([lanthanum (La)] / [hafnium (Hf)]), and the third gate dielectric layer 2233 has a third lanthanum concentration (i.e., the ratio of third lanthanum to hafnium) of approximately 0.2 ([lanthanum (La)]). In embodiments where the gate dielectric layer 222 has a fourth lanthanum concentration of zero (i.e., the ratio of fourth lanthanum to hafnium) of approximately zero ([lanthanum (La)] / [hafnium (Hf)]), the first transistor 810 has a first threshold voltage (Vt1), the second transistor 820 has a second threshold voltage (Vt2), the third transistor 830 has a third threshold voltage (Vt3), and the fourth transistor 840 has a fourth threshold voltage (Vt4). When the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 are n-type transistors, Vt1 may be approximately 250 mV smaller than Vt4, Vt2 may be approximately 150 mV smaller than Vt4, and Vt3 may be approximately 50 mV smaller than Vt4. When the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 are p-type transistors, Vt1 can be approximately 250 mV larger than Vt4, Vt1 can be approximately 150 mV larger than Vt3, and Vt1 can be approximately 50 mV larger than Vt2.

[0140] The first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 can be implemented in a static random access memory (SRAM) cell to improve the signal-to-noise margin (SNM) and write margin (WM) of the SRAM cell. For example, the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 can be implemented in... Figure 29 as well as Figure 30 In the 8-transistor (8T) SRAM cell 900 shown, or Figure 31 as well as Figure 32 The 10-transistor (10T) SRAM cell 1000 shown is an example.

[0141] In some embodiments, the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 may be implemented in Figure 29 as well as Figure 30 In the 8T SRAM cell 900 shown, in one example, a first transistor 810 having a first threshold voltage Vt1 can be implemented as a first channel gate transistor (PG1) 902 and a second channel gate transistor (PG2) 904; a second transistor 820 having a second threshold voltage Vt2 can be implemented as a first pull-down transistor (PD1) 910 and a second pull-down transistor (PD2) 912; a third transistor 830 having a third threshold voltage Vt3 can be implemented as a read pass-gate transistor (RPG) 916; and a fourth transistor 840 having a fourth threshold voltage Vt4 can be implemented as a read pull-down transistor (RPD) 914. In the aforementioned example, since the third transistor 830 and the fourth transistor 840 have lower threshold voltages than the first transistor 810 and the second transistor 820, the read port (RP) 918 can have a faster read rate. In addition, because the transistors with higher threshold voltages have smaller leakage currents (i.e., drive currents), the leakage current through the first channel gate transistor (PG1) 902 and the second channel gate transistor (PG2) 904 is less than the leakage current through the first pull-down transistor (PD1) 910 and the second pull-down transistor (PD2) 912. This arrangement allows the beta(β) ratio of the 8T SRAM cells 900 to increase, and an increase in the beta(β) ratio corresponds to improved read stability.

[0142] In the described embodiment, since the first pull-down transistor (PD1) 910, the second channel gate transistor (PG2) 904, and the read pass-gate (RPG) 916 share the first gate structure 903-1, a first transistor 810 (implemented in PG2), a second transistor 820 (implemented in PD1), and a third transistor 830 (implemented in RPG) share the first gate structure 903-1. Similarly, since the first channel gate transistor (PG1) 902, the second pull-down transistor (PD2) 912, and the read pull-down transistor (RPD) 914 share the second gate structure 903-2, a first transistor 810 (implemented in PG1), a second transistor 820 (implemented in PD2), and a third transistor 830 (implemented in RPD) share the second gate structure 903-2. As described above, since the functional metal stack of the gate structure extends over multiple transistors, the gate structure is referred to as being shared by multiple transistors. Reference Figure 28A as well as Figure 28BAlthough the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 have different gate dielectric layers, the aforementioned transistors may have a common functional metal gate stack 236. The common functional metal gate stack 236 allows the transistors of this disclosure to be shared with more than one transistor.

[0143] In other embodiments, the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 may be implemented in Figure 31 as well as Figure 32 In the 10T SRAM cell 1000 shown, in one example, a first transistor 810 having a first threshold voltage Vt1 can be implemented as a first channel gate transistor (PG1) 1002 and a second channel gate transistor (PG2) 1004; a second transistor 820 having a second threshold voltage Vt2 can be implemented as a first pull-down transistor (PD1) 1010 and a second pull-down transistor (PD2) 1012; a third transistor 830 having a third threshold voltage Vt3 can be implemented as a first read pass-gate transistor (RPG1) 1020 and a second read pass-gate transistor (RPG2) 1024; and a fourth transistor 840 having a fourth threshold voltage Vt4 can be implemented as a first read pull-down transistor (RPD1) 1018 and a second read pull-down transistor (RPD2) 1022. In the aforementioned example, because the third transistor 830 and the fourth transistor 840 have lower threshold voltages than the first transistor 810 and the second transistor 820, the first read port (RP1) 1014 and the second read port (RP2) 1016 can have faster read rates. Furthermore, because the transistors with higher threshold voltages have smaller leakage currents (i.e., drive currents), the leakage current through the first channel gate transistor (PG1) 1002 and the second channel gate transistor (PG2) 1004 is less than the leakage current through the first pull-down transistor (PD1) 1010 and the second pull-down transistor (PD2) 1012. This arrangement allows the beta(β) ratio of the 10T SRAM cell 1000 to increase, and an increase in the beta(β) ratio translates into improved read stability.

[0144] In the embodiment, since the first read pull-down transistor (RPD1) 1018, the first pull-down transistor (PD1) 1010, the second channel gate transistor (PG2) 1004, and the second read pass-gate transistor (RPG2) 1024 share the first gate structure 1003-1, a first transistor 810 (implemented as PG2), a second transistor 820 (implemented as PD1), a third transistor 830 (implemented as RPG2), and a fourth transistor 840 (implemented as RPD1) share the first gate structure 1003-1. Similarly, since the first read pass-gate (RPG1) 1020, the first channel gate transistor (PG1) 1002, the second pull-down transistor (PD2) 1012, and the second read pull-down transistor (RPD2) 1022 share the second gate structure 1003-2, a first transistor 810 (implemented in PG1), a second transistor 820 (implemented in PD2), a third transistor 830 (implemented in RPG1), and a fourth transistor 840 (implemented in RPD2) share the second gate structure 1003-2. As described above, since the functional metal stack of the gate structure extends over multiple transistors, the gate structure is referred to as being shared by multiple transistors. Reference Figure 28A as well as Figure 28B Although the first transistor 810, the second transistor 820, the third transistor 830, and the fourth transistor 840 have different gate dielectric layers, the aforementioned transistors may have a common functional metal gate stack 236. The common functional metal gate stack 236 allows the transistors of this disclosure to be shared with more than one transistor.

[0145] Throughout this disclosure, features with similar components may be designated using similar reference numerals, provided that the aforementioned device regions and features can be renumbered for different embodiments. For example, Figure 6 The three device areas are the first device area 1100, the second device area 1200, and the third device area 1300. Figure 17 The four device regions are designated as first device region 3100, second device region 3200, third device region 3300, and fourth device region 3400. The same numbering convention applies to the gate dielectric layer (e.g., Figure 15 222, 2221, 2222 and Figure 28A as well as Figure 28B 222, 2231, 2232, and 2233), transistors (e.g., Figure 15 410, 420, 430 and Figure 28A as well as Figure 28B (810, 820, 830, and 840 in the original text). In addition, while the first dipole layer 224 may be similar to methods 100 and 500 respectively, the second dipole layer 230 in method 100 and the second dipole layer 240 in method 500 may be dissimilar. Therefore, the aforementioned second dipole layers are designated with different reference numerals. Furthermore, the interface layer 220, the gate dielectric layer 222 (or the first, second, or third gate dielectric layer, as may be in different embodiments), and the functional metal gate stack 236 may, in some cases, be referred to as a metal gate structure or a functional metal gate structure.

[0146] The method disclosed herein discloses a mechanism for providing transistors with different threshold voltages without affecting the process window for forming the gate structure. One or more dipole layers are selectively deposited on the gate dielectric layer and act as a carrier for diffusion dopant to dope the gate dielectric layer, rather than introducing an additional dipole layer remaining in the gate trench. Depending on the thickness of the dipole layer, the duration of the annealing process, and the material of the dipole layer, the interface between the doped gate dielectric layer and the interface layer can have different interface dipoles. After the doping process, the used dipole layer is removed from the gate trench. That is, the method of this disclosure retains the benefits of utilizing different threshold voltages of the dipole layers without any associated disadvantages. This disclosure provides embodiments for implementing three levels of threshold voltages in a semiconductor device with three device regions, and also provides embodiments for implementing four levels of threshold voltages in a semiconductor device with four device regions. Transistors with different levels in this disclosure can be applied to SRAM cells, such as 8T SRAM cells or 10T SRAM cells, to improve the performance of the SRAM cells. Upon review of this embodiment, those skilled in the art will recognize that it is possible to have higher threshold voltages in more devices.

[0147] In one embodiment, this disclosure provides a semiconductor device including a first transistor, a second transistor, and a third transistor. The first transistor includes a first active region and a first gate dielectric layer. On the first active region, the first gate dielectric layer includes a first concentration of a dipole layer material and a first gate structure, disposed on the first gate dielectric layer. The second transistor includes a second active region and a second gate dielectric layer. On the second active region, the second gate dielectric layer includes a second concentration of a dipole layer material and a second gate structure, disposed on the second gate dielectric layer. The third transistor includes a third active region and a third gate dielectric layer. On the third active region, the third gate dielectric layer includes a third concentration of a dipole layer material and a third gate structure, disposed on the third gate dielectric layer. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration, and the second concentration is greater than the third concentration.

[0148] In some embodiments, the first gate structure, the second gate structure, and the third gate structure are substantially identical to each other. In some embodiments, the third concentration is zero. In some embodiments, the first transistor, the second transistor, and the third transistor are n-type transistors. The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, and the third transistor includes a third threshold voltage. The first threshold voltage is less than the second threshold voltage, and the second threshold voltage is less than the third threshold voltage. In some embodiments, the first transistor, the second transistor, and the third transistor are p-type transistors. The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, and the third transistor includes a third threshold voltage. The first threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the third threshold voltage. In some embodiments, the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer further include hafnium oxide.

[0149] In another embodiment, this disclosure provides a method for manufacturing a semiconductor device, comprising providing a workpiece, the workpiece including a first device region, a second device region, and a third device region; forming a first gate trench in the first device region, a second gate trench in the second device region, and a third gate trench in the third device region; depositing a gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench; depositing a first dipole layer on the gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench; selectively removing the first dipole layer in the second gate trench; depositing a second dipole layer on the first dipole layer in the first gate trench, the gate dielectric layer in the second gate trench, and the first dipole layer in the third gate trench; selectively removing the first dipole layer and the second dipole layer in the third gate trench; and annealing the workpiece.

[0150] In some embodiments, the method of manufacturing a semiconductor device further includes removing a first dipole layer and a second dipole layer from the workpiece after annealing the workpiece. In some embodiments, the first dipole layer and the second dipole layer comprise lanthanum oxide, aluminum oxide, or yttrium oxide. In some embodiments, the annealing of the workpiece is performed at a temperature between approximately 500°C and approximately 900°C. In some embodiments, the annealing of the workpiece is performed for a duration between approximately 5 seconds and approximately 20 seconds. In some embodiments, the thickness of the first dipole layer and the thickness of the second dipole layer are approximately... up to approximately In some embodiments, selectively removing the first dipole layer in the second gate trench includes depositing a hard mask layer on a workpiece, depositing a bottom antireflective coating layer on the hard mask layer, patterning the bottom antireflective coating layer and the hard mask layer to expose the second gate trench, and removing the first dipole layer in the second gate trench while the hard mask layer and the bottom antireflective coating layer cover the first gate trench and the third gate trench. In some embodiments, the first dipole layer has a first thickness, the second dipole layer has a second thickness, and the first thickness is substantially the same as the second thickness.

[0151] In another embodiment, this disclosure provides a method for manufacturing a semiconductor device, comprising providing a workpiece including a first device region, a second device region, a third device region, and a fourth device region; forming a first gate trench in the first device region; forming a second gate trench in the second device region; forming a third gate trench in the third device region; and forming a fourth gate trench in the fourth device region; depositing a gate dielectric layer; depositing a first dipole layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench; and depositing the first dipole layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench. On the gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench, the first dipole layer in the third gate trench and the fourth gate trench is selectively removed. A first annealing process is performed on the workpiece to remove the first dipole layer in the first gate trench and the second gate trench. After removing the first dipole layer, a second dipole layer is deposited on the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench. A second dipole layer in the second gate trench and the fourth gate trench is selectively removed. A second annealing process is performed on the workpiece, and the second dipole layer is removed from the workpiece.

[0152] In some embodiments, the first dipole layer has a first thickness, the second dipole layer has a second thickness, and the first thickness is greater than the second thickness. In some embodiments, the first thickness is approximately... up to approximately Between and the second thickness is approximately up to approximately Between. In some embodiments, the first and second dipole layers comprise lanthanum oxide, aluminum oxide, or yttrium oxide. In some embodiments, the first and second annealing processes are performed at temperatures between approximately 500°C and approximately 900°C. In some embodiments, the first and second annealing processes are performed for durations between approximately 5 seconds and approximately 20 seconds.

[0153] The foregoing outlines features of several embodiments that enable those skilled in the art to more readily understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device comprising: A first transistor, comprising: First active zone; A first gate dielectric layer, on the first active region, the first gate dielectric layer comprising a first concentration of a dipole layer material; and A first gate structure is disposed on the first gate dielectric layer; A second transistor, comprising: The second active zone; A second gate dielectric layer, on the second active region, the second gate dielectric layer comprising a second concentration of the dipole layer material; and A second gate structure is disposed on the second gate dielectric layer; and A third transistor, comprising: The third active zone; A third gate dielectric layer, on the third active region, the third gate dielectric layer comprising a third concentration of the dipole layer material; and A third gate structure is disposed on the third gate dielectric layer; The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide; Wherein the first concentration is greater than the second concentration, and the second concentration is greater than the third concentration; The first gate structure, the second gate structure, and the third gate structure are substantially identical to each other in terms of structure and size.

2. The semiconductor device of claim 1, wherein the first gate structure, the second gate structure, and the third gate structure are substantially identical in composition to each other.

3. The semiconductor device of claim 1, wherein the third concentration is zero.

4. The semiconductor device of claim 1, wherein: The first transistor, the second transistor, and the third transistor are n-type transistors; The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, and the third transistor includes a third threshold voltage; and The first critical voltage is less than the second critical voltage, and the second critical voltage is less than the third critical voltage.

5. The semiconductor device of claim 1, wherein: The first transistor, the second transistor, and the third transistor are p-type transistors; The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, and the third transistor includes a third threshold voltage; and The first critical voltage is greater than the second critical voltage, and the second critical voltage is greater than the third critical voltage.

6. The semiconductor device of claim 1, wherein the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer further comprise hafnium oxide.

7. A method for manufacturing a semiconductor device, comprising: A workpiece is provided, the workpiece comprising a first device area, a second device area and a third device area; A first gate trench is formed in the first device region, a second gate trench is formed in the second device region, and a third gate trench is formed in the third device region. A gate dielectric layer is deposited in the first gate trench, the second gate trench, and the third gate trench; A first dipole layer is deposited on the gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench; Selectively removing the first dipole layer in the second gate trench includes: A hard masking layer is deposited on the workpiece; A bottom anti-reflective coating (BARC) layer is deposited on the hard mask layer; The bottom anti-reflective coating layer and the hard mask layer are patterned to expose the second gate trench; as well as While the hard mask layer and the bottom anti-reflective coating layer cover the first gate trench and the third gate trench, the first dipole layer in the second gate trench is removed; A second dipole layer is deposited on the first dipole layer in the first gate trench, the gate dielectric layer in the second gate trench, and the first dipole layer in the third gate trench; Selectively remove the first dipole layer and the second dipole layer in the third gate trench; Anneal the workpiece; as well as A first gate structure, a second gate structure, and a third gate structure are formed in the first gate trench, the second gate trench, and the third gate trench, respectively, wherein the first gate structure, the second gate structure, and the third gate structure are identical to each other in terms of structure and size.

8. The method of manufacturing a semiconductor device as claimed in claim 7, further comprising: After annealing the workpiece, the first dipole layer and the second dipole layer are removed from the workpiece.

9. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the first dipole layer and the second dipole layer comprise lanthanum oxide, aluminum oxide, or yttrium oxide.

10. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the annealing of the workpiece is performed at a temperature between 500°C and 900°C.

11. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the annealing of the workpiece comprises a duration between 5 seconds and 20 seconds.

12. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the thickness of the first dipole layer and the thickness of the second dipole layer are between 1 Å and 10 Å.

13. The method of manufacturing a semiconductor device as claimed in claim 7, wherein: The first dipole layer has a first thickness; The second dipole layer comprises a second thickness; and The first thickness is essentially the same as the second thickness.

14. A method for manufacturing a semiconductor device, comprising: A workpiece is provided, the workpiece comprising a first device area, a second device area, a third device area and a fourth device area; A first gate trench is formed in the first device region, a second gate trench is formed in the second device region, a third gate trench is formed in the third device region, and a fourth gate trench is formed in the fourth device region. A gate dielectric layer is deposited in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench; A first dipole layer is deposited on the gate dielectric layer in the first gate trench, the second gate trench, the third gate trench and the fourth gate trench; Selectively remove the first dipole layer in the third gate trench and the fourth gate trench; The workpiece undergoes a first annealing process. Remove the first dipole layer in the first gate trench and the second gate trench; After removing the first dipole layer, a second dipole layer is deposited on the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench. Selectively remove the second dipole layer in the second gate trench and the fourth gate trench; The workpiece undergoes a second annealing process. Remove the second dipole layer from the workpiece; as well as After the second dipole layer is removed, a first metal gate stack, a second metal gate stack, a third metal gate stack, and a fourth metal gate stack are formed in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench, respectively, wherein the first metal gate stack, the second metal gate stack, the third metal gate stack, and the fourth metal gate stack are identical to each other in terms of structure and size.

15. The method of manufacturing a semiconductor device as claimed in claim 14, wherein: The first dipole layer has a first thickness; The second dipole layer comprises a second thickness; and The first thickness is greater than the second thickness.

16. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the first thickness is between 5 Å and 10 Å, and the second thickness is between 1 Å and 5 Å.

17. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the first dipole layer and the second dipole layer comprise lanthanum oxide, aluminum oxide, or yttrium oxide.

18. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the first annealing process and the second annealing process are performed at temperatures between 500°C and 900°C.

19. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the first annealing process and the second annealing process comprise a duration between 5 seconds and 20 seconds.

20. A semiconductor device comprising: A first transistor, comprising: First active zone; A first gate dielectric layer, on the first active region, the first gate dielectric layer comprising a dipole-containing material of a first concentration; and A first metal gate stack is disposed above and in contact with the first gate dielectric layer; A second transistor, comprising: The second active zone; A second gate dielectric layer, on the second active region, the second gate dielectric layer comprising a second concentration of the dipole-containing material; and A second metal gate stack is disposed above and in contact with the second gate dielectric layer; A third transistor, comprising: The third active zone; A third gate dielectric layer, on the third active region, the third gate dielectric layer comprising a third concentration of the dipole-containing material; and A third metal gate stack is disposed above and in contact with the third gate dielectric layer; A fourth transistor, comprising: The fourth active zone; A fourth gate dielectric layer, wherein the fourth active region contains no dipole-containing material; and A fourth metal gate stack is disposed above and in contact with the fourth gate dielectric layer; The first metal gate stack, the second metal gate stack, the third metal gate stack, and the fourth metal gate stack are identical to each other in terms of structure and size; The dipole-containing material contains lanthanum, aluminum, or yttrium oxide; The first concentration is greater than the second concentration, and the second concentration is greater than the third concentration.

21. The semiconductor device of claim 20, wherein the first metal gate stack, the second metal gate stack, the third metal gate stack, and the fourth metal gate stack share the same components.

22. The semiconductor device of claim 20, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are n-type transistors; The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, the third transistor includes a third threshold voltage, and the fourth transistor includes a fourth threshold voltage. as well as The first critical voltage is less than the second critical voltage, the second critical voltage is less than the third critical voltage, and the third critical voltage is less than the fourth critical voltage.

23. The semiconductor device of claim 20, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are p-type transistors; The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, the third transistor includes a third threshold voltage, and the fourth transistor includes a fourth threshold voltage. as well as The first critical voltage is greater than the second critical voltage, the second critical voltage is greater than the third critical voltage, and the third critical voltage is greater than the fourth critical voltage.

24. A memory device comprising: A first pull-down transistor, a first pull-up transistor, a first channel gate transistor, and a read channel gate transistor, wherein the first pull-down transistor, the first pull-up transistor, the first channel gate transistor, and the read channel gate transistor share a first gate electrode; and A second-channel gate transistor, a second pull-up transistor, a second pull-down transistor, and a read-down transistor, wherein the second-channel gate transistor, the second pull-up transistor, the second pull-down transistor, and the read-down transistor share a second gate electrode; The first channel gate transistor and the second channel gate transistor each include a first gate dielectric layer, the first pull-down transistor and the second pull-down transistor each include a second gate dielectric layer, the read channel gate transistor includes a third gate dielectric layer, and the read pull-down transistor includes a fourth gate dielectric layer. The first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer contain hafnium oxide; The first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer further comprise lanthanum; The fourth gate dielectric layer does not actually contain lanthanum.

25. The memory device of claim 24, wherein: The first gate dielectric layer contains a first lanthanum concentration; The second gate dielectric layer contains a second lanthanum concentration; The third gate dielectric layer contains a third lanthanum concentration; and The first lanthanum concentration is greater than the second lanthanum concentration, and the second lanthanum concentration is greater than the third lanthanum concentration.

26. The memory device of claim 24, wherein: The first gate dielectric layer includes a first lanthanum-to-hafnium ratio; The second gate dielectric layer includes a second lanthanum-to-hafnium ratio; The third gate dielectric layer includes a third lanthanum-to-hafnium ratio; and The first lanthanum-to-hafnium ratio is greater than the second lanthanum-to-hafnium ratio, and the second lanthanum-to-hafnium ratio is greater than the third lanthanum-to-hafnium ratio.

27. The memory device of claim 26, wherein the first lanthanum-to-hafnium ratio is 0.6, the second lanthanum-to-hafnium ratio is 0.4, and the third lanthanum-to-hafnium ratio is 0.

2.

28. The memory device of claim 24, wherein the drain of the first channel gate transistor, the drain of the second pull-up transistor, and the drain of the second pull-down transistor are electrically connected together.

29. The memory device of claim 24, wherein the drain of the first pull-down transistor, the drain of the first pull-up transistor, and the drain of the second channel gate transistor are electrically connected together.

30. The memory device of claim 24, wherein the first pull-down transistor includes a first pair of fins, the first pull-up transistor includes a first fin, the first channel gate transistor includes a second pair of fins, the read channel gate transistor includes a third pair of fins, the second channel gate transistor includes a fourth pair of fins, the second pull-up transistor includes a second fin, the second pull-down transistor includes a fifth pair of fins, and the read pull-down transistor includes a sixth pair of fins.

31. The memory device of claim 24, wherein the source of the first pull-down transistor, the source of the second pull-down transistor, and the source of the read pull-down transistor are connected to electrical ground.

32. A memory device comprising: A first read pull-down transistor, a first pull-up transistor, a first channel gate transistor, and a first read channel gate transistor, wherein the first read pull-down transistor, the first pull-up transistor, the first channel gate transistor, and the first read channel gate transistor share a first metal gate electrode; and A second read channel gate transistor, a second channel gate transistor, a second pull-up transistor, a second pull-down transistor, and a second read pull-down transistor, wherein the second read channel gate transistor, the second channel gate transistor, the second pull-up transistor, the second pull-down transistor, and the second read pull-down transistor share a second metal gate electrode; The first channel gate transistor and the second channel gate transistor each include a first gate dielectric layer, the first pull-down transistor and the second pull-down transistor each include a second gate dielectric layer, the first read channel gate transistor and the second read channel gate transistor each include a third gate dielectric layer, and the first read pull-down transistor and the second read pull-down transistor each include a fourth gate dielectric layer. The first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer contain hafnium oxide; The first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer further comprise lanthanum; The fourth gate dielectric layer does not actually contain lanthanum.

33. The memory device of claim 32, wherein: The first gate dielectric layer contains a first lanthanum concentration; The second gate dielectric layer contains a second lanthanum concentration; The third gate dielectric layer contains a third lanthanum concentration; and The first lanthanum concentration is greater than the second lanthanum concentration, and the second lanthanum concentration is greater than the third lanthanum concentration.

34. The memory device of claim 32, wherein: The first gate dielectric layer includes a first lanthanum-to-hafnium ratio; The second gate dielectric layer includes a second lanthanum-to-hafnium ratio; The third gate dielectric layer includes a third lanthanum-to-hafnium ratio; and The first lanthanum-to-hafnium ratio is greater than the second lanthanum-to-hafnium ratio, and the second lanthanum-to-hafnium ratio is greater than the third lanthanum-to-hafnium ratio.

35. The memory device of claim 34, wherein the first lanthanum-to-hafnium ratio is 0.6, the second lanthanum-to-hafnium ratio is 0.4, and the third lanthanum-to-hafnium ratio is 0.

2.

36. The memory device of claim 32, wherein the drain of the first channel gate transistor, the drain of the second pull-up transistor, and the drain of the second pull-down transistor are electrically connected together.

37. The memory device of claim 32, wherein the drain of the first pull-down transistor, the drain of the first pull-up transistor, and the drain of the second channel gate transistor are electrically connected together.

Images