Semiconductor device

Abstract

A semiconductor device includes a first fin and a second fin extending from a substrate and an epitaxial source / drain region. The epitaxial source / drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are connected at a merged boundary. The epitaxial source / drain region further includes a first sub-region extending from a location level with a highest point of the epitaxial source / drain region to a location level with a highest point of the merged boundary, a second sub-region extending from the location level with the highest point of the merged boundary to a location level with a lowest point of the merged boundary, and a third sub-region extending from the location level with the lowest point of the merged boundary to a location level with a top surface of an STI region, wherein the third sub-region has a third height, and wherein a first height is less than the third height, and a second height is less than the third height.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a method for forming a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using optical lithography to pattern the various material layers to form circuit components and elements.

[0003] As the semiconductor industry progresses to nanometer technology process nodes in pursuit of higher device density, higher performance, lower power consumption, and lower costs, challenges from manufacturing and design issues have led to the development of 3D designs, such as FinFETs. FinFET devices typically include semiconductor fins in which channels and source / drain regions are formed. Taking advantage of the increased channel surface area, gates are formed above the fin structure and along its sides (e.g., by covering the fin structure) to produce faster, more reliable, and better-controlled semiconductor transistor devices. However, with the scaling down, new challenges have emerged in IC fabrication. Summary of the Invention

[0004] According to one embodiment, a semiconductor device includes: a first fin and a second fin extending from a substrate; a shallow trench isolation (STI) region disposed between the first and second fins on the substrate; and an epitaxial source / drain region, wherein the epitaxial source / drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and wherein the first portion and the second portion are connected at a merge boundary. The epitaxial source / drain region further includes: a first sub-region extending from a position level with the highest point of the epitaxial source / drain region to a position level with the highest point of the merge boundary, wherein the first sub-region has a first height, and wherein the top surface of the first sub-region includes a valley between the first fin and the second fin; a second sub-region extending from a position level with the highest point of the merge boundary to a position level with the lowest point of the merge boundary, wherein the second sub-region has a second height, and wherein the first height is less than the second height; and a third sub-region extending from a position level with the lowest point of the merge boundary to a position level with the top surface of the STI region, wherein the third sub-region has a third height, and wherein the first height is less than the third height, and the second height is less than the third height.

[0005] According to another embodiment, a semiconductor device includes: a high-density (HD) circuit region on a substrate including HD memory cells, and a high-current (HC) circuit region on a substrate including HC memory cells with an operating speed greater than that of HD memory cells, wherein the fin spacing in the HD memory cells is smaller than that in the HC memory cells, and the HD memory cell includes: a first fin extending from the substrate; a first epitaxial source / drain region on the first fin; a second fin extending from the substrate and adjacent to the first fin; a third fin extending from the substrate and adjacent to the first fin; a second epitaxial source / drain region on the second fin; and a third epitaxial source / drain region on the third fin, wherein the third epitaxial source / drain region is physically separated from the second epitaxial source / drain region and the first epitaxial source / drain region; and the high-current (HC) circuit region on the substrate includes HC memory cells with an operating speed greater than that of HD memory cells. The memory cell, the fin spacing in the HD memory cell is smaller than the fin spacing in the HC memory cell, the HC memory cell includes: a fourth fin and a fifth fin extending from the substrate; and a fourth epitaxial source / drain region, wherein the fourth epitaxial source / drain region includes a first portion grown on the fourth fin, wherein the fourth epitaxial source / drain region includes a second portion grown on the fifth fin, wherein the first portion and the second portion are connected at a merge boundary, and the fourth epitaxial source / drain region further includes: a first sub-region extending from a position flush with the highest point of the fourth epitaxial source / drain region to a position flush with the highest point of the merge boundary; a second sub-region extending from a position flush with the highest point of the merge boundary to a position flush with the lowest point of the merge boundary; and a third sub-region extending from a position flush with the lowest point of the merge boundary to a position flush with the lowest point of the fourth epitaxial source / drain region.

[0006] According to another embodiment, a method for forming a semiconductor device includes: forming a shallow trench isolation (STI) region adjacent to a first fin and a second fin disposed on a substrate; forming a first groove in the first fin; forming a second groove in the second fin; and epitaxially growing a first source / drain region in the first groove and epitaxially growing a second source / drain region in the second groove, wherein the first source / drain region and the second source / drain region each have a circular top profile, and wherein the first source / drain region and the second source / drain region merge at a merging boundary to form a merged source / drain region. The merged source / drain regions have a first height measured from a position level with the highest point of the merged source / drain regions to a position level with the highest point of the merged boundary; the merged source / drain regions have a second height measured from a position level with the highest point of the merged boundary to a position level with the lowest point of the merged boundary; and the merged source / drain regions have a third height measured from a position level with the lowest point of the merged boundary to a position level with the top surface of the STI region. The first height is less than the second height, the first height is less than the third height, and the second height is less than the third height. Attached Figure Description

[0007] The complete disclosure is based on the following detailed description and accompanying drawings. It should be noted that, in accordance with the general practice of the industry, the illustrations are not necessarily drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity.

[0008] Figure 1 A perspective view of a FinFET example according to some embodiments is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D ,as well as Figure 16E This is a cross-sectional view of an intermediate stage in FinFET manufacturing according to some embodiments.

[0010] The reference numerals in the attached figures are explained as follows:

[0011] 50: Substrate

[0012] 50P, 50N, 89: Area

[0013] 51: Divider

[0014] 52: Fins

[0015] 54: Insulation materials

[0016] 56: Shallow Trench Isolation (STI) Area

[0017] 58: Passage Area

[0018] 60: Dummy dielectric layer

[0019] 62: Dummy gate layer

[0020] 64: Masking layer

[0021] 68, 88: Interlayer Dielectric (ILD)

[0022] 72: Dummy Gate

[0023] 74: Mask

[0024] 80: Gate sealing spacer

[0025] 82: Source / Drain Region

[0026] 82A: First subregion

[0027] 82B: Second subregion

[0028] 82C: Third Subregion

[0029] 86: Gate spacer

[0030] 87: Contact Etching Stop Layer (CESL)

[0031] 90: Groove

[0032] 92: Gate dielectric layer

[0033] 94, 114: Gate electrode

[0034] 94A: Liner

[0035] 94B: Work Function Adjustment Layer

[0036] 94C: Filler material

[0037] 96: Gate mask

[0038] 104: Merge Boundary

[0039] 108: Interlayer Dielectric (ILD)

[0040] 110: Gate contact

[0041] 112: Source / Drain Contact

[0042] H1: First Height

[0043] H2: Second Altitude

[0044] H3: Third Height

[0045] H4: Fourth Height

[0046] W1: First width

[0047] W2: Second width

[0048] W3: Third Width Detailed Implementation

[0049] The following disclosure provides numerous different embodiments or examples to implement the various features of this application. The following disclosure describes specific examples of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the same reference numerals and / or designations may be repeated in the different examples disclosed below. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the different embodiments and / or structures discussed.

[0050] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0051] This disclosure relates to an epitaxial scheme for source / drain regions in semiconductor devices, such as n-type field-effect transistors (nFETs), which may be FinFET devices. Described herein, for example, are source / drain regions of transistors and methods for forming such components. This document provides techniques and apparatus for forming source / drain regions in semiconductor devices having a rounded top profile. The techniques can reduce nodule defects by selecting a carrier gas and optimizing gas ratios. In embodiments of FinFETs used in memory arrays including high-current (HC) static random-access memory (SRAM) regions, the rounded top shape of the epitaxial source / drain regions avoids non-merging of the fin-extra-epitaxy regions (e.g., silicon phosphide (SiP)) of adjacent source / drain regions. In embodiments of FinFETs used in memory arrays including high-density (HD) SRAM regions, the rounded top shape of the epitaxial source / drain regions improves fin coverage of the HD SRAM structure and prevents merging or short circuits between adjacent HD SRAM source / drain regions by creating a narrower epitaxial source / drain shape. The rounded top profile of the epitaxial regions allows for a larger positioning area for the contacts of both the HC and HD SRAM structures, which further reduces contact resistance. The rounded top profile reduces losses in the highly doped SiP source / drain regions during downstream middle-end (MEOL) and back-end (BEOL) processes. Overall yield can be increased by approximately 20% due to higher epitaxial growth rates and shorter transition times. The higher in-fin merging height of the HC SRAM structure and the narrower epitaxial source / drain region shape of the HD SRAM structure improve device performance by reducing the capacitive effect of the source / drain regions. The enlarged highly doped source / drain volume can lead to a reduction in source / drain contact plug resistance.

[0052] This document describes and illustrates techniques for forming source / drain regions with reference to FinFETs; however, epitaxial solutions within the scope of this disclosure can also be implemented in other semiconductor devices. Furthermore, intermediate stages for forming a FinFET are described herein. Some of the states described herein are described in the context of FinFETs formed using a gate-displacement process. In other examples, a gate-first process, as will be readily understood by those skilled in the art, is used. Some variations of the example methods and structures are described herein. Other modifications that can be made will be readily understood by those skilled in the art and are contemplated within the scope of other embodiments. While method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more of the steps described herein.

[0053] Figure 1 A perspective view of an example FinFET according to some embodiments is illustrated. The FinFET includes fins 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and fins 52 protrude therefrom between adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated separately from the substrate 50, when the term "substrate" is used herein, it may refer only to a semiconductor substrate or a semiconductor substrate containing the isolation regions. Additionally, although fins 52 are illustrated as a single continuous material like the substrate 50, fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fins 52 refer to the portion extending between adjacent isolation regions 56.

[0054] The gate dielectric layer 92 runs along the sidewall of the fin 52 and is above the top surface of the fin 52, and the gate electrode 94 is above the gate dielectric layer 92. The source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Further reference cross-sections for use in subsequent figures are illustrated. Cross-section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the current direction between the source / drain regions 82 of the FinFET. Cross-section BB is perpendicular to cross-section AA and is along the longitudinal axis of the fin 52 and in, for example, the current flow direction between the source / drain regions 82 of the FinFET. Cross-section CC is parallel to cross-section AA and extends through the source / drain regions of the FinFET. For clarity, the following figures refer to these reference cross-sections.

[0055] Some of the embodiments discussed herein are presented in the context of FinFETs formed using a post-gate fabrication process. In other embodiments, a gate-first fabrication process may be used. Furthermore, some embodiments are envisioned for planar devices, such as planar FETs.

[0056] Figures 2 to 16E This is a cross-sectional view of an intermediate stage in FinFET manufacturing according to some embodiments. Figures 2 to 7 Draw Figure 1 The reference cross section AA shown is the portion excluding the multiple fins / FinFETs. Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A ,as well as Figure 16A Along Figure 1 The reference section AA is shown in the figure, while Figure 8B , Figure 9B , Figure 10B , Figure 10E , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 14E , Figure 15B , Figure 16B ,as well as Figure 16E Along Figure 1 The similar cross-section BB shown illustrates the portion excluding the multiple fins / FinFETs. Figure 10C , Figure 10D , Figure 11C , Figure 11D , Figure 12C , Figure 12D , Figure 13C , Figure 13D , Figure 14C , Figure 14D , Figure 15C , Figure 15D , Figure 16C ,as well as Figure 16D Along Figure 1 The reference cross section CC shown illustrates the portion excluding the multiple fins / FinFETs.

[0057] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate (typically a silicon or glass substrate). Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide, or combinations thereof.

[0058] The substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type FinFET. Region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type FinFET. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0059] exist Figure 3 In this process, fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 are formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0060] The fins can be patterned using any suitable method. For example, the fins can be patterned using one or more optical lithography processes, including dual patterning or multi-patterning processes. Generally, dual patterning or multi-patterning processes combine optical lithography and self-alignment processes, allowing the created patterns to have, for example, smaller pitches than that achievable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) may remain on the fin 52.

[0061] exist Figure 4In this process, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide, such as silicon oxide; a nitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flow CVD (FCVD) (e.g., CVD-type material deposition in a remote plasma system followed by postcuring to convert it into other materials such as oxides), or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material 54 is formed such that an excess of the insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner may be formed first along the surfaces of the substrate 50 and the fins 52. Subsequently, a filler material, such as that discussed above, may be formed over the liner.

[0062] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof, may be used. The planarization process exposes the fin 52 such that the fin 52 is flush with the top surface of the insulating material 54 after the planarization process is completed. In embodiments where the mask remains on the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surface of the mask or the top surface of the fin 52 is flush with the top surface of the insulating material 54, respectively.

[0063] exist Figure 6 In this process, grooves are made in the insulating material 54 to form shallow trench isolation (STI) regions 56. Grooving the insulating material 54 causes the upper portions of the fins 52 in regions 50N and 50P to protrude between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., pits), or a combination thereof, as shown. The top surface of the STI region 56 can be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes, such as etching processes with selectivity for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than etching the material of the fins 52), can be used to groove the STI region 56. For example, an oxide using, for example, dilute hydrofluoric acid (dHF) can be used for removal.

[0064] Reference Figures 2 to 6The described process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed via an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be slotted so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Furthermore, in some embodiments, the fin 52 may use a heteroepitaxial structure. For example, Figure 5 The fins 52 in the substrate 50 can be grooved, and a material different from the fins 52 can be epitaxially grown over the grooved fins 52. In this embodiment, the fins 52 include grooves in the material and epitaxial growth material disposed over the grooved material. In a further embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and the trenches can be etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be grooved so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be in-situ doped during growth, which eliminates the need for prior and subsequent implantation, although in-situ and implantation doping can be used together.

[0065] Furthermore, it may be advantageous to epitaxially grow a material different from that in region 50P (e.g., PMOS region) in region 50N (e.g., NMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0066] In addition Figure 6 In this process, suitable wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, either a P-well or an N-well may be formed in both region 50N and region 50P.

[0067] In embodiments with different well types, photoresist or other masks (not shown) can be used to implement different implantation steps for regions 50N and 50P. For example, photoresist can be formed over fins 52 and STI regions 56 in region 50N. The photoresist is patterned to expose regions 50P of the substrate 50, such as PMOS regions. The photoresist can be formed using spin coating techniques and can be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as NMOS regions. n-type impurities can be implanted into this region at a concentration equal to or less than 10. 18 cm -3 For example, about 10 16 cm -3 and about 10 18 cm -3 The photoresist contains phosphorus, arsenic, antimony, etc. After application, the photoresist is removed, as if through an acceptable ashing process.

[0068] After the implantation in region 50P, photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed using spin coating technology and can be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, p-type impurity implantation is performed in region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted in region 50P, such as a PMOS region. P-type impurities can be implanted in this region at a concentration equal to or less than 10. 18 cm -3 For example, about 10 16 cm -3 and about 10 18 cm -3 The photoresist contains boron, boron fluoride, indium, etc. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0069] After implantation in regions 50N and 50P, annealing can be performed to repair implantation damage and reactivate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which eliminates the need for implantation, although in-situ and implantation doping can be used together.

[0070] exist Figure 7In this process, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art for depositing the selected material. The dummy gate layer 62 may be made of other materials that have a high etch selectivity compared to etching the isolation region. The mask layer 64 may comprise, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50N and 50P. Note that the dummy dielectric layer 60 is depicted only covering the fin 52 for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the STI region 56, extending between the dummy gate layer 62 and the STI region 56.

[0071] Figures 8A to 16B Various additional steps in the manufacturing embodiment apparatus are illustrated. Figures 8A to 16B The component is shown in either region 50N or region 50P. For example, Figures 8A to 16B The structures shown in the diagram can be applied to both Region 50N and Region 50P. Differences in the structures of Region 50N and Region 50P (if any) are described in the text accompanying each diagram.

[0072] exist Figure 8A as well as Figure 8B In this process, acceptable optical lithography and etching techniques can be used to pattern the mask layer 64 (see [link]). Figure 7 A mask 74 is formed. The pattern of the mask 74 may then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 may also be transferred to the dummy dielectric layer 60 using an acceptable etching technique to form the dummy gate 72. The dummy gate 72 covers the channel region 58 of the individual fin 52. The pattern of the mask 74 may be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 may also have a length direction substantially perpendicular to the length direction of the individual epitaxial fin 52.

[0073] Continue to refer to Figure 8A as well as Figure 8BThe gate sealing spacer 80 may be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. The gate sealing spacer 80 may be formed by anisotropic etching following thermal oxidation or deposition. The gate sealing spacer 80 may be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0074] After forming the gate sealing spacer 80, the placement of lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In embodiments with different device types, the process is similar to that described above. Figure 6 The implantation discussed earlier involves forming a mask (such as a photoresist) over region 50N while exposing region 50P, and implanting an appropriate type of impurity (e.g., p-type) into the exposed fin 52 in region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity previously discussed, and the p-type impurity can be any p-type impurity previously discussed. The lightly doped source / drain region can have approximately 10... 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair damaged fabric and revitalize the fabric.

[0075] exist Figure 9A as well as Figure 9B In this configuration, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. In some embodiments, the gate spacer 86 may have dangling bonds on its outer surface.

[0076] Note that the above disclosure broadly describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the gate seal spacer 80 is not etched before forming the gate spacer 86, resulting in an "L-shaped" gate seal spacer), spacers can be formed and removed, and / or other similar processes can be used. Additionally, different structures and steps can be used to form n-type and p-type devices. For example, the LDD regions of an n-type device can be formed before forming the gate seal spacer 80, while the LDD regions of a p-type device can be formed after forming the gate seal spacer 80.

[0077] exist Figure 10A as well as Figure 10B Epitaxial source / drain regions 82 are formed in fin 52 to apply stress in individual channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in fin 52 such that each dummy gate 72 is disposed between adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into and penetrate fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the gate of the subsequently formed final FinFET.

[0078] The epitaxial source / drain region 82 in region 50N (e.g., an NMOS region) can be formed by shielding region 50P (e.g., a PMOS region) and etching the source / drain region of fin 52 in region 50N to form a groove in fin 52. The epitaxial source / drain region 82 in region 50N is then epitaxially grown in the groove. The epitaxial source / drain region 82 can contain any acceptable material, such as a material suitable for n-type FinFETs. The epitaxial source / drain region 82 in region 50N can have a surface protruding from an individual surface of fin 52 and can have facets.

[0079] Epitaxial source / drain regions 82 can be formed using an epitaxial process such as a cyclic deposition-etch (CDE) process. A CDE process comprises several repeated cycles, typically ranging from 2 to 10 cycles. Each cycle of a CDE process includes an etching process following a deposition process. In some embodiments, the deposition process of the CDE process includes a chemical vapor deposition (CVD) process, such as reduced pressure chemical vapor deposition (RPCVD), low pressure CVD (LPCVD), or combinations thereof. In some embodiments, the process is RPCVD.

[0080] For example, if fin 52 is silicon, the epitaxial source / drain region 82 in region 50N can contain a material for which tensile stress is applied in channel region 58, such as silicon phosphide (SiP), silicon carbide phosphide (SiPC), etc. A conductive dopant (e.g., an n-type dopant, such as phosphorus as described in the embodiments herein) is in situ doped into the epitaxial source / drain region 82. RPCVD can use a silicon source precursor gas. The silicon source precursor gas can be a silicon-rich precursor gas, such as containing silane (SiH4), dichlorosilane (SiH2Cl2, DCS), trichlorosilane (SiHCl3), disilane (Si2H6), or combinations thereof. The flow rate of the silicon source precursor gas in RPCVD can be in the range of approximately 40 sccm to approximately 1000 sccm.

[0081] The RPCVD process may also include a phosphorus source precursor gas. The phosphorus source precursor gas may contain phosphine (PH3), phosphorus oxychloride, other phosphorus-containing precursors, and / or any combination thereof. In some embodiments, the ratio of silicon source precursor to phosphorus source precursor gas is in the range of about 50 to about 300. A carrier gas, such as hydrogen (H2), may be mixed with the precursors of any of the embodiments described above. In some embodiments, the RPCVD process uses a silicon-rich precursor gas, such as dichlorosilane (DCS), and a phosphorus source precursor gas, such as phosphine, mixed with a hydrogen carrier gas. In some embodiments, the ratio of silicon source precursor to carrier gas is in the range of about 2:1 to about 10:1.

[0082] In some embodiments, during the epitaxial growth of the epitaxial source / drain region 82, using dichlorosilane (DCS) as a silicon source precursor and hydrogen as a carrier gas can produce a circular top profile of the epitaxial source / drain region 82. DCS allows crystalline silicon to grow uniformly on most or all lattice planes, while hydrogen can suppress the growth of crystalline silicon in the 100 plane (horizontal growth) due to hydrogen adhering to dangling bonds in the 100 plane, but does not suppress growth in the 110 and 111 lattice planes. The combination of using DCS as a silicon source precursor and hydrogen as a carrier gas allows for controlled growth of the circular top profile. To produce the circular top profile, hydrogen amounts ranging from about 2 L to about 10 L can be used.

[0083] In some embodiments, using hydrogen as a carrier gas can prevent or reduce the formation of junction defects, such as those on gate spacers 86 which may contain nitrides such as SiN. Junction defects can be generally spherical growths formed during epitaxial growth processes due to the disproportionate adhesion of precursor gases to dangling bonds, such as those on gate spacers 86. Junction defects can degrade device performance by altering the shape of the epitaxial source / drain regions 82. The hydrogen carrier gas can passivate the surface of the gate spacer 86 by terminating it, which can prevent the formation of junction defects during the growth of the epitaxial source / drain regions 82.

[0084] The pressure of RPCVD can be equal to or less than about 300 Torr, such as in the range of about 50 Torr to about 300 Torr. In some examples, an RPCVD pressure less than 50 Torr may provide insufficient dopant concentration. In some examples, an RPCVD pressure greater than 300 Torr may result in reduced selectivity. The pressure can vary depending on the specific process used. The temperature of RPCVD can range from about 650°C to about 750°C. In some embodiments, parameters can vary depending on the process.

[0085] The epitaxial source / drain region 82 can have various concentrations of conductive dopants. When phosphorus is planted as the conductive dopant, for example from epitaxial growth using phosphorus, the phosphorus concentration in the epitaxial source / drain region 82 can be approximately 1 × 10⁻⁶. 21 atoms / cm -3 Approximately 4×10 21 atoms / cm -3 Within the range.

[0086] In some embodiments, the deposition process forms an epitaxial layer, such as SiP, in the grooves formed in the fin 52 and an amorphous material on the amorphous surface. In some embodiments, after the deposition process, a post-deposition purging operation is used to remove the deposited gas from the process chamber. An inert gas, such as He, Ar, or Ne, can be used in this operation to purge the deposited gas from the process chamber. Once the deposited gas is removed from the chamber, the etching process continues.

[0087] The etching (or partial etching) process of the CDE process removes amorphous material and may also remove part of the deposited epitaxial layer. The remaining epitaxial layer forms the epitaxial source / drain region 82. The etching process may be an in-situ etching process performed in the chamber of the deposition process. In some embodiments, an etching gas is introduced into the chamber to etch the amorphous material. Etching gases such as chlorine (Cl2), hydrochloric acid (HCl), hydrofluoric acid (HF), and hydrobromic acid (HBr) may be used. The pressure during the etching process may be equal to or less than about 300 Torr, such as in the range of about 5 Torr to about 300 Torr. The temperature during the etching process may be in the range of about 625°C to about 750°C. In some examples, a purging operation is subsequently performed after the etching process to remove the etching gas from the chamber.

[0088] Etching processes can remove amorphous material at a greater rate than the epitaxial material. This can be accomplished by selective etching (e.g., HCl etching) of the amorphous material within a temperature range of approximately 625°C to approximately 750°C and a pressure range of approximately 5 Torr to approximately 300 Torr. Therefore, after a deposition-etch cycle, the epitaxial material remains on the surface of, for example, the epitaxial source / drain region 82. The deposition-etch cycle can be repeated several times until the desired thickness of the epitaxial source / drain region 82 is achieved. By removing the appropriate portions of the amorphous material, the desired shape of the epitaxial source / drain region 82 can be produced. Therefore, this repetitive deposition-etch process is called a cyclic deposition-etch (CDE) process.

[0089] The epitaxial source / drain region 82 in region 50P (e.g., a PMOS region) can be formed by shielding region 50N (e.g., an NMOS region) and etching the source / drain region of fin 52 in region 50P to form a groove in fin 52. Then, the epitaxial source / drain region 82 in region 50P is epitaxially grown in the groove. The epitaxial source / drain region 82 can contain any acceptable material, such as a material suitable for p-type FinFETs. For example, if fin 52 is silicon, the epitaxial source / drain region 82 in region 50P can contain a material that applies compressive stress in channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 82 in region 50P can also have a surface protruding from an individual surface of fin 52 and can have facets.

[0090] As a result of the epitaxial source / drain regions 82 formed in regions 50N and 50P using an epitaxial process, the upper surfaces of the epitaxial source / drain regions 82 have facets that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these facets result in adjacent source / drain regions 82 of the same FinFET being as follows: Figure 10C As shown, they are merged. In other embodiments, adjacent source / drain regions 82 remain as shown after the epitaxial process is completed. Figure 10D Keep them separated as shown. Figure 10C as well as Figure 10D In the illustrated embodiment, a gate spacer 86 is formed to cover a portion of the sidewall of the fin 52, which extends over the STI region 56 to block epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 86 may be adjusted to remove spacer material so that the epitaxial growth region can extend to the surface of the STI region 56.

[0091] exist Figure 10C In the process, the upper surfaces of adjacent source / drain regions 82 have been merged to form a merged epitaxial source / drain region 82, which has a first portion disposed in the first fin 52 and a second portion disposed in the second fin 52. Figure 10C The top surfaces of the first and second fins 52 are shown in outline. The first and second portions of the merged epitaxial source / drain region 82 are connected at a merge boundary 104. The merge boundary 104 extends from the lowest point of the valley between the fins 52 in the top surface of the merged epitaxial source / drain region 82 to the apex of the bottom surface of the merged epitaxial source / drain region 82 located between the fins 52.

[0092] The merged epitaxial source / drain region 82 may have a first width W1 ranging from about 40 nm to about 70 nm. A first width W1 ranging from about 40 nm to about 70 nm is advantageous for improving process yield and device characteristics. A first width W1 less than about 40 nm may result in lower yield and device loss. A first width W1 greater than about 70 nm may result in lower yield and device loss.

[0093] The merged epitaxial source / drain region 82 includes a first sub-region 82A extending from the highest point of the merged epitaxial source / drain region 82 to the highest point of the merge boundary 104. The top surface of the first sub-region 82A includes two circular top profiles. In some embodiments, the circular top profiles of the merged epitaxial source / drain region 82 can be produced by using dichlorosilane (DCS) as a silicon source precursor and hydrogen as a carrier gas during the epitaxial growth of the epitaxial source / drain region 82. DCS allows crystalline silicon to grow uniformly in most or all lattice planes, while hydrogen can suppress the growth of crystalline silicon in the 100 plane (horizontal growth) because hydrogen adheres to dangling bonds in the 100 plane, without suppressing growth in the 110 and 111 lattice planes. The combination of using DCS as a silicon source precursor and hydrogen as a carrier gas allows for controlled growth of the circular top profiles. To produce the circular top profiles, hydrogen amounts in the range of about 2L to about 10L can be used.

[0094] The circular top profile is located above the two opposite sides of the merge boundary 104. The first sub-region 82A may have a first height H1 in the range of less than about 10 nm. In some embodiments, the top surface of the first sub-region 82A has a valley between the fins 52. Since the merge boundary 104 is located above the widest diameter of the merged epitaxial source / drain regions 82, the valley between the circular top profiles of the merged epitaxial source / drain regions 82 may be relatively shallow compared to the valley formed at the merge boundary located at a lower position. The valley between the circular top profiles of the merged epitaxial source / drain regions 82 can provide a more stable positioning area for the source / drain contacts. Because the valley between the circular top profiles of the merged epitaxial source / drain regions 82 is relatively shallow, the possibility of the formation of source / drain contacts, such as metal plugs, breaking through the merged facets of the epitaxial source / drain regions 82 between the fins is lower.

[0095] A valley can have a height equal to a first height H1 from its lowest point to its highest point. A first height H1 within the range of approximately 10 nm is advantageous for improving process yield and device characteristics. A first height H1 greater than approximately 10 nm may result in lower yield and device losses.

[0096] The merged epitaxial source / drain region 82 further includes a second sub-region 82B extending from the highest point of the merge boundary 104 to the lowest point of the merge boundary 104. The second sub-region 82B may have a second height H2 in the range of about 18 nm to about 28 nm. A second height H2 in the range of about 18 nm to about 28 nm is advantageous for improving process yield and device characteristics. A second height H2 less than about 18 nm may result in lower yield and device losses. A second height H2 greater than about 28 nm may result in lower yield and device losses. The ratio of the first height H1 to the second height H2 may be in the range of about 0:28 to about 10:18. An H1:H2 ratio in the range of about 0:28 to about 10:18 is advantageous for improving process yield and device characteristics. An H1:H2 ratio greater than about 5:9 may result in lower yield and device losses.

[0097] The merged epitaxial source / drain region 82 further includes a third sub-region 82C extending from the lowest point of the merged boundary 104 to the top surface of the STI region 56. The third sub-region 82C may have a third height H3 in the range of approximately 25 nm to approximately 40 nm. A third height H3 in the range of approximately 25 nm to approximately 40 nm is advantageous for improving process yield and device characteristics. A third height H3 less than approximately 25 nm may result in device losses. The ratio of the first height H1 to the third height H3 may be in the range of approximately 0:25 to approximately 10:40. An H1:H3 ratio in the range of approximately 0:28 to approximately 10:40 is advantageous for improving process yield and device characteristics.

[0098] The embodiment of the merged epitaxial source / drain region 82 offers advantages. The merged epitaxial source / drain region 82 can be used in high-current (HC) SRAM transistors. HC SRAM transistors including multiple fin-type FinFETs with merged epitaxial source / drain regions can be used in high-speed circuits to achieve good speed performance. The rounded top profile of the epitaxial source / drain region 82 can prevent merging failure by increasing the horizontal width of adjacent epitaxial source / drain regions 82 near their top surfaces. The rounded top profile of the merged epitaxial source / drain region 82 provides better positioning for the source / drain contacts, as described below. Figure 16C The higher fin merging height of the merged epitaxial source / drain regions 82 can improve device performance by reducing the capacitance effect of the source / drain regions.

[0099] exist Figure 10DIn this configuration, the upper facets of adjacent source / drain regions 82 are not merged, resulting in adjacent unmerged epitaxial source / drain regions 82 disposed on adjacent fins 52. The top surface of each unmerged epitaxial source / drain region 82 includes its own circular top profile. The circular top profile of the unmerged epitaxial source / drain region 82 can be formed using hydrogen as a carrier gas. The unmerged epitaxial source / drain regions 82 may have a second width W2 in the range of approximately 25 nm to approximately 40 nm between the opposing sidewalls of the epitaxial source / drain regions 82, measured at their maximum separation distance. A second width W2 in the range of approximately 25 nm to approximately 40 nm is advantageous for improving process yield and device characteristics. A second width W2 less than approximately 25 nm may result in lower yield and device loss. A second width W2 greater than approximately 40 nm may result in lower yield and device loss.

[0100] According to such Figure 10E In some embodiments shown, the epitaxial source / drain region 82 may be formed with a circular bottom profile, rather than as shown. Figure 10B The bottom profile of the facet is shown. The shape of the bottom profile of the epitaxial source / drain region 82 can be adjusted, for example, by controlling the shape of the groove etched into the top surface of the fin 52.

[0101] The unmerged epitaxial source / drain region 82 may have a third width W3 measured 10 nm below the highest point of the unmerged epitaxial source / drain region 82. The third width W3 may be in the range of approximately 15 nm to approximately 35 nm. A third width W3 in the range of approximately 15 nm to approximately 35 nm is advantageous for improving process yield and device performance. A third width W3 less than approximately 15 nm may result in lower yield and device loss. A third width W3 greater than approximately 35 nm may result in lower yield and device loss.

[0102] The ratio of the second width W2 to the third width W3 can range from approximately 25:15 to approximately 40:35. A W2:W3 ratio within the range of approximately 25:15 to approximately 40:35 is beneficial for improving process yield and device characteristics. A W2:W3 ratio below 5:3 may result in lower yield and device losses.

[0103] The unmerged epitaxial source / drain region 82 may have a fourth height H4, measured from the bottom point of the unmerged epitaxial source / drain region 82 to the top point of the unmerged epitaxial source / drain region 82, in the range of approximately 40 nm to approximately 60 nm. A fourth height H4 in the range of approximately 40 nm to approximately 60 nm is advantageous for improving process yield and device characteristics. A fourth height H4 smaller than approximately 40 nm may result in lower yield and device losses. A fourth height H4 greater than approximately 60 nm may result in lower yield and device losses.

[0104] Embodiments with unmerged epitaxial source / drain regions 82 offer advantages. Unmerged epitaxial source / drain regions 82 can be used in high-density (HD) SRAM transistors. HD SRAM transistors including single-fin FinFETs with unmerged epitaxial source / drain regions between adjacent FinFETs can reduce power consumption and area. This enables minimal cell standby leakage current and reduces cell size, which is advantageous for miniaturization. HD SRAM cells can have a smaller pitch than HC SRAM cells. In embodiments where unmerged epitaxial source / drain regions 82 are used in high-density (HD) SRAM devices, the rounded top shape of the epitaxial source / drain regions 82 improves fin coverage of the HD SRAM structure and avoids merging or short-circuiting between adjacent HD SRAM source / drain regions by creating a narrower epitaxial source / drain shape. The narrow epitaxial source / drain region shape of the HD SRAM structure can improve device performance by reducing the capacitive effect of the source / drain regions.

[0105] like Figure 10C and Figure 10D As shown, in some embodiments, the epitaxial source / drain region 82 may extend below a surface flush with the top surface of the STI region 56. In other embodiments, the epitaxial source / drain region 82 may be flush with the top surface of the STI region 56. In yet another embodiment, the bottom surface of the epitaxial source / drain region 82 may be above a surface flush with the top surface of the STI region 56.

[0106] In some embodiments, the circular top profile of the epitaxial source / drain region 82 can reduce the source / drain region losses of highly doped SiP in downstream MEOL and BEOL processes. Overall yield can be increased by approximately 20% due to the higher epitaxial growth rate and shorter transition time. The enlarged highly doped source / drain volume can lead to a reduction in source / drain contact plug resistance.

[0107] exist Figure 11A , Figure 11B , Figure 11C as well as Figure 11D In Figure 10A , Figure 10B , Figure 10C as well as Figure 10DA first interlayer dielectric (ILD) 88 is deposited over the structure shown. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In other embodiments, a contact etch stop layer (CESL) 87 is provided between the first ILD 88 and the epitaxial source / drain region 82, the mask 74, and the gate spacer 86. The CESL 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etch rate than the material of the overlying first ILD 88.

[0108] exist Figure 12A , Figure 12B , Figure 12C as well as Figure 12D In this process, a planarization process, such as CMP, can be performed to align the top surface of the first ILD 88 with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove portions of the mask 74 on the dummy gate 72, as well as the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the top surface of the first ILD 88 are flush. Accordingly, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process aligns the top surface of the first ILD 88 with the top surface of the mask 74.

[0109] exist Figure 13A , Figure 13B , Figure 13C as well as Figure 13DIn one or more etching steps, a dummy gate 72 and a mask 74 (if present) are removed to form a recess 90. A portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed while the dummy dielectric layer 60 is retained, exposing the dummy dielectric layer 60 through the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region), while the dummy dielectric layer 60 is retained in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of an individual fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when etching the dummy gate 72. After removing the dummy gate 72, the dummy dielectric layer 60 can then optionally be removed.

[0110] exist Figure 14A , Figure 14B , Figure 14C as well as Figure 14D In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 14E It is a drawing Figure 14B Detailed diagram of region 89. A gate dielectric layer 92 is conformally deposited in the recess 90, such as on the top surface and sidewalls of fin 52, and on the sidewalls of gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, the gate dielectric layer 92 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 92 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a partially dummy dielectric layer 60 is retained in the recess 90, the gate dielectric layer 92 comprises the material of the dummy dielectric layer 60 (e.g., SiO2).

[0111] Gate electrodes 94 are deposited above the gate dielectric layer 92 and fill the remaining portion of the trench 90. Gate electrodes 94 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in… Figure 14BThe diagram shows a single-layer gate electrode 94, which can be used as follows: Figure 14E The diagram includes any number of substrates 94A, any number of work function tuning layers 94B, and filler material 94C. After filling the recess 90, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 92 and gate electrode 94 above the top surface of the ILD 88. The remaining material of the gate electrode 94 and gate dielectric layer 92 thus forms the replacement gate of the final FinFET. The gate electrode 94 and gate dielectric layer 92 can be collectively referred to as the "gate stack". The gate and gate stack can extend along the sidewalls of the channel region 58 of the fin 52.

[0112] The formation of the gate dielectric layer 92 in regions 50N and 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed from the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed from the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed using different processes, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed using different processes, such that the gate electrode 94 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0113] exist Figure 15A , Figure 15B , Figure 15C as well as Figure 15D In this process, a second ILD 108 is deposited above the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flow CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD and PECVD. According to some embodiments, before forming the second ILD 108, a trench may be formed in the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94), such that the trench is formed directly above the gate stack and between opposite portions of the gate spacer 86, as shown below. Figure 15A as well as Figure 15B As shown. A gate mask 96, comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., is filled into the groove, followed by a planarization process to remove excess dielectric material extending over the first ILD 88. A gate contact 110 is then formed through the gate mask 96. Figure 16A as well as Figure 16B( ) to contact the top surface of the gate electrode 114 of the groove.

[0114] exist Figure 16A , Figure 16B , Figure 16C as well as Figure 16D In some embodiments, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. An opening in the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening in the gate contact 110 is formed through the second ILD 108 and the gate mask 96. The openings can be formed using acceptable optical lithography and etching techniques. A liner such as a diffusion barrier layer or an adhesive layer, and a conductive material can be formed within the openings. The liner may contain titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 within the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 94. The source / drain contact 112 and the gate contact 110 can be formed in different processes or in the same process. Although illustrated as being formed in the same cross-section, it is apparent that each of the source / drain contact 112 and the gate contact 110 can be formed in a different cross-section to avoid short circuits. Figure 16C and Figure 16D As shown, the rounded top profile of the epitaxial source / drain region 82 provides a better, relatively flat positioning area for the source / drain contacts 112 of the high-current (HC) and high-density (HD) SRAM structure. This further reduces the resistance of the source / drain contacts 112. Figure 16E The drawing shows Figure 10E The following is an embodiment of the epitaxial source / drain region 82 with a circular bottom profile.

[0115] In some embodiments, the shape of the epitaxial source / drain region 82 can lead to improved characteristics. Junction defects can be reduced by selecting optimized gas ratios and carrier gases. The rounded top shape of the epitaxial source / drain region avoids non-merging of the epitaxial regions, such as silicon phosphide (SiP), between adjacent source / drain regions used in HCSRAM devices. The rounded top shape of the epitaxial source / drain region improves fin coverage of HD SRAM and avoids merging or short circuits between adjacent HD SRAM source / drain regions by creating a narrower epitaxial source / drain shape. The rounded top profile of the epitaxial region provides a larger positioning area for the contacts in HC and HD SRAM structures, which can further reduce contact resistance. The enlarged highly doped source / drain volume can lead to a reduction in source / drain contact plug resistance. The rounded top profile can reduce losses in highly doped SiP source / drain regions in downstream MEOL and BEOL processes. The higher in-fin merging height and narrower epitaxial source / drain region shape of the HC SRAM structure can improve device performance by reducing capacitance effects.

[0116] According to one embodiment, a semiconductor device includes: a first fin and a second fin extending from a substrate; a shallow trench isolation (STI) region disposed between the first and second fins on the substrate; and an epitaxial source / drain region, wherein the epitaxial source / drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and wherein the first portion and the second portion are connected at a merge boundary. The epitaxial source / drain region further includes: a first sub-region extending from a position level with the highest point of the epitaxial source / drain region to a position level with the highest point of the merge boundary, wherein the first sub-region has a first height, and wherein the top surface of the first sub-region includes a valley between the first fin and the second fin; a second sub-region extending from a position level with the highest point of the merge boundary to a position level with the lowest point of the merge boundary, wherein the second sub-region has a second height, and wherein the first height is less than the second height; and a third sub-region extending from a position level with the lowest point of the merge boundary to a position level with the top surface of the STI region, wherein the third sub-region has a third height, and wherein the first height is less than the third height, and the second height is less than the third height. In one embodiment, the epitaxial source / drain region comprises SiP. In one embodiment, the phosphorus concentration in the epitaxial source / drain region is 1 × 10⁻⁶. 21 atoms / cm 3 Up to 4×10 21 atoms / cm 3Within a certain range. In one embodiment, the epitaxial source / drain region extends below the top surface of the STI region. In one embodiment, the width of the epitaxial source / drain region is in the range of 40 nm to 70 nm. In one embodiment, the first height is less than 10 nm. In one embodiment, the device is part of a memory array. In one embodiment, the ratio of the first height to the second height is less than 5:9. In one embodiment, the ratio of the first height to the third height is less than 1:4.

[0117] According to another embodiment, a semiconductor device includes: a high-density (HD) circuit region on a substrate including HD memory cells, and a high-current (HC) circuit region on a substrate including HC memory cells with an operating speed greater than that of HD memory cells, wherein the fin spacing in the HD memory cells is smaller than that in the HC memory cells, and the HD memory cell includes: a first fin extending from the substrate; a first epitaxial source / drain region on the first fin; a second fin extending from the substrate and adjacent to the first fin; a third fin extending from the substrate and adjacent to the first fin; a second epitaxial source / drain region on the second fin; and a third epitaxial source / drain region on the third fin, wherein the third epitaxial source / drain region is physically separated from the second epitaxial source / drain region and the first epitaxial source / drain region; and the high-current (HC) circuit region on the substrate includes HC memory cells with an operating speed greater than that of HD memory cells. The memory cell, the fin spacing in the HD memory cell is smaller than the fin spacing in the HC memory cell, the HC memory cell includes: a fourth fin and a fifth fin extending from the substrate; and a fourth epitaxial source / drain region, wherein the fourth epitaxial source / drain region includes a first portion grown on the fourth fin, wherein the fourth epitaxial source / drain region includes a second portion grown on the fifth fin, wherein the first portion and the second portion are connected at a merge boundary, and the fourth epitaxial source / drain region further includes: a first sub-region extending from a position flush with the highest point of the fourth epitaxial source / drain region to a position flush with the highest point of the merge boundary; a second sub-region extending from a position flush with the highest point of the merge boundary to a position flush with the lowest point of the merge boundary; and a third sub-region extending from a position flush with the lowest point of the merge boundary to a position flush with the lowest point of the fourth epitaxial source / drain region. In one embodiment, the first epitaxial source / drain region has a first height measured from a position flush with the bottom point of the first epitaxial source / drain region to a position flush with the highest point of the first epitaxial source / drain region, wherein the first epitaxial source / drain region has a first width measured between points where the opposite sidewalls of the first epitaxial source / drain region are maximally separated, and wherein the ratio of the first width to the first height is in the range of 5:12 to 1:1. In one embodiment, the first width of the first epitaxial source / drain region is in the range of 25 nm to 40 nm. In one embodiment, the first height of the first epitaxial source / drain region is in the range of 40 nm to 60 nm. In one embodiment, the first epitaxial source / drain region has a second width measured 10 nm below the highest point of the first epitaxial source / drain region, wherein the second width is in the range of 15 nm to 29 nm.

[0118] According to another embodiment, a method for forming a semiconductor device includes: forming a shallow trench isolation (STI) region adjacent to a first fin and a second fin disposed on a substrate; forming a first groove in the first fin; forming a second groove in the second fin; and epitaxially growing a first source / drain region in the first groove and epitaxially growing a second source / drain region in the second groove, wherein the first source / drain region and the second source / drain region each have a rounded top profile, and wherein the first source / drain region and the second source / drain region merge at a merge boundary to form a merged source / drain region. The merged source / drain regions have a first height measured from a position level with the highest point of the merged source / drain regions to a position level with the highest point of the merged boundary; a second height measured from a position level with the highest point of the merged boundary to a position level with the lowest point of the merged boundary; and a third height measured from a position level with the lowest point of the merged boundary to a position level with the top surface of the STI region, wherein the first height is less than the second height, the first height is less than the third height, and the second height is less than the third height. In one embodiment, the epitaxial growth of the source / drain regions includes a reduced-pressure chemical vapor deposition (RPCVD) process. In one embodiment, the RPCVD process is performed in a temperature range of 650°C to 750°C. In one embodiment, the epitaxial growth of the source / drain regions includes a cyclic deposition etch (CDE) process. In one embodiment, the epitaxial growth of the source / drain regions includes the use of a silicon-rich precursor gas, a phosphorus-based precursor gas, and a carrier gas, wherein the carrier gas includes hydrogen. In one embodiment, the ratio of silicon source precursor to carrier gas is in the range of 2:1 to 10:1.

[0119] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. A semiconductor device, comprising: A first fin and a second fin, the first fin and the second fin extending from a substrate; A shallow trench isolation area is disposed on the substrate between the first fin and the second fin; and A first epitaxial source / drain region, wherein the first epitaxial source / drain region includes a first portion grown on the first fin and a second portion grown on the second fin, wherein the first portion and the second portion are connected at a merge boundary, wherein the first epitaxial source / drain region further includes: A first sub-region extends from a position level with the highest point of the first epitaxial source / drain region to a position level with the highest point of the merge boundary, wherein the first sub-region has a first height, and wherein the top surface of the first sub-region includes a valley between the first fin and the second fin, the depth of which is less than 10 nm. A second sub-region extends from a position level with the highest point of the merged boundary to a position level with the lowest point of the merged boundary, wherein the second sub-region has a second height, and wherein the first height is less than the second height, and the ratio of the first height to the second height is less than 5:9; and A third sub-region extends from a position level with the lowest point of the merge boundary to a position level with the top surface of the shallow trench isolation area, wherein the third sub-region has a third height, and wherein the first height is less than the third height and the second height is less than the third height.

2. The semiconductor device of claim 1, wherein the first epitaxial source / drain region comprises SiP.

3. The semiconductor device of claim 2, wherein the phosphorus concentration in the first epitaxial source / drain region is 1 × 10⁻⁶. 21 atoms / cm 3 Up to 4×10 21 atoms / cm 3 Within the range.

4. The semiconductor device of claim 1, wherein the first epitaxial source / drain region extends below a position flush with the top surface of the shallow trench isolation region.

5. The semiconductor device of claim 1, wherein the width of the first epitaxial source / drain region is in the range of 40 nm to 70 nm.

6. The semiconductor device of claim 1, wherein the first height is less than 10 nm.

7. The semiconductor device of claim 1, wherein the semiconductor device is part of a memory array.

8. The semiconductor device of claim 1, wherein the ratio of the first height to the third height is less than 1:

4.

9. The semiconductor device of claim 1, further comprising: A third fin extends from the substrate; A second epitaxial source / drain region is located on the third fin; A fourth fin extends from the substrate and is adjacent to the third fin; A fifth fin extends from the substrate and is adjacent to the first fin; A third epitaxial source / drain region is located on the fourth fin; as well as A fourth epitaxial source / drain region is located on the fifth fin, wherein the fourth epitaxial source / drain region is physically separated from the third epitaxial source / drain region and the second epitaxial source / drain region.

10. A semiconductor device, comprising: A high-density circuit region is located on a substrate including a high-density memory cell, the high-density memory cell comprising: A first fin extends from the substrate; A first epitaxial source / drain region is located on the first fin; A second fin extends from the substrate and is adjacent to the first fin; A third fin extends from the substrate and is adjacent to the first fin; A second epitaxial source / drain region is located on the second fin; and A third epitaxial source / drain region is located on the third fin, wherein the third epitaxial source / drain region is physically separated from the second epitaxial source / drain region and the first epitaxial source / drain region; and A high-current circuit region is located on a substrate including a high-current memory cell with an operating speed greater than that of the high-density memory cell, wherein the fin spacing in the high-density memory cell is smaller than that in the high-current memory cell, and the high-current memory cell includes: A fourth fin and a fifth fin extend from the substrate; and A fourth epitaxial source / drain region, wherein the fourth epitaxial source / drain region includes a first portion grown on the fourth fin, wherein the fourth epitaxial source / drain region includes a second portion grown on the fifth fin, wherein the first portion and the second portion are connected at a merge boundary, and wherein the fourth epitaxial source / drain region further includes: A first sub-region extends from a position level with the highest point of the fourth epitaxial source / drain region to a position level with the highest point of the merged boundary, wherein a valley is formed between a first circular top profile of the first part of the fourth epitaxial source / drain region and a second circular top profile of the second part of the fourth epitaxial source / drain region, and the depth of the valley is less than 10 nm. A second sub-region extends from a position level with the highest point of the merged boundary to a position level with the lowest point of the merged boundary; and A third sub-region extends from a position level with the lowest point of the merge boundary to a position level with the lowest point of the fourth epitaxial source / drain region.

11. The semiconductor device of claim 10, wherein the first epitaxial source / drain region has a first height measured from a position flush with the bottom point of the first epitaxial source / drain region to a position flush with the highest point of the first epitaxial source / drain region, wherein the first epitaxial source / drain region has a first width measured between points where the opposite sidewalls of the first epitaxial source / drain region are maximally separated, and wherein the ratio of the first width to the first height is in the range of 5:12 to 1:

1.

12. The semiconductor device of claim 10, wherein a first width of the first epitaxial source / drain region is in the range of 25 nm to 40 nm.

13. The semiconductor device of claim 10, wherein a first height of the first epitaxial source / drain region is in the range of 40 nm to 60 nm.

14. The semiconductor device of claim 10, wherein the first epitaxial source / drain region has a second width measured 10 nm below the highest point of the first epitaxial source / drain region, wherein the second width is in the range of 15 nm to 29 nm.

15. A semiconductor device, comprising: A first fin and a second fin are disposed on a substrate; An isolation region is located between the first fin and the second fin, and the isolation region is located on the substrate; A first source / drain region extending from the first fin, the first source / drain region having a first circular top profile; and A second source / drain region extends from the second fin, and the second source / drain region has a second circular top profile. A valley is formed between the first circular top profile of the first source / drain region and the second circular top profile of the second source / drain region, and the depth of the valley is less than 10 nm. The first source / drain region and the second source / drain region are in contact at a merge boundary. The second source / drain region has a first height measured from a position level with the highest point of the second source / drain region to a position level with the highest point of the merge boundary. The second source / drain region has a second height measured from a position level with the highest point of the merge boundary to a position level with the lowest point of the merge boundary. The second source / drain region has a third height measured from a position level with the lowest point of the merge boundary to a position level with the top surface of the isolation region. The first height is less than the second height, the second height is less than the third height, and the first height is less than the third height.

16. The semiconductor device of claim 15, wherein the second height is in the range of 18 nm to 28 nm.

17. The semiconductor device of claim 15, wherein the third height is in the range of 25 nm to 40 nm.

18. The semiconductor device of claim 15, wherein a combined width of the first source / drain region and the second source / drain region is in the range of 40 nm to 70 nm.

19. The semiconductor device of claim 15, wherein the first source / drain region and the second source / drain region are SiP.

20. The semiconductor device of claim 15, further comprising: A high-density memory cell is located on the substrate, wherein the first fin and the second fin are part of a high-current memory cell on the substrate, the high-current memory cell having a greater operating speed than the high-density memory cell.

21. A method for forming a semiconductor device, comprising: A shallow trench isolation region is formed adjacent to a first fin and a second fin disposed on a substrate; A first groove is formed in the first fin; A second groove is formed in the second fin; and A first source / drain region is epitaxially grown in the first groove, and a second source / drain region is epitaxially grown in the second groove. Each of the first and second source / drain regions includes a circular top profile. The step of forming the circular top profile includes introducing dichlorosilane and hydrogen gas, wherein the hydrogen gas adheres to dangling bonds in the 100° plane of each of the first and second source / drain regions. The first source / drain region and the second source / drain region merge at a merging boundary to form a merged source / drain region. The merged source / drain region has a first height measured from a position level with the highest point of the merged source / drain region to a position level with the highest point of the merging boundary. A valley is formed between the circular top contour of the first source / drain region and the circular top contour of the second source / drain region, and the depth of the valley is less than 10 nm. The merged source / drain region has a second height measured from a position level with the highest point of the merging boundary to a position level with the lowest point of the merging boundary. The merged source / drain region has a third height measured from a position level with the lowest point of the merging boundary to a position level with the top surface of the shallow trench isolation region. The ratio of the first height to the second height is less than 5:

9. The first height is less than the third height, and the second height is less than the third height.

22. The method of forming a semiconductor device as claimed in claim 21, wherein the step of epitaxially growing the first source / drain region and the second source / drain region includes a reduced-pressure chemical vapor deposition process.

23. The method of forming a semiconductor device as claimed in claim 22, wherein the reduced-pressure chemical vapor deposition process is performed in a temperature range of 650°C to 750°C.

24. The method of forming a semiconductor device as claimed in claim 21, wherein the step of epitaxially growing the first source / drain region and the second source / drain region includes a cyclic deposition-etch process.

25. The method of forming a semiconductor device as claimed in claim 21, wherein the step of epitaxially growing the first source / drain region and the second source / drain region includes using a silicon-rich precursor gas, a phosphorus-based precursor gas, and a carrier gas, the carrier gas including hydrogen.

26. The method of forming a semiconductor device as claimed in claim 25, wherein the ratio of the silicon-rich precursor gas to the carrier gas is in the range of 2:1 to 10:

1.

27. The method of forming a semiconductor device as claimed in claim 25, wherein the step of epitaxially growing the first source / drain region and the second source / drain region having their respective circular top profiles further includes using a hydrogen gas quantity in the range of 2L to 10L.

28. A method for forming a semiconductor device, comprising: An isolation region is formed on a substrate, a first semiconductor protrusion extends from the substrate to a first side of the isolation region, and a second semiconductor protrusion extends from the substrate to a second side of the isolation region, the second side being opposite to the first side. A gate structure is formed above the first semiconductor protrusion and the second semiconductor protrusion; A gate spacer is formed adjacent to the gate structure; A first groove is formed in the first semiconductor protrusion, and a second groove is formed in the second semiconductor protrusion; and A first source / drain region is epitaxially grown in the first groove, and a second source / drain region is epitaxially grown in the second groove. The first source / drain region and the second source / drain region merge at a merging boundary. The first source / drain region has a first circular top profile in a cross-sectional view, and the second source / drain region has a second circular top profile in the cross-sectional view. There is a valley between the first circular top profile and the second circular top profile, and the depth of the valley is less than 10 nm. Hydrogen gas is introduced as a carrier gas when the first source / drain region and the second source / drain region are epitaxially grown, and the hydrogen gas passivates the surface of the gate spacer.

29. The method of forming a semiconductor device as claimed in claim 28, wherein the steps of forming the first circular top profile and the second circular top profile include introducing dichlorosilane and hydrogen.

30. The method of forming a semiconductor device as claimed in claim 29, wherein hydrogen gas is attached to dangling bonds in the 100 planes of the first source / drain region and the second source / drain region, respectively.

31. The method for forming a semiconductor device as claimed in claim 29, wherein when hydrogen is introduced, a hydrogen amount in the range of 2L to 10L is used.

32. The method of forming a semiconductor device as claimed in claim 28, further comprising: Multiple trenches are etched in the substrate, wherein the etching of the multiple trenches forms the first semiconductor protrusion and the second semiconductor protrusion.

33. The method of forming a semiconductor device as claimed in claim 28, wherein the steps of epitaxially growing the first source / drain region in the first groove and epitaxially growing the second source / drain region in the second groove include using a silicon-rich precursor gas and a phosphorus-based precursor gas.

34. The method of forming a semiconductor device as claimed in claim 28, wherein the first source / drain region and the second source / drain region are epitaxially grown by a reduced-pressure chemical vapor deposition process, the reduced-pressure chemical vapor deposition process being performed at a pressure in the range of 50 Torr to 300 Torr.

35. The method of forming a semiconductor device as claimed in claim 28, wherein the first source / drain region and the second source / drain region comprise SiP.

36. The method of forming a semiconductor device as claimed in claim 35, wherein the phosphorus concentration in the first source / drain region and the second source / drain region is 1 × 10⁻⁶. 21 atoms / cm 3 Up to 4×10 21 atoms / cm 3 Within the range.

37. A method for forming a semiconductor device, comprising: A first groove is formed in a first semiconductor protrusion, a second groove is formed in a second semiconductor protrusion, and a third groove is formed in a third semiconductor protrusion. The first semiconductor protrusion, the second semiconductor protrusion, and the third semiconductor protrusion extend from a high-density circuit region in a substrate. The second semiconductor protrusion is adjacent to a first side of the first semiconductor protrusion, and the third semiconductor protrusion is adjacent to a second side of the first semiconductor protrusion. The second side is opposite to the first side. A fourth groove is formed in a fourth semiconductor protrusion and a fifth groove is formed in a fifth semiconductor protrusion. The fourth semiconductor protrusion and the fifth semiconductor protrusion extend from a high-current circuit region in the substrate. The fifth semiconductor protrusion is adjacent to the fourth semiconductor protrusion. A first spacing of semiconductor protrusions in the high-density circuit region is smaller than a second spacing of semiconductor protrusions in the high-current circuit region. A first source / drain region is epitaxially grown in the first groove, a second source / drain region is epitaxially grown in the second groove, and a third source / drain region is epitaxially grown in the third groove. The first source / drain region is separated from the second and third source / drain regions. The first, second, and third source / drain regions each have a circular top profile in a cross-sectional view. A fourth source / drain region is epitaxially grown in the fourth groove, and a fifth source / drain region is epitaxially grown in the fifth groove. The fourth source / drain region and the fifth source / drain region merge at a merging boundary. The fourth source / drain region and the fifth source / drain region have their own circular top profiles in the cross-sectional schematic diagram. A valley is formed between the circular top profiles of the fourth source / drain region and the fifth source / drain region. The depth of the valley is less than 10 nm. A high-density memory cell is formed in the high-density circuit region, wherein the high-density memory cell includes the first semiconductor protrusion, the second semiconductor protrusion, the third semiconductor protrusion, the first source / drain region, the second source / drain region, and the third source / drain region; as well as A high-current memory cell is formed in the high-current circuit region, wherein the high-current memory cell includes the fourth semiconductor protrusion, the fifth semiconductor protrusion, and the fourth source / drain region.

38. The method of forming a semiconductor device as claimed in claim 37, wherein the operating speed of the high-current memory cell is greater than the operating speed of the high-density memory cell.

39. The method of forming a semiconductor device as claimed in claim 37, wherein the first source / drain region has a first height measured from a position flush with the bottom point of the first source / drain region to a position flush with the highest point of the first source / drain region, wherein the first source / drain region has a first width measured between points where the opposite sidewalls of the first source / drain region are maximally separated, and wherein the ratio of the first width to the first height is in the range of 5:12 to 1:

1.

40. The method of forming a semiconductor device as claimed in claim 37 further includes etching a plurality of trenches in the substrate to form the first semiconductor protrusion, the second semiconductor protrusion, the third semiconductor protrusion, the fourth semiconductor protrusion and the fifth semiconductor protrusion.

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