Method of manufacturing a display device

Abstract

A method for manufacturing a display device is disclosed. The method includes: forming a dielectric layer on an encapsulation layer comprising a first encapsulation region and a second encapsulation region adjacent to the first encapsulation region; forming a conductive layer on the dielectric layer; forming a first photoresist layer on the conductive layer superimposed on each of the first and second encapsulation regions; forming a second photoresist layer on the first photoresist layer superimposed on the second encapsulation region; and etching the conductive layer based on the first and second photoresist layers. When viewed in the thickness direction of the display panel including the encapsulation layer, at least a portion of the encapsulation layer superimposed on the second encapsulation region has a thickness greater than the portion of the encapsulation layer superimposed on the first encapsulation region.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0044863, filed on April 13, 2020, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0002] Exemplary embodiments / implementations of the invention relate to a display device, and more specifically, to a method of manufacturing a display device. Background Technology

[0003] Various display devices have been developed for multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles. Such display devices may include a display module for displaying images and detecting external input, a polarizing layer disposed on a display panel, and a window. The display module may include a display panel for displaying images and an input sensing layer for detecting external input.

[0004] The image output from the display panel is visible through the window. The input sensing layer can detect external inputs that are essentially close to the window.

[0005] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] The method according to an exemplary embodiment of the present invention can provide a method for manufacturing a display device with improved detectability of external input.

[0007] Additional features of the inventive concept will be set forth in the following description, some of which will become apparent from the description or may be acquired by practicing the inventive concept.

[0008] According to some embodiments of the present invention, a method of manufacturing a display device may include the following steps: forming a dielectric layer on an encapsulation layer of a display panel, the encapsulation layer including a first encapsulation region and a second encapsulation region adjacent to the first encapsulation region; forming a conductive layer on the dielectric layer; forming a first photoresist layer on the conductive layer superimposed with each of the first and second encapsulation regions; forming a second photoresist layer on the first photoresist layer superimposed with the second encapsulation region; and etching the conductive layer based on the first and second photoresist layers. When viewed in the thickness direction of the display panel, at least a portion of the encapsulation layer superimposed with the second encapsulation region may have a thickness greater than the thickness of the portion of the encapsulation layer superimposed with the first encapsulation region.

[0009] In some embodiments, a second photoresist layer can be formed by coating a first photoresist layer superimposed on the second encapsulation region with a photosensitive solution once or more.

[0010] In some embodiments, the method may further include: using a mask to expose a first photoresist layer and a second photoresist layer; and developing the exposed first photoresist layer and the exposed second photoresist layer. A conductive layer may be etched to form a first conductive pattern superimposed on a first packaging region and a second conductive pattern superimposed on a second packaging region.

[0011] In some embodiments, at least a portion of the second conductive pattern may have a linewidth greater than that of the first conductive pattern. The sum of the thicknesses of the first photoresist layer and the second photoresist layer superimposed on at least a portion of the second encapsulation region may be greater than the thickness of the first photoresist layer superimposed on the first encapsulation region.

[0012] In some embodiments, the second conductive pattern may include: a first portion having a first linewidth; and a second portion having a second linewidth greater than the first linewidth. The sum of the thicknesses of the first photoresist layer and the second photoresist layer superimposed on the second portion may be greater than the sum of the thicknesses of the first photoresist layer and the second photoresist layer superimposed on the first portion.

[0013] In some embodiments, the first portion may be closer to the first conductive pattern than the second portion.

[0014] In some embodiments, the display panel may define a display area and a peripheral area adjacent to the display area. The encapsulation layer may be formed to overlap the display area.

[0015] In some embodiments, when viewed in a plane, the second encapsulation region may be closer to the peripheral region than the first encapsulation region.

[0016] In some embodiments, the first packaging region may have a larger planar area than the second packaging region.

[0017] In some embodiments, when viewed in a plane, the second encapsulation region may surround the first encapsulation region.

[0018] It will be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0019] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0020] Figure 1 A perspective view illustrating a display device according to some embodiments of the present invention is shown.

[0021] Figure 2 An exploded perspective view illustrating a display device according to some embodiments of the present invention is shown.

[0022] Figure 3 A cross-sectional view of a display module illustrating some embodiments of the present invention is shown.

[0023] Figure 4A A plan view illustrating an encapsulation layer according to some embodiments of the present invention is shown.

[0024] Figure 4B A plan view illustrating an encapsulation layer according to some embodiments of the present invention is shown.

[0025] Figure 4C Some embodiments of the invention are shown along Figure 4A A sectional view taken from line I-I'.

[0026] Figure 5 An input sensing layer illustrating some embodiments according to the present invention is shown. Figure 3 A partial sectional view of AA.

[0027] Figure 6A A plan view illustrating an input sensing layer according to some embodiments of the present invention is shown.

[0028] Figure 6B A plan view showing an input sensing layer superimposed on an effective area according to some embodiments of the present invention is shown.

[0029] Figure 6C A plan view is shown, partially illustrating the input sensing layer according to some embodiments of the present invention.

[0030] Figure 7 Some embodiments of the invention are shown along Figure 6B The sectional view taken from line II-II'.

[0031] Figure 8A Some embodiments according to the present invention are shown in part. Figure 6B A magnified planar view of the sensing electrode.

[0032] Figure 8B Some embodiments according to the present invention are shown in part. Figure 6B A magnified planar view of the sensing electrode.

[0033] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F A cross-sectional view is shown illustrating a method for manufacturing a display device according to some embodiments of the present invention. Detailed Implementation

[0034] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, while the various exemplary embodiments may differ, they are not necessarily exclusive. For example, the specific shapes, constructions, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0035] Unless otherwise stated, the exemplary embodiments shown are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or uniformly referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0036] The use of crosshairs and / or shading in accompanying drawings is typically to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, scale, commonalities between the elements shown, or any other characteristics, properties, etc., of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular process sequence may be performed in a different order than that described when exemplary embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0037] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or intermediate layers. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or intermediate layers. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without intermediate components. Furthermore, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system such as the x, y, and z axes, but can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0038] Although the terms “first,” “second,” etc., can be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the publicly stated teaching.

[0039] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another (other) element as shown in the accompanying drawings. Spatial relative terms are intended to include not only the orientations depicted in the drawings but also different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be oriented “above” said other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well. Furthermore, when the terms “comprising,” “including,” and / or variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, and are thus used to interpret the inherent biases in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0041] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations, for example, due to manufacturing techniques and / or tolerances, will be anticipated. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the shapes of the specifically shown areas, but will include deviations in shape caused, for example, by manufacturing processes. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, so this is not intended to be limiting.

[0042] As is customary in the art, exemplary embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where said blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of some exemplary embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0044] Some embodiments of the present invention will now be described with reference to the accompanying drawings.

[0045] Figure 1 A perspective view illustrating a display device according to some embodiments of the present invention is shown. Figure 2 An exploded perspective view illustrating a display device according to some embodiments of the present invention is shown. Figure 3 A cross-sectional view of a display module illustrating some embodiments of the present invention is shown.

[0046] This specification exemplarily illustrates a display device DD suitable for a mobile phone terminal. Although not shown, a mobile phone terminal may be configured to include a display device DD located in a bracket / housing, the bracket / housing housing housing a motherboard on which electronic modules, camera modules, and power modules are mounted. The display device DD according to embodiments of the present invention is applicable not only to large electronic products such as televisions and monitors, but also to small and medium-sized electronic products such as tablet computers, car navigation systems, game consoles, and smartwatches.

[0047] Reference Figure 1 The display device DD can display an image IM on the display surface DD-IS. An icon image is shown as an example of an image IM. The display surface DD-IS is parallel to the plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 indicates the normal direction relative to the display surface DD-IS or represents the thickness direction of the display device DD. In this specification, the phrase "when viewed in a plane" or "when viewed on a plane" can mean "when viewed on the third direction DR3". The third direction DR3 distinguishes the front and rear surfaces (or top and bottom surfaces) of each layer or unit, which will be discussed below. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can represent corresponding opposite directions.

[0048] The display surface DD-IS includes a display area DD-DA on which an image IM is displayed, and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA is the area on which no image is displayed. However, the present invention is not limited thereto; the non-display area DD-NDA may be adjacent to one side of the display area DD-DA or may be omitted.

[0049] Reference Figure 2 The display device DD may include a window WM, a display module DM, a driver chip DC, a circuit board PB, and a housing component BC. The housing component BC can house the display module DM and can be combined with the window WM.

[0050] The window WM can be positioned above the display module DM and can transmit the image IM provided from the display module DM to the outside. The window WM includes a transmissive region TA and a non-transmissive region NTA. The transmissive region TA can be superimposed on the display regions DD-DA and can have a shape corresponding to the shape of the display regions DD-DA. The image IM displayed in the display regions DD-DA of the display device DD can be seen from the outside through the transmissive region TA of the window WM.

[0051] The non-transmissive region NTA can be stacked with the non-display region DD-NDA, and can have a shape corresponding to the shape of the non-display region DD-NDA. The non-transmissive region NTA can be a region whose optical transmittance is relatively smaller than that of the transmissive region TA. However, the technical concept of the present invention is not limited thereto, and the non-transmissive region NTA can be omitted.

[0052] The window WM can be formed of glass, sapphire, or plastic. Although the window WM is shown as a single layer, it can comprise multiple layers. The window WM can include a substrate layer and at least one printed layer superimposed on and disposed on the back surface of the substrate layer with the non-transparent region NTA. The printed layer can have a certain color. For example, the printed layer can be black or any color other than black.

[0053] The display module DM is positioned between the window WM and the receiving component BC. The display module DM includes a display panel DP and an input sensing layer ISU. The display panel DP can generate an image IM and can transmit the generated image IM to the window WM.

[0054] According to some embodiments of the present invention, the display panel DP can be an emitting display panel, and there is no specific limitation on its type. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The emitting layer of a quantum dot light-emitting display panel may include quantum dots or quantum rods. Examples of using an organic light-emitting display panel as the display panel DP will be discussed below.

[0055] The following will explain an example of using an organic light-emitting display panel as a display panel DP according to an embodiment of the present invention. However, the technical concept of the present invention is not limited thereto, and various types of display panels are applicable to the present invention based on the embodiments.

[0056] Reference Figure 3 The display panel DP includes a substrate layer SUB, and also includes a circuit element layer DP-CL, a display element layer DP-OLED, and an encapsulation layer TFE, all disposed on the substrate layer SUB.

[0057] The display panel DP includes the display area DP-DA and the peripheral area DP-NDA. The display area DP-DA of the display panel DP is... Figure 1 The display area shown is DD-DA or Figure 2 The transmission area TA shown corresponds to the outer region DP-NDA of the display panel DP. Figure 1 The non-display area DD-NDA shown in the image is... Figure 2 The non-transmittent region NTA is shown in the figure.

[0058] The substrate SUB may include at least one plastic film. The substrate SUB may include a flexible substrate (e.g., at least one selected from plastic substrates, glass substrates, metal substrates, and organic / inorganic composite substrates).

[0059] The DP-CL circuit element layer includes at least one intermediate dielectric layer and circuit elements. The intermediate dielectric layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit elements include signal lines and pixel driving circuitry.

[0060] The DP-OLED display element layer includes a plurality of organic light-emitting diodes. The DP-OLED display element layer may also include an organic layer such as a pixel defining layer. According to some embodiments, when the display panel DP is configured as a liquid crystal display panel, the DP-OLED display element layer may be configured as a liquid crystal layer.

[0061] A TFE (Thin Film Encapsulation) layer encapsulates the DP-OLED display element layer. For example, the TFE layer can be a thin-film encapsulation layer. The TFE layer may include at least one dielectric layer. The TFE layer protects the DP-OLED display element layer from foreign substances such as moisture, oxygen, and dust particles.

[0062] An input sensing layer (ISU) can be positioned between the window (WM) and the display panel (DP). The ISU detects externally applied input. Externally applied input can be provided in various types. For example, external input includes the user's body parts, a stylus, light, heat, pressure, or any other type of external input. Furthermore, external input can include not only the user's touch (such as the user's hand) but also spatial touches that are near or adjacent to the user (e.g., hover touch).

[0063] The input sensing layer (ISU) can be directly disposed on the display panel (DP). In this disclosure, the phrase "A is directly disposed on B" means that no adhesive layer is disposed between A and B. In some embodiments, the input sensing layer (ISU) and the display panel (DP) can be manufactured in a continuous process. However, the inventive concept is not limited thereto. The input sensing layer (ISU) can be configured as a separate panel and can be bonded to the display panel (DP) via an adhesive layer.

[0064] Return to reference Figure 2 The DC driver chip can be set on the DP display panel, and simultaneously with... Figure 1 The non-display area DD-NDA is shown in the diagram. For example, in response to a control signal transmitted from the circuit board PB, the driver chip DC can generate the drive signals required for the operation of the display panel DP. The driver chip DC can transmit the generated drive signals to the circuit element layer DP-CL of the display panel DP. In this specification, the driver chip DC can be interpreted as an electronic component.

[0065] The circuit board PB can be disposed at the end of the substrate layer SUB and electrically connected to the circuit element layer DP-CL. The circuit board PB can be rigid or flexible. For example, when the circuit board PB is flexible, a flexible printed circuit board can be provided as the circuit board PB. The circuit board PB may include timing control circuitry for controlling the operation of the display panel DP. The timing control circuitry may be configured in the form of integrated circuit chips mounted on the circuit board PB. Additionally, the circuit board PB may include input sensing circuitry for controlling the input sensing layer ISU.

[0066] Figure 4A A plan view illustrating an encapsulation layer according to some embodiments of the present invention is shown. Figure 4B A plan view illustrating an encapsulation layer according to some embodiments of the present invention is shown. Figure 4C Some embodiments of the invention are shown along Figure 4A A sectional view taken from line I-I'.

[0067] Figure 4A and Figure 4B The relationship between the encapsulation layer TFE, the display area DP-DA, and the peripheral area DP-NDA is briefly illustrated.

[0068] The encapsulation layer TFE defines a first encapsulation region TFA1 and a second encapsulation region TFA2 surrounding the first encapsulation region TFA1 when viewed in a plan view. The first encapsulation region TFA1 may have a planar area larger than that of the second encapsulation region TFA2.

[0069] According to some embodiments of the present invention, when viewed in a plan view, the first encapsulation region TFA1 and the second encapsulation region TFA2 can be superimposed on the display region DP-DA. When viewed in a plan view, the second encapsulation region TFA2 can be disposed between the peripheral region DP-NDA and the first encapsulation region TFA1. The second encapsulation region TFA2 can be closer to the peripheral region DP-NDA than the first encapsulation region TFA1.

[0070] Figure 4B The encapsulation layer TFEa and Figure 4A The difference between the encapsulation layer TFE lies in the positional relationship between the first encapsulation region TFA1a and the second encapsulation region TFA2a.

[0071] Reference Figure 4B When viewed in the second direction DR2, the second encapsulation region TFA2a can be disposed on the opposite side surface of the first encapsulation region TFA1a. For example, as Figure 4B As shown, the second packaging region TFA2a, the first packaging region TFA1a, and the second packaging region TFA2a can be arranged sequentially along the second direction DR2.

[0072] The arrangement of the first and second packaging areas is not limited to the above. Figure 4A or Figure 4B The arrangement is illustrated in the example. For example, the second encapsulation region may be disposed on only one or three sides of the first encapsulation region.

[0073] Reference Figure 4C ,like Figure 4A As shown, the encapsulation layer TFE can be divided into a first encapsulation region TFA1 and a second encapsulation region TFA2.

[0074] The encapsulation layer TFE has a bottom surface TFE-D and a top surface TFE-U. The bottom surface TFE-D of the encapsulation layer TFE can face the display element layer DP-OLED, and the top surface TFE-U of the encapsulation layer TFE can face... Figure 3 The input sensing layer ISU is shown in the figure. For example, the input sensing layer ISU may be formed on the top surface TFE-U of the encapsulation layer TFE or otherwise disposed on the top surface TFE-U of the encapsulation layer TFE.

[0075] The top surface TFE-U of the encapsulation layer TFE includes a first top surface TFE-U1 superimposed with the first encapsulation region TFA1 and a second top surface TFE-U2 superimposed with the second encapsulation region TFA2.

[0076] The first top surface TFE-U1 can be parallel to the top surface of the substrate layer SUB. When the display panel DP has a flat shape, both the first top surface TFE-U1 and the substrate layer SUB can have flat shapes. Alternatively, when the display panel DP is bent along a specific direction, both the first top surface TFE-U1 and the substrate layer SUB can have shapes bent along that specific direction.

[0077] In this specification, the phrase "parallel" does not always refer to the dictionary definition of "parallel (two lines that do not intersect each other regardless of how they extend)." For example, the first top surface TFE-U1 may have an uneven top surface. In this specification, when viewed in cross-section, the surface literally parallel to the substrate layer SUB is defined as the reference surface RL. The first top surface TFE-U1 may undulate relative to the reference surface RL in directions away from and towards the substrate layer SUB, while extending along the reference surface RL. The distance difference between the first top surface TFE-U1 and the substrate layer SUB may be zero or fall within a specific error range. The specific error range may be less than about a few nanometers.

[0078] According to an embodiment of the invention, the second top surface TFE-U2 may convexly protrude in a direction away from the substrate layer SUB (e.g., in the third direction DR3). For example, the second top surface TFE-U2 may protrude from the reference surface RL in a direction away from the substrate layer SUB (e.g., in the third direction DR3), the reference surface RL extending from the first top surface TFE-U1.

[0079] In some embodiments, the thickness of the portion P1 of the encapsulation layer TFE overlapping with the second encapsulation region TFA2 may be greater than the thickness of the portion of the encapsulation layer TFE overlapping with the first encapsulation region TFA1. Conversely, the thickness of another portion P2 of the encapsulation layer TFE overlapping with the second encapsulation region TFA2 may be less than the thickness of the portion of the encapsulation layer TFE overlapping with the first encapsulation region TFA1.

[0080] A first distance DT1 can be set between the first top surface TFE-U1 and the substrate layer SUB. For example, when the first top surface TFE-U1 is parallel to the substrate layer SUB, the distance between the substrate layer SUB and any point on the first top surface TFE-U1 can be substantially the same within a certain error range.

[0081] In this specification, the term "distance" refers to a distance measured in a direction parallel to the third direction DR3 or in the thickness direction of the display panel DP. When the display panel DP is bent, "distance" may be a distance measured along a direction orthogonal to the tangent at the point of measurement.

[0082] The distance between the second top surface TFE-U2 and the substrate layer SUB can have various values ​​ranging from a second distance DT2, which is larger than the first distance DT1, to a third distance DT3, which is smaller than the first distance DT1. For example, the second top surface TFE-U2 and the substrate layer SUB can have a second distance DT2 as the maximum distance and a third distance DT3 as the minimum distance. The thickness of a portion P1 of the encapsulation layer TFE can correspond to the second distance DT2, and the thickness of another portion P2 of the encapsulation layer TFE can correspond to the third distance DT3.

[0083] The second top surface TFE-U2 may include a peak PK, a first tilted surface IS1, and a second tilted surface IS2. Peak PK may be defined as a region on the second top surface TFE-U2 spaced apart from the substrate layer SUB by a second distance DT2. For example, peak PK may be a region having a maximum distance from the substrate layer SUB. When viewed in the first direction DR1, the first tilted surface IS1 may extend from peak PK toward the first package region TFA1, and the first top surface TFE-U1 may be connected to peak PK. When viewed in the first direction DR1, the second tilted surface IS2 may extend from peak PK in a direction away from the first package region TFA1.

[0084] Figure 5 An input sensing layer illustrating some embodiments according to the present invention is shown. Figure 3 A partial sectional view of AA. Figure 6A A plan view illustrating an input sensing layer according to some embodiments of the present invention is shown. Figure 6B A plan view showing an input sensing layer superimposed on an effective area according to some embodiments of the present invention is shown. Figure 6C A plan view is shown, partially illustrating the input sensing layer according to some embodiments of the present invention.

[0085] Reference Figure 5 The input sensing layer ISU includes a first sensing dielectric layer IS-IL1, a first conductive layer IS-CL1, a second sensing dielectric layer IS-IL2, a second conductive layer IS-CL2, and a third sensing dielectric layer IS-IL3, which are sequentially stacked on the encapsulation layer TFE.

[0086] According to an embodiment of the present invention, the input sensing layer (ISU) may have a portion of its area that is connected to... Figure 4CThe bending shape corresponds to the bending shape of the top surface TFE-U of the encapsulation layer TFE shown in the figure. For example, a flat shape can be given to the input sensing layer ISU superimposed on the first encapsulation region TFA1, and a bending shape can be given to the input sensing layer ISU superimposed on the second encapsulation region TFA2.

[0087] The first conductive layer IS-CL1 may include a connection sensing electrode and may be disposed on the first sensing dielectric layer IS-IL1. The second sensing dielectric layer IS-IL2 may be disposed on the first sensing dielectric layer IS-IL1 and simultaneously cover the connection sensing electrode included in the first conductive layer IS-CL1. The second conductive layer IS-CL2 may include a sensing electrode and may be disposed on the second sensing dielectric layer IS-IL2. The third sensing dielectric layer IS-IL3 may be disposed on the second sensing dielectric layer IS-IL2 and simultaneously cover the sensing electrode included in the second conductive layer IS-CL2.

[0088] According to an embodiment of the present invention, the first sensing dielectric layer IS-IL1 can be directly disposed on the encapsulation layer TFE. However, the technical concept of the present invention is not limited thereto. The first sensing dielectric layer IS-IL1 can be omitted, in which case the first conductive layer IS-CL1 can be directly disposed on the encapsulation layer TFE.

[0089] According to embodiments of the present invention, each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a single-layer structure or a multilayer structure in which multiple layers are stacked along a third direction DR3. The multilayer conductive layer may include at least two layers selected from transparent conductive layers and metal layers. The multilayer conductive layer may include metal layers comprising metals that are different from each other.

[0090] The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or any alloy thereof.

[0091] Each of the first sensing dielectric layer IS-IL1, the second sensing dielectric layer IS-IL2, and the third sensing dielectric layer IS-IL3 may have a single-layer structure or a multi-layer structure, and may have at least one selected from inorganic layers and organic layers.

[0092] Reference Figure 6A The input sensing layer (ISU) includes an effective region (AR) and an ineffective region (NAR) adjacent to the effective region (AR). The effective region (AR) can be connected to the above-mentioned... Figure 2 The transmission region TA of the window WM is defined in the middle, and the invalid region NAR can correspond to the non-transmittance region NTA of the window WM.

[0093] For example, the input sensing layer (ISU) includes a first sensing electrode, a second sensing electrode, a first connector (BSP1), a second connector (BSP2), and a sensing pad (IPD). The first sensing electrode, the second sensing electrode, the first connector (BSP1), and the second connector (BSP2) are stacked with the active area (AR), and the sensing pad (IPD) is stacked with the inactive area (NAR). The first sensing electrode, the second sensing electrode, and the second connector (BSP2) can be coupled with... Figure 5 Corresponding to the sensing electrodes discussed in the article, the first connector BSP1 can be connected to... Figure 5 The connection sensing electrode discussed in the text corresponds to this.

[0094] The first sensing electrode may extend in a first direction DR1 and may be arranged in a second direction DR2. The number of the first sensing electrodes may be n, where n is a natural number. The first sensing electrode includes a plurality of first sensing portions SP1, which, when viewed in a plan view, are spaced apart from each other and arranged in the first direction DR1.

[0095] The second sensing electrode may extend in the second direction DR2 and may be arranged in the first direction DR1. The number of the second sensing electrodes may be m, where m is a natural number. The second sensing electrode includes a plurality of second sensing portions SP2, which, when viewed in a plan view, are spaced apart from each other and arranged in the second direction DR2. When viewed in a plan view, the second sensing portions SP2 may be spaced apart from and insulated from the first sensing portion SP1.

[0096] The first connector BSP1 can connect the first sensing portions SP1 to each other. For example, a single first connector BSP1 can electrically connect two adjacent first sensing portions SP1 in the first direction DR1.

[0097] The second connector BSP2 can connect the second sensing portions SP2 to each other. For example, a single second connector BSP2 can electrically connect two adjacent second sensing portions SP2 in the second direction DR2. According to an embodiment of the invention, the second connector BSP2 and the second sensing portion SP2 can have a single integral shape formed in the same process. The first connector BSP1 and the second connector BSP2 can intersect each other when viewed in a plan view, and can be insulated from each other when viewed in cross-section.

[0098] According to an embodiment of the present invention, the first sensing portion SP1, the second sensing portion SP2, and the second connector BSP2 can be formed from the same material in the same process, and can be included above. Figure 5In the second conductive layer IS-CL2 discussed earlier. For example, the first sensing portion SP1, the second sensing portion SP2, and the second connector BSP2 can be directly disposed on the second sensing dielectric layer IS-IL2.

[0099] According to an embodiment of the present invention, the first connector BSP1 may be included in Figure 5 In the first conductive layer IS-CL1 discussed herein, the first connector BSP1 can be directly disposed on the first sensing dielectric layer IS-IL1. The first connector BSP1 can be electrically connected to the first sensing portion SP1 through a contact hole defined in the first sensing dielectric layer IS-IL1.

[0100] However, the components included in the first conductive layer IS-CL1 and the second conductive layer IS-CL2 are not necessarily limited to this and can be modified in various ways. For example, the first sensing portion SP1, the second sensing portion SP2, and the second connector BSP2 can be included in the first conductive layer IS-CL1, and the first connector BSP1 can be included in the second conductive layer IS-CL2.

[0101] The sensing pad IPD includes a first sensing pad IPD1, a second sensing pad IPD2, and a third sensing pad IPD3. Each of the first sensing pad IPD1, the second sensing pad IPD2, and the third sensing pad IPD3 can be configured as multiple.

[0102] The first sensing pad IPD1 can be connected to the corresponding end of the first sensing electrode, and the second sensing pad IPD2 can be connected to the corresponding other end of the first sensing electrode. The third sensing pad IPD3 can be connected to the corresponding end of the second sensing electrode.

[0103] Although not in Figure 6A As shown, however, the input sensing layer ISU may include a first line connecting the first sensing pad IPD1 to the corresponding end of the first sensing electrode, a second line connecting the second sensing pad IPD2 to the corresponding other end of the first sensing electrode, and a third line connecting the third sensing pad IPD3 to the corresponding end of the second sensing electrode.

[0104] Reference Figure 6B The first sensing part SP1, the second sensing part SP2, the first connector BSP1 and the second connector BSP2 can all be set as metal mesh structures to reduce the possibility of external visibility.

[0105] according to Figure 6C As shown, the display area DP-DA includes multiple pixel areas PXA and a light-shielding area NPXA adjacent to the pixel areas PXA. For example, the light-shielding area NPXA may surround the pixel areas PXA. In this specification, the term "pixel area" may refer to... Figure 1The region from which the display surface DD-IS emits light is discussed in the text.

[0106] Each of the first sensing portions SP1 includes a first grid line SPt1 that defines a grid opening. Although the first grid line SPt1 is shown defining a grid opening, at least a portion of the first grid line SPt1 may not define a grid opening. For example, a portion of the first grid line SPt1 adjacent to the edge of the first sensing portion SP1 may not define a grid opening.

[0107] Each of the second sensing portions SP2 includes a second grid line SPt2 that defines a grid opening. Similar to the first grid line SPt1, although the second grid line SPt2 is shown as defining a grid opening, at least a portion of the second grid line SPt2 may not define a grid opening.

[0108] According to some embodiments of the present invention, when viewed in a planar view, the grid openings can have an area larger than the area of ​​the pixel region PXA. Furthermore, at least one of the plurality of grid openings defined by the first grid line SPt1 and the second grid line SPt2 can have different areas from each other.

[0109] Furthermore, each of the first grid line SPt1 and the second grid line SPt2 overlaps with the light-shielding region NPXA. Each of the first grid lines SPt1 includes two first extensions SPt1-A extending in a fifth direction DR5 intersecting the first direction DR1 and the second direction DR2, and also includes two second extensions SPt1-B extending in a fourth direction DR4 intersecting the fifth direction DR5. The first extensions SPt1-A may face each other and connect to the second extensions SPt1-B. The second extensions SPt1-B may face each other and connect to the first extensions SPt1-A.

[0110] Each of the second grid lines SPt2 includes two third extensions SPt2-A extending in a fourth direction DR4, which intersects the first direction DR1 and the second direction DR2, and two fourth extensions SPt2-B extending in a fifth direction DR5, which intersects the fourth direction DR4. The third extensions SPt2-A may face each other and connect to the fourth extensions SPt2-B. The fourth extensions SPt2-B may face each other and connect to the third extensions SPt2-A.

[0111] Figure 7 Some embodiments of the invention are shown along Figure 6B The sectional view taken from line II-II'. Figure 8A Some embodiments according to the present invention are shown in part. Figure 6B A magnified planar view of the sensing electrode. Figure 8BSome embodiments according to the present invention are shown in part. Figure 6B A magnified planar view of the sensing electrode.

[0112] Reference Figure 7 The image shows a sensing electrode of the second conductive layer IS-CL2 disposed on the encapsulation layer TFE. For example, Figure 7 The sensing electrode of the second conductive layer IS-CL2 shown in the figure can represent Figure 6A The first sensing portion SP1 and the second sensing portion SP2 are shown in the figure.

[0113] The first conductive pattern SP-C is interpreted as the sensing electrode superimposed on the first encapsulation region TFA1, and the second conductive pattern SP-S is interpreted as the sensing electrode superimposed on the second encapsulation region TFA2. The second conductive pattern SP-S may be closer to the invalid region NAR or peripheral region of the display panel DP than the first conductive pattern SP-C (see...). Figure 3 DP-NDA).

[0114] According to an embodiment of the present invention, a first conductive pattern SP-C can be disposed on a second sensing dielectric layer IS-IL2 having a flat shape, and a second conductive pattern SP-S can be disposed on a second sensing dielectric layer IS-IL2 having a curved shape. Furthermore, the width of each of the first conductive pattern SP-C and the second conductive pattern SP-S in the second direction DR2 can be equal to... Figure 6C The line widths of the grid lines shown correspond to the line widths of the conductive patterns. In this specification, the line width of the conductive pattern may refer to the line width of the grid lines.

[0115] When viewed in a planar view, the peak PK of the second encapsulation region TFA2 can be superimposed on the second conductive pattern SP-S. When viewed in a planar view, the position of peak PK can be adjusted within the region superimposed on the second conductive pattern SP-S.

[0116] According to some embodiments of the present invention, the second conductive pattern SP-S may have a linewidth different from that of the first conductive pattern SP-C. The second conductive pattern SP-S, with a linewidth different from that of the first conductive pattern SP-C, may be connected to portions P1 and P2 of the encapsulation layer TFE (see...). Figure 4C One or each of the stacked elements.

[0117] The second conductive pattern SP-S may include a portion P1 of the encapsulation layer TFE (see...). Figure 4C The first part S1 corresponds to the encapsulation layer TFE, and may also include another part P2 (see Figure 4C The second part S2 corresponds to the first part S1. When viewed in a plan view, the second part S2 can be set to be farther away from the first package region TFA1 than the first part S1.

[0118] For example, according to Figure 8A As shown, a first conductive pattern SP-C with a first linewidth DK1 can be assigned to the first package region TFA1. A second conductive pattern SP-S with a second linewidth DK2 can be assigned to the second package region TFA2, and the second linewidth DK2 can be larger than the first linewidth DK1. The second conductive pattern SP-S with the second linewidth DK2 can correspond to the first portion S1 of the second conductive pattern SP-S and can be superimposed with peak PK.

[0119] Furthermore, the first portion S1 and the second portion S2 of the second conductive pattern SP-S can have different line widths. In some embodiments, according to Figure 8B As shown, a second linewidth DK2 can be assigned to the first portion S1 of the second conductive pattern SP-S superimposed on a portion TFA2-1 of the second package region TFA2. A third linewidth DK3 can be assigned to the second portion S2 of the second conductive pattern SP-S superimposed on another portion TFA2-2 of the second package region TFA2. The third linewidth DK3 of the second portion S2 can be larger than the second linewidth DK2 of the first portion S1. For example, the second conductive pattern SP-S can have a linewidth that increases with distance from the first package region TFA1 or with proximity to the invalid region NAR or the peripheral region DP-NDA.

[0120] In this case, when viewed in the first direction DR1, the first distance DS1a between the substrate layer SUB and the first portion S1 of the second conductive pattern SP-S can be greater than the second distance DS2 between the substrate layer SUB and the first conductive pattern SP-C.

[0121] Furthermore, the third distance DS1b between the substrate layer SUB and the second portion S2 of the second conductive pattern SP-S can be smaller than the second distance DS2 between the substrate layer SUB and the first conductive pattern SP-C. In this case, when viewed in a plan view, the first portion S1 of the second conductive pattern SP-S can be closer to the first package region TFA1 or the first conductive pattern SP-C than the first portion S2 of the second conductive pattern SP-S.

[0122] However, the technical concept of the present invention is not limited thereto, and the linewidth of the second conductive pattern SP-S can be varied according to the shape of the second packaging region TFA2. For example, depending on the shape of the second packaging region TFA2, the linewidth of the first portion S1 of the second conductive pattern SP-S can be larger than the linewidth of the second portion S2 of the second conductive pattern SP-S.

[0123] When an external input approaches the window superimposed on the second encapsulation region TFA2 (see...) Figure 2When the window (WM) is superimposed on the second encapsulation region TFA2, the detection reliability is reduced because the second encapsulation region TFA2 has a curved shape. In contrast, as described above, the second conductive pattern SP-S according to an embodiment of the present invention can be formed with a linewidth varying according to the shape of the second encapsulation region TFA2. Therefore, the detection reliability can be improved when the window (WM) is superimposed on the second encapsulation region TFA2, which has a curved shape. Figure 2 The reliability of the detection at the window (WM).

[0124] However, the technical concept of the present invention is not limited thereto. For example, with Figure 8A or Figure 8B As shown, the first conductive pattern SP-C superimposed on the first packaging region TFA1 can have a linewidth that is substantially the same as the linewidth of the second conductive pattern SP-S superimposed on the second packaging region TFA2.

[0125] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F A cross-sectional view is shown illustrating a method for manufacturing a display device according to some embodiments of the present invention.

[0126] Reference Figure 9A The first sensing dielectric layer IS-IL1, the first conductive layer IS-CL1, and the second sensing dielectric layer IS-IL2 of the input sensing layer ISU can be sequentially formed or otherwise disposed on the encapsulation layer TFE that defines the first encapsulation region TFA1 and the second encapsulation region TFA2. In this case, the first sensing dielectric layer IS-IL1, the first conductive layer IS-CL1, and the second sensing dielectric layer IS-IL2 of the input sensing layer ISU can all have a shape corresponding to the shape of the encapsulation layer TFE. For example, the component of the input sensing layer ISU corresponding to the first encapsulation region TFA1 can have a flat shape, and the component of the input sensing layer ISU corresponding to the second encapsulation region TFA2 can have a curved shape.

[0127] Reference Figure 9B A conductive layer SP-M can be formed or otherwise disposed on the second sensing dielectric layer IS-IL2. The conductive layer SP-M can be formed by coating the entire top surface of the second sensing dielectric layer IS-IL2 with a conductive material. Figure 5 The second conductive layer IS-CL2 discussed in the text corresponds to this.

[0128] A photoresist layer can be formed or otherwise disposed to pattern the conductive SP-M layer. For example, according to Figure 9BAs shown, a first photoresist layer PR1 can be formed on the conductive layer SP-M. On the conductive layer SP-M, the first photoresist layer PR1 can be formed or otherwise configured to overlap with each of the first encapsulation region TFA1 and the second encapsulation region TFA2.

[0129] The first photoresist layer PR1 can be formed by coating a photosensitive solution onto the conductive layer SP-M. When the photosensitive solution is coated onto the conductive layer SP-M, which is stacked with a first encapsulation region TFA1 having a flat shape, the first photoresist layer PR1 can be formed with a regular thickness. When the photosensitive solution is coated onto the conductive layer SP-M, which is stacked with a second encapsulation region TFA2 having a curved shape, the first photoresist layer PR1 will not be formed with a regular thickness.

[0130] For example, the first photoresist layer PR1 superimposed on the first encapsulation region TFA1 may have a first thickness DH1, and the first photoresist layer PR1 superimposed on the second encapsulation region TFA2 may include at least a portion of a second thickness DH2 having a thickness smaller than the first thickness DH1. This may be because the photosensitive solution used to form the first photoresist layer PR1 is coated on the conductive layer SP-M in a liquid phase.

[0131] When the photoresist layer has an irregular thickness, the conductive pattern or patterned conductive layer will have an irregular linewidth. As a result, the reliability of external input detection will deteriorate.

[0132] According to some embodiments of the present invention, such as Figure 9C As shown, a second photoresist layer PR2 can be formed on a first photoresist layer PR1 superimposed on the second encapsulation region TFA2. The second photoresist layer PR2 can compensate for the irregular thickness of the first photoresist layer PR1, and can be formed by performing one or more processes for coating the photosensitive solution.

[0133] As a result, the sum of the thicknesses of the first photoresist layer PR1 and the second photoresist layer PR2 superimposed on the second encapsulation region TFA2 can be substantially similar to the thickness of the first photoresist layer PR1 superimposed on the first encapsulation region TFA1.

[0134] Optionally, the sum of the thicknesses of the first photoresist layer PR1 and the second photoresist layer PR2 superimposed on the second encapsulation region TFA2 can be greater than the thickness of the first photoresist layer PR1 superimposed on the first encapsulation region TFA1. (Refer to the above.) Figure 8A The case discussed is where the second conductive pattern SP-S has a larger linewidth than the first conductive pattern SP-C.

[0135] Additionally, according to reference Figure 8B The linewidth of the second portion S2 of the second conductive pattern SP-S discussed herein can be larger than the linewidth of the first portion S1 of the second conductive pattern SP-S. In this case, the sum of the thicknesses of the first photoresist layer PR1 and the second photoresist layer PR2 superimposed on the second portion S2 can be larger than the sum of the thicknesses of the first photoresist layer PR1 and the second photoresist layer PR2 superimposed on the first portion S1.

[0136] Reference Figure 9D A pre-patterned mask can be used to expose and develop the first photoresist layer PR1 and the second photoresist layer PR2. Therefore, the first pattern PR-C can be formed to overlap with the first encapsulation region TFA1, and the second pattern PR-S can be formed to overlap with the second encapsulation region TFA2.

[0137] Reference Figure 9E The conductive layer SP-M can be etched based on the first pattern PR-C and the second pattern PR-S. As a result, the conductive layer SP-M can be formed as a first conductive pattern SP-C superimposed on the first packaging region TFA1 and a second conductive pattern SP-S superimposed on the second packaging region TFA2.

[0138] Reference Figure 9F The first pattern PR-C and the second pattern PR-S can be removed to leave the first conductive pattern SP-C and the second conductive pattern SP-S on the second sensing dielectric layer IS-IL2.

[0139] According to some embodiments of the present invention, various linewidths can be provided to the conductive pattern of the input sensing layer superimposed on the encapsulation layer having a curved shape. Therefore, it is possible to improve the detection reliability of external inputs sensed from windows corresponding to the encapsulation region having a curved shape.

[0140] While certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A method for manufacturing a display device, the method comprising the following steps: A dielectric layer is formed on the encapsulation layer of the display panel, the encapsulation layer including a first encapsulation region and a second encapsulation region adjacent to the first encapsulation region, wherein, when viewed in the thickness direction of the display panel, at least a portion of the encapsulation layer overlapping the second encapsulation region has a thickness greater than the thickness of the portion of the encapsulation layer overlapping the first encapsulation region. A conductive layer is formed on the dielectric layer; A first photoresist layer is formed by coating a photosensitive solution onto the conductive layer stacked with each of the first and second encapsulation regions; A second photoresist layer is formed by coating a photosensitive solution onto the portion of the first photoresist layer overlapping the second encapsulation region, wherein the sum of the thicknesses of the portions of the first and second photoresist layers overlapping at least a portion of the second encapsulation region is greater than the thickness of the portion of the first photoresist layer overlapping the first encapsulation region; and The conductive layer is etched based on the first photoresist layer and the second photoresist layer to form a first conductive pattern superimposed on the first packaging region and a second conductive pattern superimposed on the second packaging region. In this embodiment, at least a portion of the second conductive pattern has a linewidth greater than that of the first conductive pattern.

2. The method of claim 1, wherein, The second photoresist layer is formed by coating the portion of the first photoresist layer that overlaps with the second encapsulation region with a photosensitive solution once or more.

3. The method according to claim 1, further comprising: A mask is used to expose the first photoresist layer and the second photoresist layer; as well as The first and second photoresist layers exposed are then developed.

4. The method of claim 3, wherein, The second conductive pattern includes: The first part has a first line width; and The second part has a second line width that is larger than the first line width. Wherein, the sum of the thicknesses of the portions of the first photoresist layer and the second photoresist layer that overlap with the second portion is greater than the sum of the thicknesses of the portions of the first photoresist layer and the second photoresist layer that overlap with the first portion.

5. The method of claim 4, wherein, The first portion is closer to the first conductive pattern than the second portion.

6. The method of claim 1, wherein, The display panel defines a display area and a peripheral area adjacent to the display area, and The encapsulation layer is formed to overlap with the display area.

7. The method of claim 6, wherein, When viewed in a plane, the second encapsulation region is closer to the peripheral region than the first encapsulation region.

8. The method of claim 1, wherein, The first packaging region has a larger planar area than the second packaging region.

9. The method of claim 1, wherein, When viewed in a plane, the second encapsulation region surrounds the first encapsulation region.

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