Amplifier module with power transistor die and peripheral ground connections

Abstract

A power amplifier module includes a module substrate, a power transistor die, and a heat sink. The module substrate has a first module pad, a second module pad, and a third module pad exposed at a mounting surface. The power transistor die has an input / output surface facing the mounting surface, an opposing ground surface, an input pad electrically coupled to the first module pad, an output pad electrically coupled to the second module pad, and a power transistor. In an embodiment, the power transistor is a field effect transistor having a gate terminal coupled to the input pad, a drain terminal coupled to the output pad, and a source terminal coupled to the ground surface. The heat sink has a thermal contact surface physically and electrically coupled to the ground surface of the power transistor die. An electrical ground contact structure is connected between the thermal contact surface and the third module pad.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to amplifier modules, and more specifically, to amplifier modules including power transistor dies. Background Technology

[0002] Wireless communication systems employ power amplifier modules to increase the power of radio frequency (RF) signals. A power amplifier module includes a module substrate and an amplifier circuit system coupled to a mounting surface of the module substrate. A typical module substrate may include input terminals, output terminals, conductive signal routing structures, bonding pads at the mounting surface, and one or more grounding / heat dissipation structures extending through the module substrate. The amplifier circuit system typically includes a power transistor die having at least one integrated power transistor, top-side input / output (I / O) bonding pads, and a bottom-side conductive ground layer. The bottom-side conductive ground layer of the power transistor die is directly connected to the grounding / heat dissipation structures(s) of the module substrate.

[0003] To transmit RF signals between the module substrate and the power transistor die, an electrical connection is made using bonding wires that extend between bonding pads on the mounting surface of the module substrate and the top-side I / O bonding pads of the power transistor die. When the integrated power transistor is a field-effect transistor (FET), the die's input bonding pad is connected to the gate terminal of the FET, and the die's output bonding pad is connected to the drain terminal of the FET. The source terminal of the FET is coupled through the die to a bottom-side conductive ground layer, which is then connected to ground / heat dissipation structures, as mentioned above. During operation, the power transistor amplifies the input RF signal received through the transistor die's input bonding pad and transmits the amplified RF signal to the transistor die's output bonding pad. Simultaneously, the heat generated by the power transistor die is dissipated through the ground / heat dissipation structures embedded in the module substrate. While conventional module designs are well-suited for many applications, amplifier module designers continuously strive to optimize amplifier module designs for current and new applications to reduce module size, improve heat dissipation, and optimize performance. Summary of the Invention

[0004] According to a first aspect of the present invention, a power amplifier module is provided, comprising:

[0005] A module substrate having a mounting surface, a first module pad exposed at the mounting surface, a second module pad exposed at the mounting surface, and a third module pad exposed at the mounting surface;

[0006] A first power transistor die has an input / output (I / O) surface, a ground surface opposite to the I / O surface, an input pad exposed at the I / O surface, an output pad exposed at the I / O surface, and an integrated power transistor. The integrated power transistor has a control terminal electrically coupled to the input pad, a first current-carrying terminal electrically coupled to the output pad, and a second current-carrying terminal electrically coupled to the ground surface. The first power transistor die is coupled to the module substrate and the I / O surface faces the mounting surface. The input pad is electrically coupled to the first module pad, and the output pad is electrically coupled to the second module pad.

[0007] A first heat sink having a first thermal contact surface physically and electrically coupled to the ground surface of the first power transistor die, wherein the first thermal contact surface has a peripheral portion extending beyond the ground surface of the first power transistor die; and

[0008] An electrically grounded contact structure is connected between the peripheral portion of the first thermal contact surface and the third module pad of the module substrate.

[0009] According to one or more embodiments, the module substrate further includes: an input signal contact electrically coupled to the first module pad; an output signal contact electrically coupled to the second module pad; and a system ground contact electrically coupled to the third module pad.

[0010] According to one or more embodiments, it further includes: an input contact structure connected between the input pad of the first power transistor die and the first module pad; and an output contact structure connected between the output pad of the first power transistor die and the second module pad.

[0011] According to one or more embodiments, the input contact structure and the output contact structure each include one or more components selected from conductive pillars and solder.

[0012] According to one or more embodiments, the electrical grounding contact structure includes one or more components selected from conductive posts and solder.

[0013] According to one or more embodiments, the first heat sink comprises a thermally and electrically conductive material selected from copper or another bulk conductive material.

[0014] According to one or more embodiments, the integrated power transistor is a field-effect transistor, the control terminal is the gate terminal of the field-effect transistor, the first current-carrying terminal is the drain terminal of the field-effect transistor, and the second current-carrying terminal is the source terminal of the field-effect transistor.

[0015] According to one or more embodiments, the first power transistor die includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface, wherein the second surface of the semiconductor substrate corresponds to the ground surface of the first power transistor die; and a stacked structure formed on the first surface of the semiconductor substrate, wherein the exposed surface of the stacked structure corresponds to the I / O surface of the first power transistor die.

[0016] According to one or more embodiments, the first power transistor die further includes: a conductive layer on the second surface of the semiconductor substrate; and a plurality of through-substrate vias, wherein each of the through-substrate vias extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, and wherein the second current-carrying terminal of the integrated power transistor is electrically coupled to the conductive layer through the plurality of through-substrate vias.

[0017] According to one or more embodiments, it further includes: an encapsulation material covering the mounting surface of the module substrate, the first power transistor die, and the sidewall of the first heat sink.

[0018] According to one or more embodiments, the first heat sink further includes a second thermal contact surface opposite to the first thermal contact surface, and the surface of the encapsulating material is coplanar with the second thermal contact surface.

[0019] According to one or more embodiments, it further includes: a heat dissipation structure coupled to the second thermal contact surface.

[0020] According to one or more embodiments, the device further includes: a second power transistor die coupled to the mounting surface; and a second heat sink physically and electrically coupled to the second power transistor die, wherein the first power transistor die corresponds to the main amplifier of the Dougherty power amplifier, and the second power transistor die corresponds to the peak amplifier of the Dougherty power amplifier.

[0021] According to a second aspect of the present invention, a method for manufacturing a power amplifier module is provided, the method comprising:

[0022] A ground surface of a power transistor die is coupled to a first portion of a first thermal contact surface of a heat sink, wherein the power transistor die has an input / output (I / O) surface, a ground surface opposite to the I / O surface, an input pad exposed at the I / O surface, an output pad exposed at the I / O surface, and an integrated power transistor having a control terminal electrically coupled to the input pad, a first current-carrying terminal electrically coupled to the output pad, and a second current-carrying terminal electrically coupled to the ground surface;

[0023] The power transistor die is connected to a mounting surface of a module substrate, the module substrate including a first module pad, a second module pad, and a third module pad exposed at the mounting surface, wherein the power transistor die is connected to the mounting surface of the module substrate such that the input pad is connected to the first module pad and the output pad is connected to the second module pad; and

[0024] The electrical grounding contact structure is connected between the outer portion of the first thermal contact surface of the heat sink and the third module pad.

[0025] According to one or more embodiments, it further includes electrically connecting the third module pad to a ground reference.

[0026] According to one or more embodiments, it further includes: encapsulating the heat sink, the power transistor die, and the module substrate to form a power amplifier module.

[0027] According to one or more embodiments, connecting the power transistor die to the mounting surface of the module substrate includes:

[0028] Couple the first contact structure to the input pad;

[0029] Couple the second contact structure to the output pad;

[0030] Align the first contact structure and the second contact structure with the first module pad and the second module pad; and

[0031] Reflow solder is used to connect the first contact structure to the first module pad and the second contact structure to the second module pad.

[0032] According to one or more embodiments, each of the first contact structure and the second contact structure includes a rigid conductive post.

[0033] According to one or more embodiments, the electrical grounding contact structure includes solder.

[0034] According to one or more embodiments, the electrical grounding contact structure includes a rigid conductive post. Attached Figure Description

[0035] A more complete understanding of the subject matter can be obtained by considering the following figures, with reference to the detailed embodiments and claims, wherein similar reference numerals in the figures refer to similar elements.

[0036] Figure 1 This is a cross-sectional side view of a radio frequency (RF) system including a power amplifier module according to an example embodiment;

[0037] Figure 2 This is a flowchart of a method for manufacturing a power amplifier module and assembling the power amplifier module into an RF system according to an example embodiment;

[0038] Figure 3 This is a top view of a power transistor die according to an example embodiment;

[0039] Figure 4 According to the example embodiment Figure 3 A cross-sectional side view of the power transistor die along line 4-4;

[0040] Figure 5 According to the example embodiment Figure 3 A cross-sectional side view of the power transistor die along line 5-5;

[0041] Figure 6 This is a top view of the heat sink according to an example embodiment;

[0042] Figure 7 According to the example embodiment Figure 6 A cross-sectional side view of the radiator along line 7-7;

[0043] Figure 8 This is a cross-sectional side view of the die / heat sink assembly according to an example embodiment;

[0044] Figure 9 and 10 This is a cross-sectional side view of a power amplifier module at two manufacturing stages according to an example embodiment;

[0045] Figure 11 This is a top view of a Doherty power amplifier module partially manufactured according to an example embodiment, including two die / heat sink assemblies;

[0046] Figure 12 It is according to the example embodiment corresponding to Figure 11 A schematic diagram of the Dougherty power amplifier's modular components; and

[0047] Figure 13 and 14These are additional cross-sectional side views of a power amplifier module at two other manufacturing stages according to an example embodiment. Detailed Implementation

[0048] Figure 1 This is a cross-sectional side view of a radio frequency (RF) system 100 including a power amplifier module 110 according to an example embodiment. The RF system 100 typically includes a system substrate 120, a power amplifier module 110, and a heat dissipation structure 130. According to an embodiment, the system substrate 120 includes a multilayer printed circuit board (PCB) having a mounting surface 124, an opposing bottom surface 125, and one or more patterned conductive layers spaced apart by a dielectric material. Figure 1 In the example embodiment depicted, a conductive layer on mounting surface 124 is patterned to define a plurality of conductive pads, including pad 126, which provides electrical connections between system substrate 120 and electrical components (e.g., module 110) coupled to mounting surface 124. Some pads at mounting surface 124 of system substrate 120 may be used to transmit RF signals between power amplifier module 110 and other components mounted on or connected to system substrate 120, while other pads at mounting surface 124 may be used to provide connections to system ground or other reference voltages (e.g., bias voltages). For example, in Figure 1 In the middle, pads 126 each achieve the connection to the system ground.

[0049] The power amplifier module 110 is physically and electrically coupled to the mounting surface 124 of the system substrate 120. As will be described in more detail later, the power amplifier module 110 has a contact surface 1412, opposing heat dissipation surfaces 1414, a power transistor die 310, a heat sink 610, and a module substrate 910. The module substrate 910, the power transistor die 310, and the heat sink 610 are held in a fixed spatial relationship to each other by an encapsulation material 1310.

[0050] According to an embodiment, the module substrate 910 includes a small multilayer PCB with a mounting surface 914, an opposing bottom surface 912, and a plurality of patterned conductive layers spaced apart by a dielectric material. Figure 1 In the example embodiment depicted, the conductive layer on the mounting surface 914 is patterned to define a plurality of conductive pads exposed at the mounting surface 914, including pads 920, 922, and 924. Pads 920, 922, and 924 provide electrical connections between the module substrate 910, the power transistor die 310, and the heat sink 610, as will be explained in more detail below. Some pads at the mounting surface 914 of the module substrate 910 can be used to transmit RF signals, while other pads at the mounting surface 914 can be used to provide connections to system ground or other reference voltages (e.g., bias voltages). For example, in Figure 1In this context, each pad 920 is connected to the system ground. More specifically, each of the pads 920 is electrically coupled to an additional pad 921 on the bottom surface 912 of the module substrate 910 via a conductive via and an intermediate patterned conductive layer, and those additional pads 921 are coupled to the corresponding ground pad 126 of the system substrate 120, as discussed above.

[0051] In contrast, pads 922 and 924 on the mounting surface 914 of the module substrate 910 are configured to transmit input and output RF signals respectively between the module substrate 910 and the power transistor die 310. Although not in Figure 1 As shown in the image, but will be combined later. Figure 11 In more detail, pads 922 and 924 are electrically coupled to other power amplifier components. Figure 1 (Not shown in the image), the other power amplifier components are also coupled to the mounting surface 914 of the module substrate 910.

[0052] The power transistor die 310 has an input / output (I / O) surface 314 and a ground surface 312 opposite to the I / O surface 314. As will be discussed in more detail later, one or more power transistors are integrally formed in the power transistor die 310. The control terminal of at least one of the transistors is electrically coupled to an input pad 321 exposed at the I / O surface 314, and a first current-carrying terminal (e.g., drain terminal) of at least one of the transistors is electrically coupled to an output pad 354 exposed at the I / O surface 314. A second current-carrying terminal (e.g., source terminal) of the transistor is electrically coupled to a conductive layer 316 on the ground surface 312 of the power transistor die 310.

[0053] like Figure 1 As shown, the power transistor die 310 is coupled to the module substrate 910, with the I / O surface 314 facing the mounting surface 914 of the module substrate 910. Additionally, the input pad 321 of the power transistor die 310 is electrically coupled to the module pad 922 via the input contact structure 320, and the output pad 354 is electrically coupled to the module pad 924 via the output contact structure 360.

[0054] The heat sink 610 has an internal thermal contact surface 612 (also referred to as a die contact surface) and an opposing external thermal contact surface 1416 (also referred to as a heat dissipation structure contact surface). The power transistor die 310, and more specifically, the conductive layer 316 on the ground surface 312 of the die 310, is physically, thermally, and electrically coupled to the internal region of the die contact surface 612 of the heat sink 610 (e.g., Figure 6Region 614). The peripheral portion of the die contact surface 612 extends beyond the ground surface 312 of the power transistor die 310, and a plurality of electrically grounded contact structures 620 are physically and electrically connected between the peripheral portion of the die contact surface 612 and a plurality of module pads 920 at the mounting surface 914 of the module substrate 910. The system heat dissipation structure 130 is physically and thermally coupled to the heat dissipation surface 1414 of the power amplifier module 110, and more specifically, to the external thermal contact surface 1416 of the heat sink 610.

[0055] During operation of the RF system 100, the input RF signal is provided to the RF input terminal at the contact surface 1412 of the power amplifier module 110 (e.g., through the patterned conductive structure of the system substrate 120) via the system substrate 120. Figure 11 The input terminal 1102). The input RF signal passes through the module substrate 910 (and other amplifier components that may be mounted on the substrate 910, for example, Figure 11 The power distributor 1106 transmits the signal to the module pad 922 and the input pad 321 of the power transistor die 310. The input RF signal is then amplified by the power transistor(s) integrated within the power transistor die 310, and the amplified output RF signal is generated at the output pad 354, which is electrically coupled to the module pad 924. The amplified output RF signal is then transmitted through the module substrate 910 (and possibly other amplifier components connected to the substrate 910) to the RF output terminal (e.g., at the contact surface 1412 of the power amplifier module 110). Figure 11 (output terminal 1104).

[0056] As previously mentioned, the current-carrying terminal (e.g., the source terminal) of each power transistor integrated within the power transistor die 310 is electrically connected to system ground. Figure 1 In the embodiment shown, to establish this ground connection, the aforementioned current-carrying end (e.g., the source end) is electrically connected to a conductive layer 316 on the ground surface 312 of the power transistor die 310. As indicated by arrow 140, the conductive layer 316 then passes through a conductive and thermally conductive heat sink 610, a ground contact structure 620, module substrate pads 920, 921, system substrate pad 126, and other conductive structures of the system substrate 120 (which are ultimately electrically connected to the system ground, such as...). Figure 1 (As shown) is electrically connected to the system ground.

[0057] During operation, a significant amount of heat can be generated by the power transistor(s) within the power transistor die 310. As indicated by arrow 150, the heat generated by the power transistor(s) is transferred through heat sink 610 to heat dissipation structure 130, which effectively dissipates the heat to the ambient atmosphere. Therefore, heat sink 610 provides two functions: 1) transferring the heat generated by the power transistor die 310 to heat dissipation structure 130; and 2) electrically coupling the integrated power transistor(s) within the power transistor die 310 to system ground.

[0058] Figure 2 This refers to the manufacture of a power amplifier module according to an example embodiment (e.g., Figure 1 The power amplifier module 110) and the power amplifier module are assembled into the RF system (e.g., Figure 1 The flowchart illustrates a method in an RF system 100. The method may begin in blocks 202 and 204, which may be executed in any order or simultaneously. Referring first to block 202, one or more power transistor dies are provided, and contact structures are formed on pads exposed at the I / O surfaces of the dies(s). For illustrative purposes, Figure 3 This is a top view of a power transistor die assembly 300 according to an exemplary embodiment. The power transistor die assembly 300 includes a power transistor die 310 having contact structures 320, 334, 337, 345, 352, and 360 respectively formed on die pads 321, 333, 336, 344, 351, and 354. For enhanced understanding, Figure 3 Should be with Figure 4 and 5 View at the same time Figure 4 and 5 According to the example embodiment Figure 3 The power transistor die 310 is shown in the cross-sectional side views along lines 4-4 and 5-5, respectively. Figure 3-5 The coordinate axis 390 is provided to illustrate the orientation of each view. As used herein, the terms “die,” “integrated circuit die,” and “IC die” refer to a single, distinct semiconductor die (or semiconductor substrate) within which one or more circuit components (e.g., transistors, passive devices, etc.) are integrally formed and / or directly physically connected to create a monolithic structure.

[0059] The power transistor die 310 can be formed together with multiple other identical or different dies in a single semiconductor wafer. Figure 3-5The power transistor die 310 is shown as a single-cut unit, but those skilled in the art will understand that blocks 202 and 206 can be performed simultaneously for multiple dies, after which these dies are single-cut from the wafer from which the multiple dies were initially formed. In either case, at some point before block 208, the power transistor die 310 is single-cut from the wafer from which the power transistor die 310 was initially formed.

[0060] The power transistor die 310 includes a two-stage amplifier integrally formed in a single IC die. The die 310 has a substantially rectangular periphery, the periphery being defined by opposing input sides 302 and output sides 304 (e.g., in...). Figure 3 The bottom and top sides of the orientation are defined by the opposite left side 303 and right side 304 extending between the input and output sides. Figure 3 In the specific embodiment shown, the power transistor die 310 includes the following circuitry integrally and individually formed on and within the semiconductor die 310: an input pad 321, an input impedance matching network 322, a two-stage amplifier including a preamplifier transistor 330 and a final-stage amplifier transistor 340, an interstage impedance matching network 338, an output pad 354, and bias voltage pads 333, 336, 344, and 351. Essentially, the preamplifier FET 330 and the final-stage amplifier FET 340 are coupled in series between the input pad 321 and the output pad 354. The preamplifier FET 330 can be configured to apply a gain in the range of approximately 15 dB to the corresponding input RF signal. The final-stage amplifier FET 340 is significantly larger than the preamplifier FET 330 (e.g., at least twice as large to apply at least twice the gain) and can be configured to apply a gain in the range of approximately 15 dB to approximately 25 dB to the corresponding input RF signal.

[0061] As in Figure 4 As most clearly seen, the power transistor die 310 includes a base semiconductor substrate 308 and a plurality of stacked layers 313 on the top surface 311 of the base semiconductor substrate 308. In a specific example embodiment, the base semiconductor substrate 308 is a high-resistivity silicon substrate (e.g., a silicon substrate with a bulk resistivity in the range of about 1,000 ohms / cm to about 100,000 ohms / cm or greater). Alternatively, the base semiconductor substrate 308 may be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a bulk resistivity up to 10...). 8 (GaAs substrate with ohms / cm) or another suitable high resistivity substrate. In other alternative embodiments, the base semiconductor substrate 308 may be any of several variations of a GaN substrate or other III-V semiconductor substrate.

[0062] Multiple stacked layers 313 may include, for example, multiple interleaved dielectric layers, patterned conductive layers, and other conductive structures (e.g., conductive polysilicon structures). The top surface of stacked layers 313 corresponds to the top surface 314 of die 310. In stacked layers 312, portions of different patterned conductive layers and structures are electrically coupled to conductive vias (e.g., via 323). Additionally, conductive through-substrate vias (TSVs) (e.g., TSV 318) may provide a conductive path between the top surface 311 and bottom surface 312 of the base semiconductor substrate 308. TSVs may or may not be lined with a dielectric material that insulates the TSV from the base semiconductor substrate 308. According to an embodiment, a conductive layer 316 on the bottom surface 312 of the base semiconductor substrate 308 (corresponding to the bottom surface 312 of die 310) serves as a ground node for the power transistor die 310. According to an embodiment, the height 374 of the power transistor die 310 is in the range of about 75 micrometers to about 100 micrometers, but the die 310 may also be thinner or thicker.

[0063] As mentioned above, die 310 includes two power transistors arranged in series, namely a relatively low-power preamplifier transistor 330 and a relatively high-power final-stage amplifier transistor 340. For example, each of transistors 330 and 340 may be a field-effect transistor (FET), such as a laterally diffused metal-oxide-semiconductor (LDMOS) FET or a high electron mobility transistor (HEMT). The description herein refers to each transistor including a control terminal and two conductive terminals. For example, using the terminology associated with FETs, "control terminal" refers to the gate terminal of the transistor, and the first and second conductive terminals refer to the drain and source terminals of the transistor (or vice versa). Although the following description may use terminology commonly used in conjunction with FET devices, the various embodiments are not limited to implementations using FET devices, but are intended to also apply to implementations using bipolar junction transistor (BJT) devices or other suitable types of transistors.

[0064] Each transistor 330, 340 includes a gate terminal 332, 343 (or a control terminal), a drain terminal 335, 350 (or a first current-carrying terminal), and an unnumbered source terminal (or a second current-carrying terminal). In a specific embodiment, each transistor 330, 340 is an LDMOS FET, which includes an active region disposed between the gate terminal and the drain terminal. Each active region includes a plurality of elongated, parallel-aligned, and intersecting drain and source regions, wherein each drain and source region is a doped semiconductor region formed in the base semiconductor substrate 308. Due to their elongated shape, each set of adjacent drain and source regions, together with the associated gate structure, may be referred to as a "transistor finger," and each transistor 330, 340 includes a plurality of parallel transistor fingers (in the active region of the transistor) Figure 3(Used as vertical lines in the middle).

[0065] A variable conductive channel (and in some embodiments, a drain drift region) exists between adjacent source and drain regions. A conductive (e.g., polysilicon or metal) gate structure formed over the base semiconductor substrate 308 is coupled to each gate end 332, 343 and extends over the channel region from the gate ends 332, 343. Similarly, an additional conductive (e.g., polysilicon) drain structure formed over the base semiconductor substrate 308 is coupled to each drain end 335, 350 and extends over the drain region from the drain ends 335, 350. The source regions are electrically coupled to conductive (e.g., polysilicon or metal) source contacts, which in turn are coupled to conductive TSVs (e.g., TSVs). Figure 4 , 5 The conductive TSV (318) extends through the base semiconductor substrate 308 to connect with the conductive layer 316 on the bottom surface of the base semiconductor substrate 308. During operation, the voltage applied to the gate terminals 332, 343 modulates the conductivity of the variable conductive channel, thereby allowing current to flow between the source and drain regions (or ultimately between the conductive layer 316 and each drain terminal 335, 350).

[0066] Input pad 321 is coupled to the input terminal (e.g., gate 332) of preamplifier FET 330 via input impedance matching network 322. The output terminal (e.g., drain 335) of preamplifier FET 330 is electrically coupled to the input terminal (e.g., gate 343) of final stage amplifier FET 340 via interstage impedance matching network 338. The output terminal (e.g., drain 350 of final stage amplifier FET 340) is electrically coupled to output pad 354. In some embodiments, an output impedance matching network (not shown) may be coupled between the drain terminal 350 of final stage amplifier FET 340 and output pad 354. The source terminal of each of FETs 330, 340 is electrically coupled to a ground reference (e.g., using a ground reference). Figure 4 , 5 The TSV 318 passes through the base semiconductor substrate 308 to the bottom conductive layer 316. (As in...) Figure 5 As most clearly shown, adjacent transistor fingers (e.g., fingers 341 and 342) can be arranged in a mirror configuration with the shared drain terminal 350.

[0067] According to an embodiment, the gate bias voltage of each of the FETs 330, 340 is provided via gate bias pads 333, 344, respectively, and the drain bias voltage of each of the FETs 330, 340 is provided via drain bias pads 336, 351, respectively. In some embodiments, an integrated bias circuitry may be included between the bias pads 333, 336, 344, 351 and the respective gates 332, 343 and drains 335, 350 of the FETs 330, 340. In other embodiments, fewer bias pads 333, 336, 344, 351 may be included, and the integrated bias circuitry may include a resistor divider network configured to provide appropriate bias voltages from a fewer number of bias contact pads to the various gate terminals 332, 343 and drain terminals 335, 350, as will be discussed later. Figure 11 and 12 As will be discussed, two instances of transistor die 310 can be incorporated into a multi-die amplifier system, such as a Dougherty amplifier, to serve as a main amplifier and a peak amplifier. In this embodiment, to ensure proper operation of the Dougherty amplifier, the first transistor die used as the main amplifier (e.g., the first instance of die 310) is biased to operate in Class AB mode, and the second transistor die used as the peak amplifier (e.g., the second instance of die 310) can be biased to operate in Class C mode.

[0068] According to an embodiment, one or more contact structures 320, 334, 337, 345, 352, 360 are formed on or attached to each of pads 321, 333, 336, 344, 351, 354. As in Figure 4 Most clearly shown in the magnified view of the contact structures 360, each contact structure 320, 334, 337, 345, 352, 360 includes a rigid conductive post 361, which has a proximal end directly connected to the corresponding pad (e.g., pad 354) and a distal end at a height 362 above the surface of the pad to which the post 361 is connected. The height 362 is substantially at the intersection of the I / O surface 314 of the die 310 and the die-facing surface of the module substrate (e.g., [surface surface]). Figure 9 A support is defined between the surfaces 914 of the module substrate 910, to which the die 310 will later be attached. For example, the height 362 may be in the range of about 50 micrometers to about 100 micrometers (e.g., about 75 micrometers), but the height 362 may also be smaller or larger.

[0069] According to an embodiment, each pillar 361 is formed of a highly conductive material, such as copper or another suitable conductive metal. For example, a mask layer 380 may be applied to the I / O surface 314 of the die 310, and the mask layer 380 may subsequently be patterned to include openings in the exposed pads 321, 333, 336, 344, 351, 354, where conductive pillars (e.g., pillar 361) of each of the contact structures 320, 334, 337, 345, 352, 360 will be formed. The conductive pillars 361 may then be formed directly on each pad 321, 333, 336, 344, 351, 354, for example, by plating (e.g., constructing pillars 361 in a series of plating operations). Alternatively, the conductive post 361 can be formed separately and then attached to each pad 321, 333, 336, 344, 351, 354 with conductive adhesive, by sintering or brazing, or by using other attachment components.

[0070] exist Figure 3 In one embodiment, the conductive post 361 is cylindrical (i.e., has a circular cross-section), and the diameter of the conductive post 361 is in the range of about 60 micrometers to about 90 micrometers (e.g., about 75 micrometers), but the diameter may also be smaller or larger. In other embodiments, the conductive post may have a shape other than cylindrical, such as rod-shaped, cubic, or other shapes. For example, Figure 3 Ten cylindrical contact structures 360 coupled to pad 354 are shown. In an alternative embodiment, some or all of the cylindrical contact structures 360 may be replaced with one or more rod-shaped contact structures of height 362 extending along the length of pad 354 (along the y-axis). The cumulative cross-sectional area (in the Xy-plane) of the group of contact structures connected to any particular pad 321, 333, 336, 344, 351, 354 is selected to ensure that the group of contact structures can handle the current generated at each particular pad 321, 333, 336, 344, 351, 354.

[0071] According to an embodiment, conductive solder balls 363 (e.g., formed of tin-silver or other solder compositions) having a height 364 are disposed at the distal end of each conductive post 361 (i.e., the end of post 361 at a height 362 above the pad, opposite the proximal end). For example, the height 364 may range from about 20 micrometers to about 40 micrometers (e.g., about 30 micrometers), but the height 364 may also be smaller or larger. (The last sentence appears to be incomplete and possibly refers to a different embodiment.) Figure 10 In more detail, the conductive solder ball 363 will ultimately be bonded to the module substrate (e.g., Figure 10 The pad (e.g., substrate 910) Figure 10The pads 922, 924) are made into contact, and the solder balls 363 are reflow soldered to attach (and electrically connect) the contact structures 320, 334, 337, 345, 352, 360 (and thus the die 310) to the module substrate. Therefore, after the solder balls 363 are reflowed (i.e., the solder balls 363 are heated above their melting point and then allowed to cool and re-solder), their height will become significantly smaller, and the total height of the power transistor die assembly 300 can be considered equal to the height 374 of the die 310 plus the height 362 of the pillar 361.

[0072] See again Figure 2 Frame 204 includes one or more heat sink assemblies formed by providing one or more heat sinks (e.g., one heat sink for each die 310) and forming a ground contact structure on the thermal contact surface of each heat sink. For illustration, Figure 6 This is a top view of a heat sink assembly 600 according to an example embodiment, the heat sink assembly 600 including a heat sink 610 having a ground contact structure 620 formed on a thermal contact surface 612 of the heat sink 610. Figure 6 Should be with Figure 7 View at the same time Figure 7 According to the example embodiment Figure 6 A side view of the cross-section of the radiator 610 along line 7-7. Figure 6 and 7 The coordinate axis 490 is provided to clarify the orientation of each view.

[0073] According to an embodiment, the heat sink 610 is formed of a thermally and electrically conductive material. For example, the heat sink 610 may be formed of copper or another bulk conductive material. The heat sink has a thermally contacting surface 612, opposing surfaces 616, and sidewalls 618 extending between surfaces 612 and 616. According to an embodiment, the height 644 of the heat sink 610 is in the range of about 700 micrometers to about 800 micrometers, but the height 644 may also be smaller or larger.

[0074] At least two non-overlapping regions are defined at the thermal contact surface 612. These regions include an “inner” region 660 and at least one “peripheral” region 650, 651, 652, 653. As used herein, the “inner” region (e.g., region 660) is defined as a two-dimensional portion of the thermal contact surface 612 having a periphery (e.g., periphery 661) that is at least partially offset from the periphery (or sidewall 618) of the heat sink 610. In contrast, the “peripheral” regions (e.g., regions 650-653) are defined as two-dimensional portions of the thermal contact surface 612 having edges that coincide with the periphery (or sidewall 618) of the heat sink 610. Figure 6The most clearly shown figure shows that the entire periphery 661 of the inner region 660 is offset from the periphery of the heat sink 610, and four peripheral regions 650-653 are located between the periphery 661 of the inner region 660 and the periphery (or sidewall 618) of the heat sink 610. In other embodiments, a portion of the periphery 661 of the inner region 660 may coincide with one or more portions of the periphery of the heat sink 610, as long as at least one peripheral region 650-653 is located between the periphery 661 of the inner region 660 and at least one sidewall 618. For example, in Figure 6, the dashed line representing the periphery 661′ indicates the area occupied by an alternative configuration of the inner region 660′, which has two edges coinciding with two sidewalls 618 of the heat sink 610 (and therefore only two peripheral regions 650, 651 exist between the left and right sides and the left and right sidewalls 618 of the inner region 660′).

[0075] In any case, the size of the periphery 661 (or 661') of the inner region 660 is set to correspond to the periphery of the die (e.g., die 310) to be attached to the thermal contact surface 612, as will be discussed below in conjunction with frame 206 and Figure 8 A more detailed description follows. Additionally, the width of each of the peripheral regions 650 (i.e., the dimension between the perimeter of the inner region and the sidewall 618 of the heat sink 610) is sufficient to provide space for the grounding contact structure 620 of the heat sink 610 to be attached to each peripheral region 650. Therefore, in this embodiment, the width 640 and length 642 of the heat sink 610 are greater than the width and length of the inner region 660. In an alternative embodiment indicated by the perimeter 661′, the width 640 of the heat sink 610 is greater than the width of the inner region 660′, and the inner region 660′ and the length 642 of the heat sink 610 are substantially equal.

[0076] According to an embodiment, in some or all of the peripheral regions 650-653, one or more ground contact structures 620 are connected to the thermal contact surface 610 of the heat sink 610. According to an embodiment, each ground contact structure 620 includes a conductive solder ball (e.g., formed of tin-silver or other solder compositions). To connect the ground contact structure 620 to the thermal contact surface 610, a mask layer 630 is applied to the thermal contact surface 612 of the heat sink 610, and the mask layer 630 is patterned to include openings in a portion 652 of the peripheral region 650 of the thermal contact surface 612, wherein the ground contact structure 620 will be formed. The mask layer 630 also includes openings to expose an inner region 660 of the thermal contact surface 612. The ground contact structure 620 is formed directly on the portion 652 of the thermal contact surface 612 exposed in the peripheral region 650.

[0077] According to the embodiment, the height 622 and mass of each grounding contact structure 620 will ultimately be sufficient to bridge the thermal contact surface 612 with the module substrate (e.g., Figure 9 The distance between the top surfaces of the module substrate 910, as will be described in more detail later. According to an embodiment, this distance is substantially equal to the total height of the power transistor die assembly 300 (e.g., the sum of the die height 374 and the pillar height 362). In an alternative embodiment, the ground contact structure 620 may be formed of a rigid conductive pillar (e.g., a copper pillar) or other conductive structure having a height substantially equal to the total height of the power transistor die assembly 300.

[0078] See again Figure 2 Box 206 includes forming a die / heatsink assembly by attaching the ground surface of a power transistor die (e.g., die 310) to the thermal contact surface of a heatsink (e.g., heatsink 610). For example, Figure 8 This is a cross-sectional side view of a die / heatsink assembly 800 according to an example embodiment. The die / heatsink assembly 800 includes components thermally and electrically connected to a heatsink assembly (e.g., Figure 6 , 7 The power transistor die assembly (e.g., heat sink assembly 600) Figure 3-5 Component 300). In order to manufacture die / heat sink assembly 800, power transistor die assembly 300 and heat sink assembly 600 (to be respectively relative to) Figure 4 and 7 The orientation is flipped 180 degrees in the orientation. Figure 8 The two are shown in the diagram. More specifically, the ground surface 312 of the power transistor die assembly 300 (and more specifically, the conductive layer 316) is attached to the inner region of the thermal contact surface 612 of the heat sink assembly 600 (e.g., Figure 6 (internal area 660).

[0079] For example, the attachment of the power transistor die assembly 300 to the heat sink assembly 600 can be achieved by applying die attachment material 810 to the inner region 660 of the thermal contact surface 612 of the heat sink assembly 600 (and / or the ground surface 312 of the power transistor die assembly 300), and the ground surface 312 (and / or the conductive layer 316) can contact the die attachment material 810 and the heat sink assembly 600. For example, the die attachment material 810 may include a conductive and thermally conductive epoxy resin material, an uncured sintered material (e.g., silver sintered paste), solder, or other suitable die attachment material. The die attachment material 810 can then be cured, reflowed, or otherwise treated to achieve a strong mechanical and thermal bond between the heat sink assembly 600 and the power transistor die assembly 300.

[0080] like Figure 8 As shown, the power transistor die assembly 300 and the heat sink assembly 600 are attached together such that one or more ground contact structures 620 of the heat sink assembly 600 are positioned on the thermal contact surface 612 between the power transistor die 310 and the periphery (or one or more sidewalls 618) of the heat sink assembly 600. Furthermore, the ground contact structures 620 and the I / O contact structures (e.g., input contact structure 320 and output contact structure 360) of the power transistor die assembly 300 face the same direction (i.e., in...). Figure 8 (Direction downwards).

[0081] See again Figure 2 Box 208 includes connecting the die / heat sink assembly 800 to the module substrate (e.g., Figure 1 , 9 (Module substrate 910). To illustrate the connection process, Figure 9 and 10 This is a cross-sectional side view of a power amplifier module at two manufacturing stages 900 and 1000, respectively, according to an example embodiment. To connect these two module components, a die / heat sink assembly 800 is aligned above the module substrate 910. As previously combined... Figure 1 As discussed, the module substrate 910 includes a small multilayer PCB having a mounting surface 914, an opposing bottom surface 912, and a plurality of patterned conductive layers spaced apart by a dielectric material. Figure 9 In the example embodiment depicted, a conductive layer on mounting surface 914 is patterned to define a plurality of conductive pads, including pads 920, 922, and 924, which are exposed at mounting surface 914 through openings in solder mask layer 930. Pads 922 and 924 correspond to RF input signal pads and RF output signal pads, respectively, and pad 920 corresponds to a ground pad. To align the die / heat sink assembly 800 over module substrate 910, the input contact structure 320 of power transistor die 310 is aligned over RF input pad 922, the output contact structure 360 ​​of power transistor die 310 is aligned over RF output pad 924, and the ground contact structure 620 coupled to the thermal contact surface 612 of heat sink assembly 600 is aligned over ground pad 920. Although Figure 9 Or other contact structures of the power transistor die 310 not depicted in 10 (e.g., Figure 3 The contact structures 334, 337, 345, and 352 are also aligned with the corresponding pads on the module substrate 910. (As shown by...) Figure 9 As indicated by the vertical arrow in the image, the die / heat sink assembly 800 and the module substrate 910 are then placed together, as shown. Figure 10As shown, the solder balls at at least the ends of the I / O contact structures 320, 360 make contact with the corresponding RF input and output pads 922, 924 (e.g., Figure 4 Solder ball 363).

[0082] Then, a solder reflow process is performed, which includes heating the component to a temperature higher than the melting temperature of the solder balls at the ends of the ground contact structure 620 and the I / O contact structures 320, 360. After exceeding their melting temperature, the ground contact structure 620 adheres to the ground pad 920, and the solder balls at the ends of the I / O contact structures 320, 360 adhere to the RF input and output pads 922, 924, respectively. The component is then cooled to a temperature lower than the melting temperature of the solder balls at the ends of the ground contact structure 620 and the I / O contact structures 320, 360, and the ground contact structure 620 and the solder balls solidify to form mechanical and electrical bonds between the die / heat sink assembly 800 and the module substrate 910, as... Figure 10 As shown in manufacturing stage 1000.

[0083] Essentially, pads 920, 922, and 924 provide electrical connections between the module substrate 910, the power transistor die 310, and the heat sink 610. Each of the grounding pads 920 is electrically coupled via a conductive via, and in some embodiments, is electrically coupled via an intermediate patterned conductive layer to an additional pad 921 (e.g., a conductive pad) on or at the bottom surface 912 of the module substrate 910. Additionally, the RF input pad 922 is electrically coupled to the RF input trace 923, which may form a patterned portion of the internal patterned conductive layer of the module substrate 910, such as... Figure 10 As shown, a patterned portion of the patterned conductive layer at the mounting surface 914 of the module substrate 910 may be formed. Similarly, the RF output pad 924 is electrically coupled to the RF output trace 925, which may form a patterned portion of the internal patterned conductive layer of the module substrate 910, such as... Figure 10 As shown, a patterned portion of a patterned conductive layer may be formed at the mounting surface 914 of the module substrate 910.

[0084] In addition to the die / heat sink assembly 800, additional components of the power amplifier module may be coupled to the module substrate 910 to form an electrically complete power amplifier module. For example, the power amplifier embodied by the module may include a single-path power amplifier or a multi-path power amplifier (e.g., a push-pull amplifier, a Dougherty power amplifier, etc.). Figure 11 This is a top view of a Dougherty power amplifier module 1100 partially manufactured according to an exemplary embodiment, including two die / heat sink assemblies 800, 800' coupled to a mounting surface 914 of a module substrate 910. Figure 11Under the orientation, the mounting surface 914 of the module substrate 910 and the top surface of each die / heat sink assembly 800, 800' (e.g., Figure 10 The surface (616) is visible.

[0085] To increase understanding, Figure 11 Should be with Figure 12 View at the same time Figure 12 This is a simplified schematic diagram depicting the circuit components embodied in the Dougherty power amplifier module 1100, specifically the Dougherty power amplifier 1200. First, refer to... Figure 12 As shown in the schematic diagram, the Dougherty amplifier 1200 includes an input node 1202, an output node 1204, a power divider 1206 (or distributor), a main amplifier path 1220 (with a main amplifier 1230), a peak amplifier path 1221 (with a peak amplifier 1240), a combination node 1280, and an impedance transformer 1286. A load 1290 (e.g., an antenna) can be coupled to the output node 1204 of the amplifier 1200 to receive the amplified RF signal generated by the amplifier 1200.

[0086] During operation of the Dougherty amplifier 1200, the main amplifier 1230 is biased to operate in Class AB mode, and the peak amplifier 1240 is biased to operate in Class C mode. When the power of the input signal at node 1202 is lower than the turn-on threshold level of the peak amplifier 1240, the amplifier 1200 operates in low-power (or back-off) mode, where the main amplifier 1230 is the only amplifier supplying current to the load 1290. When the power of the input signal exceeds the threshold level of the peak amplifier 1240, the amplifier 1200 operates in high-power mode, where both the main amplifier 1230 and the peak amplifier 1240 supply current to the load 1290. At this time, the peak amplifier 1240 provides active load modulation at the combined node 1280, thereby allowing the current of the main amplifier 1230 to increase linearly and continuously.

[0087] Compare Figure 11 and 12The components are as follows: input node 1202 corresponds to pad (or solder pad) 1102, output node 1204 corresponds to pad (or solder pad) 1104, power divider 1206 corresponds to power divider 1106, combination node 1280 corresponds to point 1180, main amplifier path 1220 includes a first die / heatsink assembly 800 and other circuit components between power divider 1106 and point 1180, peak amplifier path 1221 includes a second die / heatsink assembly 800' and other circuit components between power divider 1106 and point 1180, and impedance transformer 1286 includes circuit components abstractly indicated by box 1186. According to an embodiment, each of the input pad 1102 and output pad 1104 is on the bottom surface (e.g., Figure 10 The surface 912 is exposed, which ultimately allows module 1100 to be surface-mounted to the system substrate (e.g., Figure 1 The system substrate 120), as will be discussed later. Not in Figure 11 The load 1290 depicted in the diagram will be coupled to the output pad 1104.

[0088] Power dividers 1106 and 1206 have power divider inputs 1107 and 1207, first power divider outputs 1108 and 1208, and second power divider outputs 1109 and 1209. For example, power divider 1106 may be a surface-mount component electrically and mechanically coupled to a mounting surface 914 of the module substrate 910. Alternatively, power divider 1106 may be implemented by various discrete components and / or conductors coupled to the mounting surface 914. In either case, power dividers 1106 and 1206 receive input RF signals via power divider inputs 1107 and 1207. During backoff mode operation, where only the main amplifier path 1220 supplies current to the load 1290, power dividers 1106 and 1206 are configured to supply the full input RF signal to the main amplifier path 1220 and not supply significant signal power to the peak amplifier path 1221. During full-power mode operation, where both the main amplifier path 1220 and the peak amplifier path 1221 supply current to the load 1290, power dividers 1106 and 1206 are configured to divide the input RF signal into a main portion and a peak portion of the input signal. The main input signal is provided to the main amplifier path 1220 at power divider outputs 1108 and 1208, and the peak input signal is provided to the peak amplifier path 1221 at power divider outputs 1109 and 1209. For example, power dividers 1106 and 1206 may distribute power equally, such that approximately half of the input signal power is provided to each path 1220 and 1221 (e.g., for a symmetrical Dougherty amplifier configuration). Alternatively, power dividers 1106 and 1206 may distribute power unequally (e.g., for an asymmetrical Dougherty amplifier configuration).

[0089] The divided signals generated by power dividers 1106 and 1206 are amplified separately along the main amplifier path 1220 and the peak amplifier path 1221. The main amplifier path 1220 includes an input matching network (MNm) 1210, a main amplifier 1230, an output matching network (MNm) 1260, and a phase delay and impedance inverter circuit 1284, all of which are electrically coupled in series between the first power divider outputs 1108 and 1208 and combination nodes 1180 and 1280. The main amplifier 1230 is implemented in the first die / heatsink assembly 800 (…). Figure 11 (See also) Figure 10For example, the power transistor die 310 of the first die / heat sink assembly 800 substantially corresponds to the main amplifier 1230, wherein the main amplifier input signal is received via trace 923 and pad 922, and the main amplifier amplified output signal is generated at pad 924 and trace 925. The main amplifier input MNm 1210 and output MNm 1260 may each be implemented within the power transistor die 310 of the assembly 800 and / or using components (not shown) coupled to the module substrate 910. Finally, the phase delay and impedance inverter circuit 1284 may be implemented at least partially by a conductive trace 1184 on or within the module substrate 910, the conductive trace 1184 having a first end coupled to the output pad 924 of the assembly 800 and a second end coupled to the combination nodes 1180, 1280. In some embodiments, the main amplification path 1220 may also include additional circuitry (not shown), such as harmonic termination circuitry and / or baseband termination circuitry.

[0090] The peak amplification path 1221 includes a phase delay circuit 1282, an input matching network (MNp) 1211, a peak amplifier 1240, and an output matching network (MNp) 1261, all of which are electrically coupled in series between the second power divider outputs 1109, 1209 and combination nodes 1180, 1280. The peak amplifier 1240 is implemented in the second die / heatsink assembly 800'. Figure 11 (See again) Figure 10 The power transistor die 310 of the second die / heat sink assembly 800' essentially corresponds to the peak amplifier 1240, wherein the peak amplifier input signal passes through trace 923 (in Figure 11 The signal is received at pad 923' and pad 922, and the output signal amplified by the main amplifier is generated at pad 924 and trace 925. The main amplifier input MNm 1210 and output MNm 1260 may each be implemented within the power transistor die 310 of component 800 and / or using components (not shown) coupled to module substrate 910. Finally, phase delay and impedance inverter circuit 1284 may be implemented at least partially by conductive trace 1184 on or within module substrate 910, said conductive trace 1184 having a first end coupled to output pad 924 of component 800 and a second end coupled to combination nodes 1180, 1280. In some embodiments, peak amplification path 1221 may also include additional circuitry (not shown), such as harmonic termination circuitry and / or baseband termination circuitry.

[0091] For proper Dougherty amplifier operation, when the main amplifier 1230 or the peak amplifier 1240 amplifies each signal, the signals amplified along the main amplifier path 1220 and the peak amplifier path 1221 are 90 degrees out of phase with each other. Figure 12The diagram illustrates a "non-inverting" Dougherty amplifier, in which phase delay circuits or elements 1182, 1282 (at the amplifier's center operating frequency f0) apply a 90-degree phase delay to the input signal on peak path 1221, which is then amplified by peak amplifier 1240. To ensure that the amplified signals are combined in phase at combination nodes 1180, 1280, phase delay and impedance inverter circuits 1184, 1284 along main path 1220 apply a 90-degree phase delay to the amplified output signal of autonomous amplifier 1230. In an alternative embodiment, the Dougherty amplifier may be configured as an "inverting" Dougherty amplifier, wherein the input-side 90-degree phase delay circuitry or elements 1182, 1282 are implemented at the input to the main amplifier 1230, rather than at the input to the peak amplifier 1240, and the output-side phase delay and impedance inverter circuitry 1184, 1284 are implemented between the output of the peak amplifier 1240 and the combination node 1280, rather than between the output of the main amplifier 1230 and the combination node 1280.

[0092] As mentioned above, during the operation of the Doherty amplifier 1200, the main amplifier 1230 is biased to operate in Class AB mode, and the peak amplifier 1240 is biased to operate in Class C mode. Figure 11 In the physical implementation, an appropriate bias voltage is provided to the amplifier die 310 of the die / heatsink assembly 800, 800'. Figure 10 Each amplifier die contains a power transistor. For example, see again... Figure 3 The gate bias voltage can be provided to the gate terminals 332 and 343 of transistors 330 and 340 through gate bias voltage pads 333 and 344 and contact structures 334 and 345, respectively. Similarly, the drain bias voltage can be provided to the drain terminals 335 and 354 of transistors 330 and 340 through drain bias voltage pads 336 and 351 and contact structures 337 and 352, respectively. See again Figure 11 To provide an appropriate bias voltage to the main amplifier implemented in the die / heat sink assembly 800, the module substrate 910 may include main amplifier bias voltage pads 1134, 1137, 1145, 1152 (e.g., exposed at the bottom surface of the module substrate 910) and various conductive structures to transfer the gate bias voltage and drain bias voltage to the bias voltage contact structure (e.g., Figure 3The contact structures 334, 337, 345, and 352. Similarly, in order to provide an appropriate bias voltage to the peak amplifier implemented in the die / heat sink assembly 800', the module substrate 910 may include peak amplifier bias voltage pads 1135, 1138, 1146, and 1153 (e.g., exposed at the bottom surface of the module substrate 910) and various conductive structures to transfer the gate bias voltage and drain bias voltage to the bias voltage contact structures (e.g., contact structures 334, 337, 345, and 352). Figure 3 Contact structures 334, 337, 345, and 352.

[0093] Those skilled in the art will understand that the amplifier embodiments described herein can be used with amplifier topologies other than the Dougherty amplifier topology. Although such alternatives are not discussed in detail herein, embodiments incorporating such modifications are contemplated within the scope of the subject matter of this invention.

[0094] According to the embodiment, the power amplifier module (e.g., Figure 11 The manufacturing of module 1100, such as Figure 13 and 14 As shown, Figure 13 and 14 It is in the two late-stage manufacturing phases, 1300 and 1400. Figure 10 A cross-sectional side view of the power amplifier module. See again. Figure 2 In frame 210, one or more die / heat sink assemblies (e.g., [missing information]) coupled to mounting surface 914 of module substrate 910 are encapsulated using a non-conductive encapsulation material 1310 (e.g., a plastic encapsulation). Figure 10 , 11 Components 800, 800', such as Figure 13 As shown in the diagram. Encapsulation material 1310 encapsulates the entire die / heatsink assembly (including surface 616 of heatsink 610) and at least a portion of mounting surface 914 of module substrate 910. In block 212, and as... Figure 14 As shown, a portion of the encapsulating material 1310 is removed to create an external thermal contact surface 1416 for each heat sink 610. In some embodiments, the external thermal contact surface 1416 may be adjacent to the original heat sink surface 616. Figure 10The same applies. In other embodiments, a portion of the heat sink 610 may be removed during an encapsulation removal process (e.g., using a mechanical or chemical removal process) to create an external thermal contact surface 1416. Ultimately, the encapsulation material 1310 covers at least a portion of the mounting surface 914 of the module substrate 910, the power transistor die 310, and the sidewall 618 of the heat sink 610. At this stage, the external thermal contact surface 1416 is coplanar with the heat dissipation surface 1414 of the power amplifier module, and the contact surface 912 of the module substrate 910 corresponds to the contact surface 1412 of the power amplifier module. Thus, the power amplifier module 110 is completed.

[0095] See again in box 214. Figure 1 The RF system 100 is completed by electrically and mechanically coupling the power amplifier module 110 to the system substrate 120, and thermally and mechanically coupling the heat dissipation structure 130 to the power amplifier module 110. To couple the power amplifier module 110 to the system substrate 120, a module pad (e.g., pad 921) exposed at the contact surface 1412 of the power amplifier module 110 is aligned with a corresponding system substrate pad (e.g., pad 126) exposed at the mounting surface 124 of the system substrate 120. The power amplifier module 110 and the system substrate 120 are placed together, and the module and substrate pads (e.g., pads 921, 126) are electrically and mechanically connected to conductive solder or epoxy resin 128. Although not in... Figure 1 It is depicted in the text, but will be shown in the RF I / O pad (e.g., Figure 11 The pads 1102 and 1104) and the bias pads of the power amplifier module 110 (e.g., Figure 11 The pads 1134, 1135, 1137, 1138, 1145, 1146, 1152, and 1153 are similarly connected to the corresponding RF I / O pads and bias pads at the mounting surface 124 of the system substrate 120.

[0096] To couple the heat dissipation structure 130 to the power amplifier module 110, a thermally conductive material 132 (e.g., thermal silicone) can be applied to the external thermal contact surface 1416 of the heat sink 610 (and / or on the surface of the heat dissipation structure 130), and the heat dissipation structure 130 can be brought into contact with the heat sink 610 and the thermal surface 1414. The heat dissipation structure 130 can then be clamped, screwed, or otherwise secured in place. The RF system 100 is then formed.

[0097] Furthermore, during the operation of the RF system 100, a significant amount of heat energy can be generated by the power transistor(s) within the power transistor die 310. As indicated by arrow 150, the heat energy generated by the power transistor(s) is transferred through the heat sink 610 to the heat dissipation structure 130, which effectively dissipates the heat to the ambient atmosphere. Additionally, as indicated by arrow 140, the conductive layer 316 on the ground surface 312 of the power transistor die 310 is connected to the system ground via the heat sink 610, ground contact structure 620, module substrate pads 920, 921 and through-substrate conductors, system substrate pad 126, and other conductive structures of the system substrate 120 (which are ultimately electrically connected to the system ground, such as...). Figure 1 (As shown in the diagram) and electrically connected to the system ground. Therefore, the heat sink 610 provides two functions: 1) to transfer the heat generated by the power transistor die 310 to the heat dissipation structure 130; and 2) to electrically couple the (multiple) integrated power transistors within the power transistor die 310 to the system ground.

[0098] An embodiment of a power amplifier module includes a module substrate, a first power transistor die, a first heat sink, and an electrically grounded contact structure. The module substrate has a mounting surface, a first module pad exposed at the mounting surface, a second module pad exposed at the mounting surface, and a third module pad exposed at the mounting surface. The first power transistor die has an input / output (I / O) surface, a ground surface opposite the I / O surface, an input pad exposed at the I / O surface, an output pad exposed at the I / O surface, and an integrated power transistor having a control terminal electrically coupled to the input pad, a first current-carrying terminal electrically coupled to the output pad, and a second current-carrying terminal electrically coupled to the ground surface. The first power transistor die is coupled to the module substrate with the I / O surface facing the mounting surface, the input pad is electrically coupled to the first module pad, and the output pad is electrically coupled to the second module pad. The first heat sink has a first thermal contact surface physically and electrically coupled to the ground surface of the first power transistor die, and the first thermal contact surface has a peripheral portion extending beyond the ground surface of the first power transistor die. The electrically grounding contact structure is connected between the peripheral portion of the first thermal contact surface and the third module pad of the module substrate.

[0099] According to another embodiment, the power amplifier module further includes: an input signal contact electrically coupled to the first module pad; an output signal contact electrically coupled to the second module pad; and a system ground contact electrically coupled to the third module pad. According to yet another embodiment, the power amplifier module further includes: an input contact structure connected between the input pad of the first power transistor die and the first module pad; and an output contact structure connected between the output pad of the first power transistor die and the second module pad. According to yet another embodiment, the input contact structure and the output contact structure each include one or more components selected from conductive pillars and solder. According to yet another embodiment, the electrically grounded contact structure includes one or more components selected from conductive pillars and solder. According to yet another embodiment, the first heat sink includes a thermally and electrically conductive material selected from copper or another bulk conductive material.

[0100] According to yet another embodiment, the integrated power transistor is a field-effect transistor (FET), the control terminal is the gate terminal of the FET, the first current-carrying terminal is the drain terminal of the FET, and the second current-carrying terminal is the source terminal of the FET. According to yet another embodiment, the first power transistor die includes a semiconductor substrate and a stacked structure. The semiconductor substrate has a first surface and a second surface opposite to the first surface, wherein the second surface of the semiconductor substrate corresponds to the ground surface of the first power transistor die. The stacked structure is formed on the first surface of the semiconductor substrate, and the exposed surface of the stacked structure corresponds to the I / O surface of the first power transistor die. According to yet another embodiment, the first power transistor die further includes: a conductive layer on the second surface of the semiconductor substrate; and a plurality of through-substrate vias, wherein each of the through-substrate vias extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, and wherein the second current-carrying terminal of the integrated power transistor is electrically coupled to the conductive layer through the plurality of through-substrate vias.

[0101] According to yet another embodiment, the power amplifier module further includes an encapsulation material covering the mounting surface of the module substrate, the first power transistor die, and the sidewall of the first heat sink. According to yet another embodiment, the first heat sink further includes a second thermal contact surface opposite the first thermal contact surface, and the surface of the encapsulation material is coplanar with the second thermal contact surface.

[0102] According to yet another embodiment, the power amplifier module further includes a heat dissipation structure coupled to the second thermal contact surface.

[0103] According to yet another embodiment, the power amplifier module further includes: a second power transistor die coupled to the mounting surface; and a second heat sink physically and electrically coupled to the second power transistor die, wherein the first power transistor die corresponds to the main amplifier of the Dougherty power amplifier, and the second power transistor die corresponds to the peak amplifier of the Dougherty power amplifier.

[0104] An embodiment of a method for manufacturing a power amplifier module includes coupling a ground surface of a power transistor die to a first portion of a first thermal contact surface of a heat sink, wherein the power transistor die has an input / output (I / O) surface, the ground surface opposite the I / O surface, an input pad exposed at the I / O surface, an output pad exposed at the I / O surface, and an integrated power transistor having a control terminal electrically coupled to the input pad, a first current-carrying terminal electrically coupled to the output pad, and a second current-carrying terminal electrically coupled to the ground surface. The method further includes connecting the power transistor die to a mounting surface of a module substrate, the module substrate including a first module pad, a second module pad, and a third module pad exposed at the mounting surface, wherein the power transistor die is connected to the mounting surface of the module substrate such that the input pad is connected to the first module pad and the output pad is connected to the second module pad. The method further includes connecting an electrically grounded contact structure between a peripheral portion of the first thermal contact surface of the heat sink and the third module pad.

[0105] According to another embodiment, the method of manufacturing the power amplifier module further includes electrically connecting the third module pad to a ground reference. According to yet another embodiment, the method further includes encapsulating the heat sink, the power transistor die, and the module substrate to form the power amplifier module.

[0106] According to yet another embodiment, connecting the power transistor die to the mounting surface of the module substrate includes: coupling a first contact structure to the input pad; coupling a second contact structure to the output pad; aligning the first and second contact structures with the first and second module pads; and reflowing solder to connect the first contact structure to the first module pad and the second contact structure to the second module pad. According to yet another embodiment, each of the first and second contact structures includes a rigid conductive post. According to yet another embodiment, the electrically grounded contact structure includes solder. According to yet another embodiment, the electrically grounded contact structure includes a rigid conductive post.

[0107] The foregoing specific embodiments are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, one should not be bound by any expressed or implied theory presented in the foregoing technical field, background art, or specific embodiments.

[0108] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of the subject matter. Furthermore, certain terms may be used herein for reference only, and therefore these terms are not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0109] As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes can be implemented using a single physical element (and although received or output at a common node, two or more signals can still be multiplexed, modulated, or distinguished).

[0110] The foregoing description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly connected to) another element, and not necessarily mechanically engaged. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly connected to) another element electrically or otherwise, and not necessarily mechanically engaged. Therefore, while the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0111] While at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed descriptions will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. A power amplifier module, characterized in that, include: A module substrate having a mounting surface, a first module pad exposed at the mounting surface, a second module pad exposed at the mounting surface, and a third module pad exposed at the mounting surface; A first power transistor die has an input / output surface, a ground surface opposite to the input / output surface, an input pad exposed at the input / output surface, an output pad exposed at the input / output surface, and an integrated power transistor. The integrated power transistor has a control terminal electrically coupled to the input pad, a first current-carrying terminal electrically coupled to the output pad, and a second current-carrying terminal electrically coupled to the ground surface. The first power transistor die is coupled to the module substrate and the input / output surface faces the mounting surface. The input pad is electrically coupled to the first module pad, and the output pad is electrically coupled to the second module pad. A first heat sink has a first thermal contact surface that is physically and electrically coupled to the ground surface of the first power transistor die, wherein the first thermal contact surface has a peripheral portion that extends beyond the ground surface of the first power transistor die. Encapsulation material covering the mounting surface of the module substrate, the first power transistor die, and the sidewall of the first heat sink; as well as An electrically grounding contact structure is provided, wherein the electrically grounding contact structure is connected between the peripheral portion of the first thermal contact surface and the third module pad of the module substrate. The first heat sink further includes a second thermal contact surface opposite to the first thermal contact surface, and the surface of the encapsulating material is coplanar with the second thermal contact surface.

2. The power amplifier module according to claim 1, characterized in that, The module substrate further includes: An input signal contact, which is electrically coupled to the first module pad; Output signal contacts, said output signal contacts being electrically coupled to the second module pad; and The system grounding contact is electrically coupled to the third module pad.

3. The power amplifier module according to claim 1, characterized in that, In addition, including: An input contact structure is provided, wherein the input contact structure is connected between the input pad of the first power transistor die and the first module pad; as well as An output contact structure is provided, which is connected between the output pad of the first power transistor die and the second module pad.

4. The power amplifier module according to claim 3, characterized in that, The input contact structure and the output contact structure each include one or more components selected from conductive pillars and solder.

5. The power amplifier module according to claim 1, characterized in that, The electrical grounding contact structure includes one or more components selected from conductive posts and solder.

6. The power amplifier module according to claim 1, characterized in that, The first heat sink comprises a thermally and electrically conductive material selected from copper.

7. The power amplifier module according to claim 1, characterized in that, The integrated power transistor is a field-effect transistor, the control terminal is the gate terminal of the field-effect transistor, the first current-carrying terminal is the drain terminal of the field-effect transistor, and the second current-carrying terminal is the source terminal of the field-effect transistor.

8. The power amplifier module according to claim 1, characterized in that, The first power transistor die includes: A semiconductor substrate having a first surface and a second surface opposite to the first surface, wherein the second surface of the semiconductor substrate corresponds to the ground surface of the first power transistor die; and A stacked structure is formed on the first surface of the semiconductor substrate, wherein the exposed surface of the stacked structure corresponds to the input / output surface of the first power transistor die.

9. The power amplifier module according to claim 8, characterized in that, The first power transistor die further includes: A conductive layer, said conductive layer on the second surface of the semiconductor substrate; and A plurality of through-substrate vias, wherein each of the through-substrate vias extends from a first surface of the semiconductor substrate to a second surface of the semiconductor substrate, and wherein the second current-carrying terminal of the integrated power transistor is electrically coupled to the conductive layer through the plurality of through-substrate vias.

10. A method for manufacturing a power amplifier module, characterized in that, The method includes: A ground surface of a power transistor die is coupled to a first portion of a first thermal contact surface of a heat sink, wherein the power transistor die has an input / output surface, a ground surface opposite to the input / output surface, an input pad exposed at the input / output surface, an output pad exposed at the input / output surface, and an integrated power transistor having a control terminal electrically coupled to the input pad, a first current-carrying terminal electrically coupled to the output pad, and a second current-carrying terminal electrically coupled to the ground surface; The power transistor die is connected to the mounting surface of a module substrate, the module substrate including a first module pad, a second module pad, and a third module pad exposed at the mounting surface, wherein the power transistor die is connected to the mounting surface of the module substrate such that the input pad is connected to the first module pad and the output pad is connected to the second module pad; The electrical grounding contact structure is connected between the outer portion of the first thermal contact surface of the heat sink and the third module pad; and The mounting surface of the module substrate, the power transistor die, and the sidewall of the heat sink are encapsulated with encapsulation material; The heat sink further includes a second thermal contact surface opposite to the first thermal contact surface, and the surface of the encapsulating material is coplanar with the second thermal contact surface.

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