Communication system, gate driver system and method for gate driver communication

Abstract

A communication system, gate driver system, and method for gate driver communication are disclosed. The communication system includes a power generator configured to generate a modulated power supply in accordance with a data transmission; a light emitting diode (LED) emulator including an emulator input coupled to the power generator and an emulator output configured to output a sensed voltage, wherein the emulator input is configured to receive a forward current derived from the modulated power supply and convert the forward current to the sensed voltage; a voltage comparator coupled to the emulator output and configured to receive the sensed voltage and convert the sensed voltage to a modulated output signal based on a communication voltage threshold; and a transmitter coupled to the comparator output and configured to receive the modulated output signal and generate a communication signal in accordance with the data transmission based on the modulated output signal.

Description

Technical Field

[0001] This invention generally relates to the field of electronics, and more particularly to an isolation barrier communication system in a package for isolated gate driver communication. Background Technology

[0002] A high-voltage (HV) gate driver circuit may include a low-voltage (LV) gate driver for driving a low-side transistor switch and an HV gate driver for driving a high-side transistor switch. The LV gate driver is arranged in the low-voltage domain, while the HV gate driver is arranged in the high-voltage domain. In practice, the gate driver also includes a termination region that isolates the high-voltage domain from the low-voltage domain and may be referred to as an isolation termination region. Therefore, the termination region provides a high-voltage isolation barrier between the two voltage domains.

[0003] Typically, the HV gate driver receives control signals and possibly other communication signals from a circuit system located in the low-voltage domain. These signals are then transmitted from the low-voltage domain to the high-voltage domain via a termination region. A light-emitting diode (LED) optocoupler can be used to transmit signals from the low-voltage domain to the high-voltage domain. Specifically, a modulated current is transmitted through the LED located in the low-voltage domain. The amplitude of the current is modulated based on the data to be transmitted. The LED then transmits the modulated light as a communication signal based on the modulated current. A receiver, including a phototransistor or demodulator, is located in the high-voltage domain to receive the light-modulated communication signal. Thus, an LED optocoupler transmits electrical signals between two isolated circuits using light.

[0004] LED optocoupler simulators can also be used to transmit signals between two isolated circuits. Instead of using an LED, an LED optocoupler simulator "simulates" the input behavior of the optocoupler LED. However, these solutions are still under development. Summary of the Invention

[0005] One or more embodiments provide a communication system comprising: a power generator configured to generate a modulated power supply according to data transmission; a light-emitting diode (LED) emulator including an emulator input coupled to the power generator and an emulator output configured to output a sensed voltage, wherein the emulator input is configured to receive a forward current obtained according to the modulated power supply, wherein the LED emulator is configured to convert the forward current into a sensed voltage; a voltage comparator including a comparator input coupled to the emulator output and a comparator output, wherein the voltage comparator is configured to receive the sensed voltage and convert the sensed voltage into a modulated output signal based on a communication voltage threshold, wherein the voltage comparator generates a modulated output signal having a first value under a first condition that the sensed voltage is equal to or greater than the communication voltage threshold, and generates a modulated output signal having a second value under a second condition that the sensed voltage is less than the communication voltage threshold; and a transmitter coupled to the comparator output and configured to receive the modulated output signal and generate a communication signal based on the modulated output signal according to data transmission.

[0006] One or more embodiments also provide a gate driver system comprising: a first region operating in a first voltage domain; a second region operating in a second voltage domain lower than the first voltage domain; a termination region electrically isolating the first region from the second region; a gate driver disposed in the first region and configured to drive a transistor; and a communication system configured to transmit communication signals across the termination region. The communication system includes: a power generator configured to generate a modulated power supply according to data transmission; a light-emitting diode (LED) emulator including an emulator input coupled to the power generator and an emulator output configured to output a sensed voltage, wherein the emulator input is configured to receive a forward current obtained according to the modulated power supply, wherein the LED emulator is configured to convert the forward current into a sensed voltage; a voltage comparator including a comparator input coupled to the emulator output and a comparator output, wherein the voltage comparator is configured to receive the sensed voltage and convert the sensed voltage into a modulated output signal based on a communication voltage threshold, wherein the voltage comparator generates a modulated output signal having a first value under a first condition that the sensed voltage is equal to or greater than the communication voltage threshold, and generates a modulated output signal having a second value under a second condition that the sensed voltage is less than the communication voltage threshold; a transmitter coupled to the comparator output and configured to receive the modulated output signal and generate a communication signal based on the modulated output signal according to data transmission; and a receiver configured to receive the communication signal and demodulate the communication signal.

[0007] One or more embodiments also provide a method for gate driver communication, the method comprising: generating a modulated power supply to generate a forward current based on data transmission; providing the forward current to an emulator input of a light-emitting diode (LED) emulator; converting the forward current into a sense voltage generated at an emulator output of the LED emulator by the LED emulator; converting the sense voltage into a modulated output signal by a voltage comparator based on a communication voltage threshold, wherein the modulated output signal has a first value under a first condition that the sense voltage is equal to or greater than the communication voltage threshold, and has a second value under a second condition that the sense voltage is less than the communication voltage threshold; and generating a communication signal by a transmitter based on the modulated output signal according to data transmission. Attached Figure Description

[0008] The embodiments are described herein with reference to the accompanying drawings.

[0009] Figure 1 This is a schematic block diagram illustrating a control actuator for a power semiconductor device according to one or more embodiments;

[0010] Figure 2 It is a schematic block diagram of a power module according to one or more embodiments;

[0011] Figure 3 This illustration shows a coreless transformer (CT) communication system implemented in a gate driver package for isolated gate driver communication, according to one or more embodiments; and

[0012] Figure 4 Various signal diagrams are shown according to one or more implementations of a communication protocol. Detailed Implementation

[0013] In the following sections, details are set forth to provide a more thorough description of exemplary embodiments. However, it will be apparent to those skilled in the art that embodiments may be practiced without these specific details. In other instances, well-known structures and apparatuses are shown in block diagrams or schematic representations rather than in detail to avoid obscuring the embodiments. Furthermore, unless otherwise specifically indicated, features of the different embodiments described below may be combined with each other.

[0014] Furthermore, in the following description, equivalent or similar elements, or elements having equivalent or similar functions, are indicated by equivalent or similar reference numerals. Since identical or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of elements with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals are interchangeable.

[0015] In this regard, directional terms such as "top," "bottom," "below," "above," "front," "back," "rear," "front part," and "tail" may be used with reference to the orientation of the described drawings. Because components of an embodiment can be positioned in multiple different orientations, directional terms are used for illustrative purposes. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Therefore, the following detailed description should not be construed as limiting. The directional terms used in the claims help define the spatial or positional relationship between one element and another element or feature, and are not limited to a specific orientation.

[0016] It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be interpreted in the same way (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0017] In the embodiments described herein or shown in the accompanying drawings, any direct electrical connection or coupling—i.e., any connection or coupling without additional intermediate elements—can also be achieved through an indirect connection or coupling—i.e., a connection or coupling with one or more additional intermediate elements—as long as the general purpose of the connection or coupling, such as transmitting a signal or transmitting information, is substantially maintained. Features from different embodiments can be combined to form other embodiments. For example, unless otherwise stated, variations or modifications described with respect to one embodiment can also be applied to other embodiments.

[0018] Without departing from aspects of the embodiments described herein, the terms "substantially" and "approximately" may be used herein to interpret small manufacturing tolerances (e.g., within 5%) that are considered industrially acceptable. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of that approximate resistance value.

[0019] In this disclosure, the use of ordinal expressions such as "first," "second," etc., can modify various elements. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and / or importance of elements. The above expressions are used only for the purpose of distinguishing elements from other elements. For example, a first box and a second box indicate different boxes, but both a first box and a second box are boxes. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0020] One or more aspects of this disclosure can be implemented as a non-transitory computer-readable recording medium on which a program for implementing a method / algorithm for an instruction processor to execute is recorded. Therefore, the non-transitory computer-readable recording medium may have electrically readable control signals stored thereon that cooperate (or are capable of cooperating with) a programmable computer system to cause execution of the various methods / algorithms. The non-transitory computer-readable recording medium can be, for example, a CD-ROM, DVD, Blu-ray disc, RAM, ROM, PROM, EPROM, EEPROM, FLASH memory, or electronic storage device.

[0021] Each of the elements in this disclosure can be configured by implementing dedicated hardware or software programs on memory that control a processor to perform the functions of any component or combination thereof. Any component may be implemented as a central processing unit (CPU) or other processor that reads from and executes software programs from a recording medium such as a hard disk or semiconductor memory device. For example, instructions may be executed by one or more processors—such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic unit systems.

[0022] Therefore, as used herein, the term "processor" refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. A controller including hardware may also perform one or more of the techniques of this disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its receiving, analyzing, and controlling functions, which may also include correction functions. Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various techniques described in this disclosure.

[0023] In motor vehicles, consumer, and industrial applications, many functions of modern devices, such as converting electrical energy and driving motors, rely on power semiconductor devices. For example, to name just a few, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in a wide range of applications, including but not limited to switches in power supplies and power converters.

[0024] Power semiconductor devices typically include semiconductor structures configured to conduct load current along a load current path between two load terminal structures or load electrodes (e.g., source / emitter and drain / collector) of the device. Furthermore, the load current path can be controlled by means of a control electrode, sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to one of a conducting state and a blocking state. The control signal can be a voltage signal or a current signal with a controlled value.

[0025] A power transistor (also known as a power switch or transistor switch) is a power semiconductor device that can be used to drive load current. For example, an IGBT is turned on or off by activating and deactivating its gate terminal. Applying a positive input voltage signal across the gate and emitter will keep the device in its "on" state, while making the input gate signal zero or slightly negative will cause it to be "off". There are turn-on and turn-off processes for turning a power transistor on and off.

[0026] During the conduction process, a gate driver integrated circuit (IC) can be used to provide (supply) a gate current (i.e., a turn-on current) to the gate of the power transistor to charge the gate to a sufficient voltage to turn the device on. Specifically, the current Io+ is the gate driver output current used to boost (i.e., charge) the gate of the power transistor during the turn-on transient. Therefore, the current Io+ is used to turn on the power transistor.

[0027] In contrast, during the turn-off process, the gate driver IC is used to draw (absorb) gate current (i.e., turn-off current) from the gate of the power transistor to fully discharge the gate for use in the turn-off mechanism. The current Io- is the gate driver output current used to discharge the gate of the power transistor during the turn-off transient. Therefore, Io- is used to turn off the power transistor.

[0028] According to the pulse width modulation (PWM) scheme, a voltage pulse can be output from the gate driver IC as a control signal. Therefore, during the PWM cycle used to control the power transistor, the control signal can be switched between the on-state voltage level and the off-state voltage level. This, in turn, charges and discharges the gate voltage to turn the power transistor on and off, respectively.

[0029] Specifically, the gate of the power transistor is a capacitive load, and the initial currents (i.e., gate pull-in current and gate sink current) are specified when a switching event is initiated. During the turn-off event, the gate current decreases after a short time (smaller than the PWM cycle) and reaches zero when the gate reaches 0V. During the turn-on event, the gate current decreases after a short time (smaller than the PWM cycle) and reaches zero when the gate reaches the high-side supply level.

[0030] Transistors can include insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., Si MOSFETs or SiC MOSFETs). While IGBTs may be used as examples in the embodiments described below, it should be understood that MOSFETs can be used to replace IGBTs, and vice versa. In this case, in any of the examples described herein, when an IGBT is replaced with a MOSFET, the drain of the MOSFET can replace the collector of the IGBT, the source of the MOSFET can replace the emitter of the IGBT, and the drain-source voltage VDS of the MOSFET can replace the collector-emitter voltage VCE of the IGBT. Therefore, any IGBT module can be replaced with a MOSFET module, and vice versa.

[0031] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used within power converters or power supplies. Therefore, in these embodiments, the power semiconductor device can be configured to carry load current to be supplied to a load and / or load current supplied by a power supply, respectively. For example, the semiconductor device may include one or more power semiconductor units such as monolithic integrated diode units and / or monolithic integrated transistor units. Such diode units and / or such transistor units may be integrated within a power semiconductor module.

[0032] Power semiconductor devices, including transistors appropriately connected to form a half-bridge, are commonly used in power electronics. For example, a half-bridge can be used to drive a motor or a switch-mode power supply.

[0033] For example, multiphase inverters are configured to provide multiphase power by supplying multiphase loads, such as three-phase motors. Three-phase power, for instance, involves three symmetrical sine waves, each 120 electrical degrees out of phase with the others. In a symmetrical three-phase power system, each of the three conductors carries alternating current (AC) with the same frequency and voltage amplitude relative to a common reference, but with a phase difference of one-third of a cycle. Due to this phase difference, the voltage on any conductor reaches its peak at one-third of a cycle after one of the other conductors and one-third of a cycle before the remaining conductors. This phase delay provides constant power delivery for balanced linear loads. This also allows for the generation of a rotating magnetic field in the motor.

[0034] In a three-phase system with a balanced and linear load, the sum of the instantaneous currents in the three conductors is zero. In other words, the current in each conductor is equal in magnitude to the sum of the currents in the other two conductors, but with opposite signs. The return path of the current in any phase conductor is through the other two phase conductors. Instantaneous currents produce a current space vector.

[0035] A three-phase inverter comprises three inverter branches, one for each of the three phases, and each inverter branch is connected in parallel to a direct current (DC) voltage source. Each inverter branch includes a pair of power transistors, arranged, for example, in a half-bridge configuration, for converting DC to AC. In other words, each inverter branch includes two complementary transistors connected in series (i.e., a high-side transistor and a low-side transistor), which are complementary in turning on and off to drive the phase load.

[0036] Figure 1 This is a schematic block diagram illustrating a control actuator 100 of a power semiconductor device according to one or more embodiments. In this example, the control actuator 100 is a motor control actuator for controlling and driving a motor. However, it will be understood that the control actuator 100 can control and / or drive other types of loads. Therefore, Figure 1 A non-limiting example of the use of a control actuator is shown, in which a motor is a possible load type.

[0037] The control actuator 100 includes a power inverter 1 and an inverter control unit 2. The inverter control unit 2 is a control unit (e.g., a motor control unit) and can therefore also be referred to as a controller or control IC (e.g., a motor controller or motor control IC). The control unit can be a monolithic IC or can be distributed across two or more ICs containing microcontrollers and gate drivers.

[0038] In this example, the control actuator 10 is also coupled to a three-phase motor M comprising three phases: U, V, and W. The power inverter 1 is a three-phase current generator configured to provide three-phase power for driving the motor M by supplying three-phase current. It will also be understood that the power inverter 1 and the inverter control unit 2 may be placed on the same circuit board or on separate circuit boards.

[0039] Both amplitude and phase deviations can cause power and torque losses in the motor M. Therefore, the control actuator 100 can be configured to monitor and control the amplitude and phase of the current supplied to the motor M in real time to ensure proper current balance is maintained based on a feedback control loop. An open-loop motor control unit is also present and can be implemented.

[0040] Power inverter 1 includes a switch array of six transistor modules 3u+, 3u-, 3v+, 3v-, 3w+, and 3w- (collectively referred to as transistor modules 3) arranged in complementary pairs. Each complementary pair constitutes an inverter branch that supplies phase current to a three-phase motor M. Therefore, each inverter branch includes an upper (high-side) transistor module 3 and a lower (low-side) transistor module 3. Each transistor module may include a transistor and may also include a diode (not shown). Thus, each inverter branch includes an upper transistor (i.e., a high-side switch) and a lower transistor (i.e., a low-side switch). Load current paths U, V, and W extend from the outputs of each inverter branch located between the complementary transistors (i.e., the outputs of each half-bridge) and are configured to be coupled to a load such as motor M. Power inverter 1 is coupled to a DC power supply 4 (e.g., a battery or a diode bridge rectifier) ​​and to inverter control unit 2.

[0041] In this example, the inverter control unit 2 includes motor control circuitry and gate driver circuitry for controlling the switch array. In some examples, the inverter control unit 2 can be monolithic, where the motor control circuitry and gate driver circuitry are integrated onto a single die. In other examples, the motor control circuitry and gate driver circuitry can be separated into separate ICs. A “monolithic” gate driver is a gate driver on a single silicon chip and can also be fabricated using specific high-voltage (HV) techniques. Furthermore, the gate driver IC can be integrated onto the power inverter 1 to form a power module.

[0042] The controller IC executes the control functions of the actuator 100 in real time. When driving the motor, the control function is a motor control function, which may include controlling a permanent magnet motor or an induction motor, and may be configured as sensorless control that does not require rotor position sensing, sensor-based control with Hall sensors and / or encoder devices, or a combination of sensor-based control (e.g., used at lower rotor speeds) and sensorless control (e.g., used at higher rotor speeds).

[0043] For example, the inverter control unit 2 includes a controller and driver unit 5, which includes a microcontroller unit (MCU) as a controller IC and a gate driver IC for generating driver signals for controlling the transistors of each transistor module 3. Therefore, the load current paths U, V, and W can be controlled by the controller and driver unit 5 via the control electrode (i.e., the gate electrode) of the transistor 3. For example, upon receiving a control signal from the microcontroller, the gate driver IC can set the corresponding transistor to one of a conducting state (i.e., an on state) or a blocking state (i.e., an off state).

[0044] The gate driver IC can be configured to receive instructions from the MCU, including power transistor control signals, and to turn the corresponding transistor 3 on or off according to the received instructions and control signals. For example, during the turn-on process of the corresponding transistor 3, the gate driver IC can be used to provide (supply) gate current to the gate of the corresponding transistor 3 to charge the gate. In contrast, during the turn-off process, the gate driver IC can be used to draw (absorb) gate current from the gate of the transistor 3 to discharge the gate.

[0045] The inverter control unit 2 or controller and driver unit 5 may itself include a PWM controller, ADC, DSP and / or clock source (i.e., timer or counter) for implementing a PWM scheme to control the state of each transistor and ultimately control each phase current provided on the corresponding load current paths U, V and W.

[0046] Specifically, the microcontroller in controller and driver unit 5 can use motor control algorithms, such as field-oriented control (FOC) algorithms, to provide real-time current control for each phase current output to a multiphase load, such as a multiphase motor. For example, during FOC, the motor phase current should be measured so that the accurate rotor position can be determined in real time. To achieve the determination of the motor phase current, MCU 5 can employ an algorithm using single-segment current sensing (e.g., space vector modulation (SVM), also known as space vector pulse width modulation (SVPWM)).

[0047] Furthermore, the switch 3 (i.e., transistor) in the power inverter 1 is controlled so that the two switches in the same inverter branch will never be turned on simultaneously, otherwise the DC power supply will be short-circuited. This requirement can be met by performing complementary operations on the switch 3 in the inverter branch according to the motor control algorithm.

[0048] Figure 2 This is a schematic block diagram of a power module 200 according to one or more embodiments. The power module 200 includes a single-phase drive stage 10 (i.e., an inverter branch) and a gate driver system 20 electrically coupled to the single-phase drive stage 10. However, the single-phase drive stage can be extended to a multi-phase drive state by adding additional inverter branches. Both the single-phase drive stage 10 and the gate driver system 20 are integrated into a single package (not shown). Therefore, the power module 200 is packaged as a single device.

[0049] The single-phase drive stage 10 includes a load current I controlled to supply a load current I to one phase of a load (not shown). LOAD The low-side transistor 11 and the high-side transistor 12 are shown. Freewheeling diodes D1 and D2 coupled to their respective power transistors 11 and 12 are also shown.

[0050] Gate driver system 20 is a high-voltage (HV) gate driver system, which includes a low-side (LS) gate driver 21 for driving low-side transistor switch 11 and a high-side (HS) gate driver 22 for driving high-side transistor switch 12. As will be explained later, LS gate driver 21 and HS gate driver 22 are located in different voltage domains of gate driver system 20.

[0051] Both gate drivers 21 and 22 perform gate driving of their respective power transistors 11 and 12 based on digital PWM signals LIN and HIN received from the microcontroller unit (MCU). The PWM signals are control signals received from the MCU at the PWM logic unit 35 of gate driver 20. The PWM logic unit 35 receives the LIN and HIN signals from the MCU and ensures a minimum dead time to prevent bridge shoot-through. Finally, the corresponding PWM control signals are passed to the respective low-side gate driver 21 and high-side gate driver 22, with the PWM signal HIN sent to high-side gate driver 22. After this, low-side gate driver 21 and high-side gate driver 22 perform gate driving.

[0052] Gate drivers 21 and 22 each include separate pre-driver circuit systems 26 and 27, and buffers 33 and 34. Pre-driver circuit systems 26 and 27 are configured to receive a PWM signal and, based on the PWM signal, control the on / off state of a corresponding first current source (e.g., a pull-up FET) for generating current Io+. Additionally, pre-driver circuit systems 26 and 27 are configured to receive a PWM signal and, based on the PWM signal, control the on / off state of a corresponding second current source (e.g., a sink FET) for generating current Io-. The corresponding current sources are located in buffers 33 and 34. Therefore, buffers 33 and 34 may each include a pair of complementary FETs for generating on-current Io+ and off-current Io- for their respective power transistors 11 and 12. Each of the pre-driver circuit systems 26 and 27 can also command its respective buffer 33 or 34 to use a certain current capability.

[0053] The low-side gate driver 21 is arranged in a low-side region defined by a medium or low voltage domain, while the high-side gate driver 22 is arranged in a high-side region defined by a high voltage domain. In fact, the gate driver system 20 also includes a termination region 44, which isolates the different voltage domains from each other and may be referred to as an isolation termination region. Therefore, the termination region provides voltage isolation barriers between two or more voltage domains.

[0054] The gate driver system 20 can be configured to receive PWM control signals from the MCU and turn on or off the corresponding transistors 11 and 12 according to the received PWM control signals. For example, during the turn-on process of the corresponding transistor 11 or 12, the gate driver 20 can be used to provide (supply) a gate current Io+ to the gate of the corresponding transistor 11 / 12 to charge the gate. In contrast, during the turn-off process, the gate driver 20 can be used to draw (absorb) a gate current from the gate of the transistor 11 / 12 to discharge the gate.

[0055] Therefore, the MCU is electrically coupled to the gate driver system 20 for transmitting information signals and control signals HIN and LIN between them, and the gate driver system 20 is electrically coupled to the inverter branch 10 for driving its power transistors.

[0056] Specifically, the MCU is configured to generate PWM control signals LIN and HIN for controlling transistors 11 and 12, respectively, and transmit these control signals to the LV domain 43. For example, the gate driver system 20 is configured to receive instructions from the MCU to use the PWM control signals to drive the load phase (i.e., the inverter branch) connected to the voltage VS. These PWM control signals are received by the gate driver system 20 at the LV domain 43 (i.e., at the input pins HIN and LIN) and transmitted via appropriate logic units (e.g., PWM logic unit 35) to the corresponding pre-driver circuit systems 26 and 27. Buffers 33 and 34 are configured to receive the PWM control signals and drive the corresponding power transistors 11 and 12 via the output terminals HO and LO of the gate driver system 20.

[0057] exist Figure 2 In the example shown, there are four regions: a high-side region defined by HV domain 41, a low-side region defined by medium voltage domain (MV) domain 42 or a medium voltage domain, a low-voltage region defined by LV domain 43, and a termination region 44. LV domain 43 is the region that includes low-voltage devices, MV domain 42 is the region that includes medium voltage devices, and HV domain 41 is the region that includes high-voltage devices. For example, low-voltage devices can be supplied from 0V to 5V, medium-voltage devices can be supplied from 0V to 30V, and high-voltage devices can be supplied above 100V (e.g., 120V to 160V). The voltage domains are not limited to these voltage ranges but are intended to provide an example of an implementation. However, the general principle that voltage domain levels differ at different voltage levels remains unchanged.

[0058] Termination region 44 is represented by dashed lines between different voltage domains. Termination region 44 isolates different voltage domains from each other. Therefore, termination region 44 provides voltage isolation barriers between different voltage domains. Termination region 44 can be a single continuous region, or it can include two or more regions for separating various voltage domains.

[0059] The gate driver system 20 can be a multi-die gate driver with three separate voltage islands. In this case, each of zones 41, 42, and 43 is a separate die or IC. Termination zone 44 provides current isolation between ICs 41, 42, and 43 to electrically isolate the dies.

[0060] If in Figure 3As further described, LV domain 43 provides information from PWM logic unit 35 to gate drivers 22 and 21 located in other voltage domains 41 and 42 via transformers 60 and 61, which are respectively indicated by pairs of transmitter (TX) coils 60tx and 61tx and receiver (RX) coils 60rx and 61rx. Thus, transformer 60 is configured to transmit electrical signals (e.g., PWM control signals) from PWM logic unit 35 to gate driver 22 (i.e., from the first voltage domain to the second voltage domain). Additionally, transformer 61 is configured to transmit electrical signals (e.g., PWM control signals) from PWM logic unit 35 to gate driver 21 (i.e., from the first voltage domain to the third voltage domain).

[0061] although Figure 2 A multi-die solution including three dies is shown; however, it should be understood that two dies can also be used. In this case, the individual components of MV domain 42 and LV domain 43 can be combined into the same voltage domain (e.g., LV domain), so that they are integrated onto a single die. The remaining dies may include, for example, Figure 2 The HV domain 41 is shown. Therefore, only transformer 60 is needed for transmission between the two existing voltage domains (e.g., LV domain 43 and HV domain 41).

[0062] Although Figure 2 An example including three isolated voltage domains is shown, but some implementations may have a configuration where there is no isolation between MV domain 42 and LV domain 43. In other words, isolation may not be present. Figure 2 The diagram shows a portion of the termination area 44 between the MV domain 42 and the LV domain 43. In this case, to isolate the HV domain 41 from the other voltage domains 42 and 43, the termination area 44 is retained between the HV domain 41 and the other voltage domains 42 and 43.

[0063] Alternatively, some implementations may have a configuration in which the LV domain 43 is entirely arranged within the MV domain 42. In this case, to isolate the LV domain 43 from the MV domain 42, the LV domain 43 may be a voltage island completely surrounded by the termination area 44. Furthermore, to isolate the HV domain 41 from the MV domain 42, the termination area 44 is positioned between the HV domain 41 and the MV voltage domain 42. Therefore, the LV domain 43 is isolated from the MV domain 42, and the HV domain 41 is isolated from the MV domain 42. Of course, the LV domain 43 and the HV domain 41 are also isolated from each other by two separate termination areas 44.

[0064] Alternatively, it will be understood that the four regions 41 to 44 can be monolithically constructed on a single integrated circuit. In a monolithic solution, such as Figure 2 Similarly, as shown in the diagram, the termination area within the die is used to isolate different voltage domains. Here, as... Figure 2As similarly illustrated, transformers 60 and 61 can be used to transmit electrical signals between different voltage domains.

[0065] In any case, VB refers to the high-side floating supply voltage; VS refers to the high-side floating ground voltage; VDD or VCC refers to the low-side and logic fixed supply voltage; VSS or VEE refers to the low-side ground voltage; HO refers to the high-side floating output voltage; LO refers to the low-side output voltage; DC+ refers to the positive terminal of the DC link; DC- refers to the negative terminal of the DC link; and HIN and LIN refer to the logic input voltage (i.e., control signal) received from the MCU.

[0066] In one example, the gate driver system 20 can operate at a common-mode voltage of 130V with a floating supply of 30V as its maximum operating range. In this example, VB operates at a maximum of 160V, VS at a maximum of 130V, VCC at 30V, and VSS at 0V. Specifically, VS equals DC+ when transistor 12 is on (and transistor 11 is off), and VS equals DC- when transistor 11 is on (and transistor 12 is off). In both cases, VB remains approximately 30V above VS due to the bootstrap capacitor 24. Therefore, with DC+ equal to a common-mode voltage of 130V, the low-side (external) supply voltage to VCC can be set to 30V, and the high-side supply voltage VB can operate at a maximum voltage of 160V. DC- is connected to ground / VSS, but is not required.

[0067] In another example, the gate driver system 20 can operate at a common-mode voltage of 1500V with a floating supply of 35V as its maximum operating range. In this example, VB operates at a maximum of 1535V, VS operates at a maximum of 1500V, VCC operates at 35V, and VSS operates at 0V. Specifically, VS equals DC+ when transistor 12 is on (and transistor 11 is off), and VS equals DC- when transistor 11 is on (and transistor 12 is off). In both cases, VB remains approximately 35V above VS due to the bootstrap capacitor 24. Therefore, with DC+ equal to a common-mode voltage of 1500V, the low-side (external) supply voltage to VCC can be set to 35V, and the high-side supply voltage VB can operate at its maximum voltage of 1535V. DC- is connected to ground / VSS, but is not required.

[0068] It will be understood that the common-mode voltage and maximum operating range of the floating power supply are configurable and can be set to different voltages provided in the two examples above, including common-mode voltages between 130V and 1500V, less than 30V, or greater than 1500V.

[0069] The voltages mentioned above are configured so that the high-side voltage domain operates at a higher voltage or power level compared to the low-side voltage domain. Additionally, the medium voltage or power domain is set at an intermediate level between the HV and LV domains.

[0070] HV domain 41 includes pre-driver circuitry 27, buffer 34, and MV ESD device 51 coupled to VS and VB.

[0071] LV domain 43 includes PWM logic unit 35 and transmitter circuitry that transmits communication signals to other voltage domains.

[0072] MV domain 42 includes a pre-driver circuit 26 and a buffer 33. MV domain 42 also includes a power management unit (PMU) 37 powered by VSS and VCC. PMU 37 is a microcontroller that manages and regulates power functions. For the starter, PMU 37 converts the intermediate supply voltage (i.e., VCC) to a low supply voltage (e.g., 5V) supplied to LV domain 43. Specifically, PMU 37 supplies this low supply voltage to PWM logic unit 35. PWM logic unit 35 uses the low supply voltage to perform its function. Furthermore, PMU 37 is configured to monitor for faults and, in the event of an event, shut down the power supply to PWM logic unit 35. By shutting down the power supply to PWM logic unit 35, PWM logic unit 35 is disabled and high-side transistor 12 is turned off.

[0073] Other implementations involve communication between voltage domains and transmission of electrical signals across the termination area 44. Figure 3 A coreless transformer (CT) communication system 300 implemented in a gate driver package for isolated gate driver communication is shown according to one or more embodiments. The CT transmission system 300 includes a power generator Vtx, an LED emulator circuit 70, a voltage comparator circuit 80, an optional level shifter 91, a power extractor 92, a CT transmitter 93, and a CT receiver 94. The CT transmitter 93 is coupled to one of the TX coils 60tx or 61tx to transmit a CT signal (e.g., a PWM control signal), and the CT receiver 94 is coupled to one of the RX coils 60rx or 61rx to receive a CT signal. The CT transmission system 300 can be provided for each communication path traversing two voltage domains. Therefore, in Figure 2 In the middle, two CT communication systems 300 can be provided.

[0074] In this example, the power generator Vtx is a voltage generator that modulates its power supply to generate a forward current iF and a forward voltage VF. However, a current generator that modulates its power supply output can also be used as a power generator Vtx to generate a forward current iF and a forward voltage VF. Since the power generator Vtx is used to generate voltage and / or current signals, it can also be referred to as a signal generator.

[0075] The power generator Vtx, LED emulator circuit 70, voltage comparator circuit 80, optional level shifter 91, power extractor 92, and CT transmitter 93 are arranged in LV domain 43 and can be incorporated into PWM logic unit 35. CT receiver 94 is arranged across termination area 44 in different voltage domains to receive, for example, the corresponding PWM control signal. Alternatively, CT receiver 94 can be arranged in LV domain 43 and CT transmitter 93 can be arranged in HV domain 41 to transmit feedback information to PWM logic unit 35. Alternatively, CT receiver 94 can be arranged in MV domain 42 and CT transmitter 93 can be arranged in HV domain 41 to transmit feedback information to PMU 37.

[0076] The LED emulator circuit 70 is designed to replace the current-modulated optical communication characteristic of optocouplers. Specifically, the LED emulator circuit 70 is a current extraction circuit that simulates the LED characteristics of an LED optocoupler.

[0077] Voltage comparator circuit 80 receives the output Vsense of LED emulator circuit 70 and converts Vsense into a modulated output signal Vmod. The modulated signal Vmod is used to trigger (enable) or disable the carrier generated by CT transmitter 93. As a result, the modulated output signal Vmod is a communication control signal used for on / off keying of CT transmitter 93.

[0078] Specifically, the CT transmitter 93 generates a communication signal comprising binary 1 and binary 0 data bits. For example, the communication signal could be a PWM control signal. The binary symbol 1 is represented by transmitting a fixed-amplitude carrier wave and a bit duration of T seconds at a fixed frequency. If the signal value is 1, the carrier signal is transmitted; otherwise, the signal value is 0. Therefore, the carrier is enabled based on the modulated output signal Vmod of the voltage comparator circuit 80, which depends on the value of the sensed voltage Vsense provided at the output of the LED emulator circuit 70, which is coupled to the input of the voltage comparator circuit 80. The carrier can be a sinusoidal carrier wave or a rectangular signal including pulses.

[0079] Therefore, the CT transmitter 93 can be an on / off keyed (e.g., amplitude shift keying (ASK)) transmitter, wherein modulated conduction pulses are transmitted to the secondary chip via inductive coupling (e.g., via a transformer) through the CT receiver circuit 94. The CT receiver 94 can be an on / off keyed demodulator. The secondary chip can be a die defined by the HV domain 41 or the MV domain 42.

[0080] As described above, the CT transmission system 300 includes a power generator Vtx, such as a voltage oscillator, that generates a modulated power supply voltage based on the data to be transmitted. A resistor Rtx provides an electrical path to the LED simulator circuit 70. The forward current iF is generated based on the modulated power supply voltage, the value of resistor Rtx, and other resistances.

[0081] The LED simulator circuit 70 includes an anode node Z1, which simulates the anode of the LED where a forward voltage VF (i.e., the anode voltage) exists. Thus, the anode node Z1 can be referred to as the forward voltage node or the input node. The forward voltage VF is the anode voltage generated by the injection of a current as a forward current iF. Similarly, the LED simulator circuit 70 includes a cathode node Z2, which simulates the cathode of the LED where a cathode voltage exists. Thus, the cathode node Z2 can be referred to as the output node or the sensing node.

[0082] The LED simulator circuit 70 also includes a resistor R0 and a sensing resistor R2 connected in series between the forward voltage node and the cathode node Z2. Specifically, resistor R0 is coupled between nodes Z1 and Z3, and resistor R1 is coupled between nodes Z3 and Z2.

[0083] The active shunt-regulated clamping circuit is connected in parallel with resistor R0. The active shunt-regulated clamping circuit includes a diode chain of four diodes D0, D1, D2, and D3 connected in series between nodes Z1 and Z3, along with resistor R1. The active shunt-regulated clamping circuit also includes a clamping transistor Ncl, which is also coupled in parallel with resistor R0 (i.e., between nodes Z1 and Z3). For example, the clamping transistor Ncl could be an n-channel MOSFET with its drain connected to node Z1, its source connected to node Z3, and its gate connected to node Z4, which is connected between the last pair of diodes in the diode chain—diodes D2 and D3—(i.e., connected to the cathode of diode D2 and the anode of diode D3).

[0084] Finally, the LED simulator circuit 70 includes diode D ESD diode D ESD Connected to nodes Z1 and Z2 in a reverse bias arrangement to provide protection against electrostatic discharge (ESD).

[0085] Resistor R0 is used to simulate the forward voltage of the simulated optocoupler LED with a forward current of approximately 1 mA iF. For example, the resistances of Rtx, R0, and R2 can be chosen to be approximately 970 ohms, where, in this example, the sum of R0 and R2 is approximately 700 ohms. Therefore, when the voltage Vtx is 1.0V, the forward voltage VF (at the anode node Z1) is approximately 0.7V, and the forward current iF through resistors R0 and R2 is approximately 1 mA. Diode chains D0 through D3 remain off because there is not enough voltage to forward bias all four diodes. Here, for illustrative purposes only, it is assumed that each of diodes D0 through D3 has a forward voltage of 0.65V. Therefore, a forward voltage VF of approximately 2.6V is required to forward bias all four diodes D0 through D3 and to allow diode current to flow through diode chains D0 through D3.

[0086] When a binary 1 data bit is needed, the voltage generator Vtx increases its output voltage to increase the positive voltage VF flowing into node Z1. Conversely, when a binary 0 data bit is needed, the voltage generator Vtx decreases its output voltage to decrease the positive voltage VF flowing into node Z1.

[0087] When a binary 1 data bit is needed, the forward voltage VF increases. When the forward voltage VF is approximately 2.6V, all four diodes D0 through D3 in the diode chain are forward biased, the clamping transistor Ncl is turned on, and the fixed-amplitude carrier is triggered via the voltage comparator circuit 80. As the voltage generator Vtx continues to increase its supply voltage to its peak level, the diode chain D0 through D3 remains forward biased, but the excess current iclamp generated by the increased supply voltage flows through the clamping transistor Ncl to clamp the forward voltage to approximately 2.6V, depending on the value of resistor R1 (i.e., the voltage required to forward bias the diode chain D0 through D3 plus the voltage drop across resistor R1). In other words, the clamped forward voltage can be adjusted by changing the resistance of resistor R1. For example, depending on the value of resistor R1, the forward voltage can be clamped to a value between 2.6V and 3.1V.

[0088] By clamping the forward voltage VF, the clamping transistor Ncl prevents VF from increasing to levels that could damage the LED emulator circuit 70 (e.g., diodes D0 to D3) and / or the voltage comparator circuit 80, since many components are powered by the forward voltage VF. Therefore, the clamping transistor Ncl protects the circuit by limiting the forward voltage VF to a safe operating level.

[0089] As a result, the forward bias threshold of diode chains D0 to D3 is the forward voltage threshold used to trigger a fixed-amplitude carrier. When the forward voltage VF at least meets this forward bias threshold, the currents iF0, idiode, and iclamp are added at node Z3 as the total current isum flowing through the sensing resistor R2.

[0090] It should also be noted that when the forward voltage VF is less than this forward bias threshold, the total current isum is equal to the current iF0 flowing through resistor R0 because other parallel branches are disabled. In this case, according to Ohm's law, the forward voltage VF changes proportionally to the forward current iF.

[0091] Therefore, the voltage drop across the sensing resistor R2 (sensing voltage Vs) varies based on the total current isum, which in turn varies based on the power supply driven by the voltage generator Vtx. In either case, the total current isum equals the forward current iF. Therefore, these two currents can be used interchangeably.

[0092] By sensing the voltage Vs, the total current isum is used by the voltage comparator circuit 80 to trigger the simulated light emission. As described above, when the forward current iF increases due to the communication requirement of transmitting binary 1 data bits, the forward voltage VF is clamped by an active shunt-regulated clamping circuit including clamping transistor Ncl, diode chains D0 to D3, and resistor R1. Any additional current exceeding the threshold current value is passed through the active shunt-regulated clamping circuit.

[0093] When the forward current iF is less than the threshold current used for the simulated light emission, the voltage at node Z4 is insufficient to turn on the clamping transistor Ncl. Therefore, when the forward current iF is less than the threshold current, essentially all current flows through resistor R0. In this case, the total current isum is equal to the initial forward current iF0, and the total current isum flows through the sensing resistor R2, which generates the voltage drop (sensing voltage) Vsense. The voltage drop Vsense represents the total current isum, which can also be referred to as the signaling current.

[0094] When the forward current iF reaches the threshold current value used for the simulated light emission (i.e., when the forward voltage VF is equal to the forward voltage threshold), the active shunt regulation clamp circuit acts as a shunt regulator by clamping the forward voltage VF to the voltage drop of approximately four diodes in the diode chain D0 to D3, 4Vd, plus the voltage drop of resistor R1.

[0095] Therefore, for a wide range of forward currents iF that meet or exceed the threshold current value, the voltage across diode chains D0 to D3 (and between nodes Z1 and Z3) will effectively remain stable. Additionally, the voltage controlling the gate of the clamping transistor Ncl at node Z4 is sufficient to turn on the clamping transistor Ncl and keep it in active mode. The voltage at node Z4 is also clamped to a fixed value. Voltage comparator circuit 80 is a self-biased ΔVgs comparator (i.e., a dVgs comparator or ΔVgs comparator) used for dynamic voltage comparison and dynamic real-time modulation of the modulation signal Vmod. With the aid of sensing resistor R2, voltage comparator circuit 80 converts the signaling current (isum) into a voltage decision. The signaling current is used to signal the CT transmitter 93 via voltage comparator 80 whether a carrier wave is generated for the communication signal.

[0096] Specifically, the voltage comparator circuit 80 continuously monitors the sensed voltage Vsense, representing the signaling current (isum), and converts the sensed voltage Vsense into a modulation signal Vmod. For example, when the sensed voltage Vsense meets or exceeds a communication voltage threshold (corresponding to a threshold current value), the voltage comparator circuit 80 generates a modulation signal Vmod with a first value that triggers a fixed-amplitude carrier. In contrast, when the sensed voltage Vsense is less than the communication voltage threshold, the voltage comparator circuit 80 generates a modulation signal Vmod with a second value that disables the fixed-amplitude carrier.

[0097] Essentially, the voltage comparator circuit 80 continuously compares the sensed voltage Vsense with a communication voltage threshold and modulates the modulated output signal Vmod based on the comparison result. This comparison is accomplished through a cascade effect of turning transistor devices on or off based on the sensed voltage Vsense received at the input of the voltage comparator circuit 80.

[0098] The voltage comparator circuit 80 includes a low-pass filter (LPF), which comprises two resistors R. LPF1 and R LPF2 resistor R LPF1 and R LPF2 The circuit is coupled across the sensing resistor R2 (i.e., each component is coupled to a different terminal of the sensing resistor R2), and is therefore configured to extract the sensed voltage Vsense from the LED emulator circuit 70. The LPF also includes a capacitor C. LPF The LPF is configured to remove noise from the signaling current or sensed voltage Vsense caused by the voltage generator Vtx.

[0099] The voltage comparator circuit 80 also includes an M:1 current mirror, where M is a positive integer. The current mirror includes transistors N0, N1, and P0, and self-biased current sources Ibias1, Ibias2, and Ibias3 that generate equal currents. Transistors N0 and N1 are n-channel MOSFETs, and P0 is a P-channel MOSFET. Transistor P0 is also the output transistor of the voltage comparator circuit 80, which modulates the modulated output signal Vmod based on the sensed voltage Vsense.

[0100] If the signaling current (isum) is less than the threshold current value, the sensed voltage Vsense is less than the communication voltage threshold, and the modulation output signal Vmod of the voltage comparator circuit 80 is pulled low to approximately zero (i.e., logic low). Specifically, when the sensed voltage Vsense is less than the communication voltage threshold, the source terminal of transistor N0 is low, thereby causing transistor N1 to be turned off.

[0101] Specifically, transistor N0 has its own Vgs, which is equal to Vds provided by Ibias1, and the Vgs of transistor N1 is defined by Ibias2. Accordingly, if Ibias1 equals Ibias2, then due to the gain factor M, the Vgs of N1 > the Vgs of N0. Therefore, when the sensed voltage Vsense is low (i.e., less than the communication threshold), when Ibias = Ibias1 = Ibias2, the Vgs of N0 will be insufficient to drive transistor N1 to conduct. Therefore, transistor N1 is turned off.

[0102] When transistor N1 is turned off, the gate of output transistor P0 is pulled high to a positive voltage VF by current source Ibias2, thereby turning off output transistor P0. When output transistor P0 is turned off, the modulated output signal Vmod is pulled low by current source Ibias3.

[0103] When the modulated output signal Vmod is low, the fixed-amplitude carrier is disabled for the communication signal, and the communication signal is transmitted by the CT transmitter 93, where the signal value is zero. The CT receiver 94 is configured to receive the communication signal and interpret the zero signal value during the bit duration of T seconds as the binary symbol 0.

[0104] Conversely, if the signaling current (isum) is equal to or greater than the threshold current value, the sensed voltage Vsense is equal to or greater than the communication voltage threshold, and the modulation output signal Vmod of the voltage comparator circuit 80 is pulled high to the positive voltage VF (i.e., logic high). Specifically, when the sensed voltage Vsense is equal to or greater than the communication voltage threshold, the source terminal of transistor N0 is high (i.e., above the communication threshold). Since Vgs of transistor N0 is limited by Ibias1 and is much smaller than the signaling current isum, the increase in the sensed voltage Vsense will cause the voltage at the drain terminal and gate terminal of transistor N0 to increase due to the current source Ibias1, resulting in the gate terminal of transistor N1 being high and transistor N1 being turned on. When transistor N1 is turned on, the gate of output transistor P0 is pulled low, thereby turning on output transistor P0. When output transistor P0 is turned on, the modulation output signal Vmod is pulled high to the positive voltage VF.

[0105] When the modulated output signal Vmod is high, the fixed-amplitude carrier is enabled. With the fixed-amplitude carrier enabled, the CT transmitter 93 is configured to generate a fixed-amplitude carrier for the transmitted communication signal. The CT receiver 94 is configured to receive the communication signal and decode the fixed-amplitude carrier for a bit duration of T seconds into binary symbol 1.

[0106] Transmitter coils 60tx and 61tx are coupled to the output of CT transmitter 93 and are configured to transmit communication signals. Transmitter coils 60tx and 61tx include a positive terminal CTp, a negative terminal CTn, and a reference or midpoint terminal CTm.

[0107] Similarly, receiver coils 60rx and 61rx are coupled to the input of CT receiver 94 and are configured to receive communication signals via inductive coupling.

[0108] Power extractor 92 is configured to tap or extract a positive voltage VF from node Z1 to supply power to CT transmitter 93 via power lines 92a and 92b. Power line 92a can be coupled to the positive terminal CTp and power line 92b can be coupled to the negative terminal CTn.

[0109] In some cases, the CT transmitter 93 requires a voltage higher than that supplied by the positive voltage VF. In this case, the power extractor 92 can convert the positive voltage VF into one or more higher power signals (e.g., into a higher voltage or a higher current equivalent).

[0110] Additionally, in cases where the CT transmitter 93 requires a voltage higher than that supplied by the positive voltage VF, an optional level converter 91 is provided to level-convert or convert the modulated output signal Vmod into a higher voltage equivalent signal that can be processed by the CT transmitter 93.

[0111] As an example, the power extractor 92 is a charge pump and a ring oscillator with pre-biasing and a fast settling time. The ring oscillator generates a clock signal, which is transmitted via signal line 92c to generate an on / off keyed carrier. That is, the CT transmitter 93 uses the clock signal to generate the carrier. The charge pump can approximately double the input voltage (i.e., the forward voltage VF) and is used to provide a larger amplitude to the coil power supply of the CT transmitter 93. However, (without the charge pump) the design of the power extractor 92 can be simpler and can be strictly determined as a load by the CT transmitter 93.

[0112] Figure 4 Various signal diagrams according to one or more implementations of the communication protocol are shown. The top signal diagram shows an example of voltages VF and Vtx relative to each other. The positive voltage VF is limited (clamped) to a fixed positive voltage by an active shunt regulating clamping circuit.

[0113] The intermediate signal diagram illustrates the forward current iF related to voltages VF and Vtx. Based on the peak voltage Vtx, the forward current iF reaches its maximum, iFmax. As the forward current iF increases or decreases, it crosses the threshold current value I. TH-com (i.e., communication threshold). If the forward current iF meets or exceeds the threshold current value I... TH-com Then, the CT transmitter 93 triggers (enables) the carrier for the communication signal Scomm. If the forward current iF is less than the threshold current value I... TH-com Then the CT transmitter 93 disables the carrier for the communication signal Scomm.

[0114] The bottom signal diagram illustrates the communication signal Scomm generated by the CT transmitter 93 based on the modulated output signal Vmod described above. Modulation of the modulated output signal Vmod is performed based on the threshold intersection shown in the intermediate signal diagram. As can be seen, the carrier is based on the forward current iF and the threshold current value I. TH-com It is then enabled. The sensed voltage Vsense is modulated based on the forward current iF. The carrier has a period T. carrier Period T carrier It is the reciprocal of the oscillator frequency Fosc of the clock signal provided by the power extractor 92.

[0115] Based on the above, the following advantages can be achieved. Due to the fast response time of the LED simulator circuit 70 and the voltage comparator circuit 80, a higher switching frequency can be used. Higher common-mode transient immunity (CMTI) can be achieved by using a CT communication system. The voltage comparator circuit 80 determines the communication voltage threshold faster and more accurately. The complexity of the power extractor 92 can be reduced to a center bias generator and oscillator for the carrier of the ASK system directly linked to the CT communication transmitter 93, and the complexity of the ASK T system can be reduced.

[0116] While various embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made to achieve some of the advantages of the concepts disclosed herein without departing from the spirit and scope of the invention. For example, although the above embodiments are directed to transmitters using coreless transformers (i.e., inductively coupled transmission), transformers 60 and 61 can be interchanged with different types of transmitters, including capacitive transmitters that use capacitive coupling to transmit capacitance. Therefore, other transmitter types can be used, and it will be apparent to those skilled in the art that other components performing the same or similar functions can be suitably replaced. It should be understood that other embodiments and structural or logical changes can be utilized without departing from the scope of the invention. It should be mentioned that features illustrated with reference to specific drawings can be combined with features of other drawings, even those not explicitly mentioned. Such modifications to the general inventive concept are intended to be covered by the appended claims and their legal equivalents.

[0117] Furthermore, the appended claims are thus incorporated into the detailed description, wherein each claim may be considered independently as a separate exemplary embodiment. While each claim may be considered independently as a separate exemplary embodiment, it should be noted that although a dependent claim may refer in the claim to a specific combination of one or more other claims, other exemplary embodiments may also include combinations of dependent claims with the subject matter of each of the other dependent or independent claims. Such combinations are presented herein unless the description does not intend to suggest a particular combination. Furthermore, it is intended that features of the claims be included in any other independent claim, even if that claim is not directly dependent on an independent claim.

[0118] It should also be noted that the methods disclosed in the specification or claims can be implemented by means having means for performing each of the corresponding actions of these methods. For example, the techniques described in this disclosure can be implemented, at least in part, in hardware, software, firmware, or any combination thereof—including any combination of computer programs on non-transitory computer-readable recording media, computing systems, and integrated circuits. For example, aspects of the described techniques can be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic unit systems, and any combination of such components.

[0119] Furthermore, it should be understood that the disclosure of multiple actions or functions in the specification or claims is not to be construed as being in a particular order. Therefore, unless such actions or functions are technically incomparable, the disclosure of multiple actions or functions does not limit these actions or functions to a specific order. Additionally, in some embodiments, a single action may include or may be decomposed into multiple sub-actions. Unless expressly excluded, such sub-actions may be included and such sub-actions may be part of the disclosure of the single action.

Claims

1. A communication system, comprising: An LED emulator includes an emulator input coupled to a power generator and an emulator output configured to output a sensed voltage, wherein the emulator input is configured to receive a forward current from a modulated power supply, wherein the LED emulator is configured to convert the forward current into the sensed voltage, and wherein the modulated power supply signal is modulated according to transmitted data. A voltage comparator includes a comparator input coupled to the output of the emulator and a comparator output, wherein the voltage comparator is configured to receive the sensed voltage and convert the sensed voltage into a modulated output signal based on a communication voltage threshold, wherein the voltage comparator generates a modulated output signal having a first value under a first condition that the sensed voltage is equal to or greater than the communication voltage threshold, and generates a modulated output signal having a second value under a second condition that the sensed voltage is less than the communication voltage threshold; and A transmitter, coupled to the output of the comparator, is configured to receive the modulated output signal and generate a communication signal based on the modulated output signal and the transmitted data.

2. The communication system according to claim 1, wherein, The transmitter is an on / off keyed transmitter configured to generate a carrier as the communication signal in response to a modulated output signal having the first value, and configured to generate a communication signal without the carrier in response to a modulated output signal having the second value.

3. The communication system according to claim 2, wherein, A positive voltage is generated at the input of the simulator, and the communication system further includes: A power extractor, coupled to the input of the emulator, is configured to receive the positive voltage and provide the power supply voltage derived from the positive voltage to the transmitter to power it.

4. The communication system according to claim 3, wherein: The power extractor includes an oscillator configured to generate a clock signal and transmit the clock signal to the transmitter. The transmitter is configured to receive the clock signal and generate the carrier based on the clock signal.

5. The communication system according to claim 1, wherein, The voltage comparator is configured to continuously monitor the sensed voltage and continuously generate the modulated output signal.

6. The communication system according to claim 1, wherein, The voltage comparator is a ΔVgs comparator.

7. The communication system according to claim 1, wherein, The LED simulator includes: A first current path, coupled between the simulator input and the simulator output to conduct at least a first portion of the positive current; and An active shunt regulating clamping circuit is coupled between the emulator's input and output terminals and connected in parallel with the first current path. Specifically, under the third condition where the forward current is less than the forward current threshold, the active shunt adjustment clamping circuit is disabled, and In the fourth condition where the forward current is equal to or greater than the forward current threshold, the active shunt adjustment clamping circuit is activated.

8. The communication system according to claim 7, further comprising: A sensing resistor, coupled to the output of the emulator, is configured to receive the current flowing through the first current path and the current flowing through the active shunt adjustment clamping circuit, wherein the sum of the current flowing through the first current path and the current flowing through the active shunt adjustment clamping circuit generates a signaling current flowing through the sensing resistor, and the sensing resistor generates the sensing voltage at the output of the emulator.

9. The communication system according to claim 7, wherein: In response to the satisfaction of the fourth condition, the first condition is satisfied, and In response to the satisfaction of the third condition, the second condition is also satisfied.

10. The communication system according to claim 9, wherein, The forward current threshold and the communication voltage threshold have a predetermined relationship.

11. The communication system according to claim 7, wherein, The active shunt adjustment clamping circuit includes: The second current path includes a diode chain of multiple diodes connected in parallel with the first current path; and The third current path includes a clamping transistor connected in parallel with the first current path, the clamping transistor including a control terminal coupled to a node between diode pairs coupled among the plurality of diodes.

12. The communication system according to claim 11, wherein, In response to the satisfaction of the fourth condition, the diode chain is fully forward biased.

13. The communication system according to claim 11, wherein: A positive voltage is generated at the input terminal of the simulator. The active shunt regulation clamping circuit is configured to clamp the positive voltage to a fixed positive voltage in response to the satisfaction of the fourth condition, and In response to the satisfaction of the third condition, the forward voltage changes proportionally to the forward current.

14. The communication system according to any one of claims 1 to 13 further includes a power generator configured to generate the modulated power signal based on the transmitted data.

15. A gate driver system, comprising: The first region operates in the first voltage domain; The second region operates in a second voltage domain that is lower than the first voltage domain; The termination area electrically isolates the first area and the second area; A gate driver, disposed in the first region and configured to drive a transistor; and The communication system according to any one of claims 1 to 14 is configured to transmit communication signals across the termination area and further includes a receiver configured to receive and demodulate the communication signals.

16. A method for gate driver communication, comprising: A modulated power signal is generated based on the transmitted data to produce a positive current; The positive current is supplied to the emulator input terminal of the LED emulator; The LED simulator converts the positive current into a sensing voltage generated at the simulator output terminal of the LED simulator. The sensed voltage is converted into a modulated output signal by a voltage comparator based on a communication voltage threshold, wherein the modulated output signal has a first value under a first condition that the sensed voltage is equal to or greater than the communication voltage threshold, and the modulated output signal has a second value under a second condition that the sensed voltage is less than the communication voltage threshold; as well as The transmitter generates a communication signal based on the modulated output signal and the transmitted data.

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