Integrated circuit system, DRAM circuit system, method for forming an integrated circuit system, and method for forming a DRAM circuit system

Abstract

A method for forming an integrated circuit system includes forming a plurality of conductive paths including conductive material. The conductive paths are spaced relative to each other by intermediate materials. Discontinuous materials are formed on top of the conductive material of the paths and on top of the intermediate materials between the paths. Metal materials are formed on top of the discontinuous materials, directly against the discontinuous materials and between the discontinuous materials and on top of the conductive material of the paths and directly against the conductive material of the paths. The metal material has a composition different from that of the discontinuous materials and is on top of the intermediate materials between the paths. The metal material having discontinuous materials thereunder is formed to include conductive lines on top of the intermediate materials between the paths and directly against individuals of the paths. Structures independent of the method are disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to integrated circuit systems, DRAM circuit systems, methods for forming integrated circuit systems, and methods for forming DRAM circuit systems. Background Art

[0002] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written or read using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Digit lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long time without power. Conventionally, non-volatile memory is designated as memory with a retention time of at least about 10 years. Volatile memory dissipates, so it is refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store the memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two information levels or states.

[0004] A capacitor is a type of electronic component that can be used in a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material. Energy can be stored electrostatically in this material as an electric field. Depending on the composition of the insulator material, the storage field will be volatile or non-volatile. For example, a capacitor insulator material that only includes SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has at least a portion of a ferroelectric material as an insulating material. Ferroelectric materials are characterized by having two stable polarization states and can therefore include programmable materials for capacitors and / or memory cells. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and is maintained (at least for a period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance from one another, and ideally, it can be used to write (i.e., store) and read memory states without reversing the polarization state until such reversal is desired. Less desirable is that in some memories with ferroelectric capacitors, the act of reading the memory state can reverse the polarization. Thus, when the polarization state is determined, rewriting of the memory cell is performed immediately after its determination to place the memory cell in the pre-read state. In any case, due to the bistable nature of the ferroelectric material forming part of the ferroelectric capacitor, the memory cell incorporating the capacitor is ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0005] Field effect transistors are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductor channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region, as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator may be programmable, such as ferroelectric.

[0006] Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may have a BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives instead of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices to enhance features.

[0007] NAND may be the infrastructure for integrated flash memory. A NAND cell unit includes at least one selection device coupled in series to a series combination of memory cells (the series combination is often referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0008] Capacitors and transistors may of course be used in circuits other than memory circuits. Regardless, conductive interconnects are used to connect the various components of an integrated circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic cross-sectional view of a portion of a DRAM structure according to some embodiments of the present invention and is taken along Figures 2 to 8 Intercepted by line 1-1.

[0010] Figure 2 It is along Figure 1 , 7 and the view taken along line 2-2 in FIG. 8 .

[0011] Figure 3 It is along Figure 1 , 7 and the view taken along line 3-3 in 8.

[0012] Figure 4 It is along Figure 1 , 7 and the view taken along line 4-4 in FIG. 8 .

[0013] Figure 5 It is along Figure 1 , 7 and the view taken along line 5-5 in FIG. 8 .

[0014] Figure 6 It is along Figure 1 , 7 and the view taken along line 6-6 in FIG. 8 .

[0015] Figure 7 It is along Figures 1 to 6 A view taken along line 7-7 in FIG.

[0016] Figure 8 It is along Figures 2 to 6 A view taken along line 8-8 in FIG.

[0017] Figures 9 to 29 is an ongoing process according to some embodiments of the present invention Figures 1 to 8 Schematic sequential cross-sectional view of the predecessor structure.

[0018] Figures 30 to 32 is an ongoing process according to some embodiments of the present invention Figures 9 to 28 Schematic sequential cross-sectional views of alternative predecessor configurations to the predecessor configuration shown. DETAILED DESCRIPTION

[0019] Embodiments of the present invention encompass integrated circuit system configurations such as DRAM circuit configurations, and methods for forming integrated circuit system configurations such as DRAM circuit configurations. Figures 1 to 8 A first example embodiment comprising a DRAM configuration is described, Figures 1 to 8 An example fragment of a substrate construction 8 is shown that includes an array or array region 10 that has been fabricated relative to a base substrate 11. The substrate construction 11 may include any one or more of conductive / conductor / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / insulating (i.e., electrically herein) materials. Various materials are on the base substrate 11. The materials may be Figures 1 to 8 11. For example, other portions or all of the fabricated components of the integrated circuit system may be provided somewhere above, around, or within the base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within the memory array may also be fabricated and may or may not be fully or partially within the memory array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently, in series, or otherwise relative to each other. As used in this document, a "sub-array" may also be considered an array.

[0020] Base substrate 11 includes semiconductive material 12 (e.g., appropriately and differently doped single crystal silicon and / or polycrystalline silicon, Ge, SiGe, GaAs, and / or other existing or future developed semiconductive materials), trench isolation region 14 (e.g., silicon nitride and / or silicon dioxide), and active area region 16 (which includes appropriately and differently doped semiconductive material 12). In one embodiment, construction 8 includes memory cell 75 ( Figure 4 , 5 and 8, for clarity in such figures, Figure 4 and 5 Only four contours 75 are shown in Figure 8 Only two outlines 75 are shown in FIG. 7 ), for example, each of which includes a field effect transistor device 25 ( Figure 3 ) and a storage element (e.g., capacitor 85; Figure 1 and 8 ) of a DRAM memory cell. However, embodiments of the present invention encompass other memory cells and other integrated circuit system configurations, regardless of whether or not the memory cell is included.

[0021] The example transistor devices 25 individually include a pair of source / drain regions, a channel region between the pair of source / drain regions, a conductive gate operatively proximate the channel region, and a gate insulator between the conductive gate and the channel region. The devices 25 are shown as recessed access devices, wherein the example configuration 8 shows such recessed access devices grouped in individual pairs of such devices. Individual recessed access devices 25 include buried access line configurations 18, such as within trenches 19 in semiconductive material 12. Configurations 18 include conductive gate material 22 (e.g., conductively doped semiconductor material and / or metallic material, including, for example, elements W, Ru, and / or Mo) that serves as a conductive gate for the individual devices 25. Gate insulators 20 (e.g., silicon dioxide and / or silicon nitride) are along sidewalls 21 and bases 23 of individual trenches 19 between the conductive gate material 22 and the semiconductive material 12. Insulator material 37 (e.g., silicon dioxide and / or silicon nitride) is located within the trenches 19 above materials 20 and 22. Individual devices 25 include a pair of source / drain regions 24, 26 in upper portions of semiconductive material 12 on opposite sides of individual trenches 19 (e.g., regions 24, 26 are laterally outside and above access line structures 18). At least a portion of each of source / drain regions 24, 26 has therein a conductivity-increasing dopant having a maximum concentration of such dopant within the respective source / drain region 24, 26, e.g., to render such portion conductive (e.g., having at least 10 19 Atom / cm 3 Thus, all or only a portion of each source / drain region 24, 26 may have this maximum concentration of conductivity-increasing dopant. Source / drain regions 24 and / or 26 may include other doped regions (not shown), such as halo regions, LDD regions, etc.

[0022] One of the source / drain regions of the pair of source / drain regions (e.g., region 26) in individual pairs of recessed access devices 25 is laterally interposed between the conductive gate material 22 and is shared by the pair of devices 25. The other of the source / drain regions of the pair of source / drain regions (e.g., region 24) is not shared by the pair of devices 25. Thus, in an example embodiment, each active area region 16 includes two devices 25 (e.g., a pair of devices 25), each of which shares a central source / drain region 26.

[0023] Example channel region 27 ( Figure 1 , 3 , 7 and 8) are located in the semiconductive material 12 below a pair of source / drain regions 24, 26 and along the trench sidewall 21 ( Figure 7 and 8) and surrounds the trench base 23. The channel region 27 may be undoped or may be suitably doped with a conductivity-increasing dopant that may have a conductivity type opposite to that of the dopant in the source / drain regions 24, 26, and, for example, has a maximum concentration in the channel of no greater than 1×10 17 Atom / cm 3 When a suitable voltage is applied to the gate material 22 of the access line structure 18, a conductive channel is formed within the channel region 27 near the gate insulator 20 (eg, along the channel current flow line / path 28 [ Figure 8 ]), so that current can flow between a pair of source / drain regions 24 and 26 located below the access line structure 18 within the respective active area region 16. The stippling is shown schematically to indicate the primary conductivity-modifying dopant concentration (regardless of type), with denser stippling indicating higher dopant concentrations and lighter stippling indicating lower dopant concentrations. The conductivity-modifying dopant can and likely is in other portions of the material 12, as shown. For convenience, only two different stippling densities are shown in the material 12, and additional dopant concentrations may be used, and a constant dopant concentration is not required in any region.

[0024] The first conductive / conductor paths 36 are individually directly electrically coupled to one of the source / drain regions (eg, 24) in the pair of source / drain regions. A storage element (eg, capacitor 85) is directly electrically coupled to the individual first conductive / conductor paths 36.

[0025] The second conductive vias 33 are individually directly electrically coupled to the other of the source / drain regions (e.g., 26) in the pair of source / drain regions. The second vias 33 are spaced relative to each other (e.g., longitudinally relative to the digit line 39 thereon, as described below) through intermediate materials (e.g., one or more of materials 32, 37, 14, 38, 48, and / or 46 when present, wherein materials 32, 38, 48, and 46 are described below) and include conductive materials (e.g., 34 and 35). In one embodiment, the conductive materials 34 / 35 of the second vias 33 include a lower conductive-doped semiconductive material 34 (e.g., conductive-doped polysilicon) below an upper conductive material 35 (e.g., a metal material) having a composition different from that of the conductive-doped semiconductive material 34. Additional example conductive materials for materials 34 and 35, by way of example only, include metal nitrides (e.g., TiN, TaN, WN, MoN), metal carbonitrides (e.g., TiCN, TaCN, WCN, MoCN), and elemental metals (e.g., Ti, Ta, W, Mo, Co, Cu, Ru, Be), including combinations, compounds, and alloys thereof.

[0026] A digit line 39 is on top of the intermediate materials 32, 37, 14, 38, 48, 46 between the second vias 33 and directly electrically coupled to the individual second vias 33 of the plurality of transistors 25. The digit line 39 includes a metal material 42 (e.g., elemental W, Ru, and / or Mo) directly against the conductive material 34 / 35 of the second vias 33. The example digit line 39 includes a portion of the digit line structure 30 including opposite longitudinal insulating sides 38 (e.g., silicon dioxide and / or silicon nitride) and an insulating cap 50 (e.g., silicon nitride and / or silicon dioxide). The example material 46 is below the digit line 39 between the second vias 33 that are adjacent in the longitudinal direction. An under-insulating material 48 (e.g., one or more of silicon dioxide, silicon nitride, aluminum dioxide, hafnium oxide, etc.; e.g., 50 to 200 angstroms thick) is below the material 46 between the second vias 33 that are adjacent in the longitudinal direction. Material 46 may be insulating, semiconductive (ie, material that is not sufficiently doped to be conductive), or conductive or may be eliminated, with metallic material 42 extending inwardly to underlying insulating material 48 (not shown).

[0027] In one embodiment, the uppermost portion of the intermediate material (e.g., the uppermost portion of one or both of materials 32 and 46) comprises an insulating material, in one embodiment a conductive material, and in one embodiment a semiconductive material (i.e., not fully doped to be conductive). In one embodiment, if conductive, the uppermost portion of the intermediate material comprises a conductively doped semiconductive material. In one embodiment, the uppermost portion of the intermediate material comprises an insulating material and a conductive material. By way of example only, example insulating materials include silicon dioxide, silicon nitride, aluminum oxide, high-k materials, low-k materials, hafnium oxide, zirconium oxide, and insulating metal oxides including combinations of two or more elemental metals. Example conductive materials include conductively doped polysilicon as example conductively doped semiconductive materials and metallic materials. Example semiconductive materials are undoped or lightly doped polysilicon.

[0028] The discontinuous material 55 is vertically between the digit line 39 and the conductive material 34 / 35 of the second via 33, and vertically between the intermediate materials 32, 46 between the digit line 39 and the second via 33. The discontinuous material 55 has a composition different from the composition of the metal material 42 of the digit line 39. In one embodiment and as shown, the discontinuous material 55 includes void spaces therethrough (i.e., void spaces laterally between and among the spaced portions of the material 55), wherein the void spaces have a total horizontal area greater than the total horizontal area of ​​the material of the discontinuous material 55. In one embodiment, the discontinuous material is insulating, in one embodiment is conductive, in one embodiment is semiconductive, and in one embodiment includes elemental form silicon. In one embodiment, the discontinuous material 55 includes an elemental form metal (e.g., Ti, Ta, W, Mo, Co, Cu, Ru, Be), and in one embodiment has a composition different from the composition of the conductive material 34 / 35.

[0029] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0030] Embodiments of the present invention encompass integrated circuit system constructions (e.g., 8) that are independent of whether DRAM or other memory circuitry is included. This construction includes a plurality of conductive paths (e.g., 33) spaced relative to each other by intermediate materials (one or more of materials 32, 37, 14, 38, 48, and / or 46 when present). Conductive wires (e.g., 39) are on top of the intermediate materials between the paths and directly electrically coupled to the individual ones of the paths. The conductive wires include a metal material (e.g., 42) that is directly against the conductive material (e.g., 34 / 35) of the paths. Discontinuous material (e.g., 55) is vertically between the conductive wire and the conductive material of the paths and vertically between the conductive wire and the intermediate material located between the paths. The discontinuous material has a composition different from that of the metal material. In one embodiment, the conductive wire is part of a memory circuitry (e.g., a digit line) that includes a NAND architecture. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0031] Embodiments of the invention encompass a method for forming an integrated circuit system configuration (e.g., including DRAM, other memory and / or non-memory circuitry). Regardless, the method aspects of the invention may use or have any of the attributes described herein in the structural and / or device embodiments. Likewise, the structural embodiments described above may incorporate any of the attributes described with respect to the method embodiment aspects.

[0032] Initial reference Figures 9 to 29 Description used to generate Figures 1 to 8 Example method embodiment of construction 8 and example of this embodiment. Fig. 9 and 10 , this display Figure 1 and 7 A predecessor construction of a construction in which structure 8 has been fabricated to the point where it includes materials 46 and 48 within array 10. Figures 11 to 13 Opening 56 is shown formed therethrough to source / drain regions 26 , and in one embodiment as shown to a height below the bottom of material 48 .

[0033] refer to Figures 14 to 16 , opening 56 has been lined with insulating material 32, which is then anisotropically etched to remove material 32 centrally over source / drain region 26. Conductive material 34 / 35 is then formed and planarized back to at least the vertical outermost surfaces of materials 46 and 32. This includes only one example of forming conductive paths 33, which are individually directly electrically coupled to one of the source / drain regions (e.g., 26) in the pair of source / drain regions. Conductive paths 33 are spaced relative to each other through intermediate materials (e.g., one or more of materials 32, 37, 14, 48, and / or 46 when present) and include conductive materials 34 / 35. In one such embodiment, the method sequentially includes forming a lower conductive doped semiconductor material (e.g., 34) within opening 56 in the intermediate material. For example, this may be formed to completely fill the remaining volume of opening 56, and then planarized back to at least the vertical outermost surfaces of materials 32 and 46. Then, conductively-doped semiconductor material 34 is vertically recessed (e.g., by etching) within opening 56. Thereafter, conductor material 35 is formed within opening 56 on top of vertically recessed conductively-doped semiconductor material 34, e.g., to overfill the remaining volume of opening 56, and then planarized back to at least the vertically outermost surfaces of materials 32 and 46.

[0034] refer to Figures 17 to 19 , discontinuous material 55 has been formed on top of the conductive material 34 / 35 of the conductive via 33 and on top of the intermediate materials 32 and 46 between the conductive vias 33 .

[0035] refer to Figures 20 to 22 , metal material 42 has been formed on top of, directly against and between discontinuous material 55 and on top of and directly against conductive material 34 / 35 of conductive via 33 and over intermediate materials 32 and 46 between conductive vias 33. Discontinuous material 55 may be used as a crystal growth seed material to promote the growth of metal material 42 so that metal material 42 is formed in a desired crystal orientation / phase. Example insulating material 50 has been formed on top thereof.

[0036] refer to Figures 23 to 25, metal material 42 having discontinuous material 55 thereunder has been formed (e.g., by subtractive etching) to include digit lines 39 atop intermediate material 32 and 46 between conductive vias 33 and directly against individual conductive vias 33 of a plurality of transistors 25. For example, and in one embodiment, a plurality of digit lines 39 have been formed by subtractive patterning and etching, wherein, in one example, etching removes discontinuous material 55 laterally between lines 39.

[0037] refer to Figures 26 to 28 , insulating spacers 38 leading to the formation of digit line structures 30 have been formed, and dielectric material 40 deposited therebetween. Fig.29 An opening 41 is shown formed therethrough to the source / drain region 24. Processing will then occur to produce Figures 1 to 8 For example, a conductor via 36 will be formed in the opening 41 to be directly electrically coupled to the other source / drain region 24 in the source / drain region pair. A storage element (e.g., capacitor 85) will be formed to be directly electrically coupled to an individual one of the conductor vias 36.

[0038] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0039] The example processing and depicted constructions described above show the formation of multiple digit lines 39 that are laterally spaced relative to each other, wherein discontinuous material is not laterally between such multiple digit lines 39. For example, Figures 23 to 25 The discontinuous material 55 is shown removed from between the digit lines 39. Alternatively, the discontinuous material may be laterally between multiple digit lines, such as with respect to Figures 30 to 32 8a and an alternative embodiment structural embodiment are shown and described in FIG. 8a. Like numerals from the above-described embodiments are used where appropriate, with some structural differences indicated by the suffix "a".

[0040] refer to Fig.30 and 31 , patterning metal material 42 to form digit lines 39 has left discontinuous material 55 laterally therebetween. Fig.32Subsequent processing is shown whereby the discontinuous material 55 is thus maintained outside the level of the conductive / conductor vias 36. In one embodiment, the discontinuous material 55 is non-insulating (e.g., elemental silicon), and the method further includes converting the non-insulating discontinuous material 55 to be lateral insulation between the plurality of conductive lines (e.g., by annealing in an oxygen-containing environment). For example, and by way of example only, elemental silicon as material 55 may be annealed in an oxygen-containing environment to form silicon dioxide material 55, or the conductive material 55 may be coated with a non-conductive material. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] Embodiments of the present invention encompass a method for forming an integrated circuit system, regardless of whether the circuit system is a DRAM or other memory circuit system. The method includes forming a plurality of conductive paths (e.g., 33) including conductive materials (e.g., 34 / 35). The conductive paths are spaced relative to each other by intermediate materials (e.g., one or more of materials 32, 37, 14, 38, 48, and / or 46 when present). Discontinuous materials (e.g., 55) are formed on top of the conductive materials of the paths and on top of the intermediate materials between the paths. Metal materials (e.g., 42) are formed on top of the discontinuous materials, directly against the discontinuous materials, and between the discontinuous materials and on top of the conductive materials of the paths and directly against the conductive materials of the paths. The metal material has a composition different from that of the discontinuous materials and is on top of the intermediate materials between the paths. A metal material with discontinuous materials below is formed to include conductive lines (e.g., 39) on top of the intermediate materials between the paths and directly against the individual ones in the paths. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0042] The above processing or construction may be considered to be relative to an array of components that is formed as a single stack or single level of such components or within a single stack or single level of such components on or as part of an underlying base substrate (although a single stack / level may have multiple layers). Control circuits and / or other peripheral circuits for operating or accessing such components in the array may also be formed anywhere as part of the completed construction, and in some embodiments, may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / levels may be provided or fabricated above and / or below the stacks / levels shown in the drawings or described above. In addition, the arrays of components may be the same or different relative to each other in different stacks / levels. Intermediate structures (e.g., additional circuits and / or dielectric layers) may be provided between closely vertically adjacent stacks / levels. In addition, different stacks / levels may be electrically coupled relative to each other. Multiple stacks / levels may be fabricated individually and sequentially (e.g., one above another), or two or more stacks / levels may be fabricated substantially simultaneously.

[0043] The assemblies and structures discussed above can be used in integrated circuits and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0044] In this document, unless otherwise indicated, "vertical", "higher", "up", "down", "top", "at the top of...", "bottom", "above", "below", "below", "below", "upward", and "downward" are generally with reference to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees), and can be relative to the direction in which the substrate is processed during manufacturing, and vertical is a direction generally orthogonal to the horizontal. By "completely horizontal" is meant a direction along the surface of the main substrate (i.e., not at an angle to the surface of the main substrate), and can be relative to the direction in which the substrate is processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally with respect to directions that are perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to directions that are at least 45° apart in angle from completely horizontal. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending" and the like with respect to field effect transistors are with reference to the orientation of the channel length of the transistor along which current flows in operation between source / drain regions. For bipolar junction transistors, "extending vertically", "extending vertically", extending horizontally, extending horizontally, and the like are referenced to the orientation of the base length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or extends within 10° of vertical.

[0045] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to one another. Furthermore, the use of "above" without a preceding "directly" requires only that some portion of the stated region / material / component that is above another stated region / material / component is vertically outside of the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated region / material / component that is below / beneath another stated region / material / component is vertically inside of the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components).

[0046] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any event may be continuous or discontinuous over any material overlying any of the materials, regions, and structures. Where one or more example components are provided for any material, the material may comprise, consist essentially of, or consist of such one or more components. Furthermore, unless otherwise specified, each material may be formed using any suitable present or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0047] In addition, "thickness" itself (without a preceding directional adjective) is defined as the average straight-line distance perpendicularly through a given material or region from the closest surface of an adjacent material or adjacent region of different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and since the thickness is variable, this material or region will have a certain minimum thickness and a certain maximum thickness. As used herein, "different composition" requires only those parts of the two stated materials or regions that can directly abut against each other to be chemically and / or physically different, for example, provided that such materials or regions are not homogeneous. If the two stated materials or regions are not directly against each other, then "different composition" requires only those parts of the two stated materials or regions that are closest to each other to be chemically and / or physically different, provided that this material or region is not homogeneous. In this document, when the materials, regions or structures are in at least some physical touching contact relative to each other, the stated materials, regions or structures are "directly against" each other. In contrast, "over," "on," "adjacent," "along," and "against" without the word "directly" in front of them encompass "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical touching contact between the stated materials, regions, or structures relative to each other.

[0048] As used herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current can flow continuously from one region-material-component to another region-material-component, and when sufficient subatomic positive and / or negative charge is generated, the flow is primarily achieved by the movement of subatomic positive and / or negative charge. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0049] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any or a combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0050] As used herein, "selective" with respect to etching / etching, removing / removal, depositing, forming / formation is the action of doing so with respect to one stated material relative to another stated material at a ratio of at least 2:1 by volume. Additionally, selectively depositing, selectively growing, or selectively forming means depositing, growing, or forming one material relative to another stated material at a ratio of at least 2:1 by volume for at least the first 75 angstroms of the deposition, growth, or formation.

[0051] Unless stated otherwise, the use of "or" herein includes either and both.

[0052] in conclusion

[0053] In some embodiments, a method for forming an integrated circuit system includes forming a plurality of conductive paths including conductive material. The conductive paths are spaced relative to each other by intermediate materials. Discontinuous materials are formed on top of the conductive material of the paths and on top of the intermediate materials between the paths. Metal materials are formed on top of the discontinuous materials, directly against the discontinuous materials and between the discontinuous materials and on top of the conductive material of the paths and directly against the conductive material of the paths. The metal material has a composition different from that of the discontinuous materials and is on top of the intermediate materials between the paths. The metal material with discontinuous materials thereunder is formed to include conductive lines on top of the intermediate materials between the paths and directly against individuals in the paths.

[0054] In some embodiments, a method for forming a DRAM circuit system includes forming transistors, each of which includes: a pair of source / drain regions; a channel region between the pair of source / drain regions; a conductive gate operatively adjacent to the channel region; and a gate insulator between the conductive gate and the channel region. Conductive paths are formed that are individually directly electrically coupled to one of the source / drain regions of the pair. The conductive paths are spaced relative to each other by intermediate materials and include conductive materials. Discontinuous materials are formed on top of the conductive materials of the conductive paths and on top of the intermediate materials between the conductive paths. Metal materials are formed on top of the discontinuous materials, directly against the discontinuous materials, and between the discontinuous materials and on top of the conductive materials of the paths and directly against the conductive materials of the conductive paths. The metal materials have a composition different from that of the discontinuous materials and are on top of the intermediate materials between the conductive paths. The metal materials with discontinuous materials thereunder are formed to include digit lines on top of the intermediate materials between the conductive paths and directly against the individual ones of the conductive paths of a plurality of the transistors. Conductor pathways are formed that are individually and directly electrically coupled to the other source / drain region of the pair. Storage elements are formed that are directly and electrically coupled to individual ones of the conductor pathways.

[0055] In some embodiments, an integrated circuit system includes a plurality of conductive pathways including conductive material. The conductive pathways are spaced relative to each other by intermediate materials. Conductive wires are on top of the intermediate materials between the pathways and directly electrically coupled to individuals of the pathways. The conductive wires include a metallic material directly against the conductive material of the pathways. A discontinuous material is vertically between the conductive wires and the conductive material of the pathways and vertically between the conductive wires and the intermediate materials between the pathways. The discontinuous material has a composition different from that of the metallic material.

[0056] In some embodiments, a DRAM circuit system includes transistors, each of which includes: a pair of source / drain regions; a channel region between the pair of source / drain regions; a conductive gate operatively adjacent to the channel region; and a gate insulator between the conductive gate and the channel region. A first conductive path is individually directly electrically coupled to one of the source / drain regions of the pair. A storage element is directly electrically coupled to an individual of the first conductive paths, and a second conductive path is individually directly electrically coupled to the other of the source / drain regions of the pair. The second conductive paths are spaced relative to each other by an intermediate material and include a conductive material. A digit line is on top of the intermediate material between the second paths and directly electrically coupled to an individual of the second paths of a plurality of the transistors. The digit line includes a metal material directly against the conductive material of the second path. A discontinuous material is vertically between the digit line and the conductive material of the second path and vertically between the digit line and the intermediate material between the second paths. The discontinuous material has a composition different from that of the metal material.

Claims

1. A method for forming an integrated circuit system, comprising: forming a plurality of conductive pathways comprising a conductive material, the conductive pathways being spaced relative to one another by an intermediate material; forming a discontinuous material on top of the conductive material of the conductive vias and on top of the intermediate material between the conductive vias; forming a metallic material on top of, directly against and between the discontinuous materials and on top of and directly against the conductive material of the conductive pathways, the metallic material having a different composition than the discontinuous materials and over the intermediate material between the conductive pathways; and The metallic material is formed with discontinuous material thereunder to include conductive lines on top of the intermediate material between the conductive vias and directly against individual ones of the conductive vias.

2. The method of claim 1, comprising forming the conductive material of the conductive via to include a lower conductive-doped semiconductive material beneath an upper conductive material, the upper conductive material having a composition different from a composition of the lower conductive-doped semiconductive material.

3. The method according to claim 2, which sequentially comprises: forming the lower conductive doped semiconductive material within the opening of the intermediate material; vertically recessing the conductive-doped semiconductive material in the opening; and The conductor material is formed on top of the vertically recessed conductive-doped semiconductive material within the opening. The method of claim 1 , wherein the discontinuous material is insulating. The method of claim 1 , wherein the discontinuous material is electrically conductive. The method of claim 1 , wherein the discontinuous material comprises silicon in elemental form.

7. The method of claim 1, wherein the discontinuous material includes void spaces therethrough, the void spaces having a total horizontal area greater than a total horizontal area of ​​the material of the discontinuous material.

8. The method of claim 1, comprising forming a plurality of said conductive lines laterally spaced relative to one another, said discontinuous material laterally between said plurality of conductive lines.

9. The method of claim 8, wherein the discontinuous material is non-insulating, and the method further comprises converting the non-insulating discontinuous material into lateral insulation between the plurality of conductive lines.

10. The method of claim 8, wherein the plurality of conductive lines are formed by subtractive patterning and etching, the etching removing the discontinuous material laterally between the plurality of conductive lines.

11. The method of claim 1 , comprising forming a plurality of said conductive lines laterally spaced relative to one another, said discontinuous material not laterally between said plurality of conductive lines.

12. The method of claim 1, wherein an uppermost portion of the intermediate material comprises an insulating material.

13. The method of claim 1, wherein an uppermost portion of the intermediate material comprises a conductive material.

14. The method of claim 13, wherein the conductive material comprises a conductively doped semiconductive material.

15. The method of claim 1, wherein an uppermost portion of the intermediate material comprises a semiconductive material.

16. The method of claim 1, wherein an uppermost portion of the intermediate material comprises an insulating material and a conductive material.

17. A method for forming a DRAM circuit system, comprising: forming transistors, which individually include: a pair of source / drain regions; a channel region between the pair of source / drain regions; a conductive gate operably proximate to the channel region; and a gate insulator between the conductive gate and the channel region; forming conductive pathways individually and directly electrically coupled to one of the pair of source / drain regions, the conductive pathways being spaced relative to one another by an intervening material and comprising a conductive material; forming a discontinuous material on top of the conductive material of the conductive vias and on top of the intermediate material between the conductive vias; forming a metallic material on top of, directly against and between the discontinuous materials and on top of and directly against the conductive material of the conductive pathways, the metallic material having a different composition than the composition of the discontinuous materials and over the intermediate material between the conductive pathways; forming the metal material having discontinuous material thereunder to include digit lines on top of the intermediate material between the conductive pathways and directly against individual ones of the conductive pathways of a plurality of the transistors; forming conductor paths that are individually and directly electrically coupled to the other source / drain region of the pair; and Storage elements are formed that are electrically coupled directly to individual ones of the conductor pathways.

18. An integrated circuit system comprising: a plurality of conductive pathways comprising conductive material, the conductive pathways being spaced relative to one another by intermediate material; a conductive line on top of the intermediate material between the conductive pathways and directly electrically coupled to individual ones of the conductive pathways, the conductive line comprising a metallic material directly against the conductive material of the conductive pathways; and A discontinuous material is vertically between the conductive line and the conductive material of the conductive pathway and vertically between the conductive line and the intermediate material between the conductive pathways, the discontinuous material having a composition different from that of the metallic material.

19. The integrated circuit system of claim 18, wherein the conductive material of the conductive via comprises a lower conductive doped semiconductive material beneath an upper conductive material, the upper conductive material having a composition different from a composition of the lower conductive doped semiconductive material.

20. The integrated circuit system of claim 19, wherein the conductively-doped semiconductive material comprises conductively-doped polysilicon.

21. The integrated circuit system of claim 18, wherein the conductive material comprises a metal nitride.

22. The integrated circuit system of claim 18, wherein the conductive material comprises a metal carbonitride.

23. The integrated circuit system of claim 18, wherein the conductive material comprises a metal in elemental form.

24. The integrated circuit system of claim 18, wherein the metallic material comprises at least one of elemental form Ru and elemental form Mo.

25. The integrated circuit system of claim 18, wherein the discontinuous material includes void spaces therethrough, the void spaces having a total horizontal area greater than a total horizontal area of ​​the material of the discontinuous material.

26. The integrated circuit system of claim 18, wherein the discontinuous material is insulating.

27. The integrated circuit system of claim 18, wherein the discontinuous material is electrically conductive.

28. The integrated circuit system of claim 27, wherein the discontinuous material has a composition that is the same as a composition of the conductive material.

29. The integrated circuit system of claim 27, wherein the discontinuous material comprises a metal in elemental form.

30. The integrated circuit system of claim 18, wherein the discontinuous material has a composition different than a composition of the conductive material.

31. The integrated circuit system of claim 18, wherein the discontinuous material comprises elemental silicon.

32. The integrated circuit system of claim 18, comprising a plurality of the conductive lines that are laterally spaced relative to one another, the discontinuous material not being laterally between the plurality of conductive lines.

33. The integrated circuit system of claim 18, comprising a plurality of the conductive lines laterally spaced relative to one another, the discontinuity material laterally between the plurality of conductive lines.

34. The integrated circuit system of claim 18, comprising a NAND, the conductive lines being digit lines.

35. A DRAM circuit system comprising: Transistors, individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; a conductive gate operably proximate to the channel region; and a gate insulator between the conductive gate and the channel region; a first conductive path electrically coupled directly to one of the pair of source / drain regions, respectively; a storage element electrically coupled directly to individual ones of the first conductive paths; second conductive paths individually and directly electrically coupled to the other of the pair of source / drain regions, the second conductive paths being spaced relative to each other by an intervening material and comprising a conductive material; a digit line on top of the intermediate material between the second conductive paths and directly electrically coupled to individual ones of the second conductive paths of a plurality of the transistors, the digit line comprising a metal material directly against the conductive material of the second conductive paths; and A discontinuous material is vertically between the digit line and the conductive material of the second conductive path and vertically between the digit line and the intermediate material between the second conductive paths, the discontinuous material having a composition different than that of the metallic material.

36. A DRAM circuit system according to claim 35, wherein the transistors are paired, one of the source / drain regions of the pair of source / drain regions in individual ones of the pair of transistors is between the conductive gates in the individual pair of transistors and shared by the individual pair of transistors, and the other of the source / drain regions in the pair of source / drain regions is not shared in the individual pair of transistors.

37. The DRAM circuit system of claim 36, wherein the pair of transistors comprises a pair of recessed access devices, the pair of recessed access devices individually comprising: the conductive gate in a trench in the semiconductive material; the gate insulator along the sidewalls and base of the trench between the conductive gate and the semiconductive material; the pair of source / drain regions in upper portions of the semiconductive material on opposite sides of the trench; and The channel region is in the semiconductive material below the pair of source / drain regions and along the trench sidewalls and around the trench base.

Images