Neuromorphic computing device and method of operation thereof

Abstract

A neuromorphic computing device includes a first memory cell array including a plurality of resistive memory cells and configured to output a plurality of read currents through a plurality of bit lines or source lines, a second memory cell array including a plurality of reference resistive memory cells and configured to output at least one reference current through at least one reference bit line or at least one reference source line, a current-voltage conversion circuit configured to output a plurality of signal voltages respectively corresponding to the plurality of read currents and to output at least one reference voltage corresponding to the at least one reference current, and an analog-to-digital conversion circuit configured to convert the plurality of signal voltages to a plurality of digital signals using the at least one reference voltage and to output the plurality of digital signals.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application 10-2020-0049485, filed with the Korean Intellectual Property Office on April 23, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a neuromorphic computing device and a method of operating the neuromorphic computing device, and more specifically, to a neuromorphic computing device for performing operations using resistive storage units and a method of operating the neuromorphic computing device. Background Technology

[0004] Applications including deep learning neural networks (NNs), or neuromorphic computing, such as image recognition, natural language processing, and various pattern matching or classification tasks, can become as important as general computing. The core computational element of an NN, or neuron, multiplies a set of input signals by a set of weights and sums the products. Therefore, neurons perform vector-matrix multiplication or multiplication-accumulation (MAC) operations. NNs typically consist of many interconnected neurons, and each neuron performs a MAC operation. Therefore, the operations of NNs are computationally intensive.

[0005] By creating artificial neural systems at the neuron level, semiconductor circuits manufactured by simulating information processing methods handled by the brain are neuromorphic computing devices or neuromorphic chips, and can be effectively used to realize intelligent systems that adapt to unspecified environments. Summary of the Invention

[0006] This disclosure provides a neuromorphic computing device and a method of operating the neuromorphic computing device, wherein the neuromorphic computing device minimizes inaccurate inferences generated by the neuromorphic computing device due to the temperature and / or time dependence of resistive storage cells.

[0007] According to an exemplary embodiment of the present invention, a neuromorphic computing device is provided, comprising: a first memory cell array including a plurality of resistive memory cells and configured to output a plurality of read currents through a plurality of bit lines or source lines; a second memory cell array including a plurality of reference resistive memory cells and configured to output at least one reference current through at least one reference bit line or at least one reference source line; a current-to-voltage conversion circuit configured to output a plurality of signal voltages corresponding to the plurality of read currents and to output at least one reference voltage corresponding to the at least one reference current; and an analog-to-digital conversion circuit configured to convert the plurality of signal voltages into a plurality of digital signals using the at least one reference voltage and to output the plurality of digital signals.

[0008] According to an exemplary embodiment of the present invention, a method of operating a neuromorphic computing device is provided, the neuromorphic computing device including a first memory cell array including main resistive memory cells and a second memory cell array including reference memory cells, the method of operating comprising: activating all reference word lines connected to the second memory cell array; obtaining at least one reference voltage value based on at least one reference current output from the second memory cell array; and outputting a plurality of digital signals by converting a signal voltage value corresponding to a read current output from the first memory cell array using the at least one reference voltage value.

[0009] According to an exemplary embodiment of the present invention, a neuromorphic computing device is provided, comprising: A first resistive memory cell array includes multiple resistive memory cells arranged in regions where multiple word lines intersect with multiple bit lines; a second resistive memory cell array includes multiple reference resistive memory cells arranged in regions where multiple reference word lines intersect with multiple reference bit lines; a word line driver configured to drive multiple word lines and multiple reference word lines, activate at least one select word line among the multiple word lines based on the element value of an input feature vector, and activate all multiple reference word lines; a current-to-voltage conversion circuit configured to convert multiple reference currents output from the second resistive memory cell array into multiple reference voltages through an electrical path including multiple reference bit lines, and to convert multiple read currents output from the first resistive memory cell array into multiple signal voltages through an electrical path including multiple bit lines based on the activation of at least one select word line; an analog-to-digital conversion circuit configured to use the multiple reference voltages as references for analog-to-digital conversion, convert the multiple signal voltages into multiple digital signals, and output the multiple digital signals; and an adder circuit configured to use the multiple digital signals to generate at least one output data by performing an accumulation and / or summation operation.

[0010] According to an exemplary embodiment of the present invention, a method of operating a neuromorphic computing device is provided. The neuromorphic computing device includes a first memory cell array having main resistive memory cells connected to multiple word lines and a second memory cell array having reference resistive memory cells connected to multiple reference word lines. The method of operating the device includes: activating a selected word line among the multiple word lines based on element values ​​of an input feature vector used in computation within the neuromorphic computing device; activating all multiple reference word lines; and outputting multiple digital signals by converting a signal voltage value corresponding to a read current output from the first memory cell array into multiple digital signals, based on the activation of the selected word line, using at least one reference voltage value corresponding to at least one reference current output from the second memory cell array.

[0011] According to an exemplary embodiment of the present invention, a neuromorphic computing device is provided for converting current output from a cross-switch array into a digital signal, comprising: a first memory cell array having a plurality of resistive memory cells respectively connected to a plurality of word lines; a second memory cell array having a plurality of reference resistive memory cells arranged in regions where the plurality of reference word lines intersect with a plurality of reference bit lines, wherein the reference resistive memory cells have a resistive material of the same material as the plurality of resistive memory cells; and a word line driver configured to drive the plurality of word lines and the plurality of reference word lines and to activate all of the plurality of reference word lines during operation of the neuromorphic computing device, wherein the number of reference bit lines may be the same as the number obtained by subtracting 1 from a power of 2 raised to the power of the number of bits of the digital signal.

[0012] According to an exemplary embodiment of the present invention, a neuromorphic circuit includes: a first memory cell array having a plurality of memory cells, each memory cell being connected between a corresponding word line of a first plurality of word lines and a corresponding bit line of a second plurality of bit lines; and a second memory cell array having a plurality of reference memory cells, each reference memory cell being connected between a corresponding reference word line of the first plurality of reference word lines and a corresponding reference bit line of a third plurality of reference bit lines; wherein the number of the third plurality of reference bit lines is a power of one raised to the power of the number of states per bit, with the number of bits per memory cell as the base. Attached Figure Description

[0013] The embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0014] Figure 1 This is a block diagram illustrating a neuromorphic computing device according to an embodiment of the concept of the present invention;

[0015] Figure 2A and Figure 2BThis is a block diagram illustrating an example of a neural network system driven by a neuromorphic computing device according to an embodiment of the present invention.

[0016] Figure 3A , Figure 3B and Figure 3C This is a circuit diagram illustrating a first memory cell array according to an embodiment of the concept of the present invention;

[0017] Figure 4A and Figure 4B This is a circuit diagram illustrating a second memory cell array according to an embodiment of the concept of the present invention;

[0018] Figure 5 It is a graphical diagram illustrating the operating voltage range and multiple reference voltages of an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0019] Figure 6 This is a circuit diagram illustrating the state of a second memory cell array and a reference memory cell according to an embodiment of the present invention.

[0020] Figure 7A This is a block diagram illustrating an analog-to-digital conversion circuit according to an embodiment of the concept of the present invention;

[0021] Figure 7B This is a block diagram illustrating a neuromorphic computing device according to an embodiment of the concept of the present invention;

[0022] Figure 8 This is a block diagram illustrating an analog-to-digital converter according to an embodiment of the concept of the present invention;

[0023] Figure 9 This is a block diagram illustrating an analog-to-digital converter according to an embodiment of the concept of the present invention.

[0024] Figure 10 It is a graphical diagram illustrating the operating voltage range and multiple reference voltages of an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0025] Figure 11 This is a circuit diagram illustrating the state of a second memory cell array and a reference memory cell according to an embodiment of the present invention.

[0026] Figure 12 This is a circuit diagram illustrating a second memory cell array according to an embodiment of the present invention.

[0027] Figure 13 This is a block diagram illustrating an analog-to-digital converter according to an embodiment of the concept of the present invention;

[0028] Figure 14 This is a flowchart of an operation method of a neuromorphic computing device according to an embodiment of the present invention; and

[0029] Figure 15 This is a block diagram illustrating an electronic system according to an embodiment of the inventive concept. Detailed Implementation

[0030] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 A neuromorphic computing device 10 according to an embodiment of the present invention is shown.

[0032] The neuromorphic computing device 10 may include a first memory cell array 100, a second memory cell array 200, a word line driver 150, a current-to-voltage conversion circuit 300, an analog-to-digital conversion circuit 400, and an adder circuit 500. Similarly, the neuromorphic circuit device may include, but is not limited to, a current-to-voltage conversion circuit 300 coupled to the first memory cell array 100 and the second memory cell array 200; an analog-to-digital conversion circuit 400 coupled to the current-to-voltage conversion circuit; and an adder circuit 500 coupled to the analog-to-digital conversion circuit.

[0033] In one embodiment, the following reference is made Figure 2A and Figure 2B The neuromorphic computing device 10 can be used to drive any neural network system, such as an artificial neural network (ANN) system, a convolutional neural network (CNN) system, a deep neural network (DNN) system, a deep learning system, and / or a machine learning system. For example, various services and / or applications, such as image classification services, biometric-based user authentication services, advanced driver assistance systems (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., can be executed and processed by the neuromorphic computing device 10. In this case, the data stored in the first storage cell array 100 can be weights included in multiple layers constituting the neural network system, and multiple read currents (Iread_1, Iread_2, ..., Iread_M) and multiple signal voltages (Vsig_1, Vsig_2, ..., Vsig_M) can indicate the result of a multiplication-accumulation operation performed by the neural network system. In other words, the first storage cell array 100 can immediately perform data storage and computation operations, as described in subsequent references. Figure 3B The neuromorphic circuit of the exemplary embodiment may include memory cells RMC of a first array 100 formed as resistive memory cells and reference memory cells RRMC of a second array 200. The values ​​stored by the memory cells RMC may correspond to the weights of the input signals to be applied in the neuromorphic circuit.

[0034] The first memory cell array 100 may include multiple resistive memory cells RMC, which are arranged in the region where multiple word lines WL1, WL2, ..., WLN (N is a natural number of 2 or greater) intersect with multiple bit lines BL1, BL2, ..., BLM (M is a natural number of 2 or greater). Each of the multiple resistive memory cells may include a resistive element RE. Detailed structure of the first memory cell array 100 will be provided in a later reference. Figure 3A and Figure 3C Describe it.

[0035] The first memory cell array 100 can store multiple data entries. For example, multiple data entries can be stored in multiple resistive memory cells RMC by using the resistance variation of the resistive element RE included in each of the multiple resistive memory cells RMC. Similarly, multiple word lines WL1, WL2, ..., WLN connected to the first memory cell array 100 can be driven by word line driver 150. The first memory cell array 100 can output multiple read currents Iread_1, Iread_2, ..., Iread_M corresponding to multiple signal voltages Vsig_1, Vsig_2, ..., Vsig_M, respectively. For example, the first memory cell array 100 can output multiple read currents Iread_1, Iread_2, ..., Iread_M through electrical paths including bit lines BL1, BL2, ..., BLM, respectively. The first memory cell array 100 can provide the first read current Iread_1 to the Mth read current Iread_M to the current-to-voltage conversion circuit 300.

[0036] The second memory cell array 200 may include multiple reference resistor memory cells RRMC, which are arranged in the region where multiple reference word lines RWL1, RWL2, ..., RWLN intersect with multiple reference bit lines RBL1, RBL2, ..., RBLn (n is a natural number of 2 or greater). Figure 1 The illustration shows an embodiment where the second memory cell array 200 is connected to multiple reference bit lines RBL1, RBL2, ..., RBLn, but is not limited thereto, and for example, the second memory cell array 200 may be connected to a single reference bit line. The number of reference bit lines connected to the second memory cell array 200 will be described below. Each of the multiple reference resistor memory cells RRMC may include a resistive element RE. The specific structure of the second memory cell array 200 will be described in subsequent references. Figure 4A and Figure 4B Describe it.

[0037] In one embodiment, each of the plurality of reference resistor memory cells RRMCs included in the second memory cell array 200 may include the same resistive material as the plurality of resistor memory cells RMCs included in the first memory cell array 100.

[0038] Furthermore, in one embodiment, the number of reference bit lines connected to the second memory cell array 200 can be determined based on the number of bits in the digital signals DS_1, DS_2, ..., DS_M described below. For example, when each of the digital signals DS_1, DS_2, ..., DS_M has k bits, the number of reference bit lines connected to the second memory cell array 200 can correspond to the number obtained by subtracting 1 from 2 to the power of k. For example, when the digital signals DS_1, DS_2, ..., DS_M are 1-bit digital signals, the second memory cell array 200 can be connected to one reference bit line, and when the digital signals DS_1, DS_2, ..., DS_M are 2-bit digital signals, the second memory cell array 200 can be connected to three reference bit lines.

[0039] The second memory cell array 200 can output multiple reference currents Iref_1, Iref_2, ..., Iref_n, each corresponding to a plurality of reference voltages Vref_1, Vref_2, ..., Vref_n. For example, the second memory cell array 200 can output multiple reference currents Iref_1, Iref_2, ..., Iref_n through electrical paths including reference bit lines RBL1, RBL2, ..., RBLn. The second memory cell array 200 can provide the first reference current Iref_1 to the nth reference current Iref_n to the current-to-voltage conversion circuit 300.

[0040] The word line driver 150 can drive multiple word lines WL1, WL2, ..., WLN connected to the first memory cell array 100 and multiple reference word lines RWL1, RLW2, ..., RWLN connected to the second memory cell array 200.

[0041] For example, based on the element values ​​of the input feature vector used in the operation of the neuromorphic computing device 10, the word line driver 150 can drive multiple word lines WL1, WL2, ..., WLN such that at least one word line selected from the multiple word lines WL1, WL2, ..., WLN is activated. For example, when each element value of the input feature vector of length N is "1" or "0", the word line driver 150 can drive multiple word lines WL1, WL2, ..., WLN such that the word line corresponding to the position of the element with the value "1" is activated.

[0042] The word line driver 150 can drive multiple reference word lines RWL1, RWL2, ..., RWLN, such that all multiple reference word lines RWL1, RWL2, ..., RWLN are activated during the operation period of the neuromorphic computing device 10.

[0043] The current-to-voltage conversion circuit 300 can convert an input current signal into a voltage signal. For example, the current-to-voltage conversion circuit 300 can convert a first read current Iread_1 to output a first signal voltage Vsig_1, convert a second read current Iread_2 to output a second signal voltage Vsig_2, and in the same manner, convert an Mth read current Iread_M to output an Mth signal voltage Vsig_M. Similarly, for example, the current-to-voltage conversion circuit 300 can convert a first reference current Iref_1 to output a first reference voltage Vref_1, convert a second reference current Iref_2 to output a second reference voltage Vref_2, and in the same manner, convert an nth reference current Iref_n to output an nth reference voltage Vref_n. Therefore, the current-to-voltage conversion circuit 300 can include a plurality of current-to-voltage converters, wherein the number of current-to-voltage converters can be the same as the number of input current signals, and, according to one embodiment, can be less than the number of input current signals. In the latter case (when the number of current-to-voltage converters is less than the number of input current signals), the current-to-voltage converters can sequentially convert the input current signals into voltage signals. The current-to-voltage conversion circuit 300 can provide multiple signal voltages Vsig_1, Vsig_2, ..., Vsig_M and multiple reference voltages Vref_1, Vref_2, ..., Vref_n to the analog-to-digital conversion circuit 400.

[0044] The analog-to-digital converter (ADC) 400 can use multiple reference voltages Vref_1, Vref_2, ..., Vref_n to convert multiple signal voltages Vsig_1, Vsig_2, ..., Vsig_M into multiple digital signals DS_1, DS_2, ..., DS_M, respectively, and can output multiple digital signals DS_1, DS_2, ..., DS_M. For example, the ADC 400 can use multiple reference voltages Vref_1, Vref_2, ..., Vref_n as references for analog-to-digital conversion to convert multiple signal voltages Vsig_1, Vsig_2, ..., Vsig_M into multiple digital signals DS_1, DS_2, ..., DS_M. For this purpose, the ADC 400 may include multiple analog-to-digital converters (ADCs), and the number of ADCs may be the same as the number of input signal voltages, and, according to one embodiment, may be less than the number of input signal voltages. Further reference will be made to Figures 7A and 7B. Figure 7BTo provide a more specific description, the analog-to-digital converter circuit 400 can provide multiple digital signals DS_1, DS_2, ..., DS_M to the adder circuit 500.

[0045] Adder circuit 500 can generate output data ODAT by performing accumulation and / or summation operations using multiple digital signals DS_1, DS_2, ..., DS_M. For example, adder circuit 500 can use multiple digital signals DS_1, DS_2, ..., DS_M to output first output data ODAT_1, second output data ODAT_2 to m-th output data ODAT_m. In one embodiment, adder circuit 500 may include at least one adder and at least one shift register.

[0046] Typically, the multiple resistive storage cells RMCs included in the first storage cell array 100 can be temperature-dependent and time-dependent. For example, the resistive element RE included in each of the multiple resistive storage cells RMCs can be temperature-dependent, where the resistance decreases as the temperature rises and increases as the temperature falls. Furthermore, the resistive element RE can be time-dependent, exhibiting characteristics such as a holding characteristic where resistance decreases over time, or, in some cases, a drift characteristic where resistance increases after a certain period of time following data writing. Therefore, the multiple read currents Iread_1, Iread_2, ..., Iread_M output from the first storage cell array 100 can depend on temperature and time, and it may be desirable to reduce or eliminate the impact of temperature and time dependence on accurate data storage and operation.

[0047] The neuromorphic circuit embodiment may include a word line driver circuit 150 configured to simultaneously or substantially simultaneously drive a corresponding word line WLi of a first plurality of word lines and a corresponding word line RWLi of a first plurality of reference word lines. The plurality of memory cells may include a cell material substantially the same as that of the plurality of reference memory cells, and the plurality of memory cells may have at least one of substantially the same temperature characteristics or substantially the same time decay characteristics as the plurality of reference memory cells.

[0048] According to an embodiment of the present invention, the neuromorphic computing device 10 can convert multiple signal voltages Vsig_1, Vsig_2, ..., Vsig_M into multiple digital signals DS_1, DS_2, ..., DS_M using multiple reference voltages Vref_1, Vref_2, ..., Vref_n, and obtain multiple reference voltages Vref_1, Vref_2, ..., Vref_n from multiple reference currents Iref_1, Iref_2, ..., Iref_n output from the second memory cell array 200, wherein the second memory cell array 200 includes the same resistive material as the resistive element RE included in the first memory cell array 100.

[0049] The second memory cell array 200 has the same temperature and / or time dependence as the first memory cell array 100, thereby preventing a decrease in the inference accuracy of the neuromorphic computing device 10 based on the temperature and / or time dependence of the multiple resistive memory cells RMC. In other words, according to embodiments of the present invention, the reliability and accuracy of the operation or inference of the neuromorphic computing device 10 can be improved.

[0050] Figure 2A and Figure 2B This is a diagram illustrating an example of a neural network system driven by a neuromorphic computing device according to an embodiment of the present invention.

[0051] refer to Figure 2A The network structure of a general neural network can include an input layer IL, multiple hidden layers HL1, HL2, ..., HLn, and an output layer OL.

[0052] The input layer IL can include i (where i is a natural number) input nodes x1, x2, ..., xi, and a vector input data IDAT of length i can be input to each input node.

[0053] Multiple hidden layers HL1, HL2, ..., HLn include n (where n is a natural number) hidden layers and hidden nodes h. 1 1,h 1 2,h 1 3, ..., h 1 m h 2 1,h 2 2,h 2 3, ..., h 2 m h n 1,h n 2,h n 3, ..., h nm For example, the hidden layer HL1 can include m (where m is a natural number) hidden nodes h. 1 1,h 1 2, h 1 3, ..., h 1 m The hidden layer HL2 can include m hidden nodes h 2 1,h 2 2,h 2 3, ..., h 2 m And the hidden layer HLn can include m hidden nodes h n 1,h n 2,h n 3, ..., h n m .

[0054] The output layer OL can include j (where j is a natural number) output nodes y1, y2, ..., yj corresponding to the categories to be classified, and can output the result (e.g., score or category score) for each category as output data ODAT for the input data IDAT. The output layer OL can be called a fully connected layer, and for example, the probability of the input data IDAT corresponding to a vehicle can be represented numerically.

[0055] Figure 2A The network structure shown may include branches between nodes, represented as straight lines between two nodes, and, although not shown, weights used in each of the respective branches. Nodes within the same layer do not need to be branched, and nodes included in different layers may be fully or partially branched.

[0056] Figure 2A Each node in (e.g., h) 1 1) It can receive and manipulate the output of previous nodes (e.g., x1), and can send output to subsequent nodes (e.g., h). 2 1) Output the result of the operation. At this point, each node can manipulate the value to be output by applying the input value to a specific function, such as a non-linear function.

[0057] Typically, the network structure of a neural network is predetermined, and appropriate values ​​are calculated using data with known correct answers, based on the weights of the branches between nodes, to determine which category the data belongs to. This data with known correct answers is called "learning data," and the process of determining the weights is called "learning." Alternatively, a set of structures and weights that can learn independently is called the "model," and the process of using the model with determined weights to predict which category the input data belongs to and output a predicted value is called the "testing" process.

[0058] refer to Figure 2B Specifically, it shows in Figure 2A The network structure includes an example of an operation performed in a node ND.

[0059] When N inputs a1, a2, a3, ..., a N When provided with a node ND, node ND can take N inputs a1, a2, a3, ..., a N and correspond to inputs a1, a2, a3, ..., a N N weights w1, w2, w3, ..., w N The input values ​​are multiplied and summed, the offset b is added to the summed input values, and the sum is applied as input to a specific function σ to generate an output value (e.g., z). It should be understood that the output z can be branched to outputs to one or more other nodes.

[0060] When included in, such as Figure 2A One layer of the network structure shown includes M elements such as Figure 2B When the node ND is shown, the output value of the first layer can be obtained by Equation 1 as shown below.

[0061] [Equation 1]

[0062] W*A=Z

[0063] In Equation 1 above, W represents the weight relative to the branches included in a layer, and can be implemented as an M*N matrix. A represents the N inputs a1, a2, a3, ..., a1 received from the layer. N Furthermore, it can be implemented as an N*1 matrix. Z represents the M outputs z1, z2, z3, ..., z from the first layer. M And it can be implemented in the form of an M*1 matrix.

[0064] Figure 3A , Figure 3B and Figure 3C First storage cell arrays 100a and 100b are shown according to embodiments of the present invention. Figures 3A to 3C The first memory cell arrays 100a and 100b shown can be connected with Figure 1 The first storage cell array 100 corresponds to this.

[0065] refer to Figure 3AThe first memory cell array 100a may include a plurality of resistive memory cells RMCs arranged in a region where a plurality of word lines WL1, WL2, ..., WLN intersect with a plurality of bit lines BL1, BL2, ..., BLM. Each of the plurality of resistive memory cells RMCs may include a resistive element RE and may be connected to one word line of the plurality of word lines WL1, WL2, ..., WLN and one bit line of the plurality of bit lines BL1, BL2, ..., BLM.

[0066] The resistance value of the resistive element RE can be changed by a write voltage applied by multiple word lines WL1, WL2, ..., WLN and / or multiple bit lines BL1, BL2, ..., BLM. Multiple resistive memory cells RMC can store data due to the resistance change. For example, when a write voltage is applied to the select word line and a ground voltage (e.g., approximately 0V) is applied to the selected bit line, the data "1" can be written to the selected resistive memory cell, and when a ground voltage is applied to the select word line and a write voltage is applied to the selected bit line, the data "0" can be written to the selected resistive memory cell. Furthermore, when a read voltage is applied to the select word line and a ground voltage is applied to the selected bit line, the data written to the selected resistive memory cell can be read.

[0067] In one embodiment, each of the plurality of resistive memory cells (RMCs) can be implemented by including any resistive memory cell, such as a phase-change random access memory (PRAM) cell, a resistive random access memory (RRAM) cell, a magnetic random access memory (MRAM) cell, a ferroelectric random access memory (FRAM) cell, etc.

[0068] In one embodiment, the resistive element RE may include a phase change material whose crystal state changes according to the amount of current. Various materials can be used for the phase change material, such as 2-element compounds GaSb, InSb, InSe, Sb₂Te₃ and / or GeTe, 3-element compounds GeSbTe, GaSeTe, InSbTe, SnSb₂Te₄ and / or InSbGe, and 4-element compounds AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and / or Te₈1Ge₁₅Sb₂S₂, etc. In another embodiment, the resistive element RE may include a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material. However, the resistive material included in the resistive element RE is not limited to the materials described above.

[0069] refer to Figure 3B , showing that Figure 3A First memory cell array 100a reference Figure 2AThe above operation is performed as shown in Figure 2B.

[0070] Each resistive storage cell (RMC) can correspond to a synapse or branch of a neural network system and can store a weight. Therefore, the M*N data stored in the first storage cell array 100a can correspond to the data included in the reference above. Figure 2A and Figure 2B The weight matrix in the aforementioned layer is implemented in the form of an M*N matrix, namely, W in [Equation 1] above.

[0071] The N input voltages V1, V2, ..., VN applied through multiple word lines WL1, WL2, ..., WLN can correspond to the N inputs a1, a2, a3, ..., aN received from a layer. N And it can correspond to the input matrix implemented in the form of an N*1 matrix, that is, A in [Equation 1] above.

[0072] The M read currents Iread_1, Iread_2, ..., Iread_M output through multiple bit lines BL1, BL2, ..., BLM can correspond to the M outputs z1, z2, z3, ..., z from layer 1. M And it can correspond to the output matrix implemented in the form of an M*1 matrix, that is, Z in the above [Equation 1].

[0073] In other words, when the first memory cell array 100a is implemented by storing multiple weights in multiple resistive memory cells (RMCs) in matrix form, when input voltages V1, V2, ..., VN corresponding to multiple input values ​​are input through multiple word lines WL1, WL2, ..., WLN, the read currents Iread_1, Iread_2, ..., Iread_M output through multiple bit lines BL1, BL2, ..., BLM can be the result of multiplication-accumulation operations performed by the neural network system. When multiple layers of the neural network system are implemented as described above, a neuromorphic computing device that performs both data storage and computation operations can be realized.

[0074] refer to Figure 3C The first memory cell array 100b may include multiple resistive memory cells RMC' arranged in a region where multiple word lines WL1, WL2, ..., WLN, multiple bit lines BL1, BL2, ..., BLM and multiple source lines SL1, SL2, ..., SLM intersect each other.

[0075] Each of the multiple resistive memory cells RMC' may include a cell transistor CT and a resistive element RE, and may be connected to one word line from multiple word lines WL1, WL2, ..., WLN, one bit line from multiple bit lines BL1, BL2, ..., BLM, and one source line from multiple source lines SL1, SL2, ..., SLM. For example, the cell transistor CT may include a first electrode, a second electrode connected to one source line from multiple source lines SL1, SL2, ..., SLM, and a gate electrode connected to one word line from multiple word lines WL1, WL2, ..., WLN. The resistive element RE may be connected between the second electrode of the cell transistor CT and one bit line from multiple bit lines BL1, BL2, ..., BLM.

[0076] For example, when a power supply voltage (e.g., VCC) is applied to the select word line, a write voltage is applied to the select bit line, and a ground voltage is applied to the select source line, the data "1" can be written to the selected resistor memory cell. Similarly, when a power supply voltage is applied to the select word line, a ground voltage is applied to the select bit line, and a write voltage is applied to the selected source line, the data "0" can be written to the selected resistor memory cell. Furthermore, when a power supply voltage is applied to the select word line, a read voltage is applied to the select bit line, and a ground voltage is applied to the selected source line, the data written to the selected resistor memory cell can be read.

[0077] The first memory cell array 100b can output multiple read currents Iread_1, Iread_2, ..., Iread_M through a circuit including multiple bit lines BL1, BL2, ..., BLM. In one embodiment, the first memory cell array 100b can output a first read current Iread_1 flowing through the first bit line BL1 and exiting through the first source line SL1, a second read current Iread_2 flowing through the second bit line BL2 and exiting through the second source line SL2, and an Mth read current Iread_M flowing through the Mth bit line BLM and exiting through the Mth source line SLM.

[0078] In addition, refer to Figure 3A , Figure 3B and Figure 3C The invention describes the formation of the first memory cell arrays 100a and 100b in a two-dimensional array structure, but the inventive concept is not limited thereto, and according to one embodiment, the first memory cell array can be formed in a three-dimensional vertical array structure. The structure of the resistive memory cells RMC and RMC' can also be changed according to the embodiment.

[0079] Figure 4A and Figure 4BSecond memory cell arrays 200a and 200b are shown according to embodiments of the present invention. Regarding... Figure 4A and Figure 4B The described second memory cell arrays 200a and 200b can correspond to Figure 1 The second storage cell array 200.

[0080] refer to Figure 4A The second memory cell array 200a may include a plurality of reference resistor memory cells RRMCs arranged in a region where a plurality of reference word lines RWL1, RWL2, ..., RWLN intersect with a plurality of reference bit lines RBL1, RBL2, ..., RBLn. Each of the plurality of reference resistor memory cells RRMCs may include a resistor element RE and may be connected to one of the plurality of reference word lines RWL1, RWL2, ..., RWLN and one of the plurality of reference bit lines RBL1, RBL2, ..., RBLn. In one embodiment, the resistor element RE may include a resistor element RE connected to the first memory cell array ( Figure 1 The 100) resistor element RE is made of the same resistive material and can be obtained from Figure 1 and Figure 3A Understand its detailed description from the description.

[0081] The second memory cell array 200a can output multiple reference currents Iref_1, Iref_2, ..., Iref_n through an electrical path including multiple reference bit lines RBL1, RBL2, ..., RBLn. For example, the second memory cell array 200a can output a first reference current Iref_1 through the first reference bit line RBL1, a second reference current Iref_2 through the second reference bit line RBL2, and an nth reference current Iref_n through the nth reference bit line RBLn.

[0082] refer to Figure 4B The second memory cell array 200b may include multiple reference resistor memory cells RRMC' arranged in the region where multiple reference word lines RWL1, RWL2, ..., RWLN intersect with multiple reference bit lines RBL1, RBL2, ..., RBLn and multiple reference source lines RSL1, RSL2, ..., RSLn.

[0083] Each of the multiple reference resistor memory cells RRMC' may include a cell transistor CT and a resistor element RE, and may be connected to one of the multiple reference word lines RWL1, RWL2, ..., RWLN, one of the multiple reference bit lines RBL1, RBL2, ..., RBLM, and one of the multiple reference source lines RSL1, RSL2, ..., RSLM. For example, the cell transistor CT may include a first electrode, a second electrode connected to one of the multiple reference source lines RSL1, RSL2, ..., RSLM, and a gate electrode connected to one of the multiple reference word lines RWL1, RWL2, ..., RWLN. The resistor element RE may be connected between the second electrode of the cell transistor CT and one of the multiple reference bit lines RBL1, RBL2, ..., RBLM. It can be obtained from... Figure 1 and Figure 3C Understand its detailed description from the description.

[0084] The second memory cell array 200b can output multiple reference currents Iref_1, Iref_2, ..., Iref_n through electrical paths including multiple reference bit lines RBL1, RBL2, ..., RBLn. In one embodiment, the second memory cell array 200b can output a first reference current Iref_1 flowing through the first reference bit line RBL1 and exiting through the first reference source line RSL1, a second reference current Iref_2 flowing through the second reference bit line RBL2 and exiting through the second reference source line RSL2, and an nth reference current Iref_n flowing through the nth reference bit line RBLn and exiting through the nth reference source line RSLn.

[0085] Figure 5 The operating voltage range of the analog-to-digital converter circuit according to an embodiment of the present invention and a plurality of reference voltages Vref_1, Vref_2 and Vref_3 are shown. Figure 5 An embodiment is illustrated, wherein the multiple digital signals DS_1, DS_2, ..., DS_M output by the analog-to-digital converter circuit 400 of Figure 1 are 2-bit digital signals. The number of bits in the digital signals and the number of reference voltages described above are merely examples for ease of description and are not limited to this embodiment. Figure 5 Those shown. Reference Figure 1 Describe together Figure 5 .

[0086] The analog-to-digital converter circuit 400 can convert multiple signal voltages into multiple digital signals using multiple reference voltages provided by the current-to-voltage converter circuit 300. The multiple reference voltages can be used as reference values ​​for converting signal voltages in analog signal form into digital signals.

[0087] For example, when the first signal voltage Vsig_1 is less than the first reference voltage Vref_1, the analog-to-digital converter 400 can output "00" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1. Alternatively, for example, when the first signal voltage Vsig_1 is greater than or equal to the first reference voltage Vref_1 and less than the second reference voltage Vref_2, the analog-to-digital converter 400 can output "01" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1. Furthermore, for example, when the first signal voltage Vsig_1 is greater than or equal to the second reference voltage Vref_2 and less than the third reference voltage Vref_3, the analog-to-digital converter 400 can output "10" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1. Additionally, for example, when the first signal voltage Vsig_1 is greater than or equal to the third reference voltage Vref_3, the analog-to-digital converter 400 can output "11" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1.

[0088] refer to Figure 5 The multiple reference voltages, including the first reference voltage Vref_1 to the third reference voltage Vref_3, can divide the operating voltage range of the analog-to-digital converter circuit 400 substantially equally. However, the inventive concept is not limited thereto, and the multiple reference voltages can divide the operating voltage range of the analog-to-digital converter circuit 400 unequally. This embodiment will be referred to... Figure 10 Detailed description.

[0089] Figure 6 The illustration shows the state of a second memory cell array and a reference memory cell according to an embodiment of the present invention. Figure 6 An embodiment can be illustrated, wherein, according to Figure 4B In the embodiment, the number of reference bit lines in the second memory cell array 200b is 3. Specifically, Figure 6 One embodiment can be shown, wherein, as Figure 5 The diagram shows that the operating voltage range of the analog-to-digital converter circuit 400 is divided into approximately equal parts. (Reference) Figure 1 and Figure 5 Describe it together Figure 6 .

[0090] The second memory cell array 200 can output a first reference current Iref_1 corresponding to the first reference voltage Vref_1 through the first reference source line RSL1. Figure 5Corresponding to the first reference source line RSL1, a first reference voltage Vref_1 can be generated by writing data. The written data ensures that in the reference resistor memory cells connected to the first reference bit line RBL1, there are more memory cells in the high-resistance state HRS than in the low-resistance state LRS. As a non-limiting example, the ratio of the number of memory cells in the high-resistance state HRS to the number of memory cells in the low-resistance state LRS connected to the first reference bit line RBL1 can be 8:0.

[0091] The second memory cell array 200 can output a second reference current Iref_2 corresponding to the second reference voltage Vref_2 via the second reference source line RSL2. Corresponding to the second reference source line RSL2, the second reference voltage Vref_2 can be generated by writing data such that the number of memory cells in the high-resistance state HRS is the same as the number of memory cells in the low-resistance state LRS in the reference resistor memory cells connected to the second reference bit line RBL2. As a non-limiting example, the ratio of the number of memory cells in the high-resistance state HRS to the number of memory cells in the low-resistance state LRS in the reference resistor memory cells connected to the second reference bit line RBL2 can be 4:4.

[0092] The second memory cell array 200 can output a third reference current Iref_3 corresponding to a third reference voltage Vref_3 via a third reference source line RSL3. Corresponding to the third reference source line RSL3, the third reference voltage Vref_3 can be generated by writing data such that, in the reference resistor memory cells connected to the third reference bit line RBL3, the number of memory cells in the high-resistance state HRS is less than the number of memory cells in the low-resistance state LRS. As a non-limiting example, with respect to the reference resistor memory cells connected to the third reference bit line RBL3, the ratio of the number of memory cells in the high-resistance state HRS to the number of memory cells in the low-resistance state LRS can be 0:8.

[0093] As described above, in order for the second memory cell array 200 to output reference currents corresponding to different levels of reference voltages, the ratio of memory cells in the high-resistance state HRS to memory cells in the low-resistance state LRS can be different.

[0094] Figure 7A An analog-to-digital converter circuit 400a according to an embodiment of the present invention is shown. Figure 7A The analog-to-digital converter circuit 400a corresponds to Figure 1 400 analog-to-digital converter circuit.

[0095] The analog-to-digital conversion circuit 400a may include multiple analog-to-digital converters, and in one embodiment, the number of analog-to-digital converters may be the same as the number of signal voltages Vsig_1, Vsig_2, ..., Vsig_M.

[0096] For example, analog-to-digital converter circuit 400a may include a first analog-to-digital converter 401_1a and second analog-to-digital converters 401_2a to Mth analog-to-digital converters 401_Ma.

[0097] The first analog-to-digital converter 401_1a can convert the first signal voltage Vsig_1 to output the first digital signal DS_1 by using the first reference voltage Vref_1 to the third reference voltage Vref_3.

[0098] The second analog-to-digital converter 401_2a can convert the second signal voltage Vsig_2 to output the second digital signal DS_2 by using the first reference voltage Vref_1 to the third reference voltage Vref_3.

[0099] Similarly, the Mth analog-to-digital converter 401_Ma can convert the Mth signal voltage Vsig_M to output the Mth digital signal DS_M by using the first reference voltage Vref_1 to the third reference voltage Vref_3.

[0100] Reference Figure 8 and Figure 9 A more specific description is given of each of the first analog-to-digital converters 401_1a to the Mth analog-to-digital converters 401_Ma.

[0101] Figure 7B A neuromorphic computing device 10 according to an embodiment of the present invention is shown. Figure 7B An embodiment is illustrated in which multiplexing circuitry 350 is added to Figure 1 Between the current-to-voltage conversion circuit 300 and the analog-to-digital conversion circuit 400 of the neuromorphic computing device 10.

[0102] and Figure 1 In contrast, the neuromorphic computing device 10 may further include a multiplexing circuit 350 and a MUX decoder 360.

[0103] The analog-to-digital conversion circuit 400b may include multiple analog-to-digital converters, and in one embodiment, the number of analog-to-digital converters may be less than the number of signal voltages Vsig_1, Vsig_2, ..., Vsig_M.

[0104] For example, the analog-to-digital converter circuit 400b may include a first analog-to-digital converter 401_1b and second analog-to-digital converters 401_2b to kth analog-to-digital converters 401_kb. Here, k is a natural number of 2 or greater, and may be less than M.

[0105] The multiplexing circuit 350 can select k signal voltages from M signal voltages based on the selection signal SEL and provide the selected k signal voltages to the analog-to-digital converter circuit 400b. For example, the multiplexing circuit 350 can select the first signal voltage Vsig_1 to the kth signal voltage Vsig_k from the first signal voltage Vsig_1 to the Mth signal voltage Vsig_M based on the selection signal SEL and provide the first signal voltage Vsig_1 to the kth signal voltage Vsig_k to the analog-to-digital converter circuit 400b.

[0106] The MUX decoder 360 can output the selection signal SEL to the multiplexing circuit 350 to select which signal voltage to output to the analog-to-digital converter circuit 400b.

[0107] The first analog-to-digital converter 401_1b can convert the first signal voltage Vsig_1 to output the first digital signal DS_1 by using the first reference voltage Vref_1 to the third reference voltage Vref_3.

[0108] The second analog-to-digital converter 401_2b can convert the second signal voltage Vsig_2 to output the second digital signal DS_2 by using the first reference voltage Vref_1 to the third reference voltage Vref_3.

[0109] Similarly, the k-th analog-to-digital converter 401_kb can convert the k-th signal voltage Vsig_k to output the k-th digital signal DS_k by using the first reference voltage Vref_1 to the third reference voltage Vref_3.

[0110] Reference Figure 8 and Figure 9 A more detailed description is given of the first analog-to-digital converter 401_1b to the kth analog-to-digital converter 401_kb.

[0111] Figure 8 An analog-to-digital converter 401 according to an embodiment of the present invention is shown. Figure 8 The analog-to-digital converter 401 can be used with Figure 7A Any one of the first analog-to-digital converters 401_1a to the Mth analog-to-digital converters 401_Ma, or Figure 7B It corresponds to any one of the first analog-to-digital converters 401_1b to the kth analog-to-digital converter 401_kb.

[0112] The analog-to-digital converter 401 can use the first reference voltage Vref_1 to the third reference voltage Vref_3 to convert the corresponding signal voltage Vsig into a digital signal DS to output the digital signal DS. For example, the analog-to-digital converter 401 can compare the corresponding signal voltage Vsig with the first reference voltage Vref_1 to the third reference voltage Vref_3 to output the digital signal DS.

[0113] For this purpose, the analog-to-digital converter 401 may include a comparator circuit 420 and an encoder circuit 440.

[0114] Comparator circuit 420 can compare the signal voltage Vsig with first reference voltages Vref_1 to third reference voltages Vref_3 to output multiple comparison signals CS. For this purpose, as follows... Figure 9 As shown, the comparison circuit 420 may include multiple comparators. The comparison circuit 420 can provide multiple comparison signals CS to the encoding circuit 440.

[0115] The encoding circuit 440 can generate a digital signal DS corresponding to the signal voltage Vsig based on multiple comparison signals CS and output the digital signal DS.

[0116] Figure 9 An analog-to-digital converter 401 according to an embodiment of the present invention is shown. Figure 9 It can be shown Figure 8 Detailed block diagram of analog-to-digital converter 401.

[0117] The comparator circuit 420 may include a first comparator 421, a second comparator 422, and a third comparator 423.

[0118] The first comparator 421 can compare the signal voltage Vsig with the first reference voltage Vref_1 to output a first comparison signal CS1. For example, when the signal voltage Vsig is greater than the first reference voltage Vref_1, the first comparator 421 can output the first comparison signal CS1 with a first logic level of "1", and when the signal voltage Vsig is not greater than the first reference voltage Vref_1, the first comparator 421 can output the first comparison signal CS1 with a second logic level of "0".

[0119] The second comparator 422 can compare the signal voltage Vsig with the second reference voltage Vref_2 to output a second comparison signal CS2. For example, when the signal voltage Vsig is greater than the second reference voltage Vref_2, the second comparator 422 can output a second comparison signal CS2 with a first logic level of "1", and when the signal voltage Vsig is not greater than the second reference voltage Vref_2, the second comparator 422 can output a second comparison signal CS2 with a second logic level of "0".

[0120] The third comparator 423 can compare the signal voltage Vsig with the third reference voltage Vref_3 to output a third comparison signal CS3. For example, when the signal voltage Vsig is greater than the third reference voltage Vref_3, the third comparator 423 can output a third comparison signal CS3 with a first logic level of "1", and when the signal voltage Vsig is not greater than the third reference voltage Vref_3, the third comparator 423 can output a third comparison signal CS3 with a second logic level of "0".

[0121] The encoding circuit 440 may include an encoder 442. The encoder 442 may receive a power supply voltage VCC as input, and may receive a first comparison signal CS1 from a first comparator 421, a second comparison signal CS2 from a second comparator 422, and a third comparison signal CS3 from a third comparator 423. The encoder 442 may output a 2-bit digital signal DS based on the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3.

[0122] Figure 10 The operating voltage range and multiple reference voltages Vref_1, Vref_2 and Vref_3 of an analog-to-digital conversion circuit 400 according to an embodiment of the present invention are shown. Figure 10 An embodiment is shown, wherein by Figure 1 The analog-to-digital converter circuit 400 outputs multiple digital signals DS_1, DS_2, ..., DS_M, which are 2-bit digital signals. The number of bits in the digital signals and the number of reference voltages described above are merely examples for ease of description and are not intended to be limiting. Figure 10 The number of reference voltages shown can be one less than the square of the number of bits in a binary state; or more generally, one less than the corresponding power of the number of bits in a multivariate state, such as a ternary state. Reference Figure 1 Describe together Figure 10 .

[0123] The analog-to-digital converter circuit 400 can convert multiple signal voltages into multiple digital signals using multiple reference voltages provided from the current-to-voltage converter circuit 300. The multiple reference voltages can be used as reference values ​​for converting signal voltages in analog signal form into digital signals.

[0124] For example, when the first signal voltage Vsig_1 is less than the first reference voltage Vref_1, the analog-to-digital converter 400 can output "00" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1. Alternatively, for example, when the first signal voltage Vsig_1 is greater than or equal to the first reference voltage Vref_1 and less than the second reference voltage Vref_2, the analog-to-digital converter 400 can output "01" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1. Furthermore, for example, when the first signal voltage Vsig_1 is greater than or equal to the second reference voltage Vref_2 and less than the third reference voltage Vref_3, the analog-to-digital converter 400 can output "10" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1. Additionally, for example, when the first signal voltage Vsig_1 is greater than or equal to the third reference voltage Vref_3, the analog-to-digital converter 400 can output "11" as the first digital signal DS_1 corresponding to the first signal voltage Vsig_1.

[0125] refer to Figure 10 The multiple reference voltages, including the first reference voltage Vref_1 to the third reference voltage Vref_3, can unequally divide the operating voltage range of the analog-to-digital converter circuit 400.

[0126] In one embodiment, multiple reference voltages can divide the operating voltage range of the analog-to-digital converter circuit 400 such that the voltage interval between reference voltages near the center of the operating voltage range of the analog-to-digital converter circuit 400 is formed to be narrower than the voltage interval near the edge of the operating voltage range.

[0127] When performing analog-to-digital conversion in general-purpose neuromorphic computing devices, relatively precise operation may be required near the center of the operating voltage range. The neuromorphic computing device 10 according to an embodiment of the present invention can quantize the operating voltage range unequally according to the required precision of operation within a specific voltage range, thereby improving the accuracy of the operation required by the neuromorphic computing device 10 as appropriate.

[0128] Figure 11 The illustration shows the state of a second memory cell array 200 and a reference memory cell according to an embodiment of the present invention. Figure 11 This could be an example, where, according to Figure 4B In the embodiment, the number of reference bit lines in the second memory cell array 200b is 3. Specifically, Figure 11 An embodiment can be shown, wherein, as Figure 10 The diagram shows the uneven division of the operating voltage range of the analog-to-digital converter circuit. (Reference) Figure 1 describe Figure 11And mainly describes relative to Figure 6 The differences.

[0129] and Figure 5 Compared to the situation shown, in Figure 10 In the illustrated embodiment, since the reference voltage must be further aggregated near the center of the operating voltage range, it can be compared with... Figure 6 The write state of the reference resistor storage cell is written to the reference resistor storage cell differently.

[0130] For example, for a reference resistor memory cell connected to the first reference bit line RBL1, the ratio of the number of memory cells in the high-resistance state HRS to the number of memory cells in the low-resistance state LRS can be 6:2. However, the inventive concept is not limited to this, and for example, according to design or requirement specifications, the ratio of the number of memory cells in the high-resistance state HRS to the number of memory cells in the low-resistance state LRS can be 7:3.

[0131] Additionally, for example, for a reference resistor memory cell connected to the third reference bit line RBL3, the ratio of the number of memory cells in the high-resistance state HRS to the number of memory cells in the low-resistance state LRS can be 2:6. However, the inventive concept is not limited thereto, and for example, according to design or requirement specifications, the ratio of the number of memory cells in the high-resistance state HRS to the number of memory cells in the low-resistance state LRS can be 3:7.

[0132] When performing analog-to-digital conversion in a general-purpose neuromorphic computing device 10, relatively precise operation may be required near the center of the operating voltage range. The neuromorphic computing device 10, according to an embodiment of the present invention, can quantize the operating voltage range unevenly according to the required precision of operation within a specific voltage range, thereby improving the accuracy of the operation required by the neuromorphic computing device 10 as appropriate.

[0133] Figure 12 The illustration shows a second memory cell array 200 according to an embodiment of the concept of the present invention. Figure 12 Here is an example where a load resistor is added according to... Figure 4B The second storage cell array 200b of the embodiment. This will primarily target the... Figure 4B The differences in the embodiments are described. Figure 12 .

[0134] The load resistor can be connected to the reference bit line or reference source line of the second memory cell array 200.

[0135] For example, the first reference source line RSL1 can be connected to the first terminal of the first source transistor ST1, which is selected by the read signal READ, and the first load resistor Rload_1 can be connected between the second terminal of the first source transistor ST1 and the ground node. Similarly, the second reference source line RSL2 can be connected to the first terminal of the second source transistor ST2, which is selected by the read signal READ, and the second load resistor Rload_2 can be connected between the second terminal of the second source transistor ST2 and the ground node. Similarly, the nth reference source line RSLn can be connected to the first terminal of the nth source transistor STn, which is selected by the read signal READ, and the nth load resistor Rload_n can be connected between the second terminal of the nth source transistor STn and the ground node.

[0136] The first load resistor Rload_1 to the nth load resistor Rload_n may all have the same resistance value, but are not limited to this, and may have different resistance values ​​from each other. In one embodiment, the resistance value of the first load resistor Rload_1 to the nth load resistor Rload_n is a value between the resistance value of the reference resistor storage cell when it is in the low resistance state LRS and the resistance value when it is in the high resistance state HRS.

[0137] As mentioned above, in resistive storage devices, their resistive characteristics change with time or temperature, and therefore, reference... Figure 5 or Figure 10 The distributions of the reference voltages Vref_1, Vref_2, and Vref_3 can vary. Therefore, some of the reference voltages Vref_1, Vref_2, and Vref_3 may coincide with the boundary values ​​between the actual voltages to be classified. According to... Figure 12 The second memory cell array 200 shown can solve the problem of reference voltage and voltage boundary overlap or shift caused by reference voltage drift due to the presence of load resistance.

[0138] Figure 13 An analog-to-digital converter 401 according to an embodiment of the present invention is shown. Figure 13 The analog-to-digital converter 401 can be used with Figure 7A Any one of the first analog-to-digital converters 401_1a to the Mth analog-to-digital converters 401_Ma, or Figure 7B It corresponds to any one of the first analog-to-digital converters 401_1b to the kth analog-to-digital converter 401_kb. Figure 13 An embodiment is shown, wherein when with Figure 9 In contrast, the digital signal DS is a 3-bit digital signal.

[0139] The comparator circuit 420 may include a first comparator 421 to a seventh comparator 427, and the encoder 442 may output a 3-bit digital signal DS.

[0140] The operation of the first comparators 421 to the seventh comparators 427 and the encoder 442 can be similar to that of the following: Figure 9 The described procedure will be executed.

[0141] For example, the first comparator 421 can compare the signal voltage Vsig with the first reference voltage Vref_1 to output a first comparison signal CS1. For example, when the signal voltage Vsig is greater than the first reference voltage Vref_1, the first comparator 421 can output the first comparison signal CS1 with a first logic level of "1", and when the signal voltage Vsig is not greater than the first reference voltage Vref_1, the first comparator 421 can output the first comparison signal CS1 with a second logic level of "0".

[0142] Similarly, the second comparator 422 can compare the signal voltage Vsig with the second reference voltage Vref_2 to output the second comparison signal CS2, the third comparator 423 can compare the signal voltage Vsig with the third reference voltage Vref_3 to output the third comparison signal CS3, the fourth comparator 424 can compare the signal voltage Vsig with the fourth reference voltage Vref_4 to output the fourth signal CS4, the fifth comparator 425 can compare the signal voltage Vsig with the fifth reference voltage Vref_5 to output the fifth comparison signal CS5, the sixth comparator 426 can compare the signal voltage Vsig with the sixth reference voltage Vref_6 to output the sixth comparison signal CS6, and the seventh comparator 427 can compare the signal voltage Vsig with the seventh reference voltage Vref_7 to output the seventh comparison signal CS7.

[0143] Encoder 442 can receive power supply voltage VCC as input, and receive a first comparison signal CS1 from a first comparator 421, a second comparison signal CS2 from a second comparator 422, a third comparison signal CS3 from a third comparator 423, a fourth comparison signal CS4 from a fourth comparator 424, a fifth comparison signal CS5 from a fifth comparator 425, a sixth comparison signal CS6 from a sixth comparator 426, and a seventh comparison signal CS7 from a seventh comparator 427. Encoder 442 can output a 3-bit digital signal DS based on the first comparison signal CS1, the second comparison signal CS2, the third comparison signal CS3, the fourth comparison signal CS4, the fifth comparison signal CS5, the sixth comparison signal CS6, and the seventh comparison signal CS7.

[0144] Figure 14This is a flowchart illustrating the operation method of a neuromorphic computing device 10 according to an embodiment of the present invention. (See reference...) Figure 1 Describe together Figure 14 .

[0145] The neuromorphic computing device 10 can activate all reference word lines connected to the second memory cell array 200 (S120). For example, the word line driver 150 can drive multiple reference word lines RWL1, RWL2, ..., RWLN, so that all multiple reference word lines RWL1, RWL2, ..., RWLN are activated.

[0146] The neuromorphic computing device 10 can obtain reference voltage values ​​based on reference currents Iref_1, Iref_2, ..., Iref_n output from the second storage cell array 200 (S140).

[0147] The neuromorphic computing device 10 can use the obtained reference voltage value to convert multiple signal voltages Vsig_1, Vsig_2, ..., Vsig_M, which correspond to multiple read currents Iread_1, Iread_2, ..., Iread_M respectively, into multiple digital signals DS_1, DS_2, ..., DS_M (S160).

[0148] Figure 15 An electronic system 1000 according to an embodiment of the inventive concept is shown.

[0149] Electronic system 1000 may include processor 1010, storage device 1020, connectivity 1030, input / output (I / O) device 1040, power supply 1050, and neuromorphic computing device 1060. Electronic system 1000 may further include various ports capable of communicating with video cards, sound cards, memory cards, USB devices, or other systems.

[0150] The processor 1010 controls all operations of the electronic system 1000 and can execute operating systems, applications, etc. The storage device 1020 stores data necessary for the operation of the electronic system 1000. The connection 1030 enables communication with external devices. The I / O device 1040 may include input tools such as a keyboard, keypad, touchpad, touchscreen, mouse, remote control, etc., and output tools such as a monitor, speaker, printer, etc. The power supply 1050 provides the power required for the operation of the electronic system 1000.

[0151] The neuromorphic computing device 1060 can drive and / or execute a neural network system, and can be a neuromorphic computing device according to an embodiment of the inventive concept described with reference to the foregoing figures. The neuromorphic computing device 1060 may include a main memory array 1100 corresponding to the first memory array 100 in the previous figures, a reference memory array 1200 corresponding to the second memory array 200 in the previous figures, a current-to-voltage conversion circuit 1300, and an analog-to-digital conversion circuit 1400.

[0152] For example, the main memory cell array 1100 can provide multiple read currents Iread to the current-to-voltage conversion circuit 1300, and the reference memory cell array 1200 can provide multiple reference currents Iref to the current-to-voltage conversion circuit 1300.

[0153] The current-to-voltage conversion circuit 1300 can convert multiple read currents Iread to output multiple signal voltages Vsig, and provide the multiple signal voltages Vsig to the analog-to-digital conversion circuit 1400. The current-to-voltage conversion circuit 1300 can convert multiple reference currents Iref to output multiple reference voltages Vref, and provide the multiple reference voltages Vref to the analog-to-digital conversion circuit 1400.

[0154] The analog-to-digital converter circuit 1400 can convert multiple signal voltages Vsig into multiple digital signals DS by using multiple reference voltages Vref as references for analog-to-digital conversion.

[0155] Although the concept of the invention has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A neuromorphic computing device, comprising: The first memory cell array contains multiple resistive memory cells and is configured to output multiple read currents through multiple bit lines or source lines; The second memory cell array includes multiple reference resistor memory cells and is configured to output at least one reference current through at least one reference bit line or at least one reference source line; A current-to-voltage conversion circuit is configured to output multiple signal voltages corresponding to the multiple read currents and to output at least one reference voltage corresponding to the at least one reference current; as well as An analog-to-digital converter circuit is configured to convert the plurality of signal voltages into a plurality of digital signals using the at least one reference voltage and to output the plurality of digital signals.

2. The neuromorphic computing device according to claim 1, wherein, The plurality of reference resistor storage cells and the plurality of resistor storage cells contain the same resistor material.

3. The neuromorphic computing device according to claim 1, wherein, The number of at least one reference bit line is the same as the number obtained by subtracting 1 from the base 2, with the number of bits of each of the plurality of digital signals as the exponent.

4. The neuromorphic computing device according to claim 1, wherein, The at least one reference bit line includes a first reference bit line and a second reference bit line, and The ratio of the number of high-resistance state memory cells to the number of low-resistance state memory cells in the first reference memory cell connected to the first reference bit line in the plurality of reference resistor memory cells is different from the ratio of the number of high-resistance state memory cells to the number of low-resistance state memory cells in the second reference memory cell connected to the second reference bit line in the plurality of reference resistor memory cells.

5. The neuromorphic computing device according to claim 1, wherein, The at least one reference voltage equally quantizes the operating voltage range of the analog-to-digital conversion circuit, and The resistive storage cell connected to each of the at least one reference bit line has a resistance state distribution to form a corresponding reference voltage in the at least one reference voltage.

6. The neuromorphic computing device according to claim 1, wherein, The at least one reference voltage unequally quantifies the operating voltage range of the analog-to-digital conversion circuit. Among them, the quantization interval near the center of the operating voltage range is narrower than the quantization interval near the edge of the operating voltage range, and The resistive storage cell connected to each of the at least one reference bit line has a resistance state distribution to form a corresponding reference voltage in the at least one reference voltage.

7. The neuromorphic computing device according to claim 1, wherein, The analog-to-digital conversion circuit includes multiple analog-to-digital converters corresponding to each of the plurality of signal voltages and configured to convert the corresponding signal voltage into a digital signal.

8. The neuromorphic computing device of claim 1, further comprising: a multiplexing circuit configured to select a signal voltage from a plurality of signal voltages and output the selected signal voltage. in, The analog-to-digital conversion circuit includes a plurality of analog-to-digital converters configured to convert the selected signal voltage into a digital signal, wherein the number of analog-to-digital converters is less than the number of signal voltages.

9. The neuromorphic computing device according to claim 1, wherein, The analog-to-digital conversion circuit includes multiple analog-to-digital converters configured to convert corresponding signal voltages from a plurality of signal voltages into digital signals, and Each of the plurality of analog-to-digital converters is configured to output a digital signal corresponding to the corresponding signal voltage by comparing the corresponding signal voltage with the at least one reference voltage.

10. The neuromorphic computing device according to claim 9, wherein, Each of the multiple analog-to-digital converters contains: The comparator circuit is configured to output at least one comparison signal by comparing the corresponding signal voltage with the at least one reference voltage; as well as The encoding circuit is configured to output a digital signal corresponding to the corresponding signal voltage based on at least one comparison signal.

11. The neuromorphic computing device according to claim 1, wherein, Between the at least one reference source line and the ground node, a load resistor is connected with a resistance value between the low resistance state and the high resistance state of the reference resistance storage cell.

12. The neuromorphic computing device of claim 1, further comprising: a word line driver configured to drive a plurality of word lines connected to a first memory cell array, drive a plurality of reference word lines connected to a second memory cell array, and drive the plurality of reference word lines such that all the plurality of word lines are activated during computational operations of the neuromorphic computing device.

13. The neuromorphic computing device according to claim 12, wherein, The states corresponding to the elements of the weight matrix used in the computational operations of the neuromorphic computing device are written into multiple resistive storage units, and The word line driver is configured to activate at least one of a plurality of word lines in a computational operation of a neuromorphic computing device based on the element values ​​of an input feature vector.

14. The neuromorphic computing device of claim 13, further comprising: an adder circuit configured to generate output data by performing an accumulation and / or summation operation using the plurality of digital signals.

15. A method of operating a neuromorphic computing device, the neuromorphic computing device comprising a first memory cell array having main resistive memory cells and a second memory cell array having reference resistive memory cells, the method comprising: Activate all reference word lines connected to the second memory cell array; At least one reference voltage value is obtained by a current-to-voltage conversion circuit based on at least one reference current output from the second memory cell array; as well as The analog-to-digital converter circuit converts a signal voltage value corresponding to the read current output from the first memory cell array by using at least one reference voltage value, and outputs multiple digital signals.

16. The method according to claim 15, wherein, Each of the reference resistor storage cells contains the same resistive material as the main resistor storage cell.

17. The method according to claim 15, wherein, The output of multiple digital signals includes: At least one comparison signal is generated by comparing a first signal voltage value among the signal voltage values ​​with the at least one reference voltage value; as well as Based on the at least one comparison signal, a first digital signal corresponding to the voltage value of the first signal is output.

18. The method of claim 15, further comprising: generating output data by performing an accumulation and / or summation operation using a plurality of digital signals.

19. A neuromorphic computing device, comprising: The first resistive memory cell array includes multiple resistive memory cells arranged in a region where multiple word lines and multiple bit lines intersect; The second resistor memory cell array includes multiple reference resistor memory cells arranged in a region where multiple reference word lines and multiple reference bit lines intersect; A word line driver is configured to drive multiple word lines and multiple reference word lines, activate at least one selected word line among the multiple word lines based on the element values ​​of the input feature vector, and activate all multiple reference word lines. The current-to-voltage conversion circuit is configured to convert multiple reference currents output from a second resistive memory cell array into multiple reference voltages via an electrical path containing multiple reference bit lines, and to convert multiple read currents output from a first resistive memory cell array into multiple signal voltages via an electrical path containing multiple bit lines based on the activation of at least one select word line. An analog-to-digital converter circuit is configured to use the plurality of reference voltages as references for analog-to-digital conversion, convert the plurality of signal voltages into a plurality of digital signals, and output the plurality of digital signals; as well as An adder circuit is configured to generate at least one output data using the plurality of digital signals by performing an accumulation and / or summation operation.

20. The neuromorphic computing device according to claim 19, wherein, Each of the plurality of reference resistor memory cells contains the same resistive material as the plurality of resistor memory cells, and The number of reference bit lines corresponds to the number obtained by subtracting 1 from the exponent of the number of bits of each of the multiple digital signals, which is base 2.

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