Memory device

Abstract

A memory device includes: a memory region having a first memory block and a second memory block; and control logic configured to control the first memory block and the second memory block in the first mode and the second mode, wherein in the first mode only control operations for the first memory block are executable, while in the second mode control operations for both the first and second memory blocks are executable, wherein the control logic counts the number of accesses to the second memory block in the first mode and stores the access count as scan data in the second memory block.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent No. 10-2020-0049740, filed on April 24, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to memory devices. Background Technology

[0004] Memory devices are used to store and transfer data. They provide the ability to write and erase data or read stored data. Security data for a system can be stored in non-volatile memory devices. In this case, the security data is retained even when the system power is off. Memory devices can store security data separately from general data. Even with this protection, security data can still be compromised by hackers. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a memory device is provided, comprising: a memory region having a first memory block and a second memory block; and control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only control operations for the first memory block are executable, while in the second mode control operations for both the first and second memory blocks are executable, wherein the control logic counts the number of accesses to the second memory block in the first mode and stores the number of accesses as scan data in the second memory block.

[0006] According to an exemplary embodiment of the present invention, a memory device is provided, comprising: a memory region having a plurality of memory blocks; and control logic configured to control the memory region, wherein the control logic blocks access to at least one secure block among the plurality of memory blocks in a first mode, and allows access to at least one secure block in a second mode different from the first mode, and performs a read operation and a programming operation for at least one secure block when a read operation for at least one secure block is performed in the first mode.

[0007] According to an exemplary embodiment of the present invention, a memory device is provided, comprising: a first word line stacked on a substrate; a first channel layer extending through the first word line in a first direction perpendicular to the substrate and providing a first memory cell accessible in a first mode and a second mode other than the first mode; a second word line stacked on the substrate and electrically isolated from the first word line; a second channel layer extending through the second word line in the first direction and providing a second memory cell accessible only in the second mode; and control logic configured to select one of the first mode and the second mode as an operating mode, and to store in the second memory cell data corresponding to the number of times the second memory cell is accessed in the first mode. Attached Figure Description

[0008] The above and other features of the inventive concept will be more clearly understood by referring to the accompanying drawings and describing exemplary embodiments thereof in detail, wherein:

[0009] Figure 1 This is a diagram schematically illustrating a memory system according to an exemplary embodiment of the concept of the present invention;

[0010] Figure 2 This is a diagram schematically illustrating a memory device according to an exemplary embodiment of the concept of the present invention;

[0011] Figure 3 , 4 Views 5 and 6 are schematic views illustrating an exemplary embodiment of a memory device according to a concept of the present invention.

[0012] Figure 6 This is a circuit diagram provided to describe the operation of a memory device according to an exemplary embodiment of the present invention.

[0013] Figure 7 , 8 Figures 9 and 1 are provided to illustrate the operation of a memory device according to an exemplary embodiment of the present invention;

[0014] Figure 10 and 11 This is a circuit diagram schematically illustrating a page buffer included in a memory device according to an exemplary embodiment of the present invention.

[0015] Figure 12 This is a flowchart provided to describe the operation of a memory device according to an exemplary embodiment of the present invention;

[0016] Figure 13 These are diagrams provided to illustrate the operation of a memory device according to an exemplary embodiment of the present invention.

[0017] Figure 14 and 15This is a diagram illustrating a method for storing scan data in a memory device according to an exemplary embodiment of the present invention;

[0018] Figure 16 and 17 These are diagrams provided to illustrate the operation of a memory device according to an exemplary embodiment of the present invention.

[0019] Figure 18 This is a diagram schematically illustrating a memory system according to an exemplary embodiment of the concept of the present invention;

[0020] Figure 19 The diagram schematically illustrates a mobile system including a memory device according to an exemplary embodiment of the present invention; and

[0021] Figure 20 This is a view schematically illustrating the structure of a memory device according to an exemplary embodiment of the present invention. Detailed Implementation

[0022] In the following description, exemplary embodiments of the inventive concept will be illustrated with reference to the accompanying drawings. In the drawings, similar reference numerals may refer to similar elements.

[0023] Figure 1 This is a diagram schematically illustrating a memory system according to an exemplary embodiment of the concept of the present invention.

[0024] refer to Figure 1 According to an exemplary embodiment of the present invention, the memory system 1 may include a memory controller 10, memory devices (21-25: 20), an input / output interface 30, etc. The memory system 1 may be a solid-state drive (SSD), a memory card, etc., and may communicate with a host 2 via the input / output interface 30. The host 2 is a device that stores data in and reads data from the memory system 1, and may include computer devices such as smartphones, tablet PCs, laptops, desktop computers, etc., as well as household appliances such as televisions, refrigerators, set-top boxes, etc.

[0025] The memory controller 10 is provided as a semiconductor chip separate from the memory device 20 and can control the memory device 20. Each of the memory devices 20 is implemented with a separate semiconductor chip and can operate in response to control commands received from the memory controller 10. For example, each of the memory devices 20 can store data received from the memory controller 10, or read stored data and send read data to the memory controller 10.

[0026] The memory device 20 can be non-volatile, and the data stored in the memory device 20 can be retained even after the power from the host 2 or the internal power of the memory system 1 is cut off. Therefore, various types of secure data used for the operation of the memory system 1 and / or the host 2, such as secure data like root keys, master keys, public keys, and personal keys, can be stored in the memory device 20 of the memory system 1. The memory system 1 can employ various security strategies to protect the secure data from attacks, such as external hacking attacks.

[0027] As an example of a security strategy, the operating modes of the memory system 1 can be differentiated, and access permissions to the memory device 20 can be managed so that secure data can only be accessed in specific operating modes. However, despite such a security strategy, secure data can still be obtained by hackers using methods such as scanning all memory regions included in the memory device 20 and analyzing data patterns.

[0028] In an exemplary embodiment of the present invention, access permissions can be managed such that, by differentiating the operating modes of the corresponding memory device 20, secure data can only be accessed in a specific operating mode. Therefore, when abnormal access to secure data is detected, the number of abnormal accesses can be counted and stored. The number of abnormal accesses can be stored as flag data in a memory area that includes the secure data. For example, the memory area can be a cell area where deletion operations are performed. Therefore, when an attacker wishes to delete the flag data, since the secure data is stored in the same memory area as the flag data, the flag data and the secure data are deleted together to prevent the secure data from being leaked to the outside.

[0029] Figure 2 This is a diagram schematically illustrating an exemplary embodiment of a memory device according to a concept of the present invention.

[0030] refer to Figure 2 The memory device 40 may include a memory region 50 and peripheral circuitry 60. The peripheral circuitry 60 may include a line decoder 61, a voltage generator 62, a page buffer 63, input / output circuitry 64, control logic 65, etc.

[0031] Memory region 50 includes multiple memory cells and can be divided into multiple blocks BLK1-BLKn. The multiple memory cells can be connected to row decoder 61 via string select line SSL, word line WL, and ground select line GSL, and can be connected to page buffer 63 via bit line BL. In one example, in each of blocks BLK1-BLKn, multiple memory cells arranged at the same height from the substrate are connected to the same word line WL, and multiple memory cells placed at the same location in a plane parallel to the upper surface of the substrate can provide a memory cell string sharing a single channel region. Furthermore, some of the memory cell strings included in each of blocks BLK1-BLKn can be connected to the same bit line BL.

[0032] The line decoder 61 can decode the address data ADDR received from the control logic 65, etc., and generate and transmit the voltage for driving the word line WL. The line decoder 61 can, in response to the control of the control logic 65, input the word line voltage generated by the voltage generator 62 to the word line WL. For example, the line decoder 61 is connected to the word line WL via a transmission transistor, and the word line voltage can be input to the word line WL when the transmission transistor is turned on in response to a signal provided from the control logic 65.

[0033] Page buffer 63 is connected to memory region 50 via bit line BL and can read data stored in memory cells or write data to memory cells. Page buffer 63 may include column decoder, latching circuitry, etc. During a read operation, the column decoder can select at least a portion of bit line BL of memory region 50, and the latching circuitry can read data connected to the memory cell connected to the bit line BL selected by the column decoder.

[0034] Input / output circuit 64 can receive data (DATA) during programming operations and transfer the data to page buffer 63. Furthermore, input / output circuit 64 can output data read from memory region 50 to an external location from page buffer 63. Input / output circuit 64 can also send addresses or commands received from an external memory controller to control logic 65.

[0035] Control logic 65 can control the operation of line decoder 61, voltage generator 62, page buffer 63, etc. In an exemplary embodiment of the present invention, control logic 65 can operate in response to control commands sent from an external memory controller, etc.

[0036] Voltage generator 62 can use an external input voltage to generate control voltages for the operation of memory device 40, such as programming voltage, read voltage, erase voltage, pass voltage, etc. The voltage generated by voltage generator 62 can be provided to peripheral circuitry 60, or it can be input to memory region 50 through line decoder 61, etc.

[0037] Control logic 65 can select one of a first mode and a second mode to control memory blocks BLK1-BLKn included in memory region 50. In an exemplary embodiment of the inventive concept, at least one of memory blocks BLK1-BLKn can be set as a secure block, and unlike the other memory blocks, the secure block can be set to be accessible only in the second mode. Control logic 65 can store secure data of memory device 40 and / or a host operating in conjunction with memory device 40 in the secure block.

[0038] When an access to a secure block is detected in the first mode, control logic 65 can count the number of accesses to the secure block in the first mode and store the counted access count in the secure block as scan data. For example, control logic 65 can detect whether an abnormal access to the secure block occurs in an operation mode where normal access to the secure block is not possible. Furthermore, the number of executions of abnormal accesses to the secure block can be stored in the secure block as scan data. Therefore, in the first mode, when an access to the secure block occurs or an access attempt occurs, the programming operation for recording scan data can be executed in the secure block together with the read operation. In the example, the programming operation can be executed before or after the read operation, or it can be executed simultaneously with the read operation.

[0039] When the number of executions included in the scan data increases to a predetermined reference number, control logic 65 can perform security processing. For example, security processing may include completely blocking access to a secure block containing both the stored secure data and the scan data. For instance, after an authentication process using a predetermined password, biometric information, etc., the access block block can be released. Alternatively, when any access to the secure block occurs or any access attempt is made, a security process can be executed to restrict access to the secure block until an authentication process based on password, biometric information, etc., is completed.

[0040] Furthermore, by storing the scanned data in secure blocks that store secure data, attempts to initialize the scanned data can be prevented. In the example, the erase operation that deletes data stored in memory region 50 of memory device 40 can be performed on a per-block basis within memory blocks BLK1-BLKn. Therefore, when an attempt is made to initialize the scanned data, all data stored in the secure blocks is deleted, and secure data leakage is prevented.

[0041] Figures 3 to 5 This is a schematic view illustrating an exemplary embodiment of a memory device according to the concept of the present invention.

[0042] First refer to Figure 3 The memory device 100 according to an exemplary embodiment of the present invention may include a plurality of blocks BLK1 and BLK2. The plurality of blocks BLK1 and BLK2 may have the same structure as each other and may be distinguished by a separation layer 140.

[0043] Figure 4 It can be shown Figure 3 A perspective view of one of blocks BLK1 and BLK2 in the memory device 100 shown. (See also...) Figure 3 and Figure 4 According to an exemplary embodiment of the present invention, a memory device 100 may include a cell region C and a peripheral circuit region P arranged vertically to each other. The peripheral circuit region P may be located below the cell region C, and the peripheral circuit region P includes a first substrate 101, while the cell region C includes a second substrate 102 different from the first substrate 101.

[0044] For example, the peripheral circuit region P may include a plurality of peripheral circuit elements 103 provided on the first substrate 101, a plurality of wirings 105 connected to the peripheral circuit elements 103, a first interlayer insulating layer 107 covering the peripheral circuit elements 103 and the wirings 105, etc. The peripheral circuit elements 103 included in the peripheral circuit region P may provide circuitry for the memory device 100, such as a page buffer, a line decoder, etc.

[0045] The second substrate 102 included in the cell region C can be disposed on the first interlayer insulating layer 107. The cell region C may include a ground select line GSL, a word line WL, and string select lines SSL1 and SSL2 stacked on the second substrate 102, as well as multiple insulating layers IL. The insulating layers IL may be stacked alternately with the ground select line GSL, the word line WL, and the string select lines SSL1 and SSL2. The number of ground select lines GSL and string select lines SSL1 and SSL2 is not limited to [a specific number]. Figure 4 As shown, and various modifications can be made. Furthermore, the number of word lines (WL) is not limited to as shown. Figure 4 As shown, it can be modified in various ways.

[0046] Furthermore, the cell region C may include a channel structure CH extending in a first direction (Z-axis direction) perpendicular to the upper surface of the second substrate 102, and the channel structure CH may pass through the ground select line GSL, word line WL, and serial select lines SSL1 and SSL2 to connect to the second substrate 102. The channel structure 110 may include a channel region 110, a buried insulating layer 120 filling the internal space of the channel region 110, a bit line connection layer 130, etc. Each of the channel structures may be connected to at least one bit line through the bit line connection layer 130. The ground select line GSL, word line WL, serial select lines SSL1 and SSL2, insulating layer IL, and channel structure CH may be referred to as a stacked structure.

[0047] At least one gate insulating layer may be disposed outside the channel region 110. In an exemplary embodiment of the present invention, the gate insulating layer may include a tunneling layer, a charge storage layer, and a barrier layer arranged sequentially from the channel region 110. In an exemplary embodiment of the present invention, at least one of the tunneling layer, the charge storage layer, and the barrier layer may surround the ground select line GSL, the word line WL, and the serial select lines SSL1 and SSL2.

[0048] The ground select line GSL, word line WL, and serial select lines SSL1 and SSL2 can be covered by interlayer insulation layer 150. Furthermore, the ground select line GSL, word line WL, and serial select lines SSL1 and SSL2 can be separated into multiple blocks BLK1 and BLK2 by separation layer 140. In an exemplary embodiment of the inventive concept, between a pair of separation layers 140 adjacent to each other along the second direction (Y-axis direction), the serial select lines SSL1 and SSL2 can be divided into multiple regions by upper separation layer 160.

[0049] In an exemplary embodiment of the present invention, a virtual channel structure DCH may be provided in the region where the separation layer 160 is arranged. The virtual channel structure DCH may have the same structure as the channel structure CH, but may not be connected to a bit line.

[0050] exist Figure 4 In the illustrated embodiment, the channel structure CH and the separation layer 140 have a shape extending in the first direction, and therefore their width can vary in the first direction. (Reference) Figure 4 Each of the channel structure CH and the separation layer 140 may have a tapered structure that narrows in width as it approaches the second substrate 102.

[0051] Next, refer to Figure 5 A memory device 200 according to an exemplary embodiment of the present invention may include a cell region C and a peripheral circuit region P arranged vertically to each other. Figure 5 The memory device 200 of the illustrated embodiment may have a similar design to that according to Figure 4 The structure of the memory device 100 in the illustrated embodiment is such that descriptions of similar features can be omitted. Figure 4 and Figure 5 In this context, similar reference numerals can be used to denote the same elements. For example, in... Figure 4 In the diagram, 101 is used to represent the first substrate, while... Figure 5 In the text, 201 is used to represent the first substrate, where "2" is the only distinguishing element. Figure 5 The remaining elements are similarly represented by "2", and correspond to Figure 4 The components represented by "1" in the text.

[0052] exist Figure 5 In the illustrated embodiment, to reduce process problems caused by the increased number of word lines WL, after stacking some word lines WL to form a lower channel structure, the remaining word lines WL can be stacked to form an upper channel structure. Therefore, as... Figure 5 As shown, each of the channel structures CH can include an upper channel structure and a lower channel structure. For example, the word lines traversed by the lower channel structure and the lower channel structure can be referred to as the lower stack structure, and the word lines traversed by the upper channel structure and the upper channel structure can be referred to as the upper stack structure.

[0053] The lower channel structure can extend from the second substrate 202, and the upper channel structure can extend from the lower channel structure to be connected to the bit line via the bit line connection layer 230. In each of the channel structures CH, the channel region 210 of the upper channel structure and the channel region 210 of the lower channel structure can be connected to each other.

[0054] Based on reference Figures 3 to 5 In the memory devices 100 and 200 of the described embodiments, memory cells may be provided by a channel structure CH and a word line WL. Memory cells included in each of memory blocks BLK1 and BLK2 may share a channel structure CH or a word line WL. For example, memory cells arranged at the same height in a first direction (Z-axis direction) in each of memory blocks BLK1 and BLK2 may share one of the word lines WL. Furthermore, memory cells arranged at the same positions in a second direction (Y-axis direction) and a third direction (X-axis direction) in each of memory blocks BLK1 and BLK2 may share one of the channel structures CH. Figure 5 The virtual word line (DWL) is also shown.

[0055] Erasing operations on data stored in memory cells can be performed on a per-unit basis in memory blocks BLK1 and BLK2, which are divided by separation layers 140 and 240. In an exemplary embodiment of the present invention, a predetermined bias voltage is input to word line WL, and an erase voltage is input to substrates 102 and 202 to perform the erase operation. Therefore, erase operations can be performed on a per-unit basis in memory blocks BLK1 and BLK2, which are separated by word lines WL.

[0056] In an exemplary embodiment of the present invention, at least one of memory blocks BLK1 and BLK2 is allocated as a security block for storing secure data. Scan data obtained by counting the number of times the secure data is accessed abnormally during operation can also be stored in the security block. Furthermore, when the number of executions included in the scan data increases to a predetermined reference number, access to the security block can be prevented by performing security processing. For example, in the event of an attempt to access the secure data again by initializing the scan data, the secure data stored in the security block along with the scan data is initialized (e.g., deleted), thereby effectively protecting the secure data.

[0057] Figure 6 This is a circuit diagram provided to describe the operation of a memory device according to an exemplary embodiment of the present invention.

[0058] refer to Figure 6 A memory block BLK may include multiple memory cell strings CS, and at least some of the memory cell strings CS may include word lines WL1-WLn and / or bit lines BL1-BL3.

[0059] Each of the memory cell strings CS may include a plurality of memory cells MC connected between first and second string select transistors SST1 and SST2 and a ground select transistor GST. The first and second string select transistors SST1 and SST2 are connected in series with each other, and a second string select transistor SST2 disposed on the first string select transistor SST1 may be connected to one of bit lines BL1-BL3. The ground select transistor GST may be connected to a common source line CSL. The memory cells MC included in each of the memory cell strings CS may share a channel region.

[0060] Multiple memory cells MC can be connected in series with each other between the first and second string select transistors SST1 and SST2 and the ground select transistor GST. According to an exemplary embodiment of the present invention, the number of string select transistors SST1 and SST2 and the ground select transistor GST can be modified differently, and each of the memory cell strings CS can further include at least one dummy memory cell. For example, the dummy memory cell can be connected between the first string select transistor SST1 and the memory cell MC and / or between the ground select transistor GST and the memory cell MC.

[0061] The gate electrodes of multiple memory cells MC can be connected to word lines WL1-WLn. In addition, the gate electrode of the ground select transistor GST can be connected to the ground select line GSL, and the gate electrodes of the first and second string select transistors SST1 and SST2 can be connected to the string select lines SSL11, SSL12, SSL13, SSL21, SSL22 and SSL23.

[0062] The ground select line GSL, word lines WL1-WLn, and string select lines SSL11-SSL23 can be stacked in a first direction perpendicular to the upper surface of the substrate. The ground select line GSL, word lines WL1-WLn, and string select lines SSL11-SSL23 can be traversed by a channel structure including a channel region. The channel structure can be connected to one of the bit lines BL1-BL3.

[0063] A memory block BLK can be a cell region in which an erase operation is performed within a memory device. For example, a bias voltage can be applied to word lines WL1-WLn, serial select lines SSL11-SSL23, and ground select line GSL, and a high erase voltage can be applied to the common source line CSL. Charge trapped in a memory cell MC can be eliminated by the erase voltage applied to the common source line CSL, and the memory cells MC included in the memory block BLK can be changed to an erase state.

[0064] When memory block BLK is a secure block storing secure data, scan data obtained by counting the number of abnormal accesses to the secure data can be stored in memory block BLK. For example, secure data can be stored in memory cell MC connected to word line j-th WLj, and scan data can be stored in memory cell connected to word line i-th WLi. For example, secure data and scan data can be stored in different pages of memory block BLK.

[0065] When an initialization attempt to delete scan data occurs, data in all memory cells (MCs) included in the memory block (BLK) can be deleted. Therefore, by attempting to initialize the scan data, secure data is deleted along with it, preventing the leakage of secure data.

[0066] Figures 7 to 9 This is a diagram provided to illustrate the operation of a memory device according to an exemplary embodiment of the present invention.

[0067] refer to Figure 7 The memory device 300 according to an exemplary embodiment of the present invention may include a memory region 310 and peripheral circuitry 320. Peripheral circuitry 320 may include a line decoder 321, a voltage generator 322, a page buffer 323, input / output circuitry 324, control logic 325, etc. The operation of components 321-325 included in peripheral circuitry 320 may be similar to that described above. Figure 2 The operations described in the embodiments.

[0068] Memory region 310 may include a first memory block BLK1 and a second memory block BLK2. However, in addition to the first memory block BLK1 and the second memory block BLK2, memory region 310 may also include other memory blocks. The first memory block BLK1 may be connected to a first page buffer PB1, and the second memory block BLK2 may be connected to a second page buffer PB2.

[0069] Each of the first memory block BLK1 and the second memory block BLK2 may include a plurality of pages PAGE1-PAGEn. Each of the pages PAGE1-PAGEn may be a unit for writing data to the peripheral circuitry 320. In an exemplary embodiment of the present invention, the pages PAGE1-PAGEn may be defined by word lines included in each of the memory blocks BLK1 and BLK2.

[0070] exist Figure 7 In the illustrated embodiment, the first memory block BLK1 and the second memory block BLK2 can be controlled by control logic 325 in different schemes. In the example, control logic 325 can select one of a first mode and a second mode to control memory region 310. For example, one of the first mode and the second mode could be a normal mode, in which access to at least one of the memory blocks BLK1 and BLK2 included in memory region 310 is restricted, and the other of the first mode and the second mode could be a secure mode in which both memory blocks BLK1 and BLK2 are accessible. In the following, for ease of description, it is assumed that the first mode is the normal mode, the second mode is the secure mode, and the second memory block BLK2 is a secure block accessible only in the second mode.

[0071] Figure 8 This is a diagram provided to illustrate the operation of the memory device 300 in a first mode. (Reference) Figure 8In the first mode, control logic 325 can control memory device 300 such that only the first memory block BLK1 is accessible. The second memory block BLK2, allocated as a secure block, can store secure data of memory device 300 and / or hosts connected to memory device 300, and access to the second memory block BLK2 can be restricted in the first mode.

[0072] exist Figure 8 In an exemplary embodiment of the present invention shown, security data can be stored in the first page PAGE1 of the second memory block BLK2. Furthermore, depending on the capacity of the security data, it can also be stored in two or more pages PAGE1-PAGEn included in the second memory block BLK2. Additionally, scan data indicating the number of times the security data has been accessed can be recorded on the second page PAGE2 of the second memory block BLK2. The scan data can be data recorded by counting the number of times the second memory block BLK2 has been accessed or the number of times the second memory block BLK2 has been attempted to be accessed in a first mode.

[0073] In the first mode, which is the normal mode, access to the second memory block BLK2 is essentially restricted. However, secure data stored in the second memory block BLK2 may be leaked by attackers such as hackers who scan the entire memory region 310 and analyze the data patterns. In an exemplary embodiment of the inventive concept, the number of times the second memory block BLK2 is accessed or attempted to be accessed in the first mode can be counted and written to the second memory block BLK2 as scan data.

[0074] When the number of accesses stored as scan data reaches a predetermined reference number, control logic 325 can prevent external sources from accessing the second memory block BLK2 in various ways. As an example, control logic 325 can control row decoder 321 and / or voltage generator 322 to prevent bias voltages used for programming or read operations from being supplied to the word line WL connected to the second memory block BLK2. Alternatively, access to the second memory block BLK2 can be limited by disabling the second page buffer PB2 connected to the second memory block BLK2.

[0075] Figure 9 This is a schematic diagram provided to illustrate the operation of the memory device 300 in the second mode. (Reference) Figure 9In the second mode, control logic 325 can control memory device 300 to access the second memory block BLK2. In the second mode, operations such as writing data to the second memory block BLK2 or reading secure data stored in the first page PAGE1 of the second memory block BLK2 can be performed normally and are not counted as access counts or stored as scan data.

[0076] According to an exemplary embodiment of the present invention, the first memory block BLK1 and the second memory block BLK2 can be controlled in different ways. Compared to the first memory block BLK1, which stores general data, the second memory block BLK2 stores security data of high importance; therefore, a relatively large data storage capacity can be allocated to the first memory block BLK1. For example, N bits of data can be stored in each memory cell included in the first memory block BLK1, and M bits of data can be stored in each memory cell included in the second memory block BLK2. N and M are both natural numbers, and M can be less than N. For example, each memory cell in the first memory block BLK1 can operate as a three-level or four-level cell, and each memory cell in the second memory block BLK2 can operate as a single-level or multi-level cell.

[0077] In the second memory block BLK2, security data and scan data of relatively high importance can be stored in pages PAGE1 and PAGE2, which consist of memory cells operating as single-level units. In the example, scan data can be stored in multiple flag cells operating as single-level units, and these flag cells can share a single word line WL in the second memory block BLK2. Furthermore, the scan data can be partitioned in bit format and stored in the flag cells. The method for storing scan data in the second memory block BLK2 will be described later.

[0078] When different methods are used to control the first memory block BLK1 and the second memory block BLK2, the structures of the first page buffer PB1 and the second page buffer PB2 can be different, which will be referred to below. Figure 10 and 11 Describe it.

[0079] Figure 10 and 11 This is a circuit diagram schematically illustrating a page buffer included in a memory device according to an exemplary embodiment of the present invention.

[0080] refer to Figure 10 and 11A memory device 400 may include multiple memory blocks BLK1 and BLK2 and multiple page buffers PB1 and PB2. For example, when the memory device 400 operates in normal mode and safe mode, the first memory block BLK1 may be an accessible block. On the other hand, the second memory block BLK2 is not accessible in normal mode and may be a block accessible only in safe mode.

[0081] First refer to Figure 10 The first page buffer PB1, connected to the first memory block BLK1, may include a p-type metal-oxide-semiconductor (PMOS) device PM1, first, second, and third n-type metal-oxide-semiconductor (NMOS) devices NM1, NM2, and NM3, and latches LAT1, LAT2, and LAT3. The first memory block BLK1 may include multiple memory cells MC1-MCn, and the memory cells MC1-MCn may be connected to word lines WL1-WLn. According to an exemplary embodiment of the present invention, the number of latches LAT1-LAT3 included in the first page buffer PB1 may vary, and the latches LAT1-LAT3 may be connected to a sensing node SO. For example, the number of latches LAT1-LAT3 included in the first page buffer PB1 may vary depending on the number of bits of data stored in each of the memory cells MC1-MCn.

[0082] The first page buffer PB1 can be connected to the memory cells MC1-MCn of the first memory block BLK1 via bit line BL. Figure 10 In this configuration, the serial select element and the ground select element can be connected to the two ends of memory cells MC1-MCn. Furthermore, with... Figure 10 Compared to the previous diagram, a greater number of memory cells MC1-MCn can be further connected to bit lines BL that are connected to the first page buffer PB1.

[0083] During the read operation, the first page buffer PB1 precharges the sensing node SO and the bit line BL, and inputs a predetermined bias voltage to the memory cells MC1-MCn to develop the sensing node SO, thereby reading the selected memory cell MC1. SEL The data is processed as follows. For example, to precharge the sensing node SO and bit line BL, PMOS device PM1 is turned on by the load signal LOAD, so the power supply voltage VDD can be input to the sensing node SO. Furthermore, bit line BL can be precharged by turning on the first NMOS device NM1 and the second NMOS device NM2 by the bit line select signal BLSLT and the control signal BLSHF. In response to the shield signal SHLD, the third NMOS device NM3 can be turned on and the bit line BL can be discharged. Therefore, during a read operation, the third NMOS device NM3 can be turned off.

[0084] When the precharge operation is complete, the PMOS device PM1 can be turned off. Charge can then be applied to all memory cells except the selected memory cell MC. SEL The remaining memory cells, other than those in the memory cell MC, can input voltage and can supply voltage to the selected memory cell MC. SEL Input the predetermined read voltage. This depends on the selected memory cell MC. SEL The amplitude relationship between the read voltage and the threshold voltage, and the selected memory cell MC SEL It can be identified as an on-cell or off-cell. The voltage of the sensing node SO depends on the selected memory cell MC. SEL The threshold voltage is determined by one of the latches LAT1, which latches the voltage of the sensing node SO to read the selected memory cell M. CSEL The data.

[0085] Two or more bits of data can be stored in each of the memory cells MC1-MCn of the first memory block BLK1, which can be accessed in both normal and safe modes. Therefore, the first page buffer PB1 can include multiple latches LAT1-LAT3. Figure 10 In the embodiment shown, the memory cells MC1-MCn of the first memory block BLK1 can store three or more bits of data.

[0086] refer to Figure 11 The second page buffer PB2 can be connected to the second memory block BLK2, which is accessible only in safe mode. The structure and operation of the second page buffer PB2 can be similar to the above reference. Figure 10 The first page buffer PB1 is described.

[0087] On the other hand, the number of bits of data stored in each of the memory cells MC1-MCn in the second memory block BLK2 can be less than the number of bits of data stored in each of the memory cells MC1-MCn in the first memory block BLK1. (Reference) Figure 11 The second page buffer PB2 includes a first latch LAT1 and a second latch LAT2, such that each of the memory cells MC1-MCn of the second memory block BLK2 can store two bits or less of data. In an exemplary embodiment of the present invention, the number of latches included in the first page buffer PB1 connected to the first memory block BLK1, which is accessible in both safe and normal modes, may differ from the number of latches included in the second page buffer PB2 connected to the second memory block BLK2, which is accessible only in safe mode.

[0088] Figure 12This is a flowchart provided to describe the operation of a memory device according to an exemplary embodiment of the present invention.

[0089] refer to Figure 12 Operation of the memory device can begin by receiving a read command (S10). The read command can be generated from a host and / or memory controller connected to the memory device. The memory device can receive address information, in which the data to be read is provided along with the read command, and can determine whether the address information corresponds to a secure block (S11).

[0090] When a read command determines that a secure block should be accessed, the memory device can determine whether the current operating mode is a first mode or a second mode (S12). For example, the first mode can be a normal mode and can be an operating mode where secure blocks cannot be accessed. On the other hand, the second mode is a secure mode and can be an operating mode where secure blocks can be accessed. When the address information received along with the read command does not correspond to a secure block, the memory device can perform a data read operation (S16).

[0091] As a result of the determination in operation S12, if the current operating mode is not the first mode, for example, if the current operating mode is the second mode, the memory device may perform a data read operation (S16). On the other hand, if the current operating mode is the first mode as a result of the determination in operation S12, the memory device may determine that an abnormal access to the secure block has occurred in the first mode. In the first mode, the memory device counts the number of accesses to the control operations that have been performed on the secure block (S13) and determines whether the number of executions has been counted to a predetermined reference number or more (S14).

[0092] When the number of executions of the count is less than the reference count, as determined in operation S14, the memory device may perform a data read operation (S16). Conversely, when it is determined in operation S14 that the number of executions of the count has increased to the reference count or more, the memory device may perform security processing for the secure block (S15). Security processing may include operations that prevent access to the secure block. For example, the control logic of the memory device may delete data stored in the page buffer connected to the secure block, or it may set the page buffer to an unavailable state. Alternatively, when the address information received along with a read command from the memory controller or host corresponds to a secure block, access to the secure block may be prevented by stopping the operation of the line decoder and / or voltage generator. Alternatively, when the address information received along with the read command corresponds to a secure block, the amplitude of the voltage output by the voltage generator may be changed to prevent normal operation from being performed.

[0093] Figure 13This is a diagram provided to illustrate the operation of a memory device according to an exemplary embodiment of the present invention.

[0094] exist Figure 13 In the illustrated embodiment, the memory device includes a first memory block BLK1 and a second memory block BLK2, and highly important security data can be stored in the second memory block BLK2. Each of the first memory block BLK1 and the second memory block BLK2 can be a cell region in the memory device where an erase operation is performed. In an example scenario, an attacker, such as a hacker, can scan the entire memory region including the first memory block BLK1 and the second memory block BLK2 and steal the security data stored in the second memory block BLK2 by analyzing the data pattern.

[0095] In an exemplary embodiment of the present invention, when an access to the second memory block BLK2 is detected through a memory region scan as described above, the number of times the second memory block BLK2 is accessed is counted and stored as scan data in the second memory block BLK2. For example, the number of abnormal accesses to the second memory block BLK2 storing secure data can be counted and stored in the second memory block BLK2. (Reference) Figure 13 In the second memory block BLK2, security data can be stored in the second page PAGE2, and scan data can be stored in the fourth page PAGE4. Furthermore, as described above, when the number of accesses stored in the scan data increases to a predetermined reference number, security processing to prevent access to the second memory block BLK2 can be performed.

[0096] On the other hand, even when security processing is performed, an attack on the second memory block BLK2 can be attempted again. For example, an attacker, such as a hacker, could initialize the scan data to release the security processing and attempt to access the second memory block BLK2 again. In an exemplary embodiment of the present invention, since the scan data is stored together with the security data in the second memory block BLK2, the security data can be deleted along with the scan data when an attacker attempts to initialize the scan data, thus preventing a hacker from obtaining the security data.

[0097] Figure 14 and 15 This is a diagram illustrating a method for storing scan data in a memory device according to an exemplary embodiment of the present invention.

[0098] First of all, Figure 14 In the illustrated embodiment, the memory device can store scan data by increasing the threshold voltage of the flag cell storing the scan data. (See reference...) Figure 14When the number of accesses to the secure block in normal mode is 0, the flag cell can be in an erase state (E0), as shown in the first figure 500. When the number of accesses to the secure block in normal mode is detected, as shown in the second graph 510, the memory device can increase the threshold voltage of the flag cell to transition from the erase state (E0) to the first programming state (P1).

[0099] When the flag unit is in the first programming state P1, the memory device can reprogram the flag unit to the second programming state P2 when access to the secure block in normal mode is detected again, as shown in the third curve 520. When access to the secure block in normal mode is detected n times, the flag unit can be programmed to the nth programming state Pn, as shown in the fourth curve 530.

[0100] In normal mode, when access to and / or attempted access to a secure block occurs a predetermined number of references or more, the memory device can perform security procedures to prevent access to the secure block. For example, in the case of n references, and when the threshold voltage of the flag cell is greater than the reference voltage V shown in the fourth curve 530. REF At this time, the memory device can determine that the number of accesses to the security block in normal mode is greater than or equal to the reference number. Therefore, the memory device can set the threshold voltage of the flag cell relative to the reference voltage V. REF The comparison is performed, and the threshold voltage of the flag cell is greater than the reference voltage V. REF At that time, security procedures will be implemented.

[0101] Reference Figure 14 In the described embodiment, there may be two or more flag units. When the threshold voltage of each of the two or more flag units is greater than the reference voltage V... REF At this time, the memory device can perform security processing. According to an exemplary embodiment of the present invention, different reference voltages V REF It can also be applied to at least some of two or more flag units.

[0102] exist Figure 15 In the illustrated embodiment, scan data D1-Dn can be distributed and stored in multiple flag units MC1-MCn connected to a word line WL. In an exemplary embodiment of the inventive concept, each of the flag units MC1-MCn can be provided by different channel regions CH1-CHn.

[0103] exist Figure 15In the illustrated embodiment, when each of the flag units MC1-MCn stores 1 bit of data, the scan data D1-Dn can be n bits of data. Alternatively, when each of the flag units MC1-MCn stores 2 bits of data, the scan data D1-Dn can be 2n bits of data. The memory device can generate the scan data D1-Dn by merging the data read from the corresponding flag units MC1-MCn.

[0104] In the example, scan data D1-Dn can be distributed in bit format and stored in flag cells MC1-MCn. The maximum number of abnormal accesses to the secure block stored in scan data D1-Dn can be set to 2. n The data stored in each of the flag cells MC1-MCn and the count of abnormal accesses to the secure block can be set as shown in Table 1 below. For ease of description, Table 1 shows the case where the number of flag cells MC1-MCn storing scan data is six.

[0105] [Table 1]

[0106] count D1 D2 D3 D4 D5 D6 0 0 0 0 0 0 0 1 1 0 0 0 0 0 2 0 1 0 0 0 0 3 1 1 0 0 0 0 … … … … … … … 63 1 1 1 1 1 1

[0107] In an exemplary embodiment of the inventive concept described with reference to Table 1, the number of abnormal accesses generated for the secure block can be counted up to 63 times and can be stored as scan data in the flag unit. However, the reference number of times the memory device performs security processing for the secure block is not necessarily limited to 63, which is the maximum number that can be stored, and the reference number can be defined differently.

[0108] Figure 16 and 17 This is a diagram provided to illustrate the operation of a memory device according to an exemplary embodiment of the present invention.

[0109] exist Figure 16 and 17 In the illustrated embodiment, the memory device 600 may include a memory region 610 and peripheral circuitry 620. Peripheral circuitry 620 may include a line decoder 621, a voltage generator 622, a page buffer 623, input / output circuitry 624, control logic 625, etc. The operation of components 621-625 included in peripheral circuitry 620 may be similar to that described above. Figure 2 and 7 Those described in -9. For example, memory device 600 can operate in one of a first mode and a second mode, and can access only the first memory block BLK1 in the first mode and only the second memory block BLK2 in the second mode.

[0110] refer to Figure 16In the first mode, the number of accesses to the second memory block BLK2 for control operations increases to a predetermined reference number or more; therefore, control logic 625 can perform security processing on the second memory block BLK2. Thus, as... Figure 16 As shown, access to the second memory block BLK2 can be blocked. Control logic 625 can block access to the second memory block BLK2 by controlling at least one of the row decoder 621, voltage generator 622, and second page buffer PB2.

[0111] In an exemplary embodiment of the present invention, the number of times the control operation for the second memory block BLK2 is executed in the first mode can be stored as scan data in the second memory block BLK2. Figure 16 In the embodiment shown, scan data is stored in the second page PAGE2 of the second memory block BLK2, while security data can be stored in the first page PAGE1 of the second memory block BLK2.

[0112] In an exemplary embodiment of the present invention, when scan data is initialized, control logic 625 can release security processing performed on the second memory block BLK2. For example, when a predetermined authentication process provided by memory device 600 passes, control logic 625 reprograms the access count included in the scan data to zero to release security processing on the second memory block BLK2.

[0113] However, attempts to initialize scan data and release security processing could be performed by an attacker (such as a hacker) to forcibly delete the scan data. In this case, in an exemplary embodiment of the present invention, since the scan data is stored in the same second memory block BLK2 as the security data, the security data can be deleted along with the scan data when the attacker deletes the scan data. Figure 17 As shown. Therefore, the leakage of secure data can be prevented.

[0114] Figure 18 This is a diagram schematically illustrating a memory system according to an exemplary embodiment of the concept of the present invention.

[0115] refer to Figure 18 The memory system 700 according to an exemplary embodiment of the present invention may include a memory controller 710 and a plurality of memory devices 720-750. The memory controller 710 may communicate with a host to which the memory system 700 is connected and may control the memory devices 720-750 in response to control commands received from the host.

[0116] The memory devices 720-750 can be implemented using separate semiconductor chips. Figure 18In the illustrated embodiment, at least a portion of the memory devices 720-750 may include a normal block NB and a secure block SB. When the memory system 700 operates in normal mode, only the normal block NB is activated, and normal access to the secure block SB may be impossible. However, by scanning all the normal and secure blocks NB and SB included in the memory devices 720-750 and analyzing the data pattern, a hacker could access secure data stored in the secure block SB in normal mode.

[0117] According to an exemplary embodiment of the present invention, the number of times data stored in the secure block SB is accessed in normal mode can be counted, and the counted access counts can be stored in the secure block SB as scan data. The operation of counting the number of accesses to the secure block SB in normal mode and storing these access counts as scan data in the secure block SB can be performed by control logic included in each of the memory controller 710 and / or memory devices 720-750. For example, each of the memory devices 720-750 can count and maintain its own access count. Therefore, in cases such as when an attacker, like a hacker, removes a specific device from the memory devices 720-750, bypasses the memory controller 710, and immediately accesses the secure block SB, this immediate access can also be counted and stored as scan data, thereby effectively protecting the secure data stored in the secure block SB.

[0118] Figure 19 This is a diagram schematically illustrating a mobile system including a memory device according to an exemplary embodiment of the present invention.

[0119] refer to Figure 19 The mobile system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, dynamic random access memory (DRAM) 1500a and 1500b, flash memory devices 1600a and 1600b, input / output devices 1700a and 1700b, and an application processor (hereinafter referred to as "AP") 1800.

[0120] The mobile system 1000 can be implemented as a laptop computer, portable terminal, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, the mobile system 1000 can be implemented as a server or personal computer.

[0121] Camera 1100 can capture still images or videos according to user control. Mobile system 1000 can use the still images / videos captured by camera 1100 to obtain specific information, or convert the still images / videos into other types of data such as text and store that data. Alternatively, mobile system 1000 can recognize strings included in still images / videos captured by camera 1100 and provide text or audio translations corresponding to those strings. Thus, the applications of camera 1100 in mobile system 1000 are diverse. In an exemplary embodiment of the inventive concept, camera 1100 can send data, such as still images / videos, to AP 1800 via a D-Phy or C-Phy interface according to the MIPI standard.

[0122] Display 1200 can be implemented in various forms, such as liquid crystal display (LCD), organic light-emitting diode display (OLED), active-matrix organic light-emitting diode (AM-OLED), plasma display panel (PDP), field emission display (FED), electronic paper, etc. In an exemplary embodiment of the present invention, display 1200 can also be used as an input device for mobile system 1000 by providing touchscreen functionality. Furthermore, display 1200 can be integrated with a fingerprint sensor, etc., to provide security functions for mobile system 1000. In an exemplary embodiment of the present invention, access point 1800 can send image data to be displayed on display 1200 via a D-Phy or C-Phy interface based on the MIPI standard.

[0123] The audio processor 1300 can process audio data stored in flash memory devices 1600a and 1600b, or audio data included in content received from external sources via modem 1400 or input / output devices 1700a and 1700b. For example, the audio processor 1300 can perform various processes on the audio data, such as encoding / decoding, amplification, and noise filtering.

[0124] The modem 1400 modulates and transmits signals to send / receive wired / wireless data and demodulates signals received from external sources to recover the original signal. Input / output devices 1700a and 1700b are devices that provide digital input / output and may include components for connecting to external recording media, such as input devices like touchscreens, mechanical buttons, etc., and output devices that output vibrations in a tactile or other manner. In some examples, input / output devices 1700a and 1700b can be connected to external recording media via ports such as Universal Serial Bus (USB), Lightning cable, Secure Digital (SD) card, Micro SD card, Digital Video Disc (DVD), network adapter, etc.

[0125] AP 1800 can control the overall operation of mobile system 1000. For example, AP 1800 can control display 1200, causing some content stored in flash memory devices 1600a and 1600b to be displayed on the screen. Furthermore, when user input is received via input / output devices 1700a and 1700b, AP 1800 can execute control operations corresponding to the user input.

[0126] The AP 1800 can be provided as a system-on-a-chip (SoC) driving applications, operating systems, etc. Furthermore, the AP 1800 can be included in a semiconductor package along with other devices included in the mobile system 1000 (e.g., DRAM 1500a, flash memory 1620, and / or memory controller 1610). For example, the AP 1800 and at least one or more devices can be provided in the form of packages such as Package on Package (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-level Processed Stack Package (WSP), etc. The kernel of the operating system running on the AP 1800 can include device drivers and I / O schedulers for controlling flash memory devices 1600a and 1600b. The device driver can control the access performance of flash devices 1600a and 1600b by referencing the number of synchronization queues managed by the I / O scheduler, or control the CPU mode, Dynamic Voltage and Frequency Scaling (DVFS) level, etc. within the SoC.

[0127] In an exemplary embodiment of the present invention, the AP 1800 may include a processor block that performs operations or drives applications and / or an operating system, as well as various other peripheral components connected to the processor block via a system bus. Peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, etc. The processor block may include one or more cores, and in the case of multiple cores in the processor block, each core includes a cache memory, and a common cache memory shared by the cores may be included in the processor block.

[0128] In an exemplary embodiment of the present invention, AP 1800 may further include accelerator block 1820, which is dedicated circuitry for artificial intelligence (AI) data computation. Alternatively, according to an exemplary embodiment of the present invention, a separate accelerator chip may be provided separately from AP 1800, and DRAM 1500b may be additionally connected to accelerator block 1820 or the accelerator chip. Accelerator block 1820 is a functional block that performs specific functions of AP 1800 and includes a graphics processing unit (GPU) that is a functional block specifically for processing graphics data, a neural processing unit (NPU) that is a block for performing AI computation and inference, a data processing unit (DPU) that is a block specifically for processing data transmission, etc.

[0129] According to an exemplary embodiment of the present invention, the mobile system 1000 may include a plurality of DRAMs 1500a and 1500b. In an exemplary embodiment of the present invention, the AP 1800 may include a controller 1810 for controlling the DRAMs 1500a and 1500b, and the DRAM 1500a may be directly connected to the AP 1800.

[0130] The AP 1800 controls DRAMs 1500a and 1500b by setting a JEDEC-compliant Command and Mode Register Set (MRS), or by setting the specifications and functions required by the Mobile System 1000 (such as low voltage / high speed / reliability) and the DRAM interface protocol for CRC / ECC. For example, the AP 1800 can communicate with DRAM 1500a via a JEDEC-compliant interface (such as LPDDR4, LPDDR5, etc.). Alternatively, the AP 1800 can set a new DRAM interface protocol to control DRAM 1500b, which has a higher bandwidth than DRAM 1500a, via accelerator block 1820 or an accelerator chip provided separately from the AP 1800, thereby enabling communication.

[0131] Despite Figure 19Only DRAMs 1500a and 1500b are shown, but the configuration of the mobile system 1000 is not limited to this type. Depending on the bandwidth, response speed, and voltage conditions of the AP 1800 or accelerator block 1820, other memories besides DRAMs 1500a and 1500b can also be included in the mobile system 1000. In the example, the controller 1810 and / or the accelerator block 1820 can control various memories, such as phase-change RAM (PRAM), static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), hybrid RAM, etc. DRAMs 1500a and 1500b have relatively low latency and high bandwidth compared to input / output devices 1700a and 1700b or flash memory devices 1600a and 1600b. DRAM 1500a and 1500b can be initialized at the power-on time of the mobile system 1000, and when the operating system and application data are loaded, DRAM 1500a and 1500b can be used as temporary storage locations for the operating system and application data or as execution space for various software code.

[0132] In DRAMs 1500a and 1500b, addition / subtraction / multiplication / division arithmetic operations and vector operations, address operations, or Fast Fourier Transform (FFT) operation data can be stored. In another embodiment, DRAMs 1500a and 1500b can be provided as processing-in-memory (PIM) equipped with computational capabilities. For example, functions for performing inference in DRAMs 1500a and 1500b can be executed. In this case, inference can be performed using an artificial neural network in a deep learning algorithm. The deep learning algorithm can include training operations that train a model with various data and inference operations that identify data using the trained model. For example, functions used for inference can include the hyperbolic tangent function, the sigmoid function, and the Corrected Linear Unit (ReLU) function.

[0133] In an exemplary embodiment of the present invention, an image captured by a user through a camera 1100 can be signal processed and stored in a DRAM 1500b. An accelerator block 1820 or an accelerator chip can use the data stored in the DRAM 1500b and the functions for inference to perform AI data operations on the recognition data.

[0134] According to an exemplary embodiment of the present invention, the mobile system 1000 may include multiple storage devices or multiple flash memory devices 1600a and 1600b, which have a larger capacity than DRAM 1500a and 1500b. Flash memory devices 1600a and 1600b may include a memory controller 1610 and flash memory 1620. The memory controller 1610 receives control commands and data from the AP 1800, writes data to the flash memory 1620 in response to the control commands, or reads data stored in the flash memory 1620 to access the AP 1800, and may also send data to the AP 1800.

[0135] According to an exemplary embodiment of the present invention, the accelerator block 1820 or accelerator chip can use flash memory devices 1600a and 1600b to perform training operations and AI data computation. In an exemplary embodiment of the present invention, operational logic capable of performing predetermined operations within the flash memory devices 1600a and 1600b can be implemented in the controller 1610, and the operational logic can use data stored in the flash memory 1620 to locally perform at least a portion of the training operations and inference AI data operations performed by the AP 1800 and / or the accelerator block 1820.

[0136] In an exemplary embodiment of the present invention, AP 1800 may include interface 1830, so flash memory devices 1600a and 1600b can be directly connected to AP 1800. For example, AP 1800 may be implemented as a SoC, flash memory device 1600a may be implemented as a separate chip from AP 1800, and AP 1800 and flash memory device 1600a may be mounted in a single package. However, the concept of the present invention is not limited thereto, and multiple flash memory devices 1600a and 1600b may be electrically connected to mobile system 1000 via interconnection.

[0137] Flash memory devices 1600a and 1600b can store data such as still images / movies captured by camera 1100, or data received via a communication network and / or ports included in input / output devices 1700a and 1700b, and can store, for example, augmented reality / virtual reality, high-definition (HD) or ultra-high-definition (UHD) content.

[0138] exist Figure 19 In the exemplary embodiments of the inventive concept shown, flash memory devices 1600a and 1600b can be implemented according to the above references. Figures 1 to 18The described embodiments refer to memory devices or memory systems. Because flash memory devices 1600a and 1600b are non-volatile, they can store security data required for the operation of at least one of the mobile system 1000 and its components, such as security keys and private keys. At least one of the flash memory devices 1600a and 1600b may include a security block for storing security data. Scan data obtained by counting the number of abnormal accesses to the security data may be stored along with the security data in the security block.

[0139] Flash devices 1600a and 1600b can prevent access to the security block when the number of accesses stored in the scan data is greater than or equal to a predetermined reference number. Furthermore, since the scan data is stored together with the security data in the security block, the security data is deleted along with the scan data when an attempt is made to initialize the scan data to prevent leakage of the security data.

[0140] Figure 20 This is a view schematically illustrating the structure of a memory device according to an exemplary embodiment of the present invention.

[0141] refer to Figure 20 The memory device 2000 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then bonding the upper and lower chips together. For example, the bonding method may include a method of forming adhesive metal on the topmost metal layer of the upper chip and adhesive metal on the topmost metal layer of the lower chip with electrical connections. For example, when the adhesive metal is formed of copper (Cu), the bonding method may be Cu-Cu bonding, and the adhesive metal may also be formed of aluminum or tungsten.

[0142] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device 2000 may include an external pad bonding region (PA), a word line bonding region (WLBA), and a bit line bonding region (BLBA). The cell region (CELL) may include multiple memory blocks having a first memory block and a second memory block, and the peripheral circuit region (PERI) may include circuitry driving the multiple memory blocks in the cell region (CELL). In an exemplary embodiment of the inventive concept, control logic may be included in the peripheral circuit region (PERI). The control logic may select one of a first mode and a second mode. The control logic may perform control operations on the first memory block in the first mode and on both the first and second blocks in the second mode. Furthermore, the control logic may calculate the number of times the second memory block has been accessed in the first mode and store scan data including the access count in the second memory block. When attempting to initialize the scan data, secure data stored in the second memory block may also be deleted, thus improving the security of the memory device 2000.

[0143] The Peripheral Circuit Region (PERI) may include a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210, first metal layers 2230a, 2230b, and 2230c respectively connected to the plurality of circuit elements 2220a, 2220b, and 2220c, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. In an exemplary embodiment of the present invention, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten, which has relatively high resistance, and the second metal layers 2240a, 2240b, and 2240c may be formed of copper, which has relatively low resistance.

[0144] exist Figure 20 In the exemplary embodiments of the inventive concept shown, although first metal layers 2230a, 2230b, and 2230c and second metal layers 2240a, 2240b, and 2240c are shown and described, they are not limited thereto, and one or more metal layers may be further formed on the second metal layers 2240a, 2240b, and 2240c. At least a portion of the one or more metal layers formed on the second metal layers 2240a, 2240b, and 2240c may be formed of aluminum or the like, which are different from the copper used to form the second metal layers 2240a, 2240b, and 2240c.

[0145] An interlayer insulating layer 2215 may be disposed on a first substrate 2210 and cover multiple circuit elements 2220a, 2220b and 2220c, first metal layers 2230a, 2230b and 2230c and second metal layers 2240a, 2240b and 2240c. The interlayer insulating layer 2215 may include an insulating material, such as silicon oxide, silicon nitride, etc.

[0146] The lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b in the peripheral circuit area PERI can be electrically connected to the upper bonding metals 2371b and 2372b in the cell area CELL by bonding, and the lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b can be formed of aluminum, copper, tungsten, etc.

[0147] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 2310 and a common source line 2320. On the second substrate 2310, multiple word lines 2331 to 2338 (e.g., 2330) may be stacked in a direction perpendicular to the upper surface of the second substrate 2310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged on and below the multiple word lines 2330, respectively, and the multiple word lines 2330 may be arranged between the at least one string select line and the at least one ground select line.

[0148] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 2310, and pass through multiple word lines 2330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c can be a bit line contact, and the second metal layer 2360c can be a bit line. In an exemplary embodiment of the present invention, the bit line 2360c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 2310.

[0149] exist Figure 20In the illustrated embodiment, the area where the channel structure CH, bit line 2360c, etc., are arranged can be a bit line bonding area (BLBA). Within the bit line bonding area (BLBA), bit line 2360c can be electrically connected to circuit element 2220c, and a page buffer 2393 is provided in the peripheral circuit area (PERI). For example, bit line 2360c can be connected to upper bonding metals 2371c and 2372c in the cell area (CELL), and upper bonding metals 2371c and 2372c can be connected to lower bonding metals 2271c and 2272c of the circuit element 2220c connected to the page buffer 2393.

[0150] In the word line bonding area WLBA, multiple word lines 2330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 2310 and can be connected to multiple cell contact plugs 2341 to 2347 (e.g., 2340). The multiple word lines 2330 and the multiple cell contact plugs 2340 can be connected to each other in pads provided by at least a portion of the multiple word lines 2330 extending at different lengths in the second direction. A first metal layer 2350b and a second metal layer 2360b can be sequentially connected to the upper portion of the multiple cell contact plugs 2340 connected to the multiple word lines 2330. The multiple cell contact plugs 2340 can be connected to the circuit region PERI in the word line bonding area WLBA via upper bonding metals 2371b and 2372b of the cell region CELL and lower bonding metals 2271b and 2272b of the peripheral circuit region PERI.

[0151] Multiple unit contact plugs 2340 may be electrically connected to circuit element 2220b providing line decoder 2394 in the peripheral circuitry region PERI. In an exemplary embodiment of the inventive concept, the operating voltage of circuit element 2220b providing line decoder 2394 may differ from the operating voltage of circuit element 2220c providing page buffer 2393. For example, the operating voltage of circuit element 2220c providing page buffer 2393 may be greater than the operating voltage of circuit element 2220b providing line decoder 2394.

[0152] A common source line contact plug 2380 can be disposed in an external pad bonding area PA. Furthermore, lower bonding metals 2271a and 2272a can be disposed in the external bonding area PA of the cell region CELL, and upper bonding metals 2371a and 2372a can be disposed in the external bonding area PA of the peripheral circuit region PERI. In the external pad bonding area PA, the lower bonding metals 2271a and 2272a can be electrically connected to the upper bonding metals 2371a and 2372a by adhesive bonding. The common source line contact plug 2380 can be formed of a conductive material such as metal, metal compound, polysilicon, etc., and can be electrically connected to the common source line 2320. A first metal layer 2350a and a second metal layer 2360a can be sequentially stacked on top of the common source line contact plug 2380. For example, the area where the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed can be the external pad bonding area PA.

[0153] Input / output pads 2205 and 2305 can be placed within the external pad bonding area PA. (See reference) Figure 20 A lower insulating film 2201 covering the lower surface of the first substrate 2210 may be formed below the first substrate 2210, and a first input / output pad 2205 may be formed on the lower insulating film 2201. The first input / output pad 2205 can be connected to at least one of a plurality of circuit elements 2220a, 2220b, and 2220c arranged in the peripheral circuit region PERI via a first input / output contact plug 2203, and can be separated from the first substrate 2210 via the lower insulating film 2201. Furthermore, a side insulating film may be disposed between the first input / output contact plug 2203 and the first substrate 2210 to electrically separate the first input / output contact plug 2203 and the first substrate 2210.

[0154] refer to Figure 20 An upper insulating film 2301 covering the upper surface of the second substrate 2310 can be formed on the second substrate 2310, and a second input / output pad 2305 can be disposed on the upper insulating layer 2301. The second input / output pad 2305 can be connected to at least one of a plurality of circuit elements 2220a, 2220b and 2220c disposed in the peripheral circuit region PERI via a second input / output contact plug 2303.

[0155] According to an exemplary embodiment of the present invention, the second substrate 2310 and the common source line 2320 may not be arranged in the area where the second input / output contact plug 2303 is arranged. Furthermore, the second input / output pad 2305 may not overlap with the word line 2330 in the third direction (Z-axis direction). Reference Figure 20The second input / output contact plug 2303 can be separated from the second substrate 2310 in a direction parallel to the upper surface of the second substrate 2310, and can pass through the interlayer insulating layer 2315 of the cell region to connect to the second input / output pad 2305.

[0156] According to an exemplary embodiment of the present invention, the first input / output pad 2205 and the second input / output pad 2305 can be selectively formed. For example, the memory device 2000 may include only the first input / output pad 2205 disposed on the first substrate 2210 or the second input / output pad 2305 disposed on the second substrate 2310. Alternatively, the memory device 2000 may include both the first input / output pad 2205 and the second input / output pad 2305.

[0157] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern in the uppermost metal layer can be provided as a virtual pattern, or the uppermost metal layer may not exist.

[0158] In the external pad bonding area PA, the memory device 2000 may include a lower metal pattern 2273a in the uppermost metal layer of the peripheral circuit area PERI. This lower metal pattern 2273a corresponds to the upper metal pattern 2372a formed in the uppermost metal layer of the cell area CELL and has the same shape as the upper metal pattern 2372a of the cell area CELL. In the peripheral circuit area PERI, the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern may be formed in the uppermost metal layer of the cell area CELL. This upper metal pattern corresponds to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area PERI and has the same shape as the lower metal pattern of the peripheral circuit area PERI.

[0159] Lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI can be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by Cu-Cu bonding.

[0160] Furthermore, in the bit line bonding area BLBA, an upper metal pattern 2392, corresponding to the lower metal patterns 2251 and 2252 formed in the uppermost metal layer of the peripheral circuit area PERI and having the same shape as the lower metal pattern 2252 of the peripheral circuit area PERI, can be formed in the uppermost metal layer of the cell area CELL. The contacts may not be formed on the upper metal pattern 2392 formed in the uppermost metal layer of the cell area CELL.

[0161] In an exemplary embodiment of the present invention, corresponding to the metal pattern formed in the uppermost metal layer of one of the cell region CELL and the peripheral circuit region PERI, a reinforcing metal pattern having the same shape as the metal pattern can be formed in the uppermost metal layer of the other of the cell region CELL and the peripheral circuit region PERI, and contacts may not be formed on the reinforcing metal pattern.

[0162] As described above, according to an exemplary embodiment of the present invention, the control logic of the memory device selects one of a first mode and a second mode to control a memory region. The memory region may include a first memory block accessible in both the first and second modes, and a second memory block accessible only in the second mode and storing secure data. When access to the second memory block is sensed in the first mode, the control logic may store the number of attempts to access the second memory block in the second memory block. When an attempt is made to initialize the number of access attempts stored in the second memory block, the secure data is deleted along with it, thereby providing a memory device with improved security performance.

[0163] Although the concept of the invention has been described and illustrated with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that modifications and variations may be made therein without departing from the scope of the inventive concept set forth in the appended claims.

Claims

1. A memory device, comprising: The memory region has a first memory block and a second memory block; and The control logic is configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode, only control operations targeting the first memory block are executable, while in the second mode, control operations targeting both the first memory block and the second memory block are executable. The control logic counts the number of accesses to the second memory block in the first mode and stores the number of accesses as scan data in the second memory block. When an attempt to initialize the scan data is detected, the control logic deletes the data stored in the second memory block.

2. The memory device of claim 1, wherein the second memory block stores security data that the control logic reads only in the second mode.

3. The memory device according to claim 2, wherein, When the number of accesses included in the scan data equals a predetermined reference number, the control logic restricts control operations on the second memory block.

4. The memory device according to claim 3, wherein, The control logic restricts control operations on the second memory block by using password or biometric authentication of the user.

5. The memory device of claim 3, wherein the control logic limits control operations on the second memory block by deleting data stored in a page buffer connected to the second memory block and changing the voltage level output by a voltage generator connected to the second memory block.

6. The memory device of claim 1, wherein the control logic and the memory region are included in a single semiconductor chip.

7. The memory device of claim 1, wherein the control logic is included in a first semiconductor chip, and the memory region is included in a second semiconductor chip different from the first semiconductor chip.

8. The memory device according to claim 1, wherein, The number of memory cells included in the first memory block is equal to the number of memory cells included in the second memory block, and The data storage capacity of the first memory block is greater than that of the second memory block.

9. The memory device of claim 1, wherein the control logic stores the scan data in a flag unit, the flag unit being included in the second memory block and programmed in a single-level cell (SLC) scheme.

10. The memory device of claim 9, wherein the flag unit is connected to a word line in the second memory block.

11. The memory device according to claim 1, wherein, The control logic stores the scan data in at least one flag cell within a memory cell included in the second memory block, and increases the threshold voltage of the at least one flag cell as the number of accesses increases.

12. The memory device of claim 1, further comprising: A first page buffer is connected to the first memory block and performs read and program operations on the first memory block. and The second page buffer is connected to the second memory block and performs read and program operations on the second memory block. This includes the fact that the number of latches in each of the first page buffers is different from the number of latches in each of the second page buffers.

13. A memory device, comprising: A memory region containing multiple memory blocks; and Control logic is configured to control the memory region. The control logic wherein, in a first mode, it prevents access to at least one secure block among a plurality of memory blocks, and in a second mode, different from the first mode, it allows access to the at least one secure block. When a read operation is performed on the at least one secure block in the first mode, both the read operation and the programming operation on the at least one secure block are performed. In the programming operations performed on the at least one secure block in the first mode, the control logic records scan data, wherein the scan data includes the number of read operations performed on the at least one secure block in the first mode, and When an attempt to initialize the scan data is detected, the control logic deletes the data stored in the at least one security block.

14. The memory device of claim 13, wherein when an erase command is received, the control logic performs the erase operation on a per-block basis.

15. A memory device, comprising: The first letter line is stacked on the substrate; A first channel layer extends through the first word line in a first direction perpendicular to the substrate and provides a first memory cell accessible in a first mode and a second mode different from the first mode; The second word line is stacked on the substrate and electrically separated from the first word line; The second channel layer extends through the second word line in the first direction and provides a second memory cell accessible only in the second mode; and The control logic is configured to select one of the first mode and the second mode as the operating mode, and to store in the second memory unit data corresponding to the number of times the second memory unit is accessed in the first mode.

16. The memory device of claim 15, further comprising: A word line separation layer separates the first word line and the second word line.

17. The memory device of claim 15, wherein the number of the first word lines is equal to the number of the second word lines, and the number of the first channel layers is equal to the number of the second channel layers; and The data storage capacity of the first memory unit is different from that of the second memory unit.

Images