Patterning method

Abstract

This disclosure relates to a method for providing a patterned substrate to form a first set of trenches and a second set of trenches in the substrate. The method is based on a combination of two photolithography-etching (LE) patterning processes supplemented with spacer-assisted (SA) technology. Accordingly, the method of the present invention may be referred to as a "SALELE patterning process". The method uses a stack comprising three memory layers: an upper memory layer, allowing the initial memory of upper trenches followed by the memory of one or more upper barriers; an intermediate memory layer, allowing the initial memory of intermediate trenches and one or more first intermediate barriers followed by the memory of second intermediate barriers and intermediate lines; and a lower memory layer, allowing the initial memory of first lower trenches and one or more first lower barriers followed by the memory of second lower trenches and one or more second lower barriers.

Description

Technical Field

[0001] The present invention relates to a patterning method. Background Technology

[0002] Photolithography and etching processes (“litho-etch”) are commonly used in semiconductor device fabrication, for example, to form trenches, openings, or other patterns in, for example, hard mask layers, dielectric layers, metal layers, or semiconductor layers. Patterns such as trench patterns can be defined (i.e., exposed and developed) in a resist layer by photolithography and transferred to the underlying layer by etching. The minimum critical size (CD) of patterning based on litho-etch depends on the wavelength of light used to expose the resist. Therefore, extreme ultraviolet lithography (EUVL) enables patterns with a reduced CD compared to current technologies based on, for example, 193i.

[0003] In spacer-assisted multiple patterning techniques such as SADP or SAQP (also known as self-aligned multiple patterning), raster-patterned layers of core axes and spacers can be used to form a sub-lithographic, tightly pitched line pattern in the underlying layer. Multiple patterning can be combined with blocking techniques to enable the formation of discontinuous or broken lines.

[0004] EP 3618103 discloses a patterning method based on a combination of two photolithography-etching processes supplemented with spacer-assisted (SA) technology. This method can therefore be referred to as the "SALELE patterning process." The two LE processes allow for the patterning of two sets of alternating trenches in the target layer. Using two LE processes allows for the formation of relatively tight pitch patterns by combining two loose pitch patterns. Simultaneously, the addition of the spacer-assisted technology makes it possible to ensure at least a minimum spacing between adjacent trenches in the target layer. By using blocking patterns, discontinuous trenches with small tip-to-tip spacing can be formed.

[0005] While existing patterning methods offer a path toward increasingly aggressive target CD, more aggressive target CD implies greater sensitivity to process variability, particularly to edge placement error (EPE). Summary of the Invention

[0006] In view of this, the object of the present invention is to provide a patterning method that enables the formation of groove patterns, including discontinuous grooves, and reduces sensitivity to process variations, particularly improving EPE margin. Further and alternative objectives may be understood from the following.

[0007] According to a first aspect of the present invention, a patterning method is provided, comprising:

[0008] A stack of layers, including lower, middle and upper memory layers, is formed on top of the bottom layer;

[0009] The upper memory layer is patterned using photolithography and etching to form upper trenches in the upper memory layer;

[0010] Sidewall spacers are formed along the sidewalls of the upper groove;

[0011] The first mask barriers are formed, and each first mask barrier forms a trench interruption along the corresponding upper trench;

[0012] The intermediate memory layer and the lower memory layer are patterned to form an intermediate trench in the intermediate memory layer and a first lower trench in the lower memory layer. This patterning includes etching the patterned upper memory layer, sidewall spacers, and a first mask block while simultaneously obscuring the intermediate memory layer.

[0013] At least one subset of the intermediate trenches is interrupted by a corresponding first intermediate barrier, the corresponding first intermediate barrier being formed by a corresponding first intermediate memory layer portion that is masked by a corresponding first mask barrier (during the etching of the intermediate memory layer), and at least one subset of the first lower trenches is interrupted by a corresponding first lower barrier, the corresponding first lower barrier being formed by a corresponding first lower memory layer portion that is masked by a corresponding first intermediate barrier (during the etching of the lower memory layer).

[0014] The method also includes the following steps while the deposited mask material is filling the upper, middle, and first lower trenches:

[0015] The patterned upper memory layer is patterned using photolithography and etching to form an upper barrier from the remaining portion of the upper memory layer, and

[0016] The patterned intermediate memory layer is patterned to form a second intermediate barrier and a center line. This patterning includes etching the patterned intermediate memory layer while simultaneously masking it with spacers and an upper barrier, and while a first intermediate barrier is masked by a deposited mask material. The second intermediate barrier is formed from the portion of the intermediate memory layer masked by the upper barrier during the etching of the patterned intermediate memory layer. The center line is formed from the portion of the intermediate memory layer masked by spacers during the etching of the patterned intermediate memory layer.

[0017] The method further includes (after patterning the patterned upper memory layer and the patterned intermediate memory layer) patterning the patterned lower memory layer to form a second lower trench in the patterned lower memory layer. Patterning the patterned lower memory layer includes:

[0018] An auxiliary trench mask stack is formed above the lower memory layer, and the auxiliary trenches are patterned therein by photolithography and etching; and

[0019] While the patterned lower memory layer is masked by the patterned auxiliary trench mask stack, the second intermediate barrier and the intermediate line, and the first intermediate barrier masks the first lower barrier, the patterned lower memory layer is etched, wherein at least a subset of the second lower trenches is interrupted by the corresponding second lower barrier, the corresponding second lower barrier being formed by the corresponding second lower memory layer portion masked by the corresponding second intermediate barrier during the etching of the patterned lower memory layer.

[0020] The method also includes patterning a first set of grooves below the first lower groove and a second set of grooves below the second lower groove in the underlying layer.

[0021] The method of this invention allows for patterning of a substrate to form a first set of trenches and a second set of trenches within the substrate. The method is based on an advantageous combination of two photolithography-etching (LE) patterning processes supplemented with spacer-assisted (SA) technology. Accordingly, the method of this invention may be referred to as the "SALELE" patterning process and has advantages corresponding to those of the SALELE process described above. Compared to conventional SADP and SAQP techniques, the method of this invention particularly allows for greater flexibility in the shape of the trench patterns. Furthermore, this method enables the formation of trench patterns with a smaller CD (cathode) than that provided by conventional pure photolithography patterning techniques.

[0022] Furthermore, using LE (Leaf Lens) for patterning the upper groove and for patterning the second lower groove allows for the formation of a relatively tight pitch pattern by combining two loose pitch patterns. This can be particularly advantageous when combined with EUVL, which is otherwise a technique prone to random failures if used to directly form aggressively scaled patterns. Loose printing also offers corresponding advantages in the 193i application.

[0023] The method of this invention uses a stack comprising three memory layers: a lower memory layer on top of a bottom layer (e.g., on the bottom layer) in which first and second sets of trenches are to be formed; an intermediate memory layer on top of the lower memory layer (e.g., on the lower memory layer); and an upper memory layer on top of the intermediate memory layer (e.g., on the intermediate memory layer). Each of the lower, intermediate, and upper memory layers is provided for memorizing (corresponding) patterns. As the method proceeds, each memory layer is used multiple times to facilitate trench formation in the bottom layer. The upper memory layer allows the upper trenches to be memorized first, followed by the upper barriers. Since the upper barriers are formed by patterning the already patterned upper memory layer, the upper barriers can be self-aligned relative to the first set of lower trenches and thus reliably aligned with the second set of lower trenches. The intermediate memory layer allows the intermediate trenches and one or more first intermediate barriers to be memorized first, followed by the second intermediate barriers and the center line. The lower memory layer allows for the initial memory of a first lower trench and one or more first lower barriers, followed by the memory of a second lower trench and one or more second lower barriers.

[0024] Compared to what can be achieved by directly “printing” photolithographically defined discontinuous trenches into the memory layer, using barriers (e.g., a first mask barrier and an upper barrier) to define trench breaks makes it possible to form discontinuous trenches with smaller tip-to-tip spacing.

[0025] Furthermore, the method of the present invention has the aforementioned advantages, combined with an improved margin for EPE that allows for reduced sensitivity to process variability, particularly during the patterning of the second phase trench.

[0026] The improved margin is facilitated at least in part by the intermediate memory layer existing between the lower and upper memory layers. The intermediate memory layer allows trench interruptions along the upper trench (as defined by the first mask barrier) to be memorized as a first intermediate barrier and a first lower barrier below the first intermediate barrier. These "duotones," containing the barriers (i.e., the first lower barrier below the first intermediate barrier representing two different shades), provide masking of the first lower barrier via the first intermediate barrier during the patterning of the second lower trench (within the already patterned lower memory layer). Therefore, even if auxiliary trenches in the auxiliary trench mask stack extend / overlap above the first intermediate barrier and the first lower barrier located in the first intermediate trench and the first lower trench respectively, the first intermediate barrier can resist etching of the first lower barrier. Thus, trench interruptions of the first lower trench (memorized as the first lower barrier) can also be preserved after the second lower trench is formed.

[0027] Depositing a mask material that fills the upper, middle, and first lower trenches before patterning the patterned intermediate memory layer allows the first intermediate barrier to be masked and thus retained until the subsequent patterning of the patterned lower memory layer. In other words, the mask material resists etching of the first intermediate barrier during the patterning of the patterned intermediate memory layer.

[0028] Furthermore, according to the method of the invention, the sidewall spacers are present at least during the patterning of the intermediate memory layer, the lower memory layer, the patterned upper memory layer, and the patterned intermediate memory layer, and advantageously also during the patterning of the patterned lower memory layer.

[0029] The presence of the sidewall spacer line makes it possible to ensure at least a minimum spacing between the first and second lower trenches. Therefore, if an auxiliary trench in the auxiliary trench mask stack (by design or attributable to the EPE) extends above or overlaps the first lower trench, the spacer line portion extending along the exposed first lower trench can mask (and thus resist etching) the lower memory layer portion below this spacer line portion. Thus, the second lower trench can be etched in the lower memory layer through the overlapping auxiliary trenches, while the spacer line portion ensures that the first and second lower trenches are separated by the masked lower memory layer portion, for example, having a width determined by the linewidth of the spacer line.

[0030] The presence of spacers during the patterning of the patterned intermediate memory layer allows for the formation of intermediate lines. Therefore, as can be understood, if the spacers are removed during the patterning of the patterned lower memory layer, the intermediate lines can provide a function corresponding to the spacers.

[0031] As can be understood from the above discussion of the first aspect, the lower, middle, and upper memory layers represent different layers of the stack, each formed of a corresponding material. At least, the middle memory layer is formed of a material (hereinafter referred to as the "middle layer material") that is different from the material of the lower memory layer ("lower layer material") and different from the material of the upper memory layer ("upper layer material"). Furthermore, the lower layer material and the upper layer material can be different materials. For example, the lower layer material can be a dielectric material, such as an oxide, nitride, or carbide. The middle layer material can be a metal-containing material, such as a metal nitride, metal carbide, or metal oxide. The upper layer material can be amorphous silicon (aSi).

[0032] The bottom layer below the stack represents a layer different from the memory layers of that stack. The bottom layer can be formed of a material that is at least different from the material of the lower layers (“bottom layer material”). As will be further described below, the bottom layer can also be a memory layer (i.e., a “target memory layer”). The bottom / target layer material can, for example, be formed of any material discussed in conjunction with the intermediate layer materials.

[0033] The sidewall spacers can advantageously be formed of a material that is different from each of the upper, middle, and lower layer materials and also different from the bottom layer material (“spacer material”). The sidewall spacers (“spacers”) can be formed of typical spacer materials, such as oxides or nitrides deposited by atomic layer deposition (ALD) (different from the lower, middle, or upper layer materials).

[0034] The deposited mask material filling the upper, middle, and first lower trenches during the patterning of the patterned upper and middle memory layers can generally be formed of a material different from at least the upper layer material and the middle layer material. The deposited mask material may include organic spin-coating materials such as spin-coated carbon (SOC).

[0035] Different (corresponding material) memory layers allow for etching contrast during various layer patterning steps in the first method. In other words, during the patterning of a first layer of the first material (such as an intermediate memory layer) to form trenches and / or barriers therein, the first layer can be etched at a greater rate than a second layer or component of the second material that is also exposed to the etching process during this patterning. Thus, the first material (of the first layer) can be selectively etched or removed, i.e., removed at a greater rate than the second material (of the second layer or component).

[0036] The first part that masks the second part during etching means that the first part is above the second part (or conversely, the second part is below the first part), so that the first part can act as an etching mask and thus resist the etching of the second part.

[0037] The first component masking the second component means that the second component is at least masked by the first component, and may also be masked by other components between or above the first component. In other words, the first component can (possibly together with other intermediate or upper components) serve as an etching mask for the second component.

[0038] Accordingly, patterning of the intermediate memory layer may include etching the intermediate memory layer while the patterned upper memory layer, sidewall spacers, and first mask barrier act as an etching mask. The intermediate memory layer may be etched at a greater rate than the patterned upper memory layer, sidewall spacers, and first mask barrier.

[0039] Patterning of the lower memory layer may include etching the lower memory layer while the patterned upper memory layer, sidewall spacers, and first mask block (or a first intermediate block if the first mask block has been removed) act as an etch mask. The lower memory layer may be etched at a greater rate than the patterned upper memory layer, sidewall spacers, and first mask block (and at a greater rate than the first intermediate block if the first mask block has been removed).

[0040] Patterning of the patterned intermediate memory layer can include etching the patterned intermediate memory layer while the upper barrier, spacers, and mask material act as an etching mask. The patterned intermediate memory layer can be etched at a higher rate than the upper barrier, spacers, and mask material.

[0041] Patterning of the patterned lower memory layer may include etching the patterned lower memory layer while the patterned auxiliary trench mask stack, the upper barrier (or the second intermediate barrier if the upper barrier has been removed), the spacer lines (or the intermediate lines if the spacer lines have been removed), and the first intermediate barrier act as etch masks. The patterning of the lower memory layer may be etched at a greater rate than the patterned auxiliary trench mask stack (e.g., its mask material), the upper barrier (or the second intermediate barrier if the upper barrier has been removed), the spacer lines (or the intermediate lines if the spacer lines have been removed), and the first intermediate barrier.

[0042] The first and second groups of trenches can be patterned simultaneously in the underlying layer. Alternatively, the first and second groups of trenches can be patterned sequentially. That is, the first group of trenches can be patterned in the underlying layer before the second group of trenches. This approach also allows for a reduction in the number of times layers beneath the underlying layer (such as an insulating layer) are exposed to the etchant.

[0043] Spacers can be formed using sidewall spacer layer formation processes, including conformally deposited spacer layers through etch-back. For example, the spacer layer can be conformally deposited (e.g., by ALD) to cover a patterned upper memory layer, the sidewalls of the upper trench, and the bottom surface. The spacer layer can then undergo anisotropic etching (e.g., vertically biased dry etching), adapted to remove portions of the spacer layer from horizontally oriented surfaces, including the upper surface of the patterned upper memory layer and the lower surface of the upper trench, such that portions of the spacer layer remain on the upper trench sidewalls to form spacers. Sidewall spacer formation processes allow for reliable formation of spacers with uniform linewidth / thickness, thereby helping to reduce process variability.

[0044] The first mask barrier can be removed after the intermediate and lower memory layers are patterned and before the first lower trench, (first) intermediate trench, and (first) upper trench are filled with mask material. This provides increased etch margin because the first intermediate barrier can be masked during the patterning of the lower memory layer. Removing the first mask barrier before filling the trenches with mask material allows for reduced topographic variations for subsequent patterning steps. However, it is also possible to remove the first mask barrier before patterning the lower memory layer.

[0045] The method may further include: after forming the first lower trench, forming an auxiliary barrier mask stack, the auxiliary barrier mask stack including mask material filling the upper, middle and first lower trenches and a resist layer.

[0046] Patterning of the patterned upper memory layer may include first patterning an auxiliary barrier mask stack using photolithography and etching to form an auxiliary barrier, and then patterning the patterned upper memory layer using the patterned auxiliary barrier mask stack to form the upper barrier.

[0047] During etching, the patterned upper memory layer is correspondingly masked by auxiliary barriers. The upper barriers can thus be formed from portions of the upper memory layer masked by the auxiliary barriers. The mask material of the auxiliary barrier mask stack can fill the upper, middle, and lower trenches, thereby covering the first lower barrier and the first middle barrier. The mask material can be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material can be different from the upper layer material, spacer material, and middle layer material. The mask material can be deposited to form a planarized mask material layer that fills the trenches and covers the patterned upper memory layer. The mask material can be an organic spin-coating material such as SOC.

[0048] The auxiliary trench mask stack may include a mask material forming a planarization layer covering an upper barrier, spacer lines, and a patterned lower memory layer. The auxiliary trench mask stack may further include a resist layer above the mask material. The mask material may be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material may differ at least from the spacer material and intermediate layer material, and advantageously also from the upper layer material. The mask material may be an organic spin-coating material such as SOC.

[0049] The auxiliary trenches may be formed to expose the upper surface portion of the lower memory layer between the first lower trenches. Patterning of the patterned lower memory layer may include etching a second lower trench in the lower memory layer through the auxiliary trenches.

[0050] At least one auxiliary trench of the auxiliary trench mask stack can extend above the first lower trench and above the first intermediate barrier located above the first lower barrier in the first lower trench. Therefore, the at least one auxiliary trench can expose the first intermediate barrier. Due to the presence of the first intermediate barrier, the patterned lower memory layer can still be etched to form the second lower trench without removing the trench interruption of the previous memory of the first lower trench (i.e., the first lower barrier therein). Furthermore, the presence of the spacer layer makes it possible to ensure that the second lower trench is separated from the first lower trench.

[0051] The trenches of at least one subset of the second lower trenches may be arranged alternately with the trenches of at least one subset of the first set of lower trenches. That is, in these subsets of trenches, the second lower trenches may be formed between a pair of first lower trenches, and vice versa.

[0052] Each trench of the at least one subset of the second lower trenches can be (only) spaced apart from the adjacent trenches of the at least one subset of the first lower trenches by a corresponding lower line formed by a corresponding third lower memory layer portion obscured by a corresponding intermediate line. Therefore, the minimum spacing between the first and second lower trenches can be determined by the linewidth of the spacer line.

[0053] The patterning method of the first aspect can be advantageously combined with methods for forming interconnect structures. Therefore, according to the second aspect, a method for forming an interconnect structure is provided, comprising:

[0054] A target memory layer is formed on top of the insulating layer;

[0055] In the target memory layer, a first group and a second group of trenches are formed according to the method of the first aspect, wherein the bottom layer is the target memory layer;

[0056] After forming the first and second sets of trenches in the target memory layer, while the target memory layer masks the insulating layer, the first trench is etched in the insulating layer below the first set of trenches in the target memory layer, and the second trench is etched in the insulating layer below the second set of trenches in the target memory layer.

[0057] Conductive material is deposited in trenches within the insulating layer.

[0058] The second aspect of the method may also include:

[0059] After the patterning of the middle and lower memory layers and before the patterning of the patterned upper memory layer:

[0060] Forming a through-hole etch stack includes a mask material filling the upper, middle, and first lower trenches and further includes a resist layer.

[0061] An opening is formed in the through-hole etch stack, which exposes the upper surface of the remaining portion of the patterned upper memory layer.

[0062] The exposed upper surface of the patterned upper memory layer is etched back to form openings in the patterned upper memory layer, and

[0063] The patterned middle memory layer, the patterned lower memory layer, and the target memory layer are sequentially etched back through the opening in the patterned upper memory layer to form an extended opening that runs through them;

[0064] The method also includes etching the insulating layer through the extended opening.

[0065] Thus, a (second) via opening or via can be formed in the insulating layer. The via opening can be self-aligned with the second set of trenches in the target memory layer due to this patterning method, and therefore also with the second trenches in the insulating layer.

[0066] An initial via opening can be formed by first etching through the extended opening in the insulating layer, which can then be deepened during the aforementioned etching of the (second) trench in the insulating layer to form the final via opening.

[0067] Conductive material can be deposited to fill the (final) via openings and trenches in the insulating layer.

[0068] The mask material for a through-hole etching stack can be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material can differ from the upper layer material, spacer material, and intermediate layer material. The mask material can also differ from one or more of the materials of the lower layer material, target material layer, and insulating layer. The mask material can be deposited to form a planarized mask material layer that fills trenches and covers a patterned upper memory layer. The mask material can be an organic spin-coating material such as a SOC.

[0069] The exposed upper surface of the patterned upper memory layer can be etched back using an etching process adapted to etch the patterned upper memory layer at a rate greater than that of the mask material filling the upper trench and / or greater than that of the spacer material. This allows for improved etch margin during subsequent sequential etchback of the memory layer.

[0070] The exposed upper surface of the upper memory layer can be located between a pair of upper trenches, and the width of the openings in the via etch stack can exceed the spacing between the pair of upper trenches. This allows for loose printing of the openings within the via etch stack.

[0071] The method may further include:

[0072] After the patterning of the middle and lower memory layers and before the patterning of the patterned upper memory layer:

[0073] Forming a through-hole etch stack includes a mask material filling the lower, middle, and upper trenches and further includes a resist layer.

[0074] An opening is formed in the through-hole etch stack, which exposes the bottom surface of the selected first lower trench and the spacer layer portions on the opposite sides of the selected first lower trench.

[0075] The exposed bottom surface is etched back to form an opening in the target memory layer;

[0076] The method also includes etching the insulating layer through the opening in the target memory layer.

[0077] Thus, a (first) via opening or via can be formed in the insulating layer. The via opening can be self-aligned with the first set of trenches in the target memory layer due to this patterning method, and therefore also with the first trenches in the insulating layer.

[0078] An initial via opening can be formed by etching the insulating layer through the opening, which can then be deepened during the etching of the (first) trench in the insulating layer to form the final via opening.

[0079] After an opening is formed in the target memory layer, the insulating layer can be etched immediately through that opening. However, if a second via opening is also formed as described above, it is also possible to perform etching of the insulating layer simultaneously through the opening in the target memory layer (to form the first via opening) and through the extended opening (to form the second via opening).

[0080] Conductive material can be deposited to fill the (final) via openings and trenches in the insulating layer.

[0081] The mask material for a through-hole etching stack can be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material can differ from the top layer material, spacer material, and intermediate layer material. The mask material can also differ from one or more of the bottom layer material, target memory layer, and insulating layer. The mask material can be deposited to form a planarized mask material layer that fills the trench and covers the patterned top memory layer. The mask material can be an organic spin-coating material such as a SOC.

[0082] Forming openings in a through-hole etch stack can include etching the mask material using an etching process adapted to etch the mask material at a rate greater than that of the spacer layers. This allows the openings to self-align with the first set of lower trenches. Attached Figure Description

[0083] The above and other objects, features, and advantages of the present invention will be better understood from the following illustrative and non-limiting detailed description with reference to the accompanying drawings. In the drawings, similar reference numerals will be used for similar elements unless otherwise stated.

[0084] Figure 1-2 7. The process flow of the patterning method is explained. Detailed Implementation

[0085] Now refer to Figure 1-2 7. A method for patterning a bottom layer is described. This method will be described in conjunction with patterning a target memory layer 12, which can then be used to pattern trenches in an insulating layer 10. The trenches in the insulating layer 10 may be filled with a conductive material, such as a metal, to form conductive lines at the interconnect level, for example, in a back-to-upper-process (BEOL) step, interconnecting an interconnect structure. However, it will be noted that this method has more general applicability to patterning trenches in any layer. For example, the layer 12 to be patterned may be a semiconductor layer or a metal layer.

[0086] refer to Figure 1 The diagram shows a portion of a structure that will undergo the processing steps of this patterning method, in perspective. This structure may extend laterally or horizontally beyond the shown portion. Unless otherwise specified, the extension of this portion through the shown plane of the structure is common throughout all the figures. Note that the relative dimensions of the elements shown, especially the relative thicknesses of the layers, are merely schematic and may differ from the physical structure for purposes of clarity. Figure 1 In this context, directions X and Y indicate the first and second horizontal directions, respectively, parallel to the main extension planes and main surfaces of each layer. Direction Z indicates the vertical direction, or equivalent to the bottom-up direction or the layer stacking direction, thus perpendicular to the main extension planes and main surfaces of each layer. As can be understood, terms such as "above," "above," "below," "upper part," "bottom layer," and "below" should be understood as relative positions viewed along the vertical direction. Furthermore, the "width" of a trench or the "line width" of a component should be understood as referring to the dimension along the first horizontal direction X. For example, the "longitudinal" or "length" dimension of a trench should be understood as referring to the dimension along the second horizontal direction Y.

[0087] Figure 1A stack 14 is depicted comprising a lower memory layer 16, an intermediate memory layer 18, and an upper memory layer 20 in a bottom-up direction. As shown, the intermediate memory layer 18 may be formed on the lower memory layer 16. The upper memory layer 20 may be formed on the intermediate memory layer 18. The stack 14 is formed on top of, or on, the bottom target memory layer 12, as shown. However, it is contemplated that an interface layer (such as an adhesive layer) may be provided, for example, between memory layers 12 and 16, and / or 16 and 18 and / or 18 and 20. If an interface layer exists between two memory layers (such as 16 and 18), the interface layer may be patterned in the same steps as the higher layer (such as layer 18) or in the same steps as the lower layer.

[0088] As can be understood from the following text, memory layers 16, 18, and 20 can be patterned to "memorize" or "store" one or more portions of the final "target" pattern to be transferred to the target memory layer 12. The "target pattern" can then be transferred to the insulating layer 10. Therefore, "memory layers" 12, 16, 18, and 20 can instead be referred to as "patterning layers" 12, 16, 18, and 20.

[0089] The target memory layer 12 can be such as a metal nitride, metal carbide, or metal oxide (e.g., TiN, W). x C y Al X O y Or Al x N y The lower memory layer 14 can be a dielectric material layer, such as oxides, nitrides, or carbides, for example, SiO2, SiCO, SiC, SiN, or SiCN. The middle memory layer 16 can be formed from any of the materials mentioned for bonding the target memory layer 12. The upper memory layer 20 can be an a-Si layer. A non-limiting example of the combination of materials for memory layers 12, 16, 18, and 20 is: a target memory layer 12 of TiN, a lower memory layer 16 of SiN, a middle memory layer 18 of TiN, and an upper memory layer 20 of a-Si. Memory layers 12, 14, 16, and 18 can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0090] like Figure 1 As further shown, the stack 14 can be formed on the insulating layer 10. The insulating layer 10 can be an oxide material, such as SiO2, or another conventional low-k dielectric. One or more interface layers 11 (e.g., interface layers and / or oxide capping layers) may optionally be present between the target memory layer 12 and the insulating layer 10.

[0091] An insulating layer 10 may be formed on a substrate 1, such as a semiconductor substrate. An active device layer comprising a semiconductor device such as a transistor may be fabricated on the main surface of the substrate 1. The active device layer may also be referred to as a front-end process portion (FEOL portion). The insulating layer 10 may be formed on (not shown) conductive structures such as conductive lines at lower interconnect levels, or on contact structures for devices such as source / drain or gate contacts of a semiconductor device, as known in the art.

[0092] Figure 1-2 The process steps for patterning the upper memory layer 20 to form a set of upper trenches 30 within the upper memory layer 20 are explained. The upper trenches 30 are formed using photolithography and etching. For example... Figure 1 As shown, a (first) auxiliary trench mask stack 22, comprising a mask material 24 and a resist layer 28, is formed over the upper memory layer 20. The mask material 24 may be, for example, an organic spin-coating material such as SOC. The auxiliary trench mask stack 22 is patterned to form the auxiliary trenches 28. The auxiliary trenches 28 may first be formed in the resist layer 28 by photolithography, and then transferred to the mask material 24 by etching. Subsequently, while the patterned auxiliary trench mask stack 22 masks the upper memory layer 20, the upper trench 30 can be formed by etching through the auxiliary trenches 28 to the upper memory layer 20. Although not shown, the auxiliary trench mask stack 22 may include additional layers under the resist layer 28, such as one or more anti-reflective coatings, such as SiOC layers and / or spin-coated glass layers. An alternative to the mask stack is to form the resist layer directly on the upper memory layer 30. The upper trench 30 can be etched using a suitable etching process, such as dry etching, such as reactive ion etching (RIE). For example, the etching chemicals containing bromine (e.g., HBr), chlorine (e.g., Cl2), or fluorine (e.g., SF6, CF4) can be tuned to achieve selective “a-Si etching”, that is, selectively etching a-Si relative to the auxiliary trench mask stack 22, for example containing organic spin-coating materials such as SOC.

[0093] Figure 2 The patterned upper memory layer 20 is shown, in which upper trenches 30 are formed. The auxiliary trench mask stack 22 can therefore be removed from the patterned upper memory layer 20. As shown, the upper trenches 30 can expose the upper surface portion of the intermediate memory layer 18. Each upper trench 30 is formed above the region of the target memory layer 12 (and insulating layer 10) in which the first target trench 96 will be formed (see, for example...). Figure 25 As shown in the figure, the upper groove 30 can be formed to have various widths (along the first horizontal direction X) and various longitudinal dimensions (along the second horizontal direction Y). The upper groove 30 can extend parallel to the second horizontal direction Y.

[0094] exist Figure 3 In this process, sidewall spacer lines 32 have been formed along the sidewalls of the upper trench 30. The spacer lines 32 can be formed from an ALD deposition material such as an oxide (e.g., SiO2) or an AlO2 material during the sidewall spacer deposition process. x or TiO x It is formed by metal oxide layers such as SiCO, SiN, AlN, AlON, and SiCN, or by carbides or nitrides such as SiCO, SiN, AlN, AlON, and SiCN. Figure 3 As shown, the spacer line 32 is conformal to the sidewall of each upper groove 30. In other words, the spacer line 32 can cover and extend along the sidewall of the upper groove 30. (As shown in...) Figure 3 As further shown, spacer lines 32 may also be formed on the end walls of the upper groove 30. Such end wall spacer portions can thus connect the side wall spacer lines 32 formed on the opposing side walls of each corresponding upper groove 30.

[0095] Figure 4-5 The steps for forming the first mask barrier 38 along the upper trench 30 have been explained. As shown in the figure, the first mask barrier 38 can be patterned by photolithography on the mask barrier layer 34. Figure 4 The photolithographically patterned resist barrier 36 is shown, and the resist barrier 36 is used to form the mask barrier layer 34 by etching. The mask barrier layer 36 can be formed from a SOC or some other organic spin-coating material.

[0096] Figure 5 A first mask barrier 38 is shown. Each mask barrier 38 may extend across the upper groove 30 (which has been provided with sidewall spacers 32). After the first mask barrier 38 is formed, the resist barrier 36 can be removed. It should be noted that... Figure 5 The number of first mask blocks 38 shown is merely an example, and fewer or more first mask blocks 38 may be formed, such as one or more first mask blocks 38.

[0097] The first mask barrier 38 can also be formed using a color inversion method. That is, an opening can be formed in a temporary planarization layer (e.g., a SOC layer) deposited above the upper memory layer 20 by photolithography and etching. Mask barrier materials (e.g., spin-coated glass, metal oxides (e.g., TiO2) can be used. x or ZrO x The opening is filled with a temporary layer (or another oxide, dielectric, or metal-based material compatible with the composition of the stack) to form a first mask barrier 38. This temporary layer can then be removed, leaving the mask barrier 38 along the upper trench 30.

[0098] exist Figure 6In this configuration, the intermediate memory layer 18 has been patterned to form an intermediate trench 40 therein. Patterning may include etching the intermediate memory layer 18 while the patterned upper memory layer 20, spacer lines 32, and first mask barrier 38 conceal the intermediate memory layer 18. In other words, patterning may include vertically etching back the upper surface portion of the intermediate memory layer 18 below or exposed in the upper trench 30 (i.e., the upper surface portion not concealed by the first mask barrier 38 or spacer lines 32). As shown, the intermediate trench 40 may expose the upper surface portion of the lower memory layer 16.

[0099] After the intermediate memory layer 18 is patterned, the lower memory layer 16 is patterned to form a first lower trench therein. Patterning may include etching the lower memory layer 18 while the patterned upper memory layer 20, spacer 32, first mask barrier 38, and patterned intermediate memory layer 18 mask the lower memory layer 16. In other words, patterning may include vertically etching back the upper surface portion of the lower memory layer 16 exposed below or within the intermediate trench 40. As shown, the first lower trench 42 may expose the upper surface portion of the target memory layer 12.

[0100] Figure 7 The corresponding view is shown after the removal of the first mask block 38. For example, SOC material can be removed in "SOC etching" (such as RIE using oxygen-containing etching chemicals diluted with Ar or He or N2 / H2-based etching chemicals).

[0101] If possible Figure 6 and 7 As can be seen, beneath each first mask barrier 38, a first intermediate barrier 19 has been formed by a corresponding first intermediate memory layer portion 18a, which is masked by the first mask barrier 38 during the etching of the intermediate memory layer 18. Therefore, the corresponding first intermediate memory layer portion 18a can remain beneath each first mask barrier 38. Consequently, at least a subset of the intermediate trench 40 is interrupted by the corresponding first intermediate barrier 19.

[0102] Furthermore, below each first mask barrier 38 and each first intermediate barrier 19, a first lower barrier 21 has been formed by a corresponding first lower memory layer portion 16a, which is masked by the first mask barrier 38 and the first intermediate barrier 19 during etching. Therefore, the corresponding first lower memory layer portion 16a can be retained below each first intermediate barrier 19. Thus, at least one subset of the first lower trench 42 is interrupted by the corresponding first lower barrier 21.

[0103] exist Figure 7In the small diagram, blocks 19 and 21 are shown without shading. However, this is only for illustrative purposes, and as mentioned above, blocks 19 and 21 are formed by the remaining portions 18a and 16a of layers 18 and 16, respectively.

[0104] Patterning of the intermediate memory layer 18 and the lower memory layer 16 may include etching using an etching process (such as a dry etching process), thereby allowing the respective memory layers 18, 16 to be etched at a higher rate than the upper memory layer 20, the spacer 32, and the first mask barrier 38. For example, the SiN layer and TiN layer may be patterned using a fluorine-based etching chemical RIE in ratio of SOC, a-Si, and oxides (such as silicon or metal oxides (e.g., SiO2 or TiO2)). x Each of them is etched at a greater rate.

[0105] After the intermediate memory layer 18 and the lower memory layer 16 are patterned, the first mask barrier 38 and the upper trench 30 providing the spacer are thus "memorized" in both the patterned intermediate memory layer 18 and the patterned lower memory layer 16. Although in Figure 6 In this process, the first mask block 38 is also retained during the patterning of the lower memory layer 16. It is possible to remove the first mask block 38 directly after the intermediate memory layer 18 is patterned.

[0106] The (first) via formation process for patterning (first) via openings aligned with the first set of target trenches 96 in the target memory layer 12 will now be described with reference to Figures 8-11 and 12-15, respectively, and the (second) via formation process for patterning (second) via openings aligned with the second set of target trenches 98 in the target memory layer 12. If the formation of the first and / or second via openings is not required, the relevant steps can be omitted. The method can then proceed to... Figure 16 .

[0107] Figure 8b The structure along Figure 8a The cross-section of line A-A' shown is illustrated. A (first) via-hole etch stack 44 has been formed on this structure. The via-hole etch stack 44 may include a mask material 46 filling the lower, middle, and upper trenches 30, 40, 42. The mask material 46 may form a planarization layer covering the patterned upper memory layer 20. The mask material 46 may be a SOC or other organic spin-coated layer. The via-hole etch stack 44 may also include a resist layer 48 formed on the mask material 46. Although not shown, the via-hole etch stack 44 may include additional mask material, such as one or more anti-reflective coatings (such as SiOC layers) and / or spin-coated glass layers, between the SOC layer and the resist layer 48.

[0108] An opening 50 has been formed in the via etch stack 44 by photolithography and etching. This opening is formed at a location above the "selected" first lower trench 42, below which the via opening is required. The opening 50 may extend through the via etch stack 44 to expose the bottom surface 12a of the selected first lower trench 42, which is formed, for example, by the upper surface portion of the target memory layer 12.

[0109] Etching the mask material 46 using an etching process adapted to etch it at a greater rate than that of the spacer 32 allows the opening 50 to self-align with respect to the spacer 32. The opening 50 can also self-align with respect to the selected first lower trench 42 by extension. Thus, a loose CD opening 50 can be defined in the resist layer 48 by photolithography and transferred into the mask material 46. During the etching of the mask material 46, the opening 50 can thus expose portions 32a of the spacer layer on opposite sides of the selected first lower trench 36. For example, as described above, organic spin-coating materials (such as SOC) can be etched at a greater rate than oxide spacers etched using SOC. After the opening 50 is formed, the resist layer 48 can be removed. Figure 8a , 8b An opening 50 is shown; however, it will be clear that any number of openings 50 can be formed depending on the desired number of through-hole openings.

[0110] exist Figure 9 In this process, the exposed bottom surface 12a has been etched back to form an opening 52 in the target memory layer 12. For example... Figure 10 As further shown, the opening 52 can also be transferred to the insulating layer 10 and any interface layer 11 (if present) by etching layers 10 / 11 through the opening 52 in the target memory layer 12. The depth of the opening 52 in layers 10 / 11 may be only the initial depth at this stage and deepened in later stages, such as during the etching of trenches in the insulating layer 10. Figure 11 The structure after removing the through-hole etch stack 44 is shown.

[0111] Figure 12b The structure along Figure 12a The cross-section of line B-B' is shown. A (second) via-hole etch stack 56 has been formed on this structure. The via-hole etch stack 56 may include a mask material 58 filling the upper, middle, and first lower trenches 30, 40, 42. The mask material 58 may form a planarization layer covering the patterned upper memory layer 20. The mask material 58 may be a SOC or other organic spin-coating material. The via-hole etch stack 56 may further include a resist layer 60. Similar to the discussion of via-hole etch stack 44, additional mask material (e.g., an anti-reflective coating) may be present in via-hole etch stack 44.

[0112] An opening 62 has been formed in the via etch stack 56 by photolithography and etching. Reference will now be made to the opening 62 through which the cross-section extends. However, the following description applies accordingly to any other opening 62. The opening 62 is formed on the remaining portion of the patterned memory layer 12 (where the second lower trench is to be formed) at the location below which the via is required. The remaining portion of the patterned memory layer 12 may be located between a pair of upper trenches 30, as shown. The opening 62 may extend through the via etch stack 56 to expose the upper surface 20a of the remaining portion of the patterned memory layer 20. To maintain mask budget, etching of the mask material 58 can be stopped when the upper surface 20a is exposed.

[0113] exist Figure 13 In the process, the exposed upper surface 20a of the remaining portion of the patterned upper memory layer 20 has been etched back to form an opening 64 in the patterned upper memory layer 20. Therefore, the opening 64 can expose the upper surface portion 18c of the intermediate memory layer 18. The patterned upper memory layer 20 is etched using an etching process adapted to etch at a greater rate than the mask material 58 and a greater rate than the spacer 32 (i.e., the spacer 32 of the spacer material), allowing the opening 64 to self-align relative to the spacer 24. Therefore, the loose CD opening 62 can be defined in the resist layer 60 by photolithography and transferred to the mask material 58. By extending, and as... Figure 13 As shown, the width of the opening 62 in the via etch stack 56 can exceed the spacing between a pair of upper trenches 30 on either side of the remaining portion of the patterned upper memory layer 20.

[0114] exist Figure 14 In this process, the patterned intermediate memory layer 18, the patterned lower memory layer 16, and the target memory layer 12 have been sequentially etched back through the opening 64 in the patterned upper memory layer 20. This creates an extended opening that extends through the memory layers 18, 16, and 12. As described above, if the opening 62 in the via etch stack 56 forms a loose CD opening, then the etchback of the upper surface portion of the mask material 58 and a portion of the spacer layer 32 can also occur during the etching of the opening 64. It will be understood, however, that even if the etching of the opening 64 causes the spacer layer 32 to etch back, the presence of the intermediate memory layer 18 provides an improved etch budget for subsequent patterning steps.

[0115] The bottom surface of the extended opening may be formed from a portion of the upper surface of the insulating layer 10 or the interface layer 11 (if present). Therefore, the extended opening has not yet been transferred to the lower layer to form the through-hole opening 67 (see...). Figure 26However, this can occur during subsequent patterning steps, such as during the patterning of the patterned intermediate memory layer 18, the patterning of the second lower trench 88, and / or the etching of the trenches in the insulating layer 10, as described below. However, at this stage, at least an initial via opening 67 can also be etched in the insulating layer 10 (and / or any interface layer 11) to be deepened in later stages, such as during the etching of the trenches in the insulating layer 10. The initial via opening 67 can be etched in layers 10 / 11 to... Figure 10 The initial through-hole opening 52 shown has the same horizontal / depth. Figure 15 The structure after removing the through-hole etch stack 56 is shown.

[0116] Figure 16-18 The patterning of the (already) patterned upper memory layer 20 to form the upper barrier 74 has been explained. These process steps can be performed after the above-mentioned through-hole opening patterning.

[0117] The upper barrier 74 is formed using photolithography and etching. For example... Figure 16 As shown, an auxiliary barrier mask stack 66 is formed on the patterned upper memory layer 20, comprising a mask material 68 and a resist layer 70 forming a resist barrier. The mask material 68 may fill the upper, middle, and first lower trenches 30, 40, 42. The mask material 68 may form a planarization layer covering the patterned upper memory layer 20. The mask material 68 may be a SOC or other organic spin-coated layer. Similar to the discussion of via etch stacks 44, 56, additional mask material (e.g., an anti-reflective coating) may be present in the auxiliary barrier mask stack 66.

[0118] By photolithographically patterning the resist block 70 in the resist layer and subsequently etching the mask material 68 while the resist block 70 masks the mask material 68, the auxiliary barrier mask stack 66 can be patterned to form a second mask block 72, such as... Figure 17 As shown. During the patterning of the auxiliary barrier mask stack 66, the mask material 68 can be etched back until the upper surface of the patterned upper memory layer 20 is exposed. Accordingly, the mask material 68 can be retained in the upper, middle and first lower trenches 30, 40, 42.

[0119] exist Figure 18In this process, while the second mask barrier 72 masks the patterned upper memory layer 20, the patterned upper memory layer 20 is etched. Therefore, the upper barrier 74 can be formed from the remaining portions 20b of the patterned upper memory layer 20. The patterned upper memory layer 20 is etched using an etching process adapted to etch the upper memory layer 20 at a greater rate than the mask material 68, and the mask material 68 can also fill the trenches 30, 40, 42 after the upper barrier 74 is formed. Correspondingly, the second mask barrier 72 can remain on the upper barrier 74. For example, the patterning of the patterned upper memory layer 20 can include using "a-Si etching," as described above.

[0120] exist Figure 19 In the process, the (already) patterned intermediate memory layer 18 has been patterned to form a second intermediate barrier 76 and an intermediate line 77. Patterning may include etching while the patterned intermediate memory layer 18 is being masked by the spacer line 32 and the upper barrier 74.

[0121] The second intermediate barrier 76 may be formed by the intermediate memory layer portion 18b masked by the upper barrier 74. The intermediate line 77 may be formed by the intermediate memory layer portion 18c masked by the spacer line 32. During etching, the mask material 68 may mask the first intermediate barrier 19, such that the first intermediate barrier 19 and the lower first barrier 21 below it are retained. The intermediate memory layer 18 may be etched, for example, using a fluorine-based etchant (RIE).

[0122] After the patterned intermediate memory layer 18 is patterned, the upper barrier 74 and the spacer line 32 are respectively "memorized" in the patterned intermediate memory layer 18 as the second intermediate barrier 76 and the intermediate line 77.

[0123] After patterning the patterned intermediate memory layer 18, the mask material 68 (filling the trenches 30, 40, 42 and forming the second mask barrier 72) can be applied as follows: Figure 20 The areas shown are removed (e.g., using SOC etching) to expose trenches 30, 40, 42 and the upper barrier 74.

[0124] Figure 21-24 The patterning of the (already) patterned upper memory layer 16 is explained to form the second lower trench 88 therein.

[0125] The second lower trench 88 is formed by photolithography and etching. For example... Figure 21As shown, a (second) auxiliary trench mask stack 80 is formed on a patterned lower memory layer 16, comprising a mask material 82 and a resist layer 84 above the mask material 82. The mask material 82 may fill the first lower trench 42. The mask material 82 may also cover the upper barrier 74, which may still exist on the second intermediate barrier 76. The mask material 82 may form a planarization layer. The mask material 82 may be a SOC or other organic spin-coating material. Similar to the discussion of the auxiliary trench mask stack 22, additional mask materials (e.g., an anti-reflective coating 81) may be present in the auxiliary barrier mask stack 80.

[0126] The auxiliary trench mask stack 80 can be patterned to form auxiliary trenches by photolithographically patterning auxiliary trenches 86 in the resist layer 84, such as... Figure 21 As shown, and subsequently transferred to the mask material 82 by etching through the auxiliary trench 86 in the resist layer 84, as... Figure 22 As shown. During the patterning of the auxiliary trench mask stack 80, the mask material 82 may be etched back at least until the upper surface 16b of the patterned lower memory layer 16 is exposed, or further until the upper surface of the target memory layer 12 is exposed. The auxiliary trench 86 may be exposed and extend across the upper barrier 74 and the lower second intermediate barrier 76.

[0127] exist Figure 23 In this process, while the patterned lower memory layer 16 is masked by the patterned auxiliary trench mask stack 80, the second intermediate barrier 76, and the intermediate line 77, the patterned lower memory layer 16 is etched to form the second lower trench 88. In other words, patterning may include etching back the upper surface portion of the patterned lower memory layer 16 exposed in the auxiliary trench 86 (i.e., which is not masked by the second intermediate barrier 76 and the intermediate line 77).

[0128] At each location in the patterned lower memory layer 16 below the upper barrier 74 and the second intermediate barrier 76, a corresponding second lower barrier 90 has been formed by the corresponding second lower memory layer portion 16c that was masked during etching. Therefore, at least one subset of the second lower trench 88 is interrupted by the corresponding second lower barrier 90.

[0129] Patterning of the patterned lower memory layer 16 may include selective etching of the patterned lower memory layer 16 (i.e., using an etching process adapted to etch the patterned lower memory layer 16 at a greater rate than that of the patterned intermediate memory layer 18). As will be appreciated, an etching process that etches the patterned lower memory layer 16 at a rate not only greater than that of the intermediate memory layer 18 but also greater than that of the upper barrier 74 and / or spacer 32 can further improve the etch mask budget. However, if the intermediate memory layer 18 alone provides sufficient etch mask budget, it is possible to remove the upper barrier 74 and / or spacer 32 before patterning the second lower trench 88.

[0130] For example, SiN can be selectively etched relative to TiN (as well as SOC, SiO2, and a-Si) using fluorine-based chemicals (e.g., CHF3, CH3F, C4F8, CF4, CH2F2), optionally using continuous wave plasma, plasma pulse, or cyclic processes (e.g., quasi-atomic layer etching). However, other etching processes that allow for sufficiently selective etching of the underlying layer material relative to (at least) the intermediate layer material can also be used.

[0131] Figure 21 and 22 Reference numerals 86a-c and 86d-e in the accompanying drawings denote loose CD auxiliary trenches that extend / overlap not only over the remainder of the lower memory layer 16 in which the second lower trench 88 will be formed, but also over one or more first lower trenches 42. The auxiliary trench 86 may also extend accordingly over the first intermediate stop 19 and the first lower stop 21, as... Figure 22 As shown in the enlarged illustration, along the auxiliary trench 86e. Due to the presence of the first intermediate barrier 19, each of the first lower barriers 21 exposed in the auxiliary trench 86 can be masked accordingly during the selective etching of the patterned lower memory layer 16, and thus retained after the formation of the second lower trench 88 is completed. Furthermore, the intermediate line 77 (and the spacer line 32) allows for ensuring a minimum spacing between the first and second lower trenches 42, 88.

[0132] exist Figure 24In this configuration, the patterned auxiliary trench mask stack 80 has been removed from the structure (e.g., using SOC etching), thereby exposing the (twice) patterned lower memory layer 16, in which first and second lower trenches 42, 88 are formed. The second lower trench 88 may be arranged alternately with the first lower trench 42. As further shown, one or more second lower trenches 88 may be separated from adjacent first trenches 42 only by a lower line formed by a (wall-like) portion of the patterned lower memory layer 16, namely a third lower memory layer portion 16d, retained beneath the spacer layer portion 32b and the intermediate line portion 77a. The linewidth of this lower line formed by the third lower memory layer portion 16d matches or at least corresponds to the linewidth of the spacer line portion 32b.

[0133] exist Figure 25 In this process, the target memory layer 12 has been patterned to form a first set of "target" trenches 96 below the first lower trench 42, and a second set of "target" trenches 98 below the second lower trench 88. The patterning of the target memory layer 12 may include etching the target memory layer 12 while it is being masked by the (double-patterned) lower memory layer 16. In other words, the first set of trenches 96 can be formed by etching back the target memory layer 12 through the first lower trench 42, and the second set of trenches 98 can be formed by etching back the target memory layer 12 through the second lower trench 98. The bottom surfaces of the trenches 96 and 98 may be formed from the interface layer 11 or the upper surface of the insulating layer 10.

[0134] Below each first lower barrier 21, a first target barrier 93 has been formed by a corresponding first target memory layer portion 12a that was concealed by the first lower barrier 21 during the etching of the target memory layer 12. Therefore, the corresponding first lower memory layer portion 12a can remain below each first upper barrier 21. Accordingly, at least a subset of the first target trench 96 is interrupted by the corresponding first target barrier 93.

[0135] Below each second lower barrier 90, a second target barrier 94 has been formed by the corresponding second target memory layer portion 12b that was masked by the second lower barrier 90 during the etching of the target memory layer 12. Therefore, the corresponding second lower memory layer portion 12b can remain below each second lower barrier 90. Accordingly, at least a subset of the second target trench 98 is interrupted by the corresponding second target barrier 94.

[0136] As shown in the figure, the second target trench 98 can be separated from the adjacent first target trench 96 (only) by the lower line 97 formed by the third target memory layer portion 12c, which is masked by the lower line formed by the corresponding third lower memory layer portion 16d during etching.

[0137] exist Figure 25In this process, the target memory layer 12 is also masked by the center line 77, the first and second intermediate barriers 19 and 76, the upper barrier 74, and the spacer line 32. This can provide an increased mask budget during the patterning of the target memory layer 12. However, it is possible that one or more of these components have been removed before the patterning of the target memory layer 12.

[0138] After the target memory layer 12 is patterned, the patterned lower memory layer 16, the middle line 77, the first and second intermediate barriers 19 and 76, the upper barrier 74 and the spacer line 32 can be removed from the patterned target memory layer 12. Figure 26 The resulting structure is shown in the figure.

[0139] Figure 27b and 27c The structure is shown along the respective directions. Figure 27a The corresponding cross-sectional views of lines A-A' and B-B' shown are illustrated. Trenches were etched in the insulating layer 10 and (the) interface layers 11 while the patterned target memory layer 12 masked the insulating layer 10, thereby forming a first insulating layer trench 100 under the first set of target trenches 96 and a second insulating layer trench 102 under the second set of target trenches 98. Therefore, the trench pattern defined in the target memory layer 12 has been transferred to the insulating layer 10, including any discontinuous trenches. (As can be seen...) Figure 27b , 27c As seen in the cross-sectional view, the etching of the trenches in the insulating layer can simultaneously create the final deepened via openings 52 and 67, similar to a dual damascene process.

[0140] As further illustrated, the trenches and via openings in the insulating layer 10 can be filled with a conductive material 104. However, as will be understood, the conductive material 104 may be deposited first after the target memory layer 12 has been removed. The conductive material 106 may be one or more metals conventionally used to form metal lines and vias in BEOL processes, such as providing some non-limiting examples: W, Cu, Al, Ru.

[0141] In the foregoing, the inventive concept has been described primarily with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

[0142] For example, the method can continue to deposit another insulating layer on top of insulating layer 10 and the metal wires and vias therein. The above method steps can then be repeated to form higher interconnect layers. This can be repeated until the desired number of interconnect layers are formed.

[0143] Furthermore, in the above process flow, the first set of trenches 96 and the second set of trenches 98 are patterned simultaneously in the target memory layer 12. However, a sequential approach is also possible, wherein the first set of trenches 96 is patterned in the target memory layer 12 before the second set of trenches 98 is patterned in the target memory layer 12. According to the sequential approach, the first set of trenches 96 may be formed, for example, after the formation of the first lower trench 42 and before the formation of the patterned upper memory layer 20 to form the upper barrier 30. The second set of trenches 98 may be formed after the formation of the second lower trench 88 in the patterned lower memory layer 16. If a via is to be formed during the first and / or second via formation process as described above, the first set of trenches 96 may be formed in the target memory layer 12, for example, before the via formation process.

Claims

1. A patterning method, comprising: A stack of layers (14) including a lower memory layer, a middle memory layer and an upper memory layer (16, 18, 20) is formed on top of the bottom layer (12). The upper memory layer (20) is patterned using photolithography and etching to form upper trenches (30) in the upper memory layer (20). A sidewall spacer line (32) is formed along the sidewall of the upper groove (30); The first mask barriers (38) are formed, and each first mask barrier (38) forms a groove interruption along the corresponding upper groove (30); Patterning the intermediate memory layer (18) and the lower memory layer (16) to form an intermediate trench (40) in the intermediate memory layer (18) and a first lower trench (42) in the lower memory layer (16) includes etching the intermediate memory layer (18) while the patterned upper memory layer (20), the sidewall spacer line (32), and the first mask block (38) are masking it. At least one subset of the intermediate trenches (40) is interrupted by a corresponding first intermediate barrier (19), the corresponding first intermediate barrier (19) being formed by a corresponding first intermediate memory layer portion (18a) that is covered by a corresponding first mask barrier (38), and at least one subset of the first lower trenches (42) is interrupted by a corresponding first lower barrier (21), the corresponding first lower barrier (21) being formed by a corresponding first lower memory layer portion (16a) that is covered by a corresponding first intermediate barrier (19); When the deposited mask material (68) is filling the upper trench, the middle trench, and the first lower trench (30, 40, 42): The patterned upper memory layer (20) is patterned using photolithography and etching to form an upper barrier (74) from the remaining upper memory layer portion (20b), and The patterned intermediate memory layer (18) is patterned to form a second intermediate barrier (76) and an intermediate line (77). The patterning includes etching while the patterned intermediate memory layer (18) is masked by the spacer line (32) and the upper barrier (74), and a deposited mask material masks the first intermediate barrier (19). The second intermediate barrier (76) is formed by the intermediate memory layer portion (18b) masked by the upper barrier (74), and the intermediate line (77) is formed by the intermediate memory layer portion (18c) masked by the spacer line (32). Patterning the patterned lower memory layer (16) to form a second lower trench (88) in the patterned lower memory layer (16) includes: An auxiliary trench mask stack (80) is formed on the lower memory layer (16), and the auxiliary trenches (86) are patterned therein by photolithography and etching. While the patterned lower memory layer (16) is masked by the patterned auxiliary trench mask stack (80), the second intermediate barrier (76) and the intermediate line (77) and the first intermediate barrier (19) masking the first lower barrier (21), the patterned lower memory layer (16) is etched, wherein at least a subset of the second lower trench (88) is interrupted by a corresponding second lower barrier (90), the corresponding second lower barrier (90) being formed by a corresponding second lower memory layer portion (16c) masked by the corresponding second intermediate barrier (76); The method further includes patterning a first set of grooves (96) below the first lower groove (42) and a second set of grooves (98) below the second lower groove (88) in the bottom layer (12).

2. The method of claim 1, wherein, Also includes: After the first lower trench (42) is formed, an auxiliary barrier mask stack (66) is formed, the auxiliary barrier mask stack (66) including a mask material (68) filling the upper trench, the intermediate trench and the first lower trench (30, 40, 42) and also including a resist layer (70). The patterning of the patterned upper memory layer (20) includes first patterning the auxiliary barrier mask stack (66) using photolithography and etching to form an auxiliary barrier (72), and then patterning the patterned upper memory layer (20) using the patterned auxiliary barrier mask stack (66) to form the upper barrier (74).

3. The method of claim 1 or 2, wherein, The auxiliary trench mask stack (80) includes a mask material (82) forming a planarization layer covering the upper barrier (74), the spacer line (32) and the patterned lower memory layer (16), and further includes a resist layer (84).

4. The method of claim 1 or 2, wherein, At least one auxiliary groove (86) extends above the first lower groove (42) and above the first intermediate barrier (19) located on the first lower barrier (21) in the first lower groove (42).

5. The method of claim 1 or 2, wherein, At least one subset of the second lower trench (88) is arranged alternately with at least one subset of the first lower trench (42).

6. The method of claim 5, wherein, The trenches in at least one subset of the second lower trench (88) are separated from the adjacent trenches in at least one subset of the first lower trench (42) by a corresponding lower line formed by a corresponding third lower memory layer portion (16d) that is obscured by a corresponding intermediate line (77).

7. The method of claim 1 or 2, wherein, The mask materials (68, 82) include organic spin-coating materials.

8. A method for forming an interconnect structure, comprising: A target memory layer (12) is formed on top of the insulating layer (10); A first set of trenches and a second set of trenches are formed in the target memory layer according to the method described in any one of claims 1-7, wherein the bottom layer (12) is the target memory layer; After forming the first and second sets of trenches (96, 98) in the target memory layer, while the insulating layer (10) is being masked by the target memory layer (12), trenches (100, 102) are etched in the insulating layer (10); and Conductive material (104) is deposited in the trenches in the insulating layer (10).

9. The method of claim 8, wherein, Also includes: After the patterning of the intermediate memory layer and the lower memory layer (18, 16) and before the patterning of the patterned upper memory layer (20): A second via etch stack (56) is formed, the second via etch stack (56) comprising a mask material (58) filling the upper trench, the middle trench and the first lower trench (30, 40, 42) and further comprising a resist layer (60). An opening (62) is formed in the second through-hole etch stack (56), the opening (62) exposing the upper surface (20a) of the remaining portion of the patterned upper memory layer (20). The exposed upper surface (20a) of the patterned upper memory layer (20) is etched back to form an opening (64) in the patterned upper memory layer (20), and The patterned middle memory layer, the patterned lower memory layer, and the target memory layer (18, 16, 12) are sequentially etched back through the opening (64) in the patterned upper memory layer (20) to form an extended opening therethrough; The method also includes etching the insulating layer (10) through the extended opening.

10. The method as described in claim 9, characterized in that, The exposed upper surface (20a) of the patterned upper memory layer is etched back at a rate greater than that of the mask material (58) filling the upper trench (30) and / or greater than that of the spacer line (32) to etch the patterned upper memory layer.

11. The method of any of claims 9-10, wherein, The exposed upper surface (20a) of the upper memory layer (20) is located between a pair of upper trenches (30), and the width of the opening in the second via etch stack (56) exceeds the spacing between the pair of upper trenches (30).

12. The method of any of claims 8-10, wherein, Also includes: After the patterning of the intermediate memory layer and the lower memory layer (18, 16) and before the patterning of the patterned upper memory layer (20): A first through-hole etch stack (44) is formed, the first through-hole etch stack (44) includes a mask material (46) filling the upper trench, the middle trench and the first lower trench (30, 40, 42), and further includes a resist layer (48). An opening (50) is formed in the first through-hole etch stack (44), the opening exposing the bottom surface (12a) of the first lower trench (42), and the opening (50) exposing the spacer layer portions (32a) on the opposite sides of the first lower trench (42). The exposed bottom surface (12a) is etched back to form an opening (52) in the target memory layer (12); The method also includes etching the insulating layer (10) through the opening (52) in the target memory layer (12).

13. The method of claim 12, wherein, Forming an opening (50) in the first through-hole etch stack (44) includes etching the mask material (46) filling the upper trench (30) at a rate greater than that of the spacer layer (32).

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