Packaging structure and fabrication method of interconnected multiple flip-chip stacks

Abstract

This invention provides a packaging structure for interconnected stacked flip chips and its fabrication method. The packaging structure includes: a redistribution layer; a flip chip stack structure stacked vertically on the upper surface of the redistribution layer; the flip chip stack structure includes N layers of flip chips and N-1 layers of adapter boards, where N≥2; wherein, the first layer of flip chips is soldered to the first layer of adapter boards on the redistribution layer, the Mth layer of adapter boards is soldered to the M-1th layer of adapter boards, the Mth layer of flip chips is stacked on the M-1th layer of flip chips and the M-1th layer of adapter boards, and is non-electrically connected to the M-1th layer of flip chips but electrically connected to the M-1th layer of adapter boards, where N≥M≥2; and a packaging layer. This packaging structure changes the existing packaging structure where flip chips are packaged in a horizontal arrangement to a three-dimensional packaging structure packaged in a vertical arrangement, effectively reducing the area utilization of multiple flip chip stacks, reducing the size of the package, and facilitating product miniaturization.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and in particular relates to a packaging structure for interconnecting multiple flip-chip stacks and its fabrication method. Background Technology

[0002] With the trend towards multifunctionality, high performance, and miniaturization in electronic products, high-density microelectronic assembly technology is gradually becoming mainstream in next-generation electronic products. To support the development of next-generation electronic products, especially smartphones, PDAs, and ultrabooks, chip sizes are evolving towards higher density, faster speeds, smaller dimensions, and lower costs. Simultaneously, semiconductor integrated circuit packaging is being developed towards thinner, lighter, smaller, and higher-performance designs, requiring high-density interconnection and the ability to package multiple chips of different materials and process nodes within a single package.

[0003] A redistribution layer (RDL) rearranges the pad locations on a chip, ensuring the new pads meet minimum solder ball spacing requirements and are arranged in an array. For high I / O chip packages, multiple RDL lines are necessary. However, within limited form factors and package sizes, smaller RDL line widths and spacings mean more power supply tracks can be achieved.

[0004] Currently, RDL technology allows for chip interconnection with smaller microbump pitches (10 micrometers to 50 micrometers) and finer linewidths and spacings (1 micrometer to 5 micrometers). For example... Figure 1 As shown, each flip chip 10 is connected to the RDL12 via microbumps 11 and then interconnected via the RDL12 traces. The signals and power supplies that need to be brought out of the package are connected to the solder balls 13 via the RDL12. Since they are all flip chips, the chips must be placed side by side and cannot be stacked, which is not conducive to reducing the package area. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a packaging structure of interconnected stacked flip chips and its preparation method, which solves the problem that in the prior art, flip chips must be placed side by side during the packaging process and cannot be stacked, resulting in a large packaging structure area.

[0006] To achieve the above and other related objectives, the present invention provides a package structure for interconnecting multiple flip-chip stacks, the package structure comprising:

[0007] Re-route the layer and set it to the bottom layer;

[0008] A flip-chip stack structure is stacked vertically on the upper surface of the redistribution layer; the flip-chip stack structure includes N layers of flip chips and N-1 layers of adapter boards, where N≥2; wherein, the first layer of flip chips is soldered to the first layer of adapter boards on the redistribution layer, the Mth layer of adapter boards is soldered to the M-1th layer of adapter boards, the Mth layer of flip chips is stacked on the M-1th layer of flip chips and the M-1th layer of adapter boards, and is non-electrically connected to the M-1th layer of flip chips, but electrically connected to the M-1th layer of adapter boards, where N≥M≥2;

[0009] An encapsulation layer covers the flip-chip stack structure.

[0010] Optionally, the number of the first layer flip chips is one, and the number of the Mth layer flip chips is two or more.

[0011] Optionally, the Mth flip chip and the (M-1)th layer adapter board, the first layer flip chip and the redistribution layer, the first layer adapter board and the redistribution layer, and the Mth layer adapter board and the (M-1)th layer adapter board are all electrically connected through metal microbumps.

[0012] Optionally, the M-th flip chip is stacked on the M-1-th flip chip using a chip adhesive, wherein the chip adhesive is made of polyimide or epoxy resin with added silver particles or silica particles.

[0013] Optionally, the lower surface of the redistribution layer is provided with metal solder balls; the metal solder balls include one of gold-tin solder balls, silver-tin solder balls, and copper-tin solder balls, or the metal solder balls include metal pillars and solder balls formed on the metal pillars.

[0014] Optionally, the redistribution layer includes a dielectric layer and a metal wiring layer. The dielectric layer is made of one or more materials selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorinated glass. The metal wiring layer is made of one or more materials selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium. The encapsulation layer is made of one material selected from polyimide, silicone, and epoxy resin.

[0015] The present invention also provides a method for fabricating a package structure of interconnected multiple flip-chip stacks. This method can be used to fabricate the aforementioned package structure of interconnected multiple flip-chip stacks, and the method includes the following steps:

[0016] Fabrication of the redistribution layer and adapter board;

[0017] A flip-chip stack structure is stacked vertically on the upper surface of the redistribution layer. The flip-chip stack structure includes N layers of flip chips and N-1 layers of adapter boards, where N≥2. The stack structure includes: soldering a first layer of flip chips to a first layer of adapter boards on the redistribution layer; soldering an M-th layer of adapter boards to an M-1 layer of adapter boards, where N≥M≥2; stacking an M-th layer of flip chips on an M-1 layer of flip chips and an M-1 layer of adapter boards, and non-electrically connected to the M-1 layer of flip chips, but electrically connected to the M-1 layer of adapter boards.

[0018] The flip-chip stack structure is encapsulated using an encapsulation layer.

[0019] Optionally, the redistribution layer is formed on the support substrate via a separation layer, and pads are formed on the upper surface of the redistribution layer.

[0020] Optionally, after forming the encapsulation layer, the method further includes the steps of: removing the separation layer and the support substrate; placing metal solder balls on the lower surface of the redistribution layer; and cutting the above structure into individual encapsulation structures.

[0021] Optionally, the step of fabricating the adapter board includes: providing a wafer carrier or a flat substrate; fabricating the required adapter board on the substrate; removing the substrate and forming metal microbumps on one side of the adapter board and pads on the other side; and cutting the above structure into individual adapter boards.

[0022] As described above, the interconnected stacked flip chip packaging structure and its fabrication method of the present invention stack a portion of the upper flip chip on the lower flip chip in a non-electrically connected manner, while the remaining portion is electrically connected to the redistribution layer via an adapter board. This allows all flip chips to be directly or indirectly electrically connected to the redistribution layer through the adapter board, enabling all flip chips to be interconnected through the redistribution layer. This changes the existing packaging structure where flip chips are packaged in a horizontal arrangement to a three-dimensional packaging structure packaged in a vertical arrangement, effectively reducing the area utilization of the stacked flip chip packaging, reducing the size of the package, and facilitating product miniaturization. Attached Figure Description

[0023] Figure 1 The diagram shows a package structure of multiple flip-chip stacks interconnected in the prior art.

[0024] Figure 2 The diagram shown is a schematic of a package structure of interconnected multiple flip-chip stacks according to Embodiment 1 of the present invention, wherein the flip-chip stack structure includes two layers of flip chips.

[0025] Figure 3The diagram shown is a schematic of a package structure of interconnected stacked flip chips according to Embodiment 1 of the present invention, wherein the flip chip stack structure includes three layers of flip chips.

[0026] Figure 4 The diagram shown is a schematic of a package structure of interconnected multiple flip-chip stacks according to Embodiment 1 of the present invention. The flip-chip stack structure includes two layers of flip chips, and the number of the second layer of flip chips is two or more.

[0027] Figure 5 The diagram shows a top view illustrating the positional relationship between the Mth and M-1th layers of the flip-chip stack structure in the interconnected multiple flip-chip stack packaging structure of Embodiment 1 of the present invention.

[0028] Figure 6 The diagram shows a process flow diagram of the fabrication method of a package structure of interconnected multiple flip-chip stacks according to Embodiment 2 of the present invention.

[0029] Figures 7 to 13 The diagram shows the structural schematics of each step in the preparation method of the interconnected stacked flip-chip package structure of Embodiment 2 of the present invention, wherein the flip-chip stack structure includes two layers of flip chips as an example.

[0030] Component designation explanation

[0031] 10 Flip Chips

[0032] 11 Microbumps

[0033] 12 RDL

[0034] 13 Welding balls

[0035] 20 Flip Chip Stack Structure

[0036] 21 Flip Chip

[0037] 210 First Layer Flip Chip

[0038] 211 Layer M Flip Chip

[0039] 212 Layer M-1 Flip Chip

[0040] 213 Layer M-2 Flip Chip

[0041] 22 Adapter Board

[0042] 220 First Layer Adapter Board

[0043] 221 Mth layer adapter board

[0044] 222 M-1 Layer Adapter Board

[0045] 30 Rerouting layer

[0046] 300 dielectric layer

[0047] 301 Metal Wiring Layer

[0048] 302 Separation Layer

[0049] 303 Supporting Substrate

[0050] 31 Encapsulation layer

[0051] 32 Metal microbumps

[0052] 33 Metal solder balls

[0053] 34 pads

[0054] Steps S1 to S3 Detailed Implementation

[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please see Figures 2 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be changed according to actual needs, and the layout of the components may also be more complex.

[0057] Example 1

[0058] like Figures 2 to 5 As shown, this embodiment provides a package structure for interconnected stacked flip chips, the package structure including:

[0059] Reroute layer 30 and set it to the bottom layer;

[0060] A flip-chip stack structure 20 is stacked vertically on the upper surface of the redistribution layer 30. The flip-chip stack structure 20 includes N layers of flip chips 21 and N-1 layers of adapter boards 22, where N ≥ 2. The first layer of flip chips 210 is soldered to the first layer of adapter board 220 on the redistribution layer 30, the Mth layer of adapter board 221 is soldered to the M-1th layer of adapter board 222, the Mth layer of flip chips 211 is stacked on the M-1th layer of flip chips 212 and the M-1th layer of adapter board 222, and is non-electrically connected to the M-1th layer of flip chips 212, but electrically connected to the M-1th layer of adapter board 222, where N ≥ M ≥ 2.

[0061] The encapsulation layer 31 covers the flip chip stack structure 20.

[0062] The interconnected stacked flip-chip package structure of this embodiment stacks a portion of the upper flip-chip on the lower flip-chip in a non-electrical connection manner, while the remaining portion is electrically connected to the redistribution layer via an adapter board. This allows all flip-chips to be directly or indirectly electrically connected to the redistribution layer through the adapter board, enabling all flip-chips to be interconnected through the redistribution layer. This changes the existing horizontally arranged flip-chip package structure to a three-dimensional package structure with a vertical arrangement, effectively reducing the area utilization of the stacked flip-chip package, shrinking the package size, and facilitating product miniaturization.

[0063] like Figure 2 and Figure 3 As shown, as an example, the number of layers of flip chips 21 in the flip chip stacking structure 20 can be set according to actual needs, such as... Figure 2 It contains two layers of flip-chip 21. Figure 3 It has three layers of flip chips 21, but it is not limited to this; it can also have four, five, or even more layers.

[0064] like Figure 4 and Figure 5 As shown, for example, the number of the first layer flip chip 210 is one, and the number of the Mth layer flip chip 211 is two or more, such as... Figure 5 As shown, the number of flip chips 211 in the Mth layer is 6, but it is not limited to this and can be set according to actual needs.

[0065] like Figure 3 , Figure 7 and Figure 13As shown, as an example, the Mth layer flip chip 211 and the M-1th layer adapter board 222, the first layer flip chip 210 and the redistribution layer 30, the first layer adapter board 220 and the redistribution layer 30, and the Mth layer adapter board 221 and the M-1th layer adapter board 222 are all electrically connected through metal microbumps 32.

[0066] As an example, the M-th flip chip 211 is stacked on the M-1-th flip chip 212 by a chip adhesive. The chip adhesive can be made of existing conventional chip bonding materials, such as polyimide or epoxy resin with added silver particles or silica particles.

[0067] like Figure 2 As shown, as an example, the lower surface of the redistribution layer 30 is provided with metal solder balls 33. The metal solder balls 33 facilitate signal transmission between the internal electrical signals of the entire package structure and the external structure. The metal solder balls 33 include one of gold-tin solder balls, silver-tin solder balls, and copper-tin solder balls; alternatively, the metal solder balls 33 include metal pillars and solder balls formed on the metal pillars.

[0068] like Figure 8 As shown in the illustration, the redistribution layer 30 includes a dielectric layer 300 and a metal wiring layer 301. The dielectric layer 300 is made of one or more materials selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorinated glass. The metal wiring layer 301 is made of one or more materials selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium. It should be noted that the materials, number of layers, and distribution morphology of the dielectric layer 300 and the metal wiring layer 301 can be configured according to the specific circumstances of the flip chip and are not limited here.

[0069] like Figure 2 and Figure 3 As shown, as an example, the material of the encapsulation layer 31 can be selected from existing conventional semiconductor encapsulation materials, such as encapsulation materials including polyimide, silicone and epoxy resin.

[0070] Example 2

[0071] like Figures 6 to 13 As shown, this embodiment provides a method for fabricating a package structure of interconnected multiple flip-chip stacks. The package structure of interconnected multiple flip-chip stacks described in Embodiment 1 can be fabricated using this method, but it is not limited thereto. The beneficial effects it can achieve can be found in Embodiment 1, and will not be repeated here.

[0072] Specifically, such as Figure 6As shown, the preparation method includes the following steps:

[0073] S1, Prepare the redistribution layer and adapter board;

[0074] S2, a flip-chip stack structure is stacked vertically on the upper surface of the redistribution layer. The flip-chip stack structure includes N layers of flip chips and N-1 layers of adapter boards, where N≥2. The process includes: soldering a first layer of flip chips to a first layer of adapter boards on the redistribution layer; soldering an M-th layer of adapter boards to an M-1 layer of adapter boards, where N≥M≥2; stacking an M-th layer of flip chips on an M-1 layer of flip chips and an M-1 layer of adapter boards, and non-electrically connected to the M-1 layer of flip chips, but electrically connected to the M-1 layer of adapter boards.

[0075] S3, the redistribution layer and the flip-chip stack structure are encapsulated using an encapsulation layer.

[0076] For ease of understanding, the following describes the preparation method of this embodiment in detail, taking the flip chip stacking structure as having two layers (i.e., the first layer of flip chip and the second layer of flip chip) and the adapter board as one layer (i.e., the first layer of adapter board), that is, N=2.

[0077] like Figure 7 and Figure 8 As shown, step S1 is performed first to prepare the rewiring layer 30 and the first layer adapter board 220.

[0078] It should be noted that when the flip-chip stack structure 20 has multiple layers, adapter boards for each layer need to be fabricated according to the specific connection method. For example, in addition to the first layer adapter board 220, there may be an Mth layer adapter board 221 and an (M-1)th layer adapter board 222. The structure of each layer adapter board is designed according to the actual circuit connection requirements and is not limited here. Furthermore, the fabrication order of the redistribution layer 30 and the first layer adapter board 220 does not affect each other; that is, they can be fabricated simultaneously or sequentially. This is not limited here and is determined based on the actual situation.

[0079] like Figure 7As shown, as an example, the steps for fabricating the first layer adapter 220 include: first, providing a wafer carrier or a flat substrate; then, fabricating the required adapter on the substrate; next, removing the substrate and forming metal microbumps 32 (the lower surface in this embodiment) on one side of the adapter and pads 34 (the upper surface in this embodiment) on the other side; finally, cutting the above structure into individual adapters. As an example, the material of the pads 34 can be aluminum, making them aluminum pads. When fabricating the pads 34, to improve the electrical performance of the pads 34 and their adhesion to flip chips, an adhesive layer can be formed under the pads 34, and an anti-reflective layer can be formed on the pads 34.

[0080] like Figure 8 As shown, as an example, the steps for preparing the redistribution layer 30 include: first, providing a support substrate 303, and forming a separation layer 302 on the support substrate 303; then forming the redistribution layer 30 on the separation layer 302, wherein pads 34 are formed on the upper surface of the redistribution layer 30. The support substrate 303 can be selected from one of glass substrate, metal substrate, semiconductor substrate, polymer substrate, and ceramic substrate. In this embodiment, the support substrate 303 is selected as a glass substrate. Glass substrate has low cost, it is easy to form a separation layer 302 on its surface, and it can reduce the difficulty of subsequent peeling process. The separation layer 302 can be selected from a polymer layer or an adhesive layer. The polymer layer or adhesive layer is first coated on the surface of the support substrate 303 by spin coating process, and then cured by ultraviolet curing or thermal curing process. In this embodiment, the polymer layer includes an LTHC photothermal conversion layer. When peeling off the support substrate 303, the LTHC photothermal conversion layer can be heated by laser to separate the flip chip stack structure 20 and the support substrate 303 from the LTHC photothermal conversion layer.

[0081] like Figure 9 and Figure 10 As shown, then step S2 is performed, where a flip chip stack structure 20 is stacked vertically on the upper surface of the redistribution layer 30. The flip chip stack structure 20 includes two layers of flip chips 21 and a first layer of adapter board 220, including: Figure 9 As shown, the first flip chip 210 is first soldered to the first adapter board 220 on the redistribution layer 30; as... Figure 10 As shown, the second flip chip 213 is then stacked on the first flip chip 210 and the first adapter board 220, and is non-electrically connected to the first flip chip 210, but electrically connected to the first adapter board 220.

[0082] like Figure 11As shown, the final step is S3, in which the flip chip stack structure 20 is encapsulated using the encapsulation layer 31.

[0083] As an example, the method of encapsulating the flip chip stack structure 20 with the encapsulation layer 31 includes one of compression molding, transfer molding, liquid encapsulation, vacuum lamination, and spin coating. The material of the encapsulation layer 31 includes one of polyimide, silicone, and epoxy resin. Preferably, after the encapsulation layer 31 is formed, grinding or polishing can be applied to the upper surface of the encapsulation layer 31 to provide a smooth encapsulation layer and improve product quality.

[0084] like Figure 12 and Figure 13 As shown, as an example, after forming the encapsulation layer 31, the following steps are further included: removing the separation layer 302 and the support substrate 303 (e.g., Figure 12 (as shown); metal solder balls 33 are disposed on the lower surface of the redistribution layer 30 (e.g., as shown). Figure 13 (as shown); finally, the above structure is cut into individual package structures. In this embodiment, the metal solder ball 33 is selected as a gold-tin solder ball, and its manufacturing steps include: firstly, a gold-tin layer is formed on the lower surface of the redistribution layer 30, and then the gold-tin layer is reflowed into a spherical shape using a high-temperature reflow process, and then the gold-tin solder ball is formed after cooling; or a ball-planting process is used to form the gold-tin solder ball.

[0085] In summary, this invention provides a packaging structure and fabrication method for interconnected stacked flip chips. By stacking a portion of the upper flip chip on the lower flip chip in a non-electrically connected manner, and electrically connecting the remaining portion to the redistribution layer via an adapter board, all flip chips are directly or indirectly electrically connected to the redistribution layer through the adapter board. This achieves interconnection of all flip chips through the redistribution layer, changing the existing horizontally arranged flip chip packaging structure to a three-dimensional vertically arranged packaging structure. This effectively reduces the area utilization of stacked flip chips, shrinks the package size, and facilitates product miniaturization. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A package structure for interconnecting multiple flip-chip stacks, characterized in that, The packaging structure includes: Re-route the layer and set it to the bottom layer; A flip-chip stack structure is stacked vertically on the upper surface of the redistribution layer. The flip-chip stack structure includes N layers of flip chips and N-1 layers of adapter boards, where N≥2. The first layer of flip chips is soldered to the first layer of adapter boards on the redistribution layer, the Mth layer of adapter boards is soldered to the M-1th layer of adapter boards, and the Mth layer of flip chips is stacked on the M-1th layer of flip chips and the M-1th layer of adapter boards. The Mth layer of flip chips is non-electrically connected to the M-1th layer of flip chips via chip adhesive and electrically connected to the M-1th layer of adapter boards, where N≥M≥2. Electrical connections are achieved between the Mth layer of flip chips and the M-1th layer of adapter boards, between the first layer of flip chips and the redistribution layer, between the first layer of adapter boards and the redistribution layer, and between the Mth layer of adapter boards and the M-1th layer of adapter boards via metal microbumps. An encapsulation layer covers the flip-chip stack structure.

2. The interconnected stacked flip-chip packaging structure according to claim 1, characterized in that: The number of the first layer flip chips is one, and the number of the Mth layer flip chips is two or more.

3. The packaging structure of multiple flip-chip stacks according to claim 1, characterized in that: The chip adhesive is made of polyimide or epoxy resin with added silver particles or silica particles.

4. The packaging structure of multiple flip-chip stacks according to claim 1, characterized in that: The lower surface of the redistribution layer is provided with metal solder balls; the metal solder balls include one of gold-tin solder balls, silver-tin solder balls, and copper-tin solder balls, or the metal solder balls include metal pillars and solder balls formed on the metal pillars.

5. The packaging structure of multiple flip-chip stacks according to claim 1, characterized in that: The redistribution layer includes a dielectric layer and a metal wiring layer. The dielectric layer is made of one or more materials selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorinated glass. The metal wiring layer is made of one or more materials selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium. The encapsulation layer is made of one material selected from polyimide, silicone, and epoxy resin.

6. A method for fabricating a package structure of interconnected stacked flip chips, characterized in that, The preparation method includes the following steps: Fabrication of the redistribution layer and adapter board; A flip-chip stack structure is vertically stacked on the upper surface of the redistribution layer. The flip-chip stack structure includes N layers of flip chips and N-1 layers of adapter boards, where N≥2. The structure includes: soldering a first layer of flip chips to a first layer of adapter boards on the redistribution layer; soldering an Mth layer of adapter boards to an M-1 layer of adapter boards, where N≥M≥2; stacking an Mth layer of flip chips on the M-1 layer of flip chips and the M-1 layer of adapter boards, and non-electrically connecting the M-1 layer of flip chips to the M-1 layer of flip chips and electrically connecting it to the M-1 layer of adapter boards using chip adhesive; wherein the Mth layer of flip chips and the M-1 layer of adapter boards, the first layer of flip chips and the redistribution layer, the first layer of adapter boards and the redistribution layer, and the Mth layer of adapter boards and the M-1 layer of adapter boards are all electrically connected via metal microbumps. The flip-chip stack structure is encapsulated using an encapsulation layer.

7. The method for fabricating a package structure of interconnected stacked flip chips according to claim 6, characterized in that: The redistribution layer is formed on the support substrate via a separation layer, and pads are formed on the upper surface of the redistribution layer.

8. The method for fabricating a package structure of interconnected multiple flip-chip stacks according to claim 7, characterized in that, After forming the encapsulation layer, the method further includes the step of removing the separation layer and the supporting substrate; Metal solder balls are disposed on the lower surface of the redistribution layer; the above structure is cut into individual package structures.

9. The method for fabricating a package structure of interconnected multiple flip-chip stacks according to claim 6, characterized in that, The steps for preparing the adapter board include: providing a wafer carrier or a flat substrate; preparing the required adapter board on the substrate; removing the substrate and forming metal microbumps on one side of the adapter board and pads on the other side; and cutting the above structure into individual adapter boards.

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