Display substrate and manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate and a method for manufacturing the same, and a display device. The display substrate includes a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; the first display area includes: a substrate, a light-emitting structure layer disposed on the substrate, the light-emitting structure layer includes a plurality of conductive layers, and at least one of the conductive layers is provided with a plurality of openings penetrating the conductive layers. The transmittance of the display panel in the camera area under the screen is increased without reducing the resolution of the display panel.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display technology has the characteristics of self-luminescence, wide viewing angle, high color gamut, low power consumption, lightness, and transparency, making the design of OLED more free. Among them, active matrix OLED (AMOLED) can realize large-size, high-resolution panels by integrating thin-film transistors and capacitors in each pixel. With the development of display technology, the current demand for the screen-to-body ratio of smartphone screens is getting higher and higher. In order to achieve a higher screen-to-body ratio, under-screen camera technology has become a technical difficulty in realizing the demand for a truly full-screen display. In order to enable the under-screen camera to collect more incident light when taking pictures, the display panel at this position needs to have a high optical transmittance. However, the transmittance of thin-film transistors, capacitors and wires, OLED pixel units and other positions in OLED display panels is usually low, which seriously limits the overall optical transmittance of the display panel. Summary of the invention

[0003] Embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device, which increase transmittance without reducing display resolution.

[0004] On the one hand, an embodiment of the present disclosure provides a display substrate, including a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; the first display area includes: a substrate, a light-emitting structure layer arranged on the substrate, the light-emitting structure layer includes multiple conductive layers, and at least one of the conductive layers is provided with multiple openings passing through the conductive layer.

[0005] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0006] On the other hand, the embodiments of the present disclosure further provide a method for preparing a display substrate, comprising: forming a light-emitting structure layer on a base, wherein the light-emitting structure layer comprises a plurality of conductive layers, and at least one of the conductive layers is provided with a plurality of openings penetrating the conductive layer.

[0007] The embodiments of the present disclosure provide a display substrate and a method for preparing the same, and a display device. By providing openings penetrating the conductive layers in one or more conductive layers, the optical transmittance of the film layer can be increased, thereby increasing the transmittance of the display panel in the camera area under the screen without reducing the resolution of the display panel. The manufacturing process of the display substrate of the exemplary embodiment of the present disclosure has good process compatibility, simple process realization, easy implementation, high production efficiency, and low production cost.

[0008] Of course, it is not necessary to achieve all the advantages described above at the same time for any product or method of the present disclosure. Other features and advantages of the present disclosure will be described in the subsequent description embodiments, and partly become apparent from the description embodiments, or be understood by practicing the present disclosure. The purposes and other advantages of the embodiments of the present disclosure can be achieved and obtained by the structures specifically pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0010] Figure 1A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0011] Figure 1B is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0012] Figure 2 is an equivalent circuit diagram of a pixel circuit;

[0013] Figure 3 is a schematic diagram of a cross-sectional structure of a first display area of ​​a display substrate;

[0014] Figure 4 It is a schematic diagram of the cross-sectional structure after forming the second capacitor electrode in the embodiment of the present disclosure;

[0015] Figure 5A A schematic diagram of an opening structure according to an embodiment of the present disclosure;

[0016] Figure 5B A schematic diagram of another opening structure according to an embodiment of the present disclosure;

[0017] Figure 6 It is a schematic diagram of an embodiment of the present disclosure after an opening structure is formed in the fourth wiring layer;

[0018] Figure 7It is a schematic diagram of an embodiment of the present disclosure after an opening structure is formed in the anode;

[0019] Figure 8 It is a schematic diagram of a cathode induced anti-reflection layer formed in an embodiment of the present disclosure;

[0020] Fig. 9 This is a diagram showing the effect of cathode induced anti-reflection achieved by the induced anti-reflection layer in the embodiment of the present disclosure;

[0021] Fig. 10A This is a schematic diagram of the TFT area and the OLED light-emitting area being opaque in the embodiment of the present disclosure;

[0022] Fig. 10B This is a schematic diagram showing that the TFT region, the capacitor region and the OLED light-emitting region are all light-transmissive in an embodiment of the present disclosure.

[0023] Description of reference numerals:

[0024] 10—substrate; 11—first insulating layer; 12—active layer;

[0025] 13—first wiring layer; 14—second insulating layer; 15—gate electrode;

[0026] 16—first capacitor electrode; 17—third insulating layer; 18—second capacitor electrode;

[0027] 19—fourth insulating layer; 20—source electrode; 21—drain electrode;

[0028] 22—the fourth wiring layer; 23—the flat layer; 24—the anode;

[0029] 25—pixel definition layer; 26—organic light emitting layer; 27—cathode;

[0030] 28—induced anti-reflection layer; 41—pixel circuit layer; 42—light-emitting device;

[0031] 50—packaging structure layer; 401—thin film transistor; 402—storage capacitor. DETAILED DESCRIPTION

[0032] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0033] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a unique solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other solutions to form another unique solution defined by the claims. Therefore, it should be understood that any feature shown or discussed in the present disclosure may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other limitations. In addition, one or more modifications and changes may be made within the scope of protection of the attached claims.

[0034] In addition, when describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method or process should not be limited to the steps that are performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0035] In the drawings, the size of the components, the thickness of the layers, or the regions are sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the dimensions, and the shape and size of each component in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0036] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure are the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. In the present disclosure, "multiple" can mean two or more numbers. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Coupled", "connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Electrical connection" includes the situation where the constituent elements are connected together through an element with some electrical function. "Elements with some electrical function" are not particularly limited as long as they can transfer electrical signals between the connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0037] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0038] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0039] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0040] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0041] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0042] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0043] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures can refer to the general design.

[0044] In order to improve the transmittance of the display panel in this area, some pixel design methods set a transparent window area at the pixel unit position to achieve high transmittance of the display panel. However, this technology reduces the display resolution of the panel, making the resolution of the display panel in the camera area under the screen significantly lower than the resolution of the surrounding normal display area. Some technologies use transparent metal electrodes in the capacitor area of ​​the pixel unit to improve the transmittance of the capacitor area, thereby improving the transmittance of the display panel. However, the overall transmittance of the display panel can only be limited by improving the transmittance of the capacitor area. In addition, the cathode electrode of the OLED pixel unit is usually a continuous surface of semi-transparent metal, which further limits the improvement of the transmittance of the display panel.

[0045] To this end, the embodiments of the present disclosure provide an effective solution for improving the light transmittance of the under-screen camera area panel without reducing the display resolution of the under-screen camera area panel.

[0046] The display substrate includes a first display area and a second display area, the first display area is located on at least one side of the second display area; the first display area includes: a substrate, a light-emitting structure layer arranged on the substrate, the light-emitting structure layer includes multiple conductive layers, and at least one of the conductive layers is provided with multiple openings penetrating the conductive layer.

[0047] The first display area is, for example, an under-screen camera area, and the second display area is, for example, an effective display area (AA).

[0048] By providing openings penetrating the conductive layers in one or more conductive layers, the optical transmittance of the film layer can be increased, thereby increasing the transmittance of the display panel in the camera area under the screen without reducing the resolution of the display panel. The preparation process of the display substrate of the exemplary embodiment of the present disclosure has good process compatibility, simple process realization, easy implementation, high production efficiency and low production cost.

[0049] In an exemplary embodiment, the light emitting structure layer includes a first insulating layer arranged on the substrate and a semiconductor layer arranged on the first insulating layer, the semiconductor layer includes an active layer and a first wiring layer, the active layer is provided with a plurality of openings passing through the active layer, and / or the first wiring layer is provided with a plurality of openings passing through the first wiring layer.

[0050] In an exemplary embodiment, the light-emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, and a first metal layer stacked in sequence on the substrate, the first metal layer includes a gate electrode, a first capacitor electrode and a second wiring layer, wherein one or more of the gate electrode, the first capacitor electrode and the second wiring layer are provided with the openings, the multiple openings in the gate electrode penetrate the gate electrode, the multiple openings in the first capacitor electrode penetrate the first capacitor electrode, and the multiple openings in the second wiring layer penetrate the second wiring layer.

[0051] In an exemplary embodiment, the light-emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, and a second metal layer stacked in sequence on the substrate, the second metal layer includes a second capacitor electrode and a third wiring layer, wherein the second capacitor electrode is provided with a plurality of openings passing through the second capacitor electrode, and / or the third wiring layer is provided with a plurality of openings passing through the third wiring layer.

[0052] In an exemplary embodiment, the light-emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, and a third metal layer stacked in sequence on the substrate, the third metal layer includes a source electrode, a drain electrode and a fourth wiring layer, wherein one or more of the source electrode, the drain electrode and the fourth wiring layer are provided with the openings, the multiple openings in the source electrode penetrate the source electrode, the multiple openings in the drain electrode penetrate the drain electrode, and the multiple openings in the fourth wiring layer penetrate the fourth wiring layer.

[0053] In an exemplary embodiment, the light emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, a third metal layer, a flat layer, and a conductive layer stacked in sequence on the substrate, and the conductive layer includes an anode, wherein the anode is provided with a plurality of openings passing through the anode.

[0054] In an exemplary embodiment, the plurality of conductive layers are provided with the openings, and the orthographic projections of the plurality of conductive layers on the substrate have overlapping areas, and the openings of the plurality of conductive layers overlap in the orthographic projections of the overlapping areas. For example, when the first wiring layer, the first capacitor electrode, and the second capacitor electrode are provided with the openings, in the direction perpendicular to the substrate, the orthographic projections of the conductive layers on the substrate have overlapping areas, and the orthographic projections of the plurality of openings of the first wiring layer, the first capacitor electrode, and the second capacitor electrode overlap at least in the overlapping areas of the substrate, or the plurality of opening positions of each conductive layer correspond in the direction perpendicular to the substrate, so that light can be projected from the openings of the conductive layer away from the substrate into the openings of the conductive layer close to the substrate, thereby improving the transmittance of light in the capacitor area. When some of the conductive layers in the first wiring layer, the first capacitor electrode, and the second capacitor electrode are provided with openings, the above-mentioned opening overlapping setting method can also be adopted. For another example, when the active layer, gate electrode, source electrode and drain electrode are provided with the openings, in the direction perpendicular to the substrate, the orthographic projections of the above conductive layers on the substrate have overlapping areas, and the orthographic projections of the multiple openings of the active layer, gate electrode, source electrode and drain electrode overlap at least in the overlapping areas of the substrate, that is, the multiple opening positions of each conductive layer correspond to each other, which can improve the light transmittance of the TFT area. When some of the conductive layers of the active layer, gate electrode, source electrode and drain electrode are provided with openings, the above-mentioned overlapping openings can also be used.

[0055] In an exemplary embodiment, the opening may be in a circular shape, or in a polygonal shape such as a triangle, a quadrilateral, a pentagon, or a hexagon.

[0056] In an exemplary embodiment, the light emitting structure layer further comprises a cathode, and an induced anti-reflection layer is disposed on the surface of the cathode away from the substrate. By providing the induced anti-reflection layer, the reflectivity of the cathode surface can be reduced, thereby increasing the transmittance. Optionally, the induced anti-reflection layer can be made of any one or more of silicon dioxide SiO2 and aluminum oxide Al2O3, and the thickness can be 30-500 nanometers.

[0057] Figure 1A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1B FIG. 4 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.

[0058] In some exemplary embodiments, the display substrate includes: a first display area R1 and a second display area R2, and the first display area R1 may be located on at least one side of the second display area R2. In some examples, the second display area R2 partially surrounds the first display area R1. For example, Figure 1A The first display area R1 is shown to be located in the middle of the top of the display substrate, one side of the first display area R1 is adjacent to the peripheral area, and the other three sides are surrounded by the second display area R2. However, this embodiment is not limited to this. For example, the first display area R1 can be located at other positions such as the upper left corner or the upper right corner of the display substrate.

[0059] In some exemplary embodiments, Figure 1B As shown, the second display area R2 may surround the first display area R1. The first display area R1 may be located in the middle of the upper half of the display substrate. However, this embodiment is not limited to this. The location of the first display area R1 may be determined as required.

[0060] In some exemplary embodiments, Figure 1A and Figure 1B As shown, the first display area R1 and the second display area R2 may both be rectangular, such as a rounded rectangle. However, this embodiment is not limited thereto. For example, the first display area R1 may be a circle, an ellipse, a polygon or other shapes, and the second display area R2 may be a circle, a quadrilateral, a pentagon or other shapes. For example, the shapes of the first display area R1 and the second display area R2 may be the same or different.

[0061] In some exemplary embodiments, the first display area R1 may be a light-transmitting display area. For example, the orthographic projection of hardware such as a light sensor (such as a camera) on the display substrate may be located within the first display area R1 of the display substrate. The display substrate of this example does not need to be perforated, and a true full screen may be possible while ensuring the practicality of the display substrate.

[0062] In some exemplary embodiments, the display substrate may include a plurality of sub-pixels disposed on a substrate, at least one of the sub-pixels including a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. For example, the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, or white light, etc., when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required.

[0063] In some exemplary embodiments, in order to improve the light transmittance of the first display area R1, only a light-emitting element may be provided in the first display area R1, and a pixel circuit driving the light-emitting element of the first display area R1 may be provided in the second display area R2. That is, the light transmittance of the second display area R2 is improved by separately providing the light-emitting element and the pixel circuit. Alternatively, a pixel circuit and a light-emitting element may also be provided in the first display area R1, and the present disclosure does not limit this. The following examples are described by taking the arrangement of a pixel circuit and a light-emitting element in the first display area R1 as an example, and the implementation may be referred to when no pixel circuit is provided.

[0064] The pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 2 is an equivalent circuit diagram of a pixel circuit. Figure 2 As shown, the pixel circuit may include 6 switch transistors (a first transistor T1, a second transistor T2, a fourth transistor T4 to a seventh transistor T7), a driving transistor T3, a storage capacitor Cst and a number of signal lines (including: a data signal line DT, a scanning signal line GT, an initial signal line INIT1, a first power line PL1, a second power line PL2, a light emitting control line EML, and a first reset control line RST1 and a second reset control line RST2). The light emitting element EL includes a first electrode E1, a second electrode E2 and an organic light emitting layer located between the first electrode E1 and the second electrode E2. For example, the first electrode E1 may be an anode, and the second electrode E2 may be a cathode.

[0065] In some exemplary embodiments, the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. In some exemplary embodiments, the driving transistor and the six switching transistors may be low-temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).

[0066] like Figure 2As shown, the display substrate includes a scan line GT, a data line DT, a first power line PL1, a second power line PL2, a light emitting control line EML, an initial signal line INIT1, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GT is configured to provide a scan signal SCAN to the pixel circuit, the data line DT is configured to provide a data signal DATA to the pixel circuit, the light emitting control line EML is configured to provide a light emitting control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide a scan signal SCAN to the pixel circuit. For example, in a row of pixel circuits, the second reset control line RST2 can be connected to the scan line GT to input the scan signal SCAN. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 may be input with the second reset control signal RESET2.

[0067] In some exemplary embodiments, Figure 2As shown, the driving transistor T3 is electrically connected to the light emitting element EL, and outputs a driving current under the control of the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals to drive the light emitting element EL to emit light. The gate of the data writing transistor T4 is connected to the scanning line GT, the first electrode of the data writing transistor T4 is connected to the data line DT, and the second electrode of the data writing transistor T4 is connected to the first electrode of the driving transistor T3. The gate of the threshold compensation transistor T2 is connected to the scanning line GT, the first electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is connected to the second electrode of the driving transistor T3. The gate of the first light emission control transistor T5 is connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is connected to the first power line PL1, and the second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T3. The gate of the second light emission control transistor T6 is connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode of the second light emission control transistor T6 is connected to the first electrode E1 of the light emitting element EL. The first reset transistor T1 is connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is connected to the first electrode E1 of the light emitting element EL and is configured to reset the first electrode E1 of the light emitting element EL. The gate of the first reset transistor T1 is connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is connected to the first initial signal line INIT1, and the second electrode of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element EL. The first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is connected to the first power line PL1. In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6, and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0068] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a first display area of ​​a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. Figure 3As shown, on a plane perpendicular to the display substrate, the display substrate may include a pixel circuit layer 41 (or driving circuit layer) disposed on a substrate 10, a light emitting device 42 disposed on a side of the pixel circuit layer 41 away from the substrate 10, and a packaging structure layer 50 disposed on a side of the light emitting device 42 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.

[0069] The technical solution of the embodiment of the present disclosure is explained below by showing the preparation process of the substrate.

[0070] The "patterning process" mentioned in the present disclosure includes the processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes the processes of coating organic materials, mask exposure and development, etc. for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.

[0071] The exemplary display substrate described below includes a base and a light emitting structure layer, wherein the light emitting structure layer includes a pixel circuit layer and a light emitting device.

[0072] (1) Preparing a substrate 10 on a glass carrier. In some exemplary embodiments, the preparation process may include:

[0073] A layer of transparent material is coated on the glass carrier, cured into a film, and a first material layer is formed to complete the preparation of the substrate 10. In some examples, the thickness of the first material layer can range from 5 micrometers (μm) to 20 μm. In some examples, the transparent material can be transparent polyimide (CPI). In addition to using a glass carrier, the carrier in other embodiments can also be made of plastic.

[0074] (2) Preparing a pixel circuit layer pattern on the substrate 10. In an exemplary embodiment, preparing a pixel circuit layer pattern on the substrate 10 may include:

[0075] like Figure 4 As shown, a first insulating film is deposited on a substrate 10 by chemical vapor deposition (PECVD) to form a first insulating layer 11 covering the substrate 10, a semiconductor film is deposited on the first insulating layer 11, and the semiconductor film is patterned by a patterning process to form a semiconductor layer pattern disposed on the first insulating layer 11, wherein the semiconductor layer pattern at least includes an active layer 12 located in each sub-pixel and a first wiring layer 13 that is doped and conductorized. When the semiconductor film is patterned by a patterning process, the first wiring layer 13 is formed into an opening (e.g., a hole-shaped) structure pattern. FIG5 is a schematic diagram of an opening structure, and the shape of the opening can be circular (e.g., Figure 5A ) or can be a polygon (as Figure 5B As shown), the optical transmittance of the first wiring layer 13 can be improved. The wiring in the first wiring layer includes but is not limited to reset control lines (first reset control line RST1 and second reset control line RST2), scanning signal lines GT and light emission control lines EML.

[0076] The semiconductor thin film material may be polycrystalline silicon, amorphous silicon or metal oxide.

[0077] Subsequently, the second insulating film and the first metal film are deposited in sequence, and the first metal film is patterned by a patterning process to form a second insulating layer 14 covering the semiconductor layer pattern, and a first metal layer pattern arranged on the second insulating layer 14, wherein the first metal layer pattern at least includes a gate electrode 15, a first capacitor electrode 16, and a second wiring layer (not shown) located in a sub-pixel. When the first metal film is patterned by a patterning process, the first capacitor electrode 16 and the second wiring layer are formed into an opening structure pattern to improve the optical transmittance of the first capacitor electrode 16 and the second wiring layer. In the present embodiment, the opening on the first capacitor electrode 16 corresponds to the opening in the first wiring layer 13, that is, the orthographic projection of the opening at the substrate at least partially overlaps. The wiring in the second wiring layer includes but is not limited to the initial signal line INIT1.

[0078] The second insulating film material may be SiO2, Al2O3, SiNx, etc. The second insulating layer 14 is an inorganic film layer with high transmittance.

[0079] Subsequently, a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 17 covering the first metal layer, and a second metal layer pattern disposed on the third insulating layer 17, wherein the second metal layer pattern includes at least a second capacitor electrode 18 and a third wiring layer (not shown in the figure) located in each sub-pixel, and an orthographic projection of the second capacitor electrode 18 on the substrate overlaps with an orthographic projection of the first capacitor electrode 16 on the substrate. Figure 4 As shown. When the second metal film is patterned by a patterning process, the second capacitor electrode 18 and the third wiring layer form an opening structure pattern to improve the optical transmittance of the second capacitor electrode 18 and the third wiring layer. In this embodiment, the opening on the second capacitor electrode 18 corresponds to the opening on the first capacitor electrode 16 and the opening in the first wiring layer 13, that is, the orthographic projection of the opening on the substrate at least partially overlaps. The wiring in the third wiring layer includes but is not limited to the data signal line DT and the power line (the first power line PL1, the second power line PL2).

[0080] Among them, the active layer 12, the first capacitor electrode 16, the second wiring layer, the second capacitor electrode 18 and the third wiring layer can be patterned with opening structures when preparing each layer respectively to improve the optical transmittance of each layer, or the opening structures can be patterned uniformly through a deep hole etching process after forming the second metal film to improve the optical transmittance of these film layers.

[0081] The third insulating film material may be SiO2, Al2O3, SiNx, etc. The third insulating layer 17 is an inorganic film layer with high transmittance.

[0082] Subsequently, a fourth insulating film is deposited, and a plurality of first via hole patterns are formed by a patterning process, and the fourth insulating layer 19, the third insulating layer 17, and the second insulating layer 14 in the first via holes are etched away to expose the two ends of the active layer. The fourth insulating film material can be materials such as SiO2, Al2O3, SiNx, etc. The fourth insulating layer 19 is an inorganic film layer with high transmittance.

[0083] Subsequently, a third metal film is deposited and patterned by a patterning process to form a third metal layer pattern on the fourth insulating layer 19. The third metal layer pattern includes at least a source electrode 20, a drain electrode 21 and a fourth wiring layer 22 located in the sub-pixel. The source electrode 20 and the drain electrode 21 are connected to the active layer through the first via hole, respectively. Figure 6When the third metal film is patterned by a patterning process, an opening is formed in the fourth wiring layer 22 to improve the optical transmittance of the fourth wiring layer.

[0084] Subsequently, a flat film is coated and patterned by a patterning process to form a flat layer 23 (PLN), on which a second via hole is formed, and the flat layer in the second via hole is removed to expose the drain electrode in each sub-pixel. The flat layer is an organic or inorganic film layer with high transmittance.

[0085] At this point, the pattern of the pixel circuit layer 41 is completed on the substrate 10. In an exemplary embodiment, the active layer, the gate electrode, the source electrode and the drain electrode constitute the first transistor 401, and the first capacitor electrode and the second capacitor electrode constitute the storage capacitor 402. In an exemplary embodiment, the first transistor 401 can be a driving transistor in a pixel driving circuit, and the driving transistor can be a thin film transistor (TFT for short).

[0086] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer and the third insulating layer may be called a gate insulating (GI) layer, and the fourth insulating layer may be called an interlayer insulating (ILD) layer. The first metal film, the second metal film and the third metal film may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The active layer film can be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0087] (3) Preparing a light-emitting device on the substrate having the aforementioned pattern formed thereon. In an exemplary embodiment, preparing a light-emitting device on the substrate having the aforementioned pattern formed thereon may include:

[0088] A transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the transparent conductive film is patterned by a patterning process to form an anode pattern, wherein the anode pattern at least includes an anode 24 (i.e., the aforementioned first electrode E1) located in each sub-pixel, and the anode 24 is connected to the drain electrode 21 of the first transistor 401 through a second via hole. When the transparent conductive film is patterned by a patterning process, the anode 24 is formed into a hole-shaped structure pattern to improve the optical transmittance of the anode, such as Figure 7 shown.

[0089] Subsequently, a pixel definition film is coated and patterned by a patterning process to form a pixel definition layer (PDL) 25. The pixel definition layer 25 has a pixel opening formed in each sub-pixel. The pixel definition layer in the pixel opening is removed to expose the surface of the anode 24. Figure 7 shown.

[0090] Subsequently, an organic light-emitting layer 26 and a cathode 27 (ie, the aforementioned second electrode E2) are formed in sequence, the organic light-emitting layer is connected to the anode in the pixel opening, and the cathode is connected to the organic light-emitting layer. Figure 8 shown.

[0091] The cathode can be a whole semi-transparent metal layer or a patterned semi-transparent metal layer. The transmittance of the semi-transparent cathode can reach 45%. By forming an induced anti-reflection layer 28 on the cathode surface, the reflectivity of the cathode surface to light can be reduced, and the optical transmittance of the cathode can be further improved. The thickness of the induced anti-reflection layer is 30nm-500nm (nanometers), and the film layer can be selected from SiO2, Al2O3 or a stacked combination of the two. The induced anti-reflection film achieves the effect of induced anti-reflection on the cathode. Fig. 9 As shown. Fig. 9 It can be clearly seen that after adding a 60nm SiO2 induced anti-reflection layer or a 50nm Al2O3 induced anti-reflection layer, the light transmittance is significantly improved.

[0092] In an exemplary embodiment, the light emitting layers of the light emitting devices 42 of different colors are different. For example, the red light emitting element includes a red light emitting layer, the green light emitting element includes a green light emitting layer, and the blue light emitting element includes a blue light emitting layer.

[0093] In an exemplary embodiment, the transparent conductive film may include indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc. The cathode may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

[0094] Through the above process, the preparation of the display substrate including the base and the light-emitting structure layer is completed.

[0095] In an exemplary embodiment, an encapsulation structure layer may be prepared on the light-emitting structure layer. The encapsulation structure layer may include one or more of the following: an inorganic encapsulation layer, an organic encapsulation layer, and a stacked structure of an inorganic encapsulation layer and an organic encapsulation layer. The inorganic encapsulation layer material may include silicon nitride, silicon oxide, silicon oxynitride or aluminum oxide, etc., and the thickness may be about 2000 angstroms to 12000 angstroms. The organic encapsulation layer material may include acrylate or epoxy, etc., and the thickness may be about 1.0 μm to 8.0 μm. The inorganic encapsulation layer may be formed by deposition, and the organic encapsulation layer may be formed by inkjet or coating.

[0096] The structure and preparation process shown in this embodiment are merely exemplary. In actual implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the OLED display substrate can be not only a top emission structure but also a bottom emission structure. For another example, the thin film transistor can be not only a top gate structure but also a bottom gate structure, not only a double gate structure but also a single gate structure. For another example, the thin film transistor can be an amorphous silicon (a-Si) thin film transistor, a low temperature polycrystalline silicon (LTPS) thin film transistor or an oxide thin film transistor, and other electrodes, leads and structural film layers can also be provided in the driving structure layer and the light emitting structure layer, which are not limited in the embodiments disclosed herein.

[0097] The above exemplary embodiments are described by taking the upper and lower metal electrode plates in the capacitor area, the metal electrode wiring area and the OLED anode area as an example, that is, the TFT area is opaque, and the capacitor area and the OLED light-emitting area are transmissive. In other embodiments, only the upper and lower metal electrode plates in the capacitor area and the metal electrode wiring area may be patterned with opening structures. Fig. 10A The schematic diagram shows that the TFT area and the OLED light-emitting area are opaque, and the capacitor area is transparent. In other embodiments, the active layer, gate electrode, source electrode, and drain electrode of the TFT may be patterned with opening structures to improve the optical transmittance of the substrate without affecting the TFT characteristics. Fig. 10B The diagram shows that the TFT region, the capacitor region, and the OLED light-emitting region are all light-transmissive.

[0098] From the structure and preparation process of the display substrate described above, it can be seen that the embodiment of the present disclosure designs metal opening patterning for the anode metal, the metal electrode in the capacitor area, and the metal electrode routing on the OLED display panel of the under-screen camera, and makes a cathode induced anti-reflection film above the cathode electrode of the OLED display panel, thereby improving the optical transmittance of the panel in the under-screen camera area without reducing the resolution of the OLED display panel in the under-screen camera area, thereby achieving the effect of high-resolution display and light-transmitting imaging of the under-screen camera. The preparation process of the display substrate of the exemplary embodiment of the present disclosure has good process compatibility, does not require additional masks, is simple to implement, easy to implement, has high production efficiency, and low production cost.

[0099] Based on the technical concept of the embodiment of the present disclosure, the embodiment of the present disclosure also provides a method for preparing a display substrate. The display substrate shown includes a first display area and a second display area, and the first display area is located on at least one side of the second display area; the method for preparing the display substrate of this embodiment includes:

[0100] A light emitting structure layer is formed on a substrate, wherein the light emitting structure layer comprises a plurality of conductive layers, and at least one of the conductive layers is provided with a plurality of openings penetrating the conductive layer.

[0101] In an exemplary embodiment, forming a light emitting structure layer on a substrate includes:

[0102] A first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, a third metal layer, a planar layer, and a conductive layer are sequentially stacked on the substrate;

[0103] Wherein: the semiconductor layer includes an active layer and a first wiring layer, the first metal layer includes a gate electrode, a first capacitor electrode and a second wiring layer, the second metal layer includes a second capacitor electrode and a third wiring layer, the third metal layer includes a source electrode, a drain electrode and a fourth wiring layer, and the conductive layer includes an anode;

[0104] One or more of the active layer, the first wiring layer, the gate electrode, the first capacitor electrode, the second wiring layer, the second capacitor electrode, the third wiring layer, the source electrode, the drain electrode, the fourth wiring layer and the anode are provided with the opening.

[0105] In an exemplary embodiment, a plurality of the conductive layers are provided with the openings, the orthographic projections of the plurality of conductive layers on the substrate have an overlapping area, and the openings of the plurality of conductive layers overlap in the orthographic projections of the overlapping area.

[0106] In an exemplary embodiment, the light emitting structure layer further comprises a cathode, and an induced anti-reflection layer is disposed on a surface of the cathode away from the substrate. The induced anti-reflection layer is made of any one or more of silicon dioxide SiO2 and aluminum oxide Al2O3, and has a thickness of 30-500 nanometers.

[0107] In this embodiment, the structure, materials, related parameters and detailed preparation process of the membrane layer have been described in detail in the previous embodiments and will not be repeated here.

[0108] This embodiment provides a method for preparing a display substrate. By providing openings penetrating the conductive layer in one or more conductive layers, the optical transmittance of the film layer can be increased, thereby increasing the transmittance of the display panel in the camera area under the screen without reducing the resolution of the display panel. The preparation method of this embodiment can be implemented using existing mature preparation equipment, with little improvement on the existing process, and can be well compatible with the existing preparation process, so it has the advantages of low production cost, easy process implementation, high production efficiency and high yield rate.

[0109] Based on the technical concept of the embodiment of the present disclosure, the embodiment of the present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0110] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: It includes a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; the first display area includes: a substrate, a light-emitting structure layer arranged on the substrate, the light-emitting structure layer includes multiple conductive layers, the light-emitting structure layer includes a TFT area, a capacitor area and an OLED light-emitting area, and at least one of the conductive layers in the TFT area, the capacitor area and the OLED light-emitting area is provided with multiple openings penetrating the conductive layer.

2. The display substrate according to claim 1, characterized in that: The light emitting structure layer includes a first insulating layer arranged on the substrate and a semiconductor layer arranged on the first insulating layer, the semiconductor layer includes an active layer and a first wiring layer, the active layer is provided with a plurality of openings passing through the active layer, and / or the first wiring layer is provided with a plurality of openings passing through the first wiring layer.

3. The display substrate according to claim 1, characterized in that: The light-emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, and a first metal layer which are sequentially stacked on the substrate, the first metal layer includes a gate electrode, a first capacitor electrode and a second wiring layer, wherein one or more of the gate electrode, the first capacitor electrode and the second wiring layer are provided with the openings, the multiple openings in the gate electrode penetrate the gate electrode, the multiple openings in the first capacitor electrode penetrate the first capacitor electrode, and the multiple openings in the second wiring layer penetrate the second wiring layer.

4. The display substrate according to claim 1, characterized in that: The light-emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, and a second metal layer stacked in sequence on the substrate, the second metal layer includes a second capacitor electrode and a third wiring layer, wherein the second capacitor electrode is provided with a plurality of openings passing through the second capacitor electrode, and / or the third wiring layer is provided with a plurality of openings passing through the third wiring layer.

5. The display substrate according to claim 1, characterized in that: The light emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, and a third metal layer which are sequentially stacked on the substrate, the third metal layer includes a source electrode, a drain electrode and a fourth wiring layer, wherein one or more of the source electrode, the drain electrode and the fourth wiring layer are provided with the openings, the multiple openings in the source electrode penetrate the source electrode, the multiple openings in the drain electrode penetrate the drain electrode, and the multiple openings in the fourth wiring layer penetrate the fourth wiring layer.

6. The display substrate according to claim 1, characterized in that: The light emitting structure layer includes a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, a third metal layer, a flat layer, and a conductive layer stacked in sequence on the substrate, wherein the conductive layer includes an anode, wherein the anode is provided with a plurality of openings passing through the anode.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The plurality of conductive layers are provided with the openings, the orthographic projections of the plurality of conductive layers on the substrate have an overlapping area, and the openings of the plurality of conductive layers overlap in the orthographic projections of the overlapping area.

8. The display substrate according to any one of claims 1 to 6, characterized in that: The opening is in a circular or polygonal shape.

9. The display substrate according to claim 1, characterized in that: The light emitting structure layer further comprises a cathode, and an induced anti-reflection layer is arranged on a surface of the cathode away from the substrate.

10. The display substrate according to claim 9, characterized in that: The induced anti-reflection layer is made of any one or more of silicon dioxide SiO2 and aluminum oxide Al2O3, and has a thickness of 30-500 nanometers.

11. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 10.

12. A method for preparing a display substrate, characterized in that: The display substrate includes a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; the preparation method includes: A light-emitting structure layer is formed on a substrate, wherein the light-emitting structure layer includes a plurality of conductive layers, and the light-emitting structure layer includes a TFT region, a capacitor region, and an OLED light-emitting region, and at least one of the conductive layers in the TFT region, the capacitor region, and the OLED light-emitting region is provided with a plurality of openings penetrating the conductive layer.

13. The preparation method according to claim 12, characterized in that: The step of forming a light emitting structure layer on a substrate comprises: A first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, a third metal layer, a planar layer, and a conductive layer are sequentially stacked on the substrate; Wherein: the semiconductor layer includes an active layer and a first wiring layer, the first metal layer includes a gate electrode, a first capacitor electrode and a second wiring layer, the second metal layer includes a second capacitor electrode and a third wiring layer, the third metal layer includes a source electrode, a drain electrode and a fourth wiring layer, and the conductive layer includes an anode; One or more of the active layer, the first wiring layer, the gate electrode, the first capacitor electrode, the second wiring layer, the second capacitor electrode, the third wiring layer, the source electrode, the drain electrode, the fourth wiring layer and the anode are provided with the opening.

14. The preparation method according to claim 13, characterized in that: The plurality of conductive layers are provided with the openings, the orthographic projections of the plurality of conductive layers on the substrate have an overlapping area, and the openings of the plurality of conductive layers overlap in the orthographic projections of the overlapping area.

15. The preparation method according to claim 12, characterized in that: in: The light emitting structure layer also includes a cathode. The surface of the cathode away from the substrate is provided with an induced anti-reflection layer. The induced anti-reflection layer is made of any one or more of silicon dioxide SiO2 and aluminum oxide Al2O3, and has a thickness of 30-500 nanometers.

Images