Semiconductor module and semiconductor device

Abstract

Connection terminals of a semiconductor module are appropriately configured according to a connection object of the semiconductor module. A semiconductor module (1) having at least one semiconductor element (2) is mounted to a first surface (5a) of a main substrate (5) on which a first circuit element (7) is mounted on a first surface (5a) and a second circuit element (6) is mounted on a second surface (5b). A plurality of connection terminals (8) includes a plurality of first connection terminals (81), i.e., a first connection terminal group (T1), which are connected to the first circuit element (7) via the main substrate (5), and a plurality of second connection terminals (82), i.e., a second connection terminal group (T2), which are connected to the second circuit element (6) via the main substrate (5), and the first connection terminal group (T1) is configured on an outer peripheral side more than the second connection terminal group (T2).

Description

Technical Field

[0001] The present invention relates to a semiconductor module having at least one semiconductor element and a semiconductor device having a semiconductor module. Background Technology

[0002] International Publication No. 02 / 103793 discloses a semiconductor module (multi-chip module (MCM)) in which multiple chips (1A, 2B, 3B) such as processors are mounted on one side of a package substrate (1), and solder bumps (11) constituting external connection terminals are arranged on the other side (the reference numerals in parentheses in the background art are reference numerals). Here, considering the wiring distance from the connected object, the external connection terminals are mostly arranged in a group according to the same function (or closely related functions). For example, in this MCM, the address pins (A) and data pins (D) connected to the memory are respectively arranged in a specific area (refer to the international publication). Figure 3 (Figure 40, etc.)

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 02 / 103793 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] The multi-chip module has external connection terminals arranged in a four-ring rectangular configuration, with address pins (A) and data pins (D) arranged from the first ring on the outermost periphery to the fourth ring on the innermost periphery. Therefore, it is difficult to route wiring from all terminals on the substrate surface (mounting surface) where the package substrate (1) is mounted (with the external connection terminals). That is, a portion of the multiple external connection terminals with the same function needs to be routed via vias and using wiring layers on the side opposite to the mounting surface or inner layers.

[0008] The processing speed of microprocessors and other computing devices, as well as the communication speed between microprocessors and peripheral devices, has increased significantly in recent years. Furthermore, the frequency of signals connected to external terminals of multi-chip modules has also increased. These high-frequency signals are prone to reflection when passing through vias, which can cause waveform distortion and reduce transmission reliability. Additionally, vias can lengthen wiring, thus increasing signal delay.

[0009] Given the above background, it is desirable to appropriately configure the connection terminals of the semiconductor module according to the connection objects of the semiconductor module.

[0010] means for solving problems

[0011] In view of the above-described semiconductor module, as one embodiment, a first surface of a main substrate on which a first circuit element is mounted on a first surface and a second circuit element is mounted on a second surface opposite to the first surface is provided, and at least one semiconductor element is provided, wherein a plurality of connection terminals are provided. The plurality of connection terminals are arranged in a rectangular ring on the opposing surface side facing the main substrate and connected to the main substrate. The plurality of connection terminals include a plurality of first connection terminals connected to the first circuit element via the main substrate, namely a first connection terminal group, and a plurality of second connection terminals connected to the second circuit element via the main substrate, namely a second connection terminal group. The first connection terminal group is disposed on the outer periphery side of the second connection terminal group.

[0012] Furthermore, in view of the above-described semiconductor device, as one embodiment, it includes a main substrate, a semiconductor module having at least one semiconductor element mounted on a first side of the main substrate, and a plurality of circuit elements mounted on the main substrate. The circuit elements include a first circuit element mounted on the first side and a second circuit element mounted on a second side opposite to the first side. The semiconductor module includes a plurality of connection terminals arranged in a rectangular ring on an opposing side facing the main substrate and connected to the main substrate. The plurality of connection terminals include a plurality of first connection terminals connected to the first circuit element via the main substrate, i.e., a first connection terminal group, and a plurality of second connection terminals connected to the second circuit element via the main substrate, i.e., a second connection terminal group. The first connection terminal group is disposed on a more peripheral side than the second connection terminal group.

[0013] According to these structures, it is easier to connect the first circuit element and the first connection terminal on the first surface compared to the second connection terminal. That is, since the first circuit element and the semiconductor module are mounted on the first surface, they can be connected on the first surface without having to detour to the second surface via through-holes. Since the second circuit element is mounted on the second surface opposite to the first surface where the semiconductor module is mounted, wiring extending from the second connection terminal is not necessary on the first surface. The second connection terminal can be connected to the connection terminal via through-holes anyway. Therefore, by arranging the plurality of first connection terminals, i.e., the first connection terminal group, further outward than the plurality of second connection terminals, i.e., the second connection terminal group, the circuit element and the semiconductor module can be connected effectively. As described above, according to this structure, the connection terminals of the semiconductor module can be appropriately configured according to the connection target of the semiconductor module.

[0014] Further features and advantages of the semiconductor module and semiconductor device will become apparent from the following description of embodiments with reference to the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a schematic exploded perspective view of a semiconductor device.

[0016] Figure 2 This is a component configuration diagram of a semiconductor module.

[0017] Figure 3 This is a schematic block diagram illustrating an example of a system LSI.

[0018] Figure 4 This is a perspective top view taken from the V direction, showing an example of the terminal configuration of a semiconductor module.

[0019] Figure 5 This is an enlarged perspective top view taken from the V direction, showing an example of the terminal configuration of a semiconductor module.

[0020] Figure 6 This is an explanatory diagram illustrating the principle of differential transmission.

[0021] Figure 7 This diagram illustrates an example of the wiring for a pair of signals being transmitted differentially.

[0022] Figure 8 This is a diagram illustrating another example of wiring for a pair of signals being transmitted differentially.

[0023] Figure 9 This is a cross-sectional view showing an example of a semiconductor device.

[0024] Figure 10 This is a top view from the V direction showing an example of the pads and wiring pattern on the first side of the main substrate.

[0025] Figure 11 This is a perspective view taken from the V direction, showing an example of the wiring pattern on the second side of the main substrate.

[0026] Figure 12 This is a top view from the V direction showing another example of the pads and wiring pattern on the first side of the main substrate.

[0027] Figure 13 This is a perspective view taken from the V direction, showing another example of the wiring pattern on the second side of the main substrate. Detailed Implementation

[0028] The following describes an embodiment of the semiconductor device based on the accompanying drawings. This semiconductor device, for example, is mounted in a vehicle and can be used as an Electronic Control Unit (ECU) to control in-vehicle information equipment. Of course, the applications of the semiconductor device are not limited to this.

[0029] like Figure 1As shown in the schematic exploded perspective view, the semiconductor device 10 is configured to include: a main substrate 5; a semiconductor module 1 having at least one system LSI2 (semiconductor element, processor) and mounted on a first surface (first surface 5a) of the main substrate 5; and a plurality of circuit elements 50 mounted on the main substrate 5. Here, the circuit elements 50 include a first circuit element 7 mounted on the first surface 5a of the main substrate and a second circuit element 6 mounted on a second surface 5b of the main substrate opposite to the first surface 5a. The semiconductor module 1 includes a system LSI2, a memory 3 cooperating with the system LSI2, the system LSI2, and a module substrate 4 on which the memory 3 is mounted. In this embodiment, as... Figure 2 As shown in the component configuration diagram, the System on a Chip (SoC) as System LSI2 and two Synchronous Dynamic Random Access Memory (SDRAM) modules as Memory 3 are mounted on the module substrate 4. The SDRAM is preferably, for example, DDR3 (Double Data Rate 3) SDRAM, DDR4 (Double Data Rate 4) SDRAM, etc.

[0030] Here, a System-on-a-Chip (SoC) is shown as System LSI2, but System LSI2 can also be a System in a Package (SiP). Furthermore, the SoC also includes Application-Specific Integrated Circuits (ASICs) with semi-custom LSIs, Application-Specific Standard Processors (ASSPs) with general-purpose LSIs, etc. Additionally, ASICs are not limited to gate arrays or cell-based ICs (standard cells), but also include Programmable Logic Devices (PLDs) such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Arrays (PLAs). Also, here, SDRAM is shown as memory 3, but this does not preclude it from being other memory structures such as Flash Memory (Flash Memory) or Static Random Access Memory (SRAM).

[0031] Figure 3 A schematic block diagram illustrates an example of a system LSI2. For example... Figure 3As shown, the system LSI2 has functional blocks including CPU core 22, GPU core 23, Audio DSP 24, Synchronous Dynamic Random Access Memory Interface (SDRAM I / F) 21, Sound Routing Unit (SRU) 30, Display I / F 27, Video Capture 28, USB 3.0 Host 29, Image Recognition Engine 25, CAN (Control Area Network) 32, Serial ATA 31, and Video Accelerator 26.

[0032] CPU core 22 is a computing unit that includes a central processing unit (CPU) that serves as the core of the system LSI2. GPU core 27 is a computing unit that includes a graphics processing unit (GPU) that serves as the core for image-related computations. Memory interface 21 is a functional unit that serves as an interface when the system LSI2 writes data to SDRAM, which serves as memory 3, reads data from SDRAM, and refreshes the data stored in SDRAM.

[0033] The audio DSP24 is a digital signal processor (DSP) that decodes audio data composed of various compression and storage formats. The sound routing unit 30 is a computing unit used to realize sound effects such as surround sound reproduction through the audio codec device 101 and the speaker 102, and to receive audio information such as sound input to the microphone 103 through the audio codec device 101.

[0034] The video capture 28 is, for example, a processing unit that acquires images captured by the vehicle-mounted camera 104. The image recognition engine 25 is a processing unit that includes an image signal processor (ISP) for performing image recognition based on the images captured by the vehicle-mounted camera 104 acquired by the video capture 28. The video accelerator 26 is a processing unit that includes an ISP for decoding animation data composed of various compression formats and storage formats. The display interface 27 is, for example, a processing unit that outputs the images captured by the vehicle-mounted camera 104 acquired by the video capture 28 and the images decoded by the video accelerator 26, depending on the display mode of the display 107 in the vehicle compartment. Based on the recognition results of the image recognition engine 25, various information (text, symbols, etc.) can also be superimposed on the images captured by the vehicle-mounted camera 104 to partially emphasize the image.

[0035] USB host 29 is a processing unit that serves as an interface for connecting various user-carried USB compatible devices 109, such as portable audio devices, smartphones, and digital cameras. Serial port ATA 31 is a processing unit that serves as an interface with hard disk drive (HDD) 105 and DVD optical disc drive (DVD) 106. CAN 32 is a processing unit that serves as an interface for in-vehicle communication via the in-vehicle CAN transceiver 108.

[0036] The aforementioned CPU core 22, GPU core 23, DSP, ISP, etc., cooperate with memory 3 when performing their respective computational processing. Semiconductor module 1 is constituted as a multi-chip module having system LSI 2, memory 3 cooperating with the system LSI, and a module substrate 4 on which they are mounted. Figure 1 As shown, the system LSI2 and memory 3 are mounted on one side of the module substrate 4 of the semiconductor module 1, namely the first surface 4a of the module substrate. Additionally, as... Figure 4 , Figure 5 , Figure 9 As shown, a plurality of hemispherical connection terminals 8 (module terminals) connected to the main substrate 5 are regularly arranged on the substrate surface of the module substrate 4 on the other side, namely the second surface 4b of the module substrate (the facing surface opposite to the main substrate 5). As will be explained in detail later, the connection terminals 8 are arranged in a multi-circle rectangular ring. The connection terminals 8 include signal terminals for transmitting signals and power terminals for transmitting electricity. It should be noted that "signal terminals" include "input terminals," "output terminals," and "bidirectional terminals (input / output terminals)."

[0037] Furthermore, the system LSI2 is configured as multiple functional blocks as described above, and the semiconductor module 1, as a multi-chip module, also has multiple functional blocks. For example... Figure 3As shown, each functional block collaborates with a specific circuit or device. Therefore, each functional block is connected to a specific circuit, device, or device's interface circuit (receiver, driver) or connector via connection terminal 8. Figure 1 The circuit element 50 shown corresponds to these specific circuits, devices, interface circuits, and connectors. Figure 1 In the example, an integrated circuit is used as the first circuit element 7 and the second circuit element 6 as circuit element 50, but of course, the circuit element 50 is not limited to a single integrated circuit, but can also be a circuit composed of multiple circuit components.

[0038] Taking into account the location of the circuit element 50 to be connected and the wiring distance from the circuit element 50, the connection terminals 8 arranged on the semiconductor module 1 are centrally arranged according to the same function (closely related functions). Figure 4 This shows the direction V (referring to) orthogonal to the substrate surface of the main substrate 5. Figure 1 A perspective top view of an example of the terminal configuration of semiconductor module 1, viewed from the V direction. Figure 5 This is an enlarged perspective top view taken from the V direction, showing an example of the terminal configuration of semiconductor module 1. (See attached image.) Figure 4 As shown, the plurality of connection terminals 8 include a plurality of first connection terminals 81, i.e., a first connection terminal group T1, connected to the first circuit element 7 via the main substrate 5, and a plurality of second connection terminals 82, i.e., a second connection terminal group T2, connected to the second circuit element 6 via the main substrate 5. Figure 4 As shown, within the connecting terminals 8 arranged in a multi-ring rectangular configuration, the first connecting terminal group T1 is positioned further outward than the second connecting terminal group T2. It should be noted that only a portion of the first connecting terminal group T1 needs to be positioned further outward than the entire second connecting terminal group T2. For example, as... Figure 4 As shown, it is also possible that a portion of the first connection terminal group T1 and a portion of the second connection terminal group T2 both include terminals on the third periphery from the outer periphery (see reference). Figure 5 The method of the third annular connection terminal 8c described later.

[0039] like Figure 4 and Figure 5 As shown, the various connecting terminals 8 arranged in a rectangular ring generally belong to three groups. The connecting terminals 8 arranged on the outermost three circumferences are called outer peripheral ring connecting terminals 9a. When distinguishing the connecting terminals 8 that span the three circumferences of the outer peripheral ring connecting terminals 9a, they are referred to as "first ring connecting terminal 8a", "second ring connecting terminal 8b", and "third ring connecting terminal 8c" in order from the outer periphery to the inner periphery. Here, the first ring connecting terminal 8a is the "outermost ring connecting terminal" arranged on the outermost circumference among the multiple connecting terminals 8 arranged in a rectangular ring.

[0040] The connecting terminals 8 arranged on both sides of the inner periphery of the outer peripheral annular connecting terminal 9a are called inner peripheral annular connecting terminals 9b, and there is a gap between the outer peripheral annular connecting terminals 9a and the inner peripheral annular connecting terminals 9b corresponding to a row of connecting terminals 8. When distinguishing the connecting terminals 8 of each periphery of the inner peripheral annular connecting terminals 9b arranged across both periphery, they are sequentially referred to as "fourth annular connecting terminal 8d" and "fifth annular connecting terminal 8e" in order from the outer periphery to the inner periphery.

[0041] Inside the inner peripheral annular connecting terminal 9b, four connecting terminals 8 arranged in a grid pattern with symmetrical rotation four times are called inner peripheral grid connecting terminals 9c. There is a gap between the inner peripheral annular connecting terminal 9b and the inner peripheral grid connecting terminal 9c corresponding to a row of connecting terminals 8. It should be noted that symmetrical rotation four times (four-fold symmetry, four-sided symmetry, 90-degree symmetry) means that the shape remains consistent each time it rotates 90 degrees with respect to the symmetry point P2. Furthermore, the symmetry point P2 corresponds to the center of gravity of the semiconductor module 1 (module substrate 4) when viewed from the V direction. The connecting terminals 8 of the four inner peripheral grid connecting terminals 9c are respectively referred to as "first grid connecting terminal 91", "second grid connecting terminal 92", "third grid connecting terminal 93", and "fourth grid connecting terminal 94".

[0042] As described above, the first connection terminal group T1 is positioned further outward than the second connection terminal group T2. Here, the first connection terminal 81 included in the first connection terminal group T1 is a connection terminal 8 that transmits higher frequency signals compared to the second connection terminal 82 included in the second connection terminal group T2. Furthermore, in most cases, the first connection terminal 81 is a connection terminal 8 that transmits information via a pair of differential signals (information is transmitted via differential transmission).

[0043] For example, there are cases where a vehicle-mounted camera 104 and a video capture 28, capable of outputting image signals at a high resolution of 4 megapixels or higher at 30 frames per second or higher, are connected via differential signals. Additionally, a display interface 27 and a display 107, which output image signals at a high resolution of Full HD (1920 pixels × 1080 pixels) or higher, are often connected via the High-Definition Multimedia Interface (HDMI) standard, which transmits information via differential signals. Furthermore, a USB host 29 and various USB-compatible devices 109 also transmit information via differential signals. The connection terminals 8 used for these connections are connection terminals 8 for transmitting high-frequency signals, and are connection terminals 8 that transmit signals via a pair of differential signals.

[0044] On the other hand, the transmission speed of the signal between the audio routing unit 30 and the audio codec device 101, and the transmission speed of the signal between the CAN 32 and the CAN transceiver 108, are slower and lower frequency than the aforementioned image signals and video signals. In addition, these signals, in most cases, transmit one piece of information using a transmission method called "single-ended transmission" that uses a single signal line, rather than transmitting one piece of information using a pair of differential signals.

[0045] Figure 6 The principle of differential transmission is shown. Figure 7 and Figure 8 An example of wiring for a pair of signals in differential transmission is shown. For example... Figure 6 As shown, in differential transmission, the driver DR on the transmitting signal side and the receiver RE on the receiving signal side are connected via a pair of differential signals, a positive signal Sp and a negative signal Sn. The logic of the positive signal Sp and the negative signal Sn is inverted. The receiver RE is configured, for example, to have a differential amplifier, subtracting the negative signal Sn from the positive signal Sp and outputting a differential output Sd. As a result, the waveform height A3 (amplitude = A3 / 2) of the differential output Sd is the sum of the waveform height A1 (amplitude = A1 / 2) of the positive signal Sp and the waveform height A2 (amplitude = A2 / 2) of the negative signal Sn. That is, even when transmitting signals with a low power supply voltage, a large waveform height (amplitude) relative to that power supply voltage can be ensured, thereby increasing the tolerance to external noise. In addition, even when common-mode noise is superimposed on the positive signal Sp and the negative signal Sn, the common-mode noise can be canceled by subtracting it from the positive signal Sp during differential amplification by the receiver RE.

[0046] Furthermore, in typical single-ended signal transmission using Complementary Metal-Oxide-Semiconductor (CMOS) devices, a shoot-through current flows during logic state changes, thus increasing current consumption with higher frequencies (more logic changes). However, in differential transmission, in one logic state, current flows from the upper segment of the CMOS element outputting a positive signal Sp through the terminating resistor TM to the lower segment of the CMOS element outputting a negative signal Sn; in another logic state, current flows from the upper segment of the CMOS element outputting a negative signal Sn through the terminating resistor TM to the lower segment of the CMOS element outputting a positive signal Sp. Therefore, in differential transmission, no shoot-through current flows during logic state changes as in single-ended signal transmission. Consequently, even with higher signal frequencies, the increase in current consumption can be suppressed.

[0047] Furthermore, compared to single-ended transmission, differential transmission eliminates the flow of this through-current and, with the terminating resistor TM configured as described above, suppresses waveform interference such as ringing, overshoot, and undershoot at signal change points. Moreover, since no through-current flows (resulting in relatively low energy) and there is less waveform interference (making harmonics less likely to occur), unnecessary radiation is also suppressed.

[0048] This differential transmission is a low-power transmission method with high noise immunity, suitable for high-frequency and high-current high-speed signal transmission.

[0049] However, in differential transmission, since information is transmitted through the differential of two signals, the signal delays of the positive signal Sp and the negative signal Sn must be equal. In high-frequency signal transmission, transmission on a substrate such as the main substrate 5 also requires consideration of distributed constant circuitry rather than lumped constant circuitry. Therefore, a terminating resistor TM is configured between the positive signal Sp and the negative signal Sn to suppress signal reflection, and the transmission path (signal wiring) length is made equal to achieve equal delay between the positive signal Sp and the negative signal Sn.

[0050] For example, such as Figure 7 As shown, the positive signal routing Wp from the first pad Ldrp on the driver side via the first resistor pad Ltm1 of the terminating resistor TM to the first pad Lrep on the receiver side and the negative signal routing Wn from the second pad Ldrn on the driver side via the second resistor pad Ltm2 of the terminating resistor TM to the second pad Lren on the receiver side are formed to have nearly the same shape or to have symmetrical routing.

[0051] exist Figure 7 In the circuit, the distance between the first pad Ldrp on the driver side and the first pad Larep on the receiver side is approximately the same as the distance between the second pad Ldrn on the driver side and the second pad Lren on the receiver side, but their distances may vary depending on the configuration of the circuit element 50. In this case, such as... Figure 8 As shown, the wiring is adjusted in such a way that the negative signal wiring Wn is detoured to become the same wiring length as the positive signal wiring Wp (equal length wiring).

[0052] Furthermore, although the illustrations are omitted, it is best to avoid the following routing methods: mounting positive signal traces Wp and negative signal traces Wn in shapes (paths) that significantly disrupt the symmetry between them, instead of fine-tuning like equal-length traces; bending traces at angles less than right angles; and routing via vias. In particular, bending traces at angles less than right angles and routing via vias cause signal reflections at these locations, resulting in signal waveform disturbance. Therefore, differentially transmitted signals are preferably transmitted in a straight line on a substrate surface, rather than vias.

[0053] It is known that when wiring signals unsuitable for differential transmission as described above, the eye diagram becomes susceptible to interference, resulting in a decrease in communication quality (transmission quality). In particular, the size (area) of the eye diagram decreases during high-speed signal transmission compared to constant-speed signal transmission. Therefore, even with the same degree of signal delay, the eye diagram is more susceptible to interference during high-speed signal transmission because the proportion of deviation relative to its size (area) is larger.

[0054] Figure 9 A schematic cross-sectional view of the semiconductor device 10 is shown. A first annular connection terminal 8a is connected to a first annular pad L8a, a second annular connection terminal 8b is connected to a second annular pad L8b, a third annular connection terminal 8c is connected to a third annular pad L8c, a fourth annular connection terminal 8d is connected to a fourth annular pad L8d, and a fifth annular connection terminal 8e is connected to a fifth annular pad L8e.

[0055] The first circuit element 7, mounted together with the semiconductor module 1 on the first surface 5a of the main substrate, is a circuit element 50 that transmits signals between itself and the semiconductor module 1 via differential transmission. The first circuit element terminal 7T of the first circuit element 7 is an input or output terminal for the differential signal and is connected to the first circuit element pad L7. The second circuit element 6, mounted on the second surface 5b of the main substrate, is a circuit element 50 that transmits signals via single-ended transmission instead of differential transmission. The second circuit element terminal 6T of the second circuit element 6 is an input or output terminal for single-ended transmission signals and is connected to the second circuit element pad L6.

[0056] like Figure 9 As shown, the first circuit element pad L7, which is connected to the first circuit element terminal 7T of the differential signal, is connected to the first annular pad L8a on the first surface 5a of the main substrate via the first wiring W1. On the other hand, the second circuit element pad L6, which is connected to the second circuit element terminal 6T of the single-ended transmission signal, is connected to the fourth annular pad L8d via the second wiring W2 and the via TH. That is, the first circuit element terminal 7T and the first annular connection terminal 8a are connected on the same substrate surface (the first surface 5a of the main substrate) instead of being connected via the via TH. Conversely, the second circuit element terminal 6T and the fourth annular connection terminal 8d are connected via the via TH through different substrate surfaces (the first surface 5a and the second surface 5b of the main substrate).

[0057] The connection terminals 8 of the semiconductor module 1 are disposed on the opposing surface of the main substrate, namely the second surface 4b of the module substrate, which faces the first surface 5a of the main substrate, and all the connection terminals 8 are connected to the first surface 5a of the main substrate. Therefore, in order to connect the first circuit element 7 and the semiconductor module 1 on the same substrate surface (here, the first surface 5a of the main substrate), it is preferable that the first connection terminal 81 to be connected is disposed further outward in the rectangular ring-shaped connection terminals 8. Figure 4 and Figure 5 As shown, the outermost connecting terminal, i.e., the first annular connecting terminal 8a, is assigned to the first connecting terminal 81. In other words, the outermost connecting terminal, i.e., the first annular connecting terminal 8a, is included in the plurality of first connecting terminals 81, i.e., the first connecting terminal group T1.

[0058] Since the second connection terminal 82 is a terminal that can be connected via the through-hole TH without issue, if the first annular connection terminal 8a is assigned to the second connection terminal 82, it may be impossible to assign high-frequency signals such as differential signals to the corresponding portion of the first annular connection terminal 8a. Therefore, it is preferable not to assign the first annular connection terminal 8a to the second connection terminal 82. Figure 4 and Figure 5 As shown, the outermost connecting terminal, i.e., the first annular connecting terminal 8a, is not included in the multiple second connecting terminals 82, i.e., the second connecting terminal group T2.

[0059] The following is an example of wiring and an explanation. Figure 10 and Figure 12 This is a top view from the V direction showing an example of the pattern of the pads of the connection terminal 8 and the signal wiring W formed on the first surface 5a of the main substrate. Figure 11 and Figure 13 This is a perspective top view taken from the V direction, showing an example of the pattern of the signal wiring W on the second surface 5b of the main substrate. For easy comparison with the first surface 5a of the main substrate, the pads of the connection terminals 8 formed on the first surface 5a of the main substrate are shown by dashed lines. Figure 10 and Figure 11 This illustrates an implementation where up to two signal traces can pass between the pads of adjacent connection terminals 8. Figure 12 and Figure 13 An embodiment is shown in which a maximum of one signal trace can be routed between the pads of adjacent connection terminals 8. Since the connection terminals 8 are connected to the pads formed on the first surface 5a of the main substrate, "signal traces can be routed between the pads of adjacent connection terminals 8 on the first surface 5a of the main substrate" is synonymous with "signal traces can be routed between adjacent connection terminals 8 on the first surface 5a of the main substrate".

[0060] like Figure 10As shown, when two signal traces W can pass between adjacent connection terminals 8, a first trace W1 that can be connected to the first circuit element 7 can be led out from the first annular pad L8a, the second annular pad L8b, and the third annular pad L8c only through the first surface 5a of the main substrate. Therefore, the first annular connection terminal 8a, the second annular connection terminal 8b, and the third annular connection terminal 8c can be assigned to the first connection terminal 81.

[0061] Without the first wiring W1 from the second annular pad L8b and the third annular pad L8c, the signal lines of the fourth annular pad L8d, the fifth annular pad L8e, and the grid pad L9c connected to the inner peripheral grid connection terminal 9c can be led out from the first surface 5a of the main substrate. However, it is not necessary to lead out the first wiring W1 from the fourth annular pad L8d, the fifth annular pad L8e, and the grid pad L9c. Figure 11 As shown, a second wiring W2 can be formed on the second surface 5b of the main substrate from these pads via through-holes TH. Therefore, it is preferable that the fourth annular connection terminal 8d, the fifth annular connection terminal 8e, and the inner peripheral grid-like connection terminal 9c are assigned to the second connection terminal 82.

[0062] like Figure 12 As shown, when a single signal trace W can pass between adjacent connection terminals 8, a first trace W1 capable of connecting to the first circuit element 7 can be led out from the first annular pad L8a and the second annular pad L8b via only the first surface 5a of the main substrate. Therefore, the first annular connection terminal 8a and the second annular connection terminal 8b can be assigned to the first connection terminal 81. Furthermore, since... (The sentence is incomplete and requires further context to translate accurately.) Figure 10 and Figure 11 The above description is the same, so its detailed explanation is omitted, but as Figure 13 As shown, since the second wiring W2 can be provided on the second surface 5b of the main substrate through the through hole TH, it is preferable to assign the third annular connection terminal 8c, the fourth annular connection terminal 8d, the fifth annular connection terminal 8e, and the inner peripheral grid-shaped connection terminal 9c to the second connection terminal 82.

[0063] Reference Figure 10 and Figure 12 As can be understood from the above description, the number of connection terminals 8 that can be assigned to the first connection terminal 81 depends on the number of signal wirings that can be routed between adjacent connection terminals 8 on the first surface 5a of the main substrate. Here, the number of signal wirings that can be routed between adjacent connection terminals 8 on the first surface 5a of the main substrate is set to n (n is a natural number). Preferably, the first connection terminal 81 is a connection terminal 8 arranged from the outermost perimeter to the (n+1)th perimeter among a plurality of connection terminals 8 arranged in a rectangular ring.

[0064] According to the described embodiments, the connection terminal 8 of the semiconductor module 1, which is mounted on the first surface 5a of the main substrate and has at least one semiconductor element (system LSI2), can be appropriately configured according to the connection object of the semiconductor module 1, which has a first circuit element 7 mounted on the first surface 5a of the main substrate and a second circuit element 6 mounted on the second surface 5b of the main substrate.

[0065] (Summary of the implementation method)

[0066] The following is a brief overview of the semiconductor module (1) and semiconductor device (10) described above.

[0067] In one embodiment, a semiconductor module (1) is mounted on the first surface (5a) of a main substrate (5) on which a first circuit element (7) is mounted on a first surface (5a) and a second circuit element (6) is mounted on a second surface (5b) opposite to the first surface (5a), and has at least one semiconductor element (2). The semiconductor module (1) includes a plurality of connection terminals (8), which are arranged in a rectangular ring on the opposing surface (4b) facing the main substrate (5) and connected to the main substrate (5). The plurality of connection terminals (8) include a plurality of first connection terminals (81) connected to the first circuit element (7) via the main substrate (5), namely a first connection terminal group (T1), and a plurality of second connection terminals (82) connected to the second circuit element (6) via the main substrate (5), namely a second connection terminal group (T2). The first connection terminal group (T1) is arranged on the outer periphery side of the second connection terminal group (T2).

[0068] In another embodiment, the semiconductor device (10) includes a main substrate (5), a semiconductor module (1) having at least one semiconductor element (2) mounted on a first surface (5a) of the main substrate (5), and a plurality of circuit elements (50) mounted on the main substrate (5). The circuit elements (50) include a first circuit element (7) mounted on the first surface (5a) and a second circuit element (6) mounted on a second surface (5b) opposite to the first surface (5a). The semiconductor module (1) includes components connected to the main substrate (5). A plurality of connection terminals (8) are arranged in a rectangular ring on the opposing surfaces (4b) and connected to the main substrate (5). The plurality of connection terminals (8) include a plurality of first connection terminals (81) connected to the first circuit element (7) via the main substrate (5), namely a first connection terminal group (T1), and a plurality of second connection terminals (82) connected to the second circuit element (6) via the main substrate (5), namely a second connection terminal group (T2). The first connection terminal group (T1) is arranged on the outer periphery side of the second connection terminal group (T2).

[0069] Based on these structures, it is easier to connect the first circuit element (7) and the first connection terminal (7) on the first surface (5a) compared to the second connection terminal (82). That is, since the first circuit element (7) and the semiconductor module (1) are mounted on the first surface (5a), it is possible to connect the first circuit element (7) and the first connection terminal (7) on the first surface (5a) without having to detour to the second surface (5b) via a via (TH). Since the second circuit element (6) is mounted on the second surface (5b) opposite to the first surface (5a) where the semiconductor module (1) is mounted, it is not necessary to perform wiring extending from the second connection terminal (82) on the first surface (5a). The second connection terminal (82) can be connected to the connection terminal (8) via a via (TH) in any case. Therefore, by arranging the plurality of first connection terminals (81), i.e., the first connection terminal group (T1), further outward than the plurality of second connection terminals (82), i.e., the second connection terminal group (T2), the circuit element (50) and the semiconductor module (1) can be effectively connected. As described above, according to this structure, the connection terminals of the semiconductor module (1) can be appropriately configured according to the connection object of the semiconductor module (1).

[0070] Preferably, the outermost connection terminal (8) among the plurality of connection terminals (8) arranged in a rectangular ring is used as the outermost connection terminal (8a), the first connection terminal group (T1) includes the outermost connection terminal (8a), and the second connection terminal group (T2) does not include the outermost connection terminal (8a).

[0071] If the outermost connecting terminal (8a) is assigned to the first connecting terminal (81), the first circuit element (7) and the first connecting terminal (7) can be easily mounted on the first surface (5a). Since the second circuit element (6) is mounted on the second surface (5b), the second connecting terminal (82) is a terminal connected via a through-hole (TH). Therefore, if the outermost connecting terminal (8a) is assigned to the second connecting terminal (82), there is a possibility that the corresponding portion of the first connecting terminal (81) cannot be assigned to the outermost connecting terminal (8a). Therefore, it is preferable that the outermost connecting terminal (8a) is not assigned to the second connecting terminal (82).

[0072] Preferably, the first connection terminal (81) is the connection terminal (8) that transmits a signal at a higher frequency than the second connection terminal (82).

[0073] Compared to low-frequency signals, high-frequency signals are more susceptible to the effects of wiring length and shape, which increases the likelihood of reduced transmission quality. Through-holes (TH) are prone to signal reflection, and the wiring tends to lengthen as it travels back and forth between the first surface (5a) and the second surface (5b). Therefore, it is preferable that relatively high-frequency signals are connected on the same substrate surface without passing through through-holes (TH). Therefore, the connection terminal (8) for transmitting relatively high-frequency signals is preferably the first connection terminal (81).

[0074] In addition, preferably, the number of signal wires (W) that can pass between adjacent connection terminals (8) on the first surface (5a) is set to n (n is a natural number), and the first connection terminal (81) is the connection terminal (8) arranged from the outermost perimeter to the (n+1)th perimeter among a plurality of connection terminals (8) arranged in a rectangular ring.

[0075] Viewed from a direction orthogonal to the substrate surface of the main substrate (5), in order to lead the signal wiring (W) of the first surface (5a) from the connection terminal (8) disposed on the inner periphery to the outside of the semiconductor module (1), the signal wiring (W) needs to pass between the connection terminals (8) on the outer periphery side, which are closer to the inner periphery side than the connection terminal (8). The distance between the signal wiring (W) and the distance between the signal wiring (W) and the pad for mounting the connection terminal (8) are determined by the voltage of the signal, the material of the main substrate (5), etc. Therefore, the number of signal wiring (W) that can pass between adjacent connection terminals (8) is also determined by the voltage of the signal, the material of the main substrate (5), etc. When the number of signal wiring (W) that can pass between adjacent connection terminals (8) is small, it is difficult to lead the signal wiring (W) from the connection terminal (8) connected to the inner periphery side. Therefore, it is preferable that the first connection terminal (81) is allocated according to the number of signal wiring (W) that can pass between adjacent connection terminals (8).

[0076] Explanation of reference numerals in the attached figures:

[0077] 1: Semiconductor Module

[0078] 2: System LSI (Semiconductor Component)

[0079] 4b: Second side of the module substrate (the facing side opposite to the main substrate)

[0080] 5: Main base board

[0081] 5a: First surface of the main substrate (the first surface of the main substrate)

[0082] 5b: Second side of the main substrate (second side of the main substrate)

[0083] 6: Second circuit element

[0084] 6T: Second circuit element terminal

[0085] 7: First circuit element

[0086] 7T: Terminal of the first circuit element

[0087] 8: Connecting terminals

[0088] 8a: First annular connecting terminal (outermost peripheral terminal)

[0089] 10: Semiconductor devices

[0090] 21: Memory Interface

[0091] 50: Circuit elements

[0092] 81: First connecting terminal

[0093] 82: Second connection terminal

[0094] 91: First grid-shaped connection terminal

[0095] 92: Second grid-shaped connection terminal

[0096] 93: Third grid-shaped connection terminal

[0097] 94: Fourth grid-shaped connection terminal

[0098] T1: First connection terminal group

[0099] T2: Second connection terminal group

[0100] TH: Through hole

Claims

1. A semiconductor module, mounted on the first surface of a main substrate on a first surface on which a first circuit element is mounted and on a second surface on the opposite side of the first surface on which a second circuit element is mounted, and comprising at least one semiconductor element, wherein, The semiconductor module includes a plurality of connection terminals arranged in a rectangular ring on the opposing side facing the main substrate and connected to the main substrate. The plurality of connection terminals include a plurality of first connection terminals (i.e., a first connection terminal group) connected to the first circuit element via the main substrate, and a plurality of second connection terminals (i.e., a second connection terminal group) connected to the second circuit element via the main substrate. The first connection terminal group is positioned further outward than the second connection terminal group. The first connection terminal is the connection terminal that transmits signals at a higher frequency than the second connection terminal. The first connection terminal group is a connection terminal for differentially transmitted signals that transmit information through a pair of differential signals. The second connection terminal group is a connection terminal for single-ended signal transmission using a single signal line. The number of signal wirings that can be routed between adjacent connection terminals on the first surface is set to n (n is a natural number), and the first connection terminal is the connection terminal arranged from the outermost perimeter to the (n+1)th perimeter among a plurality of connection terminals arranged in a rectangular ring.

2. The semiconductor module as claimed in claim 1, wherein, The outermost connection terminal among a plurality of connection terminals arranged in a rectangular ring is designated as the outermost connection terminal. The first connection terminal group includes the outermost connection terminal, while the second connection terminal group does not include the outermost connection terminal.

3. A semiconductor device comprising a main substrate, a semiconductor module having at least one semiconductor element mounted on a first side of the main substrate, and a plurality of circuit elements mounted on the main substrate, wherein, The circuit element includes a first circuit element mounted on the first surface and a second circuit element mounted on the second surface opposite to the first surface. The semiconductor module includes a plurality of connection terminals arranged in a rectangular ring on the opposing side facing the main substrate and connected to the main substrate. The plurality of connection terminals include a plurality of first connection terminals (i.e., a first connection terminal group) connected to the first circuit element via the main substrate, and a plurality of second connection terminals (i.e., a second connection terminal group) connected to the second circuit element via the main substrate. The first connection terminal group is positioned further outward than the second connection terminal group. The first connection terminal is the connection terminal that transmits signals at a higher frequency than the second connection terminal. The first connection terminal group is a connection terminal for differentially transmitted signals that transmit information through a pair of differential signals. The second connection terminal group is a connection terminal for single-ended signal transmission using a single signal line. Let n be the number of signal wirings that can be routed between adjacent connection terminals on the first surface (n is a natural number), where the first connection terminal is one of the connection terminals arranged in a rectangular ring from the outermost perimeter to the (n+1)th perimeter.

4. The semiconductor device of claim 3, wherein, The outermost connection terminal among a plurality of connection terminals arranged in a rectangular ring is designated as the outermost connection terminal. The first connection terminal group includes the outermost connection terminal, while the second connection terminal group does not include the outermost connection terminal.

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