Method of manufacturing a semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. Reliability and performance of the semiconductor device are improved. First, a first mask pattern is formed on a semiconductor substrate in each of a first region to a third region. Next, a second mask pattern is formed on side surfaces of the first mask pattern and on the semiconductor substrate in each of the first region to the third region, the second mask pattern being made of a material different from a material constituting the first mask pattern. Next, a plurality of fins protruding from a recessed upper surface of the semiconductor substrate are formed by performing an anisotropic etching process on the semiconductor substrate. In this way, fins each having a structure different from a fin structure in the first region can be formed in the second region and the third region.

Description

[0001] Cross-reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2020-078767, filed on April 28, 2020, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing semiconductor devices including fin-structured transistors. Background Technology

[0004] FinFETs (Fin Field-Effect Transistors) are also known as field-effect transistors, and they can improve operating speed, reduce leakage current, reduce power consumption, and miniaturize semiconductor devices. A FinFET is, for example, a semiconductor device that includes: a semiconductor layer serving as a channel region and protruding from a semiconductor substrate; and a gate electrode formed across the protruding semiconductor layer.

[0005] Semiconductor devices (semiconductor chips) include semiconductor elements such as low-voltage MISFET (metal-insulator-semiconductor field-effect transistor), high-voltage MISFET, and MONOS (metal-oxide-semiconductor-nitride) transistors. When these semiconductor elements are formed in a fin structure, different fin structures for the corresponding semiconductor elements have been studied to obtain appropriate characteristics for the corresponding semiconductor elements.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-123398

[0008] For example, Patent Document 1 discloses a technique for forming a fin structure in a low-voltage MISFET region that differs from the structure in other regions. This technique is achieved by using a different resist pattern and etching conditions for the low-voltage MISFET region than for other regions. Summary of the Invention

[0009] The method of forming different fin structures by using different etching conditions as disclosed in Patent Document 1 makes it difficult to control the cone angle and width of each fin, and further raises concerns about shape variations of each fin within the semiconductor device. Therefore, there is a risk of reducing the reliability and performance of the semiconductor device.

[0010] Other objects and novel features will be apparent from the description and accompanying drawings in this specification.

[0011] The following is a brief overview of typical aspects of the embodiments disclosed in this application.

[0012] A method for manufacturing a semiconductor device according to one embodiment includes: (a) preparing a semiconductor substrate having a first region and a second region, the second region being different from the first region; (b) forming a first pattern on the semiconductor substrate in each of the first and second regions; (c) forming a second pattern made of a material different from the first pattern on a side surface of the first pattern and on the semiconductor substrate in the first and second regions; (d) selectively removing the second pattern in the first region; and (e) after step (d), forming a first fin in the first region and a second fin in the second region by performing an anisotropic etching process on the semiconductor substrate, wherein the first pattern remains on the semiconductor substrate in the first region, and the second pattern remains on the semiconductor substrate in the second region. In this case, after step (e), the first fin protrudes from the upper surface of the semiconductor substrate adjacent to the first fin, and the second fin protrudes from the upper surface of the semiconductor substrate adjacent to the second fin.

[0013] A method for manufacturing a semiconductor device according to one embodiment includes: (a) preparing a semiconductor substrate having a first region and a second region, the second region being different from the first region; (b) forming a first fin in the first region by recessing a portion of the upper surface of the semiconductor substrate, such that the first fin, as part of the semiconductor substrate, protrudes from the recessed upper surface of the semiconductor substrate and extends along a first direction in a plan view, and forming a second fin in the second region, such that the second fin, as part of the semiconductor substrate, protrudes from the recessed upper surface of the semiconductor substrate and extends along a third direction in a plan view; (c) after step (b), in the first region... (c) The steps of forming a first insulating film on the upper and side surfaces of the fin and on the upper and side surfaces of the second fin in the second region; (d) After step (c), selectively removing the first insulating film in the second region; (e) After step (d), with the first insulating film in the first region retained, forming a second gate insulating film on the upper and side surfaces of the second fin in the second region; (f) After step (e), removing the first insulating film in the first region; (g) After step (f), forming a first gate insulating film with a thickness smaller than the thickness of the second gate insulating film on the upper and side surfaces of the first fin in the first region.

[0014] According to one embodiment, the reliability of the semiconductor device can be improved. Furthermore, the performance of the semiconductor device can be improved. Attached Figure Description

[0015] Figure 1 This is a schematic diagram showing the layout configuration of a semiconductor chip as a semiconductor device according to the first embodiment.

[0016] Figure 2 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first research example.

[0017] Figure 3 It shows the next step. Figure 2 A cross-sectional view of a method for manufacturing semiconductor devices.

[0018] Figure 4 Each of these shows a cross-sectional view of a semiconductor device according to the second research example.

[0019] Figure 5 This is a perspective view showing the outline of the fin according to the first embodiment.

[0020] Figure 6 Each of these shows a cross-sectional view of the fin profile according to the first embodiment.

[0021] Figure 7 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment.

[0022] Figure 8 It shows the next step. Figure 7 A cross-sectional view of a method for manufacturing semiconductor devices.

[0023] Figure 9 It shows the next step. Figure 8 A cross-sectional view of a method for manufacturing semiconductor devices.

[0024] Figure 10 It shows the next step. Figure 9 A cross-sectional view of a method for manufacturing semiconductor devices.

[0025] Figure 11 It shows the next step. Figure 10 A cross-sectional view of a method for manufacturing semiconductor devices.

[0026] Figure 12 It shows the next step. Figure 11 A cross-sectional view of a method for manufacturing semiconductor devices.

[0027] Figure 13 It shows the next step. Figure 12 A cross-sectional view of a method for manufacturing semiconductor devices.

[0028] Figure 14 It shows the next step. Figure 13 A cross-sectional view of a method for manufacturing semiconductor devices.

[0029] Figure 15 It shows the next step. Figure 14 A cross-sectional view of a method for manufacturing semiconductor devices.

[0030] Figure 16 It shows the next step. Figure 15 A cross-sectional view of a method for manufacturing semiconductor devices.

[0031] Figure 17 It shows the next step. Figure 16 A cross-sectional view of a method for manufacturing semiconductor devices.

[0032] Figure 18 It shows the next step. Figure 17 A cross-sectional view of a method for manufacturing semiconductor devices.

[0033] Figure 19 It shows the next step. Figure 18 A cross-sectional view of a method for manufacturing semiconductor devices.

[0034] Figure 20 It shows the next step. Figure 19 A cross-sectional view of a method for manufacturing semiconductor devices.

[0035] Figure 21 It shows the next step. Figure 20 A cross-sectional view of a method for manufacturing semiconductor devices.

[0036] Figure 22 It shows the next step. Figure 21 A cross-sectional view of a method for manufacturing semiconductor devices.

[0037] Figure 23 It shows the next step. Figure 22 A cross-sectional view of a method for manufacturing semiconductor devices, the cross-sectional view being positioned relative to... Figures 7 to 22 Different directions. Detailed Implementation

[0038] The embodiments will now be described in detail based on the accompanying drawings. In the drawings used to describe the embodiments, the same reference numerals are affixed to the same elements having the same function, and repeated descriptions will be omitted. Additionally, unless specifically required in the following embodiments, descriptions of the same or similar parts will generally not be repeated.

[0039] Furthermore, in some of the figures used in the embodiments, shading lines have been omitted to make the figures easier to see.

[0040] The X, Y, and Z directions described in this application are orthogonal to each other. In some cases, the Z direction is described as the vertical direction or the height direction of a structure. The plane formed by the X and Y directions has a flat surface perpendicular to the Z direction. For example, the expression "plan view" in this application refers to the plane formed by the X and Y directions viewed in the Z direction.

[0041] (First Embodiment)

[0042] <Layout and Configuration of Semiconductor Chip CHP>

[0043] First, refer to Figure 1 The layout configuration of the semiconductor chip CHP, which is a semiconductor device according to the first embodiment, will be described.

[0044] The semiconductor chip CHP is provided with multiple circuit blocks for various purposes. Specifically, the semiconductor chip CHP includes: flash memory circuit block C1, EEPROM (Electrically Erasable Programmable Read-Only Memory) circuit block C2, CPU (Central Processing Unit) circuit block C3, RAM (Random Access Memory) circuit block C4, analog circuit block C5, and I / O (Input / Output) circuit block C6.

[0045] Each circuit block in flash memory block C1 and EEPROM block C2 is a region used as a semiconductor element, including non-volatile memory cells, etc. The stored information in the non-volatile memory cells is electrically rewritable, and MONOS transistors are formed, for example, within the non-volatile memory cells. Approximately 10V of positive or negative voltage is used to rewrite the stored information. Flash memory block C1 and EEPROM block C2 are used for different purposes.

[0046] For example, for the computer-readable storage medium that operates on subsequent CPU circuit block C3, a high read speed is required despite a low rewrite frequency. For storing such computer-readable storage medium, a non-volatile memory cell of flash memory circuit block C1 is used. For the data used in CPU circuit block C3, although rewrite resistance is required due to the high rewrite frequency, such a high read speed is not necessary. For storing such data, a non-volatile memory cell of EEPROM circuit block C2 is used.

[0047] CPU circuit block C3 includes logic circuitry driven by a voltage of approximately 1V and is the area used as a semiconductor element, in which low-voltage MISFETs with low breakdown voltage and high-speed operation are formed.

[0048] RAM circuit block C4 is a region that includes SRAM (Static RAM), and in this region, a low-voltage MISFET as a semiconductor element is formed, which has a cross-sectional structure that is almost identical to that of CPU circuit block C3.

[0049] Analog circuit block C5 is a region that includes analog circuitry, and in this region are formed capacitor elements, resistor elements, bipolar transistors, and high-voltage MISFETs, which are semiconductor elements. The high-voltage MISFETs have a higher breakdown voltage than the low-voltage MISFETs and are driven by a voltage of approximately 5V.

[0050] I / O circuit block C6 is a region that includes input / output circuitry, and a high-voltage MIFET, which is formed as a semiconductor element, is formed in this region. The high-voltage MIFET has a cross-sectional structure that is almost identical to that of analog circuit block C5.

[0051] In the cross-sectional diagrams used for the following description, note that the formation region of the low-voltage MISFET is assumed to be region A1, the formation region of the high-voltage MISFET is assumed to be region A2, and the formation region of the non-volatile memory cell is assumed to be region A3.

[0052] Before describing the method of manufacturing a semiconductor device according to the first embodiment, semiconductor devices of the first and second research examples studied by the inventors will be described, and new problems discovered from the research will be explained.

[0053] <Regarding the first research example>

[0054] Figure 2 and Figure 3 Each of the figures shows a cross-sectional view of a low-voltage MISFET in the gate width direction.

[0055] like Figure 2 As shown, a fin FN4 is formed in region A1. The fin FN4 is a protrusion (bump) selectively projecting from the upper surface of the semiconductor substrate SUB. A p-type well region PW1 is formed in the semiconductor substrate SUB including the fin FN4. The device isolation portion STI is made of, for example, a silicon oxide film, and the upper surface of the device isolation portion STI is positioned lower than the upper surface of the fin FN4. A portion of the surface of the fin FN4 (the portion of the surface protruding from the upper surface of the device isolation portion STI) forms the channel region of the low-voltage MISFET.

[0056] like Figure 3 As shown, the step of forming the gate insulating film GI2 of the high-voltage MISFET is performed by thermal oxidation before forming the gate insulating film of the low-voltage MISFET. The gate insulating film GI2 has a much larger thickness than the gate insulating film of the low-voltage MISFET. In this process, the gate insulating film GI2 is also formed on the upper and side surfaces of the fin FN4 in region A1. Then, the gate insulating film GI2 in region A2 is removed by a solution containing hydrofluoric acid or the like.

[0057] In this process, the gate insulating film GI2 is formed by reacting with the material constituting the fin FN4. Therefore, when the width of the fin FN4 is small, the ends of the fin FN4 may become thinner or even lost in some cases. In this situation, the channel region of the low-voltage MISFET becomes smaller, and there are performance degradation issues with the low-voltage MISFET, such as reduced current capacity.

[0058] Therefore, for the step of forming the gate insulating film GI2 of the high-voltage MISFET, a technique is needed that can ensure the width of the fin FN4 in the region A1 where the low-voltage MISFET is formed.

[0059] <Regarding the example of the second study>

[0060] The second study example has different problems than the first study example. Figure 4 Cross-sectional views are shown of a low-voltage MISFET formed in region A1, a high-voltage MISFET formed in region A2, and a non-volatile memory cell formed in region A3, in the corresponding gate width directions.

[0061] like Figure 4 As shown, well regions PW1 to PW3 are formed in semiconductor substrates SUB in regions A1 to A3, gate insulating films GI1 to GI3 are formed in multiple fins FN4, and gate electrodes GE1 to GE3 are formed on gate insulators GI1 to GI3. Note that the gate insulating film GI3 of the non-volatile memory cell is made of a stack of insulating film OX1, charge accumulation layer CSL and insulating film OX2.

[0062] For high-voltage MISFETs and non-volatile memory cells, a higher voltage is used than that of low-voltage MISFETs. Therefore, if the corresponding fins FN4 in regions A1 to A3 are designed to match the properties of low-voltage MISFETs and have the same width, the electric field tends to concentrate on the upper part of the fins FN4 in regions A2 and A3. As a result, there is a decrease in the breakdown voltage of the gate insulating films GI2 and GI3, and a reduction in the reliability of the high-voltage MISFET and non-volatile memory cell.

[0063] On the other hand, if the corresponding fins FN4 in regions A1 to A3 are designed to match the properties of high-voltage MISFETs and non-volatile memory cells, the width of the fins FN4 in low-voltage MISFETs becomes larger. Therefore, there is a problem in microfabrication of low-voltage MISFETs.

[0064] Furthermore, due to the small width of fin FN4, complete depletion occurs in the upper part of fin FN4 during low-voltage MISFET operation. In this case, compared with low-voltage MISFET, punch-through is more likely to occur between the source and drain regions in high-voltage MISFET and non-volatile memory cell driven by high voltage, and therefore the breakdown voltage of high-voltage MISFET and non-volatile memory cell deteriorates.

[0065] Therefore, a technique is needed to ensure the reliability of low-voltage MISFETs, high-voltage MISFETs, and non-volatile memory cells by creating differences in the fin structures of regions A1 to A3, thereby achieving appropriate characteristics.

[0066] <Outline of the fin in the first embodiment>

[0067] First, refer to Figure 5 and Figure 6 The outlines of fins FN1 to FN3 according to the first embodiment will be described. Figure 5 This is a perspective view of the fin. Figure 6 yes Figure 5 Enlarged cross-sectional view of the main part, and cross-sectional view of the low-voltage MISFET formed in region A1, the high-voltage MISFET formed in region A2, and the non-volatile memory cell formed in region A3 in the corresponding gate width direction.

[0068] Note that each of the low-voltage MISFET, high-voltage MISFET, and non-volatile memory cell according to the first embodiment is an n-type transistor. P-type transistors are also formed in semiconductor devices (semiconductor chips CHP), but their description is omitted here.

[0069] like Figure 5 As shown, the semiconductor device is provided with a plurality of fins, which are formed by selectively recessing a portion of the semiconductor substrate SUB. In a first embodiment, fins FN1 to FN3 formed in regions A1 to A3 are illustrated as a plurality of fins. Each of the fins FN1 to FN3 is a protrusion (convexity) that is part of the semiconductor substrate SUB, extending in the X direction and selectively protruding in the Z direction from the upper surface of the semiconductor substrate SUB adjacent to each of the fins FN1 to FN3.

[0070] Note that in Figure 5 Taking fins FN1 to FN3 extending in the X direction as an example. However, the extension direction of fins FN1 to FN3 can be the Y direction or different directions. Alternatively, the extension directions of fins FN1 to FN3 can be different from each other.

[0071] like Figure 6As shown, a component isolation portion (STI) is formed on each upper surface of the semiconductor substrate SUB between adjacent fins FN1 to FN3. The upper surface of the component isolation portion (STI) is positioned lower than the upper surface of each of the fins FN1 to FN3. In other words, a portion of each of the fins FN1 to FN3 protrudes from the component isolation portion (STI). In a first embodiment, the portion of each of the fins FN1 to FN3 that is higher than the upper surface of the component isolation portion (STI) is referred to as the upper portion of each of the fins FN1 to FN3, and the portion of each of the fins FN1 to FN3 that is lower than the upper surface of the component isolation portion (STI) is referred to as the lower portion of each of the fins FN1 to FN3.

[0072] The region of the semiconductor substrate SUB, that is, the region defined by the device isolation section STI, becomes the active region. That is, the upper part of fins FN1 to FN3 becomes the active region, and the channel region, source region, and drain region of each of the low-voltage MISFET, high-voltage MISFET, and non-volatile memory cell are formed in the active region.

[0073] In each of regions A1 to A3, the upper surface of the element isolation section STI is not constantly flat, but can vary in certain situations. For example, in some cases, between two fins, the upper surface of the element isolation section STI is slightly higher as it approaches the fin. In the first embodiment, to clearly illustrate the location of the varying upper surface of the element isolation section STI, the "location of the upper surface of the element isolation section STI" is assumed to be located at the lowest surface of the upper surface of the element isolation section STI formed between the two fins.

[0074] Each of the upper surfaces of fins FN1 to FN3 is not consistently flat, but may be circular in some cases. In some cases, as seen in fin FN1, the side surfaces of the fin have an angle of inclination perpendicular or nearly perpendicular to the upper surface of the semiconductor substrate USB. However, in some cases, as seen in fins FN2 or FN3, the side surfaces of the fin are inclined relative to the upper surface of the semiconductor substrate SUB.

[0075] Each of fins FN1 to FN3 has a head and a side portion. The head is located at the highest point of each fin, and the side portion is positioned between the head of each fin and the upper surface of the semiconductor substrate SUB. In this first embodiment, each upper surface of fins FN1 to FN3 refers to the surface including the head and the head perimeter, and each side surface of fins FN1 to FN3 refers to the surface including the side portion and the side portion perimeter.

[0076] As a key feature of the structure of the semiconductor device according to the first embodiment, the angles θ1 to θ3 of the tilt angles of the corresponding side surfaces of fins SN1 to FN3 and the corresponding widths W1 to W3 of fins FN1 to FN3 are illustrated.

[0077] Figure 6 Each of the angles θ1 to θ3 shown is the angle formed by each side surface of fins FN1 to FN3 and the upper surface (bottom surface of the element isolation section STI) of the semiconductor substrate SUB adjacent to each of the fins FN1 to FN3 in the Y direction.

[0078] The side surface of fin FN1 forms an angle θ1 with respect to the upper surface of semiconductor substrate SUB. The side surface of fin FN2 has a first surface SS1 in the upper portion of fin FN2 and a second surface SS2 in the lower portion of fin FN2. The first surface SS1 forms an angle θ2 with respect to the upper surface of semiconductor substrate SUB. The second surface SS2 is positioned below the first surface SS1 and forms an angle θ3 with respect to the upper surface of semiconductor substrate SUB.

[0079] The side surfaces of fin FN3 include a third surface SS3 in the upper part of fin FN3 and a fourth surface SS4 in the lower part of fin FN3. The third surface SS3 is at an angle θ2 relative to the upper surface of semiconductor substrate SUB, and the fourth surface SS4 is positioned below the third surface SS3 and at an angle θ3 relative to the upper surface of semiconductor substrate SUB.

[0080] Angle θ1 is, for example, equal to or greater than 90 degrees and less than 100 degrees. Angle θ2 is an obtuse angle and is greater than angle θ1 or angle θ3, and is, for example, equal to or greater than 100 degrees and equal to or less than 120 degrees. Angle θ3 is the same as angle θ1, and is, for example, equal to or greater than 90 degrees and less than 100 degrees.

[0081] Figure 6 The widths W1 to W3 shown are the widths of fins FN1 to FN3 in the Y direction. Each of widths W2 and W3 is different from and greater than width W1. More specifically, each of widths W1 to W3 is the average width of each fin of FN1 to FN3 at different heights. For example, each of widths W2 and W3 is different from width W1 and is greater than width W1 at: a certain height position at the top of each fin of FN1 to FN3, and a certain height position at the bottom of each fin of FN1 to FN3.

[0082] Width W1 is, for example, equal to or greater than 10 nm and equal to or less than 20 nm, and each of widths W2 and W3 is, for example, equal to or greater than 10 nm and equal to or less than 60 nm.

[0083] <Method for manufacturing a semiconductor device according to the first embodiment>

[0084] refer to Figures 7 to 23The following describes a method for manufacturing a semiconductor device including fins FN1 to FN3 having the above-described structure. Considering each problem of the first and second research examples described above, a method for manufacturing a semiconductor device according to the first embodiment has been devised. Figures 7 to 22 Each of them is similar to Figure 6 A cross-sectional view of each semiconductor element in the gate width direction, and Figure 23 It is a cross-sectional view of each semiconductor element along the gate length direction.

[0085] First, such as Figure 7 As shown, a semiconductor substrate SUB is prepared from p-type single-crystal silicon having a specific resistivity, for example, about 1 to 10 Ωcm. Next, on the semiconductor substrate SUB, in each of regions A1 to A3, an insulating film IF1 is formed by, for example, a thermal oxidation method or a CVD (chemical vapor deposition) method, which is made of a silicon oxide film.

[0086] Next, a conductive film, made of, for example, polycrystalline silicon, is formed on the insulating film IF1 in each of regions A1 to A3 using a CVD method. Next, a resist pattern RP1 is formed on the conductive film in each of regions A1 to A3. Next, an anisotropic etching process is performed using the resist pattern RP1 as a mask to pattern the conductive film, such that each of the mandrels MD1 to MD3 is formed on the insulating film IF1 in each of regions A1 to A3. Then, the resist pattern RP1 is removed by an ashing process or the like.

[0087] Figure 8 The steps for forming the mask pattern MP1 are shown.

[0088] First, an insulating film, made of, for example, silicon oxide, is formed on the insulating film IF1 using a CVD method to cover each mandrel MD1 to MD3 in regions A1 to A3. The material forming this insulating film is different from the materials forming the mandrels MD1 to MD3 and the semiconductor substrate SUB. The thickness of this insulating film is, for example, 10 nm to 20 nm.

[0089] Next, an anisotropic etching process is performed on the insulating film, such that a mask pattern (pattern) MP1 made from the insulating film is formed on the side surfaces of each mandrel MD1 to MD3 in regions A1 to A3. In this step, the insulating film IF1 not covered by the mandrels MD1 to MD3 and the mask pattern MP1 is removed from the surface, thereby exposing the semiconductor substrate SUB.

[0090] Figure 9 The steps for removing core molds MD1 to MD3 are shown.

[0091] The mandrels MD1 to MD3 in regions A1 to A3 are removed by an isotropic etching process. Next, the insulating film IF1 covered by each mandrel MD1 to MD3 is removed by an isotropic etching process. In this step, the upper part of the mask pattern MP1 is also slightly etched. In this way, the mask pattern MP1 is retained on the substrate SUB in each region of A1 to A3.

[0092] Note that the insulating film IF1 beneath the mask pattern MP1 is retained. Furthermore, the materials of the mask pattern MP1 and the insulating film IF1 are the same, and the mask pattern and the insulating film are formed integrally. Therefore, for the sake of simplicity in the following description, only the mask pattern MP1 is illustrated.

[0093] Figure 10 The steps for forming the insulating film IF2 are shown.

[0094] An insulating film IF2, for example made of silicon oxide, is formed on the portion of the semiconductor substrate SUB exposed from the mask pattern MP1 by a thermal oxidation method. The thickness of the insulating film IF2 is, for example, 5 nm to 10 nm.

[0095] Figure 11 The steps for forming the mask pattern MP2 are shown.

[0096] First, a conductive film made of polycrystalline silicon (silicon film) is formed on the insulating film IF2, for example by a CVD method, to cover the mask pattern MP1 in each of regions A1 to A3. The thickness of the conductive film is, for example, 10 nm to 20 nm. Next, an anisotropic etching process is performed on the conductive film, such that a mask pattern (pattern) MP2 made of the conductive film is formed on the side surface of the mask pattern MP1 and on the semiconductor substrate SUB in each of regions A1 to A3. In this process, the insulating film IF2 serves as an etching stop film.

[0097] Figure 12 The steps for removing a portion of the mask pattern MP2 are shown.

[0098] First, a resist pattern RP2 is formed that covers regions A2 and A3 and forms an opening in region A1. Next, an isotropic etching process is performed using the resist pattern RP2 as a mask, selectively removing the mask pattern MP2 in region A1. Then, the resist pattern RP2 is removed by an ashing process or similar method.

[0099] In this state, the width of each mask pattern MP1 in regions A1 to A3 is, for example, 10 nm to 20 nm, and the width of the mask pattern MP2 in region A2 or A3 is, for example, 10 nm to 20 nm. That is, in region A2 or A3, the total width of mask pattern MP1 and mask pattern MP2 is, for example, 30 nm to 60 nm.

[0100] Figure 13 and Figure 14 Each of the steps shown illustrates the formation of fins FN1 to FN3.

[0101] An anisotropic etching process is performed on a semiconductor substrate SUB under the following conditions: a mask pattern MP1 is retained on the semiconductor substrate SUB in region A1, while mask patterns MP1 and MP2 are retained on the semiconductor substrate SUB in each region of region A2 and region A3, respectively.

[0102] Anisotropic etching is performed under the following conditions: the semiconductor substrate SUB and mask pattern MP2, made of silicon, are easily etched, while the mask pattern MP1, made of silicon oxide, is difficult to etch. That is, the etching rate of mask pattern MP1 is different from the etching rates of semiconductor substrate SUB and mask pattern MP2.

[0103] In such anisotropic etching processes, HBr (hydrogen bromide) gas is used, and a mixture of gases including, for example, HBr gas, CHF3 (trifluoromethane) gas, and O2 (oxygen) gas is used.

[0104] The insulating film IF2 on the semiconductor substrate SUB is exposed to the anisotropic etching process before the semiconductor substrate SUB. Because the insulating film IF2 is thin, it can be removed by this anisotropic etching process even without changing the etching conditions. Then, the semiconductor substrate SUB is etched.

[0105] Alternatively, an isotropic etching process using a hydrofluoric acid solution can be performed immediately prior to the anisotropic etching process, such that the insulating film IF2 is removed to expose the semiconductor substrate SUB to the outside.

[0106] In the middle of this anisotropic etching process, the mask pattern MP2 is etched at almost the same etching rate as the etching on the semiconductor substrate SUB. Therefore, the more etching is performed, the smaller the height of the mask pattern MP2 in the Z direction becomes. The semiconductor substrate SUB is etched vertically until the vertical portions of the side surfaces of the mask pattern MP2 are removed, and thus, the second surface SS2 and the fourth surface SS4 form an angle θ3 relative to the upper surface of the semiconductor substrate SUB.

[0107] The anisotropic etching process then continues. The more the mask pattern MP2 is removed, the smaller the horizontal width of the mask pattern MP2 becomes, and therefore, the semiconductor substrate SUB is processed to have a tapered shape. Note that in the middle of this anisotropic etching process, the mask pattern MP2 is completely removed.

[0108] In the state after removing the mask pattern MP2, the semiconductor substrate SUB in each of regions A1 to A3 is etched while using the mask pattern MP1 as a mask. Therefore, as... Figure 14 As shown, a second surface SS2 and a fourth surface SS4 are formed in regions A2 and A3 at an angle θ3 relative to the recessed upper surface of the semiconductor substrate SUB. A first surface SS1 and a third surface SS3, at an angle θ2 relative to the recessed upper surface of the semiconductor substrate SUB, are formed on the second surface SS2 and the fourth surface SS4. That is, a fin FN2 having the first surface SS1 and the second surface SS2 is formed in region A2, and a fin FN3 having the third surface SS3 and the fourth surface SS4 is formed in region A3.

[0109] In region A1, since only the mask pattern MP1 is used, a fin FN1 is formed with its side surface at an angle θ1 relative to the etched upper surface of the semiconductor substrate SUB.

[0110] The process etches the semiconductor substrate SUB from 100 nm to 250 nm, and therefore the height from the recessed upper surface of the semiconductor substrate SUB to each upper surface of the fins FN1 to FN3 is 100 nm to 250 nm.

[0111] As described above, forming a reference Figure 6 The fins FN1 to FN3 are described. Because the structures of fins FN1 to FN3 in regions A1 to A3 are different from each other, the reliability of low-voltage MISFETs, high-voltage MISFETs and non-volatile memory cells can be ensured, and thus appropriate characteristics can be obtained.

[0112] That is, because each of the upper portions of fins FN2 and FN3 has a tapered shape, the problem of electric field concentration in regions A2 and A3, which leads to a decrease in breakdown voltage, can be suppressed. Furthermore, since the widths W2 and W3 of fins FN2 and FN3 are each greater than the width W1 of fin FN1, punch-through is less likely to occur between the source and drain regions in high-voltage MISFETs and non-volatile memory cells driven by high voltages. Therefore, the reliability of the semiconductor device can be improved.

[0113] Figure 15 The steps for forming the element isolation section STI and the trap regions PW1 to PW3 are shown.

[0114] First, an insulating film made of O3-TEOS is formed on a semiconductor substrate SUB using, for example, a CVD method to fill the gap between fins FN1 to FN3 and cover a mask pattern MP1. O3-TEOS is a type of silicon oxide film. Next, a polishing process is performed using a CMP (chemical mechanical polishing) method, with fins FN1 to FN3 below the mask pattern MP1 serving as an etch stop layer. In this process, a portion of the insulating film and the mask pattern MP1 are removed, exposing the upper surfaces of FN1 to FN3 to the outside.

[0115] Next, an anisotropic etching process is performed on the insulating film, causing it to recess. In this process, the upper portion of each of the fins FN1 to FN3 protrudes from the recessed upper surface of the insulating film. Furthermore, the insulating film filling the gaps between the fins FN1 to FN3 forms the device isolation layer (STI).

[0116] Next, impurities such as boron (B) or boron difluoride (BF2) are doped into the semiconductor substrate SUB using photolithography and ion implantation methods. The semiconductor substrate SUB is then subjected to thermal treatment, causing the impurities to diffuse and forming p-type wells PW1 to PW3 in the semiconductor substrate SUB, including fins FN1 to FN3. Note that although this region is omitted from the description here, n-type well regions are formed in other regions not shown.

[0117] Figure 16 The steps for forming the insulating film IF3 are shown.

[0118] First, on the element isolation section STI, an insulating film IF3, made of, for example, silicon nitride film, is formed using a CVD method to cover the upper and side surfaces of each of the fins FN1 to FN3. The thickness of the insulating film IF3 is, for example, 5 nm to 10 nm. Next, a resist pattern RP3 is formed that covers region A1 and forms each opening in regions A2 and A3. Then, the insulating film IF3 in each region A2 and A3 is removed using a solution containing phosphoric acid. Finally, the resist pattern RP3 is removed by an ashing process or the like.

[0119] Figure 17 The steps for forming the gate insulating film GI2 are shown.

[0120] With the upper and side surfaces of fin FN1 covered by insulating film IF3, a gate insulating film GI2, for example made of silicon oxide film, is formed on the upper and side surfaces of each of fins FN2 and FN3 by means of, for example, thermal oxidation. The thickness of the gate insulating film GI2 is, for example, 10 nm to 15 nm.

[0121] At this point, oxidation in region A1 is suppressed by the insulating film IF3. Therefore, it is difficult to cause oxidation as described in the first research example ( Figure 3 The problem of thinning or loss of the upper part of the fin FN1 described in the paper can be addressed. Therefore, the performance of semiconductor devices can be improved.

[0122] Figure 18 The steps for removing the gate insulating film GI2 are shown.

[0123] First, a resist pattern RP4 is formed, covering regions A1 and A2 and forming an opening in region A3. Next, the gate insulating film GI2 is removed by an isotropic etching process. Then, the resist pattern RP4 is removed by an ashing process, etc.

[0124] Figure 19 The steps for forming a gate insulating film GI3, including a charge accumulation layer CSL, are shown.

[0125] The gate insulating film GI3 is composed of a stacked film, which has an insulating film OX1, a charge accumulation layer CSL and an insulating film OX2.

[0126] First, an insulating film OX1, for example made of silicon oxide, is formed on the upper and side surfaces of the fin FN3 by means of, for example, thermal oxidation or ISSG (In-situ Vapor Generation) oxidation. The thickness of the insulating film OX1 is, for example, 4 nm to 6 nm. Next, a charge accumulation layer CSL is formed on the insulating film OX1 by means of, for example, CVD or ALD (Atomic Layer Deposition). The charge accumulation layer CSL is an insulating film such as a silicon nitride film, having trap energy levels capable of accumulating charge, and having a thickness of, for example, 6 nm to 10 nm. Next, an insulating film OX2, for example made of silicon oxide, is formed on the charge accumulation layer CSL by, for example, CVD or ISSG oxidation. The thickness of the insulating film OX2 is, for example, 6 nm to 8 nm.

[0127] At this time, insulating film OX2 and charge accumulation layer CSL, which are part of gate insulating film GI3, are also formed on insulating film IF3 in region A1 and gate insulating film GI2 in region A2.

[0128] If an insulating film IF3 is not formed on the upper and side surfaces of the fin FN1 in region A1, then during the step of forming the insulating film OX1, the upper and side surfaces of the film FN1 are also oxidized. If this is the case, then the situation is similar to the first research example described above (…). Figure 3 The same problem exists. However, in the first embodiment, such a problem is suppressed by the insulating film IF3.

[0129] Figure 20 The steps for removing the gate insulating film GI3 (insulating film OX2 and charge accumulation layer CSL) and insulating film IF3 are shown.

[0130] First, the following resist pattern RP5 is formed: covering area A3 and forming each opening in areas A1 and A2. Next, the insulating film OX2 in each area of ​​A1 and A2 is removed using a solution containing hydrofluoric acid.

[0131] Next, the charge accumulation layer CSL and insulating film IF3 in region A1, and the charge accumulation layer CSL in region A2 are removed using a solution containing phosphoric acid, exposing the upper and side surfaces of fin FN1 to the outside. In this step, the gate insulating film GI2 in region A2 has a low etching rate to the phosphoric acid-containing solution, and therefore is retained without being removed. Then, the resist pattern RP5 is removed by an ashing process, etc.

[0132] Figure 21 The steps for forming the gate insulating film GI1 are shown.

[0133] A gate insulating film GI1, for example made of silicon oxide, is formed on the upper and side surfaces of fin FN1 by thermal oxidation or ISSG oxidation. The thickness of the gate insulating film GI1 is, for example, 1 nm to 3 nm. In this process, fins FN2 and FN3 are also exposed to an oxidizing atmosphere, and therefore, in some cases, the thickness of the gate insulating film GI2 and the insulating film OX2 is slightly increased.

[0134] Alternatively, a metal oxide film with a higher dielectric constant than that of the silicon nitride film can be used as the gate insulating film GI1. Examples of such metal oxide films include aluminum oxide (AlO film), hafnium oxide (HfO2 film), hafnium silicate (HfSiO film), hafnium silicate nitride (HfSiON film), zirconium oxide (ZrO2 film), tantalum oxide (Ta2O5 film), lanthanum oxide (La2O3 film), zirconium oxynitride zirconium silicate (ZrSiON film), and aluminum nitride (AlN film).

[0135] Figure 22 The steps for forming gate electrodes GE1 to GE3 are shown.

[0136] First, conductive films, for example, made of polysilicon, are formed on the gate insulating film GI1 in region A1, the gate insulating film GI2 in region A2, and the gate insulating film GI3 in region A3 using a CVD method. Next, the conductive films are selectively patterned using photolithography and anisotropic etching processes. In this manner, gate electrodes GE1 to GE3, each made of a conductive film, are formed.

[0137] In regions A1 to A3, gate electrodes GE1 to GE3 are formed on the upper and side surfaces of fins FN1 to FN3, such that gate insulating films GI1 to GI3 are respectively located therebetween.

[0138] Subsequently, through various manufacturing steps, a low-voltage MISFET is formed in region A1, a high-voltage MISFET is formed in region A2, and a non-volatile memory cell is formed in region A3.

[0139] about Figure 23 This will explain the various manufacturing steps. Note that... Figure 23 It is a cross-sectional view of the low-voltage MISFET, high-voltage MISFET and non-volatile memory cell in the gate length direction, and shows the state of the upper surface of each of the fins FN1 to FN3.

[0140] In formation Figure 22 After the steps of the gate electrodes GE1 to GE3, for example, arsenic (As) or phosphorus (P) is doped into the fins FN1 to FN3 by photolithography and ion implantation methods, so that n-type extended regions EX1 to E3 are formed in the fins FN1 to FN3 respectively.

[0141] Next, an insulating film, for example made of silicon oxide or silicon nitride, is formed on each of the fins FN1 to FN3 using a CVD method to cover the gate electrodes GE1 to GE3. Then, an anisotropic etching process is performed on the insulating film to form sidewall spacers SW made of the insulating film on each side surface of the gate electrodes GE1 to GE3. Note that the sidewall spacers SW can be made of a laminate of silicon oxide and silicon nitride films.

[0142] Next, for example, arsenic (As) or phosphorus (P) is doped into fins FN1 to FN3 using photolithography and ion implantation methods, thereby forming n-type diffusion regions D1 to D3 on fins FN1 to FN3, respectively. The impurity concentration of each diffusion region D1 to D3 is higher than the impurity concentration of each extension region EX1 to EX3. Each of the diffusion regions D1 to D3 and the extension regions EX1 to EX3 constitutes the source or drain region of a low-voltage MISFET, a high-voltage MISFET, or a non-volatile memory cell.

[0143] Next, a low-resistance silicide layer SL is formed on each of the gate electrodes GE1 to GE3 and the diffusion regions D1 to D3 using a self-aligned silicide technique. The silicide layer SL is made of, for example, cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel platinum silicide (NiPtSi).

[0144] In the above process, the low-voltage MISET, high-voltage MISFET and non-volatile memory cells included in the semiconductor device according to the first embodiment are manufactured.

[0145] Then, an interlayer insulating film, a plug connected to the silicide layer SL, and a multilayer wiring layer electrically connected to the plug are formed on the low-voltage MISET, the high-voltage MISFET, and the non-volatile memory cell. However, their descriptions and illustrations are omitted.

[0146] The present invention has been specifically described above based on embodiments. However, the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

[0147] For example, in the above embodiments, a non-volatile memory cell operated by a single gate electrode GE3 has been illustrated. However, the present invention can also be applied to non-volatile memory cells comprising two gate electrodes, such as a control gate electrode and a memory gate electrode formed to cover a channel region between the source and drain regions.

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device comprising a first region and a second region different from the first region, the method comprising the following steps: (a) Fabrication of a semiconductor substrate; (b) A first pattern is formed on the semiconductor substrate in each of the first and second regions; (c) A second pattern is formed on the side surface of the first pattern and on the semiconductor substrate in each of the first and second regions, the second pattern being made of a material different from the material constituting the first pattern; (d) Selectively remove the second pattern from the first region; as well as (e) After step (d), a first anisotropic etching process is performed on the semiconductor substrate to form a first fin in the first region and a second fin in the second region, wherein the first pattern is retained on the semiconductor substrate in the first region and the second pattern is retained on the semiconductor substrate in the second region. In step (e), the first fin protrudes from the upper surface of the semiconductor substrate adjacent to the first fin, and the second fin protrudes from the upper surface of the semiconductor substrate adjacent to the second fin. In the middle of step (e), the second pattern in the second region is removed. The method further includes the following steps: (f) After step (e), remove the first pattern in the first region and the first pattern in the second region; (g) After step (f), a first insulating film is formed on the upper and side surfaces of the first fin in the first region and on the upper and side surfaces of the second fin in the second region; (h) After step (g), the first insulating film in the second region is selectively removed; and (i) After step (h), while the first insulating film in the first region is retained, a second gate insulating film is formed on the upper surface and the side surface of the second fin in the second region; (j) After step (i), remove the first insulating film from the first region; and (k) After step (j), a first gate insulating film is formed on the upper surface and the side surface of the first fin in the first region, the first gate insulating film having a thickness smaller than that of the second gate insulating film.

2. The method for manufacturing a semiconductor device according to claim 1, In the plan view, the first fin extends in a first direction and has a first width in a second direction orthogonal to the first direction. In a plan view, the second fin extends upward in a third direction and has a second width in a fourth direction orthogonal to the third direction. The second width is greater than the first width.

3. The method for manufacturing a semiconductor device according to claim 2, Wherein the first width is the average width among the corresponding widths at different height positions of the first fin, and The second width is the average width among the corresponding widths at different height positions of the second fin.

4. The method for manufacturing a semiconductor device according to claim 2, The side surface of the first fin forms a first angle with respect to the upper surface of the semiconductor substrate adjacent to the first fin in the second direction. The side surface of the second fin has a first surface, which forms a second angle with respect to the upper surface of the semiconductor substrate adjacent to the second fin in the fourth direction. The second angle is greater than the first angle.

5. The method for manufacturing a semiconductor device according to claim 4, The side surface of the second fin further has a second surface, which is positioned lower than the first surface, and the second surface forms a third angle with respect to the upper surface of the semiconductor substrate adjacent to the second fin in the fourth direction. The second angle is greater than the third angle.

6. The method for manufacturing a semiconductor device according to claim 1, The first anisotropic etching process in step (e) is performed under conditions that make the semiconductor substrate and the second pattern easy to etch and the first pattern difficult to etch.

7. The method for manufacturing a semiconductor device according to claim 6, The step (e) mentioned above includes the following steps: (e1) The first anisotropic etching process is performed on the semiconductor substrate in the following cases: the first pattern is used as a mask in the first region, and the first pattern and the second pattern are used as masks in the second region; as well as (e2) After step (e1), the first anisotropic etching process is performed on the semiconductor substrate in the following condition: the first pattern is used as a mask in the first region and the second region while the second pattern is removed.

8. The method for manufacturing a semiconductor device according to claim 7, The side surface of the second fin has a second surface formed by steps (e1) and (e2), and a first surface formed by step (e2) that is higher than the second surface. The second angle formed by the first surface and the upper surface of the semiconductor substrate adjacent to the second fin is greater than the third angle, which is formed by the second surface and the upper surface of the semiconductor substrate adjacent to the second fin.

9. The method for manufacturing a semiconductor device according to claim 7, Each of the materials constituting the semiconductor substrate and the materials constituting the second pattern is silicon, and The material constituting the first pattern is silicon oxide.

10. The method for manufacturing a semiconductor device according to claim 9, In the first anisotropic etching process in step (e), a mixed gas containing HBr gas, CHF3 gas and O2 gas is used.

11. The method for manufacturing a semiconductor device according to claim 10, In step (i), the second gate insulating film is formed by thermal oxidation and is made of silicon oxide.

12. The method for manufacturing a semiconductor device according to claim 11, The first region is the first MISFET formation region, which includes the first gate insulating film, and The second region is a second MISFET formation region, which includes the second gate insulating film and is driven by a driving voltage higher than that of the first MISFET.

13. The method for manufacturing a semiconductor device according to claim 10, The step (i) further includes the following steps: (i1) A second insulating film made of silicon oxide is formed on the upper and side surfaces of the second fin in the second region by thermal oxidation or ISSG oxidation. (i2) A charge accumulation layer is formed on the second insulating film; as well as (i3) A third insulating film is formed on the charge accumulation layer, and The second gate insulating film is made of a stacked film, which includes the second insulating film, the charge accumulation layer and the third insulating film.

14. The method for manufacturing a semiconductor device according to claim 13, The first region is the first MISFET formation region, which includes the first gate insulating film, and The second region is a non-volatile memory cell formation region, which includes a second gate insulating film and uses a rewrite voltage that is higher than the drive voltage used for the first MISFET.

15. The method for manufacturing a semiconductor device according to claim 10, further comprising the following steps: (l) After step (e), an element isolation portion is formed on the upper surface of the semiconductor substrate adjacent to the first fin and the second fin; The position of the upper surface of the component isolation portion is lower than the position of the upper surface of the first fin and the position of the upper surface of the second fin. The first fin has a first head and a first side portion, the first head being at the highest point of the first fin, and the first side portion being positioned between the first head of the first fin and the upper surface of the semiconductor substrate. The upper surface of the first fin includes the first head. The side surface of the first fin includes the first side portion. The second fin has a second head and a second side portion, the second head being located at the highest point of the second fin, and the second side portion being positioned between the second head of the second fin and the upper surface of the semiconductor substrate. The upper surface of the second fin includes the second head, and The side surface of the second fin includes the second side portion.

16. The method for manufacturing a semiconductor device according to claim 1, The step (b) further includes the following steps: (b1) A first conductive film is formed on the semiconductor substrate; (b2) By patterning the first conductive film, a core mold is formed on the semiconductor substrate in each of the first and second regions; (b3) A fourth insulating film is formed on the semiconductor substrate to cover the core mold in the first region and the core mold in the second region; (b4) The first pattern is formed on the side surface of the core mold in the first region and on the side surface of the core mold in the second region by performing a second anisotropic etching process on the fourth insulating film. as well as (b5) After step (b4), remove the core mold in the first region and the core mold in the second region.

17. The method for manufacturing a semiconductor device according to claim 16, The step (c) further includes the following steps: (c1) A second conductive film is formed on the semiconductor substrate to cover the first pattern in the first region and the first pattern in the second region; as well as (c2) The second pattern is formed on the side surface of the first pattern in the first region and on the side surface of the first pattern in the second region by performing a third anisotropic etching process on the second conductive film.

18. A method of manufacturing a semiconductor device, the semiconductor device comprising a first region and a second region different from the first region, the method comprising the steps of: (a) Fabrication of a semiconductor substrate; (b) A first fin is formed in the first region by recessing a portion of the upper surface of the semiconductor substrate, the first fin being a part of the semiconductor substrate, protruding from the recessed upper surface of the semiconductor substrate and extending along a first direction in a plan view, and a second fin is formed in the second region, the second fin being a part of the semiconductor substrate, protruding from the recessed upper surface of the semiconductor substrate and extending along a third direction in a plan view; (c) After step (b), a first insulating film is formed on the upper and side surfaces of the first fin in the first region and on the upper and side surfaces of the second fin in the second region; (d) After step (c), the first insulating film in the second region is selectively removed; (e) After step (d), while the first insulating film in the first region is retained, a second gate insulating film is formed on the upper surface and the side surface of the second fin in the second region. (f) After step (e), remove the first insulating film from the first region; and (g) After step (f), a first gate insulating film is formed on the upper surface and the side surface of the first fin in the first region, the first gate insulating film having a thickness smaller than that of the second gate insulating film.

19. The method for manufacturing a semiconductor device according to claim 18, In the plan view, the first fin has a first width in a second direction orthogonal to the first direction. In the plan view, the second fin has a second width in a fourth direction orthogonal to the third direction. The first width is the average width among the corresponding widths at different height positions of the first fin, and The second width is the average width among the corresponding widths at different height positions of the second fin, and the second width is greater than the first width.

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