Semiconductor memory device

Abstract

This disclosure provides a semiconductor memory device. The semiconductor memory device includes: a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region being spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first and second impurity regions; a first conductive interconnect line connected to the first impurity region and extending in a second direction different from the first direction; and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region, and the first gate insulating film is located between the first gate electrode and the first semiconductor pattern.

Description

Technical Field

[0001] The example implementations relate to semiconductor memory devices and / or methods for manufacturing such semiconductor memory devices, and more specifically, to three-dimensional semiconductor memory devices having improved electrical properties and / or methods for manufacturing such three-dimensional semiconductor memory devices. Background Technology

[0002] To meet consumers' expected performance and low prices, there is a need to increase the integration level of semiconductor components. In the case of semiconductor components, since integration level is a significant factor determining product price, there is a need to increase integration level significantly.

[0003] In the case of conventional two-dimensional or planar semiconductor devices, the integration density is largely determined by the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine patterning technology. However, the integration density of two-dimensional semiconductor devices is improving, but remains limited, due to the need for very expensive equipment such as miniaturized photolithography tools for patterning. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells are being proposed. Summary of the Invention

[0004] Some example implementations provide three-dimensional semiconductor memory devices with improved electrical characteristics and / or reliability.

[0005] Optionally or additionally, some example implementations provide methods for manufacturing three-dimensional semiconductor memory devices with improved electrical properties and / or reliability.

[0006] However, the exemplary embodiments are not limited to those described herein. The above and other aspects of the exemplary embodiments will become more apparent to those skilled in the art upon which they pertain by referring to the following detailed description of the exemplary embodiments.

[0007] According to some exemplary embodiments, a semiconductor memory device is provided, comprising: a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region being spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region being between the first impurity region and the second impurity region; a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction; and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film. The first gate electrode penetrates the channel region, and the first gate insulating film is located between the first gate electrode and the first semiconductor pattern.

[0008] According to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region being spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region being between the first impurity region and the second impurity region; a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction; and a second conductive connection electrode extending in the first direction, penetrating the second impurity region, and contacting the semiconductor pattern.

[0009] According to some example embodiments, a semiconductor memory device is provided, comprising: a peripheral circuit region on a substrate; and a cell array region stacked together with the peripheral circuit region in a first direction. The peripheral circuit region includes peripheral circuitry configured to control the control array region. The cell array region includes: a plurality of semiconductor patterns stacked on the substrate in the first direction, each semiconductor pattern including a first impurity region having a first conductivity type, a second impurity region having a second conductivity type different from the first conductivity type, and a channel region between the first and second impurity regions; a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction; and a first gate structure extending in the first direction and including a gate electrode and a gate insulating film. Each of the first conductive connection line and the gate electrode contacts the peripheral circuitry, the gate electrode penetrating the channel region.

[0010] According to some exemplary embodiments, a semiconductor memory device is provided, comprising: a first impurity region having a first conductivity type; a second impurity region having a second conductivity type different from the first conductivity type; a channel region defined between the first impurity region and the second impurity region; a first gate structure including a first gate electrode and a first gate insulating film, and extending elongated in a first direction, the first gate structure being between the first impurity region and the second impurity region, the first gate insulating film surrounding the periphery of the first gate electrode between the channel region and the first gate electrode; and a first conductive connection line extending in a second direction different from the first direction and contacting the first impurity region. The channel region surrounds at least a portion of the first gate structure.

[0011] According to some exemplary embodiments, a method for manufacturing a semiconductor memory device is provided, the method comprising: forming a molded structure on a substrate comprising a plurality of vertically stacked molded layers, each molded layer comprising a first insulating film and a second insulating film; forming a first to third hole having contact forms and a fourth hole having a line extending in a second direction different from a first direction, the first to third holes penetrating the molded structure and arranged sequentially in the first direction, the fourth hole being adjacent to the first hole; partially etching the second insulating film exposed by the first and second holes to form a channel recess; forming a gate insulating film and a channel region, the gate insulating film and the channel region filling the channel recess and comprising a semiconductor material; partially etching the second insulating film exposed by the first and second holes to form a channel recess. A second insulating film with three holes exposed is formed to form a source recess; a first impurity region is formed, which fills the source recess and includes a semiconductor material having a first conductivity type; the second insulating film exposed by a fourth hole is partially etched to form a drain recess for exposing a channel region; a second impurity region is formed, which fills a portion of the drain recess and includes a semiconductor material having a second conductivity type different from the first conductivity type; and a gate electrode, a first conductive connection line, and a second conductive connection line are formed, the gate electrode filling the first hole and the second hole, the first conductive connection line contacting the first impurity region and filling the third hole, and the second conductive connection line contacting the second impurity region and filling the remainder of the drain recess. Attached Figure Description

[0012] The above and other aspects and features of the exemplary embodiments will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1A and Figure 1B It is a circuit diagram of a unit cell of a semiconductor memory device according to some example embodiments;

[0014] Figure 2 It is used for explanation Figure 1A A diagram of the operations of a unit cell;

[0015] Figures 3 to 4B This is an example perspective view illustrating a semiconductor memory device according to some example embodiments;

[0016] Figure 5 This is a plan view illustrating a semiconductor memory device according to some example embodiments;

[0017] Figure 6 and Figure 7 It is along Figure 5 A cross-sectional view taken by lines AA and BB;

[0018] Figure 8A and Figure 8B These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0019] Figure 9 and Figure 10 These are diagrams used to illustrate semiconductor devices according to some exemplary embodiments;

[0020] Figure 11 and Figure 12 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0021] Figure 13 and Figure 14 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0022] Figure 15 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0023] Figure 16A and Figure 16B These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0024] Figure 17 and Figure 18 These are diagrams used to illustrate semiconductor devices according to some exemplary embodiments;

[0025] Figure 19 and Figure 20 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0026] Figure 21 and Figure 22 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0027] Figure 23 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0028] Figure 24 and Figure 25 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0029] Figure 26 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0030] Figure 27 and Figure 28 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0031] Figure 29 and Figure 30 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0032] Figure 31 and Figure 32 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0033] Figure 33 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0034] Figures 34 to 36 These are diagrams used to illustrate semiconductor memory devices according to some example embodiments;

[0035] Figure 37 and Figure 38 These are diagrams used to illustrate semiconductor memory devices according to some exemplary embodiments;

[0036] Figures 39A to 48 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor memory device according to some exemplary embodiments;

[0037] Figures 49A to 57B These are intermediate stage diagrams illustrating a method for manufacturing a semiconductor memory device according to some example embodiments; and

[0038] Figures 58 to 63 This is an intermediate stage diagram used to illustrate a method for manufacturing a semiconductor memory device according to some example embodiments. Detailed Implementation

[0039] Figure 1A and Figure 1B This is a circuit diagram of a unit cell of a semiconductor memory device according to some example implementations. Figure 2 It is used for explanation Figure 1A A diagram of the operations of the unit cell.

[0040] Reference Figure 1A and Figure 2 According to some example embodiments, a semiconductor memory device may include a semiconductor region including a p-type impurity region (p+), an n-type impurity region (n+), and a base region (base) between the p-type impurity region (p+) and the n-type impurity region (n+).

[0041] A semiconductor memory device may include, for example, a first gate electrode GE1 and a second gate electrode GE2 disposed on a base region (base). The first gate electrode GE1 may be closer to the p-type impurity region (p+) than the second gate electrode GE2 is disposed to the p-type impurity region (p+). A first control transistor T1 may be defined by the first gate electrode GE1 and the base region (base). A second control transistor T2 may be defined by the second gate electrode GE2 and the base region (base).

[0042] For example, the p-type impurity region (p+) can be or corresponds to the anode region, and the n-type impurity region (n+) can be or corresponds to the cathode region. The base region (base electrode) can be or corresponds to the channel region in which charge moves. The p-type impurity region (p+) can be connected to, for example, a bit line, and a bit line voltage V can be applied to it. BL The n-type impurity region (n+) can be connected to the common source region, and a source voltage V can be applied to it. S For example, the source voltage V S It can be or correspond to the ground voltage.

[0043] The p-type impurity region (p+) can be formed from a semiconductor material such as silicon doped with p-type impurities (such as boron), and the n-type impurity region (n+) can be formed from a semiconductor material such as silicon doped with n-type impurities (such as phosphorus and / or arsenic). As an example, the base region (base electrode) can be formed from an intrinsic semiconductor material that is undoped or only lightly doped. The base region (base electrode) can be formed from an undoped semiconductor material such as undoped silicon, for example, it may include undoped semiconductor materials such as undoped silicon. As another example, the base region (base electrode) can be formed from a semiconductor material doped with p-type impurities at a low concentration. When the base region (base electrode) is doped with p-type impurities, the doping concentration of the base region (base electrode) is lower than the doping concentration of the p-type impurity region (p+), for example, several orders of magnitude lower.

[0044] By applying a positive first voltage V1 to the first gate electrode GE1, a portion of the base region (base) can exhibit the characteristics of an n-type semiconductor material. By applying a negative second voltage V2 to the second gate electrode GE2, the remaining portion of the base region (base) can exhibit the characteristics of a p-type semiconductor material. Even when the base region (base) is formed of or includes intrinsic semiconductor material or p-type semiconductor material (e.g., lightly doped p-type semiconductor material), or when the base region (base) is formed of or includes intrinsic semiconductor material or p-type semiconductor material (e.g., lightly doped p-type semiconductor material), the electrical characteristics of the base region (base) can be modulated by applying voltages to the first gate electrode GE1 and the second gate electrode GE2. For example, with voltages applied to the first gate electrode GE1 and the second gate electrode GE2, the semiconductor region of the semiconductor memory device can have a pnpn structure. Optionally or additionally, the semiconductor memory device in the example embodiment may be a memory device including a thyristor structure, or may include a memory device including a thyristor structure.

[0045] The operation of the semiconductor memory device according to the example implementation will now be described.

[0046] The band diagrams of the p-type impurity region (p+), the base region (base electrode), and the n-type impurity region (n+) with a pnpn structure can be in the first state ( Figure 2 (Shown as solid lines in the conduction band CB and valence band VB). For example, the first state can be achieved at the bit line voltage V. BL and source voltage V S There is no voltage difference between them. In the first state, current may not flow between the p-type impurity region (p+) and the n-type impurity region (n+).

[0047] When the positive voltage is used as the bit line voltage V BL When applied to the p-type impurity region (p+), the band diagrams of the p-type impurity region (p+), the base region (base), and the n-type impurity region (n+) can be in a second state (as shown by the dashed lines for the conduction band CB and the valence band VB).

[0048] In the second state, holes applied to the p-type impurity region (p+) cannot overcome the energy barrier between the p-type impurity region (p+) and the base region (base). Similarly, electrons applied to the n-type impurity region (n+) cannot overcome the energy barrier between the n-type impurity region (n+) and the base region (base).

[0049] For example, although at bit line voltage V BL With source voltage V S There is a voltage difference between them, but the current does not flow well or not at all between the p-type impurity region (p+) and the n-type impurity region (n+).

[0050] Therefore, when a pulse voltage is applied to the first gate electrode GE1 and / or the second gate electrode GE2, the energy barrier between the p-type impurity region (p+) and the base region (base) and / or between the n-type impurity region (n+) and the base region (base) can be temporarily reduced.

[0051] When the energy barrier between the n-type impurity region (n+) and the base region (base) is lowered, electrons in the n-type impurity region (n+) can move to the base region (base) (i). When the energy barrier between the p-type impurity region (p+) and the base region (base) is lowered, holes in the p-type impurity region (p+) can move to the base region (base) (ii).

[0052] Electrons (i) moving to the base region (base) can lower the energy barrier between the p-type impurity region (p+) and the base region (base). Furthermore, holes (ii) moving to the base region (base) can lower the energy barrier between the n-type impurity region (n+) and the base region (base).

[0053] This positive feedback loop generates energy barriers between the p-type impurity region (p+) and the base region (base), as well as between the n-type impurity region (n+) and the base region (base). The band diagrams of the p-type impurity region (p+), the base region (base), and the n-type impurity region (n+) can be in a third state (alternating long and short dashed lines in the conduction band CB and valence band VB).

[0054] In the third state, the current between the p-type impurity region (p+) and the n-type impurity region (n+) can flow like that of a pin diode.

[0055] Unlike the configuration / example implementation described above, a pulse voltage may not be applied to the first gate electrode GE1 and / or the second gate electrode GE2. In such a case, by further increasing the bit line voltage V... BL and source voltage V S The voltage difference between them allows current to flow between the p-type impurity region (p+) and the n-type impurity region (n+) like a pin diode.

[0056] exist Figure 1B In the middle, select transistor T SEL It can be further positioned between the p-type impurity region (p+) and the n-type impurity region (n+). This is achieved by adjusting the force applied to the select transistor T. SEL Select voltage V SEL It can control the movement of charges between the p-type impurity region (p+) and the n-type impurity region (n+).

[0057] Optionally or additionally, by adjusting the application applied to the selection transistor T SEL Select voltage V SEL The current between the p-type impurity region (p+) and the n-type impurity region (n+) can be reduced or stopped / made to zero. Optionally or additionally, this can be achieved by reducing the bit line voltage V. BL and source voltage V S When the voltage difference between them decreases to a threshold or less, the current between the p-type impurity region (p+) and the n-type impurity region (n+) can stop / become 0.

[0058] Unlike the aforementioned configuration, the base region (base) may include an n-type base region and a p-type base region. The n-type base region (base) may be formed or include a semiconductor material doped with n-type impurities, and the p-type base region (base) may be formed or include a semiconductor material doped with p-type impurities. The n-type base region of the base region (base) is in contact with the p-type impurity region (p+). For example, the semiconductor region of a semiconductor memory device may have a pnpn structure when no voltage is applied to the first gate electrode GE1 and the second gate electrode GE2. The impurity concentration of the n-type base region of the base region (base) may be lower than the impurity concentration of the n-type impurity region (n+), for example, by one or more orders of magnitude. The impurity concentration of the p-type base region of the base region (base) may be lower than the impurity concentration of the p-type impurity region (p+), for example, by one or more orders of magnitude.

[0059] In such a case, as an example, either the first gate electrode GE1 or the second gate electrode GE2 may be absent. As another example, neither the first gate electrode GE1 nor the second gate electrode GE2 may be present. However, at least one of the first gate electrode GE1 and the second gate electrode GE2 can be formed to include the energy band of the regulated base region (base), such that at a lower bit line voltage V... BL Charges can move between the p-type impurity region (p+) and the n-type impurity region (n+).

[0060] Figures 3 to 4B This is an example perspective view illustrating a semiconductor memory device according to some example embodiments. For reference, Figures 3 to 4B It can have Figure 1A The circuit diagram shown is a perspective view of a semiconductor memory device.

[0061] First, refer to Figure 1A and Figure 3 A cell array region CA comprising multiple unit cells can be disposed on a substrate SUB; each of the multiple unit cells may include Figure 1A The features shown.

[0062] The substrate SUB can be or includes bulk silicon or SOI (silicon-on-insulator). Optionally, the substrate SUB can be a silicon substrate, or can be, but is not limited to, other materials such as: heterogeneous group IV semiconductor materials, such as silicon germanium, SGOI (silicon germanium-on-insulator); or group III-V compound semiconductor materials, such as indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, the substrate SUB will be described as a silicon (e.g., single-crystal silicon) substrate.

[0063] A stacked structure SS comprising first to third layers L1, L2, and L3 can be disposed on a substrate SUB. The first to third layers L1, L2, and L3 of the stacked structure SS can be stacked such that they are spaced apart from each other in a direction perpendicular to the top surface of the substrate SUB (i.e., third direction D3). Each of the first to third layers L1, L2, and L3 may include multiple semiconductor patterns SP, a first gate electrode GE1 and a second gate electrode GE2, a first conductive connection line EL_A, and a second conductive connection line EL_C.

[0064] From a planar perspective, each semiconductor pattern SP may include a shape in which multiple closed loops are connected. For example, each closed loop may have a circular or elliptical ring shape. Alternatively, each closed loop may have a ring shape with a rectangular shape having a chamfered and / or beveled outer peripheral surface, or another polygonal shape such as a hexagon or octagon.

[0065] Semiconductor patterns SP can include semiconductor materials such as silicon, germanium, silicon germanium (SiGe), silicon carbide (SiC), metal oxides, or two-dimensional (2D) materials. As an example, a semiconductor pattern SP can include polycrystalline silicon. As another example, a semiconductor pattern SP can include amorphous metal oxides, polycrystalline metal oxides, combinations of the amorphous metal oxides and the polycrystalline metal oxides, and / or the like. When the semiconductor pattern SP includes a metal oxide, the semiconductor pattern SP may include, for example, (but not limited to) one of the following: indium oxide, tin oxide, zinc oxide, In-Zn-based oxide (IZO), Sn-Zn-based oxide, Ba-Sn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide (IGO), In-Ga-Zn-based oxide (IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide (ITZO), In-W-Zn-based oxide (IWZO), Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-L a-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides.

[0066] Optionally or additionally, when the semiconductor pattern SP includes a two-dimensional material, the semiconductor pattern SP may include at least one of two-dimensional allotropes and two-dimensional compounds, and may include at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten sulfide (WS2).

[0067] Each semiconductor pattern SP may include a channel region SP_CH, a first impurity region SP_A, and a second impurity region SP_C. The channel region SP_CH and the second impurity region SP_C may have closed loops, such as closed circular loops or closed elliptical loops. The closed loop connecting the channel region SP_CH and the second impurity region SP_C may extend in a first direction D1. The first impurity region SP_A may have a rod-shaped / linear shape extending in a second direction D2. The channel region SP_CH may be interposed between the first impurity region SP_A and the second impurity region SP_C. The channel region SP_CH may correspond to a reference. Figure 2 The base region (base electrode) is described. The first impurity region SP_A can correspond to the reference. Figure 2 The described p-type impurity region (p+) and the second impurity region SP_C can correspond to the reference. Figure 2 The n-type impurity region (n+) is described.

[0068] Each of the first gate electrode GE1 and the second gate electrode GE2 may have a linear form and / or a cylindrical shape extending in a third direction D3. The first gate electrode GE1 may be spaced apart from the second gate electrode GE2 in a first direction D1. The first gate electrodes GE1 may be spaced apart from each other in a second direction D2, and the second gate electrodes GE2 may be spaced apart from each other in a second direction D2.

[0069] Each of the first gate electrode GE1 and the second gate electrode GE2 can penetrate the channel region SP_CH, for example, it can extend completely through the opening defined by the channel region SP_CH. Each of the first gate electrode GE1 and the second gate electrode GE2 can pass through a closed loop; this closed loop can be formed as a ring, circle, ellipse, polygon, etc. Each of the first gate electrode GE1 and the second gate electrode GE2 does not contact the channel region SP_CH, but can be spaced apart from the channel region SP_CH. The first gate electrode GE1 and the second gate electrode GE2 can be respectively / corresponding to Figure 1A and Figure 2 The gate electrode of the first control transistor T1 and the gate electrode of the second control transistor T2 are described in the figure.

[0070] The first conductive connection line EL_A may have a line / linear form and / or a strip shape extending in the second direction D2. The first conductive connection lines EL_A may be spaced apart from each other in the third direction D3. The first conductive connection line EL_A may contact / directly connect to the first impurity region SP_A and may be electrically connected to the first impurity region SP_A. The first conductive connection line EL_A may be / correspond to the bit line voltage ( Figure 1A V BL The bit line applied to the first impurity region SP_A.

[0071] The second conductive connection line EL_C can be in the form of a line / linear line or a pillar shape extending in the third direction D3. The second conductive connection line EL_C can be configured to be spaced apart from the second gate electrode GE2 in the first direction D1. The second conductive connection lines EL_C can be configured to be spaced apart from each other in the second direction D2.

[0072] The second conductive connection line EL_C can penetrate (e.g., can extend completely through) the second impurity region SP_C. The second conductive connection line EL_C can pass through a closed loop; this closed loop can have one of the following shapes: annular, circular, polygonal, etc. The second conductive connection line EL_C contacts the second impurity region SP_C and can be electrically connected to the second impurity region SP_C. The second conductive connection line EL_C can be connected to the second impurity regions SP_C spaced apart from each other on the third direction D3. The second conductive connection line EL_C can be / corresponds to the source voltage ( Figure 1A V S The source supply line is applied to the second impurity region SP_C.

[0073] The first gate electrode GE1, the second gate electrode GE2, the first conductive connection line EL_A, and the second conductive connection line EL_C may each include a conductive material. For example, each of the first gate electrode GE1, the second gate electrode GE2, the first conductive connection line EL_A, and the second conductive connection line EL_C may include, but is not limited to, one of the following: conductive metal nitrides (titanium nitride, tantalum nitride, niobium nitride (NbN) etc.), metals (tungsten, titanium, tantalum, cobalt, ruthenium etc.), and metal-semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0074] The first layer L1, of the first to third layers L1, L2, and L3, will be described in representative detail. Semiconductor patterns SP in the first layer L1 can be arranged in the second direction D2. The semiconductor patterns SP in the first layer L1 can be at the same height. The semiconductor patterns SP in the first layer L1 can share a first impurity region SP_A extending in the second direction D2. In the semiconductor patterns SP disposed in the first layer L1, channel regions SP_CH can be spaced apart from each other in the second direction D2, and second impurity regions SP_C can be spaced apart from each other in the second direction D2. The channel regions SP_CH spaced apart in the second direction D2 can be connected to the first impurity region SP_A. A first gate electrode GE1, a second gate electrode GE2, and a second conductive connection line EL_C are arranged sequentially in the first direction D1 and can pass through the channel regions SP_CH and the second impurity region SP_C connected in the first direction D1. The semiconductor patterns SP arranged in the second direction D2 can be connected to the first conductive connection line EL_A disposed in the first layer L1.

[0075] Although not shown, the gate insulating film may be interposed between the first gate electrode GE1 and the channel region SP_CH, and between the second gate electrode GE2 and the channel region SP_CH. The gate insulating film may include at least one of a high-dielectric-constant insulating film, a silicon oxide film, a silicon nitride film, and a silicon nitride film. As an example, the high-dielectric-constant insulating film may include at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0076] Although not shown, the empty spaces within the stacked structure SS can be filled with an insulating material. For example, the insulating material may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxide nitride film. A wiring layer electrically connected to the cell array region CA can be disposed on the stacked structure SS. Although not shown, peripheral circuitry for operating the cell array region CA can be formed on the substrate SUB. The peripheral circuitry and the cell array region CA can be connected, for example, using this wiring layer.

[0077] Unlike the aforementioned configuration, the first impurity region SP_A can correspond to the reference. Figure 2 The described n-type impurity region (n+), the second impurity region SP_C can correspond to the reference. Figure 2 The p-type impurity region (p+) is described. In this case, the second conductive connection EL_C can be / corresponds to the bit line voltage ( Figure 1A V BL ) applied to Figure 1A and Figure 2 The bit line of the p-type impurity region (p+) described in the diagram. The first conductive connection line EL_A can be / corresponds to the source voltage V. S Apply to Figure 1A and Figure 2 The source supply line of the n-type impurity region (n+) described in the text.

[0078] The following will assume that the first impurity region SP_A corresponds to the reference. Figure 2 The described p-type impurity region (p+) and the second impurity region SP_C correspond to the use of Figure 2 A description is provided for the case of the n-type impurity region (n+).

[0079] The main focus will be on usage Figure 3 The description is based on the different key points. Figure 4A and Figure 4B The implementation method.

[0080] Reference Figure 4A and Figure 4BThe peripheral circuit area PER and the cell array area CA can be stacked in the vertical direction (i.e., the third direction D3).

[0081] exist Figure 4A In this embodiment, the peripheral circuit region PER can be disposed between the substrate SUB and the cell array region CA. The peripheral circuit region PER may include peripheral circuit transistors, such as MOSFET transistors and / or bipolar transistors, formed on the substrate SUB. The peripheral circuit region PER may include circuitry for operating the cell array region CA according to an exemplary embodiment.

[0082] The cell array region CA can be electrically connected to the peripheral circuit region PER via, for example, at least one through electrode. Optionally or additionally, the first gate electrode GE1, the second gate electrode GE2, and the second conductive connection line EL_C of the cell array region CA can be directly connected to the peripheral circuit region PER.

[0083] exist Figure 4B In this configuration, the cell array region CA can be disposed on the substrate SUB. The peripheral circuit region PER can be disposed on the cell array region CA. As described above, the peripheral circuit region PER can include circuitry for operating the cell array region CA.

[0084] As an example, the first direction D1, the second direction D2, and the third direction D3 can be perpendicular to each other, but are not limited thereto. Furthermore, the first direction D1 and the second direction D2 can be parallel to the top surface of the substrate SUB, and the third direction D3 can be perpendicular to the top surface of the substrate SUB.

[0085] Figure 5 This is a plan view illustrating a semiconductor memory device according to some example embodiments. Figure 6 and Figure 7 They are respectively along Figure 5 The cross-sectional view is taken by lines AA and BB. For ease of description, a brief description will be provided with reference to [reference needed]. Figure 1A , Figure 2 and Figure 3 The repeated parts of the description.

[0086] Reference Figures 5 to 7 According to some example embodiments, a semiconductor memory device may include a semiconductor pattern SP, a first conductive connection line EL_A, a second conductive connection line EL_C, a first gate structure GS1, and a second gate structure GS2.

[0087] A molded structure MIL can be disposed on a substrate SUB. The molded structure MIL may include a first molded insulating layer ILD1 and a second molded insulating layer ILD2. The molded structure MIL may include a first molded insulating layer ILD1 and a second molded insulating layer ILD2 alternately stacked on the substrate SUB.

[0088] exist Figure 6 and Figure 7 Although four first molded insulating layers ILD1 and three second molded insulating layers ILD2 are shown, this is only for ease of description and the example embodiment is not limited thereto. Although the layer immediately adjacent to the substrate SUB of the molded structure MIL is shown as the first molded insulating layer ILD1, the example embodiment is not limited thereto.

[0089] The first molding insulating layer ILD1 and the second molding insulating layer ILD2 may each include an insulating material. The first insulating material included in the first molding insulating layer ILD1 may have an etch selectivity ratio relative to the second insulating material included in the second molding insulating layer ILD2, for example, it may be etched more slowly than the second insulating material included in the second molding insulating layer ILD2. Each of the first molding insulating layer ILD1 and the second molding insulating layer ILD2 may include at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, and a carbon-containing silicon oxide nitride film, and may include materials that are the same as or different from each other. As an example, the first molding insulating layer ILD1 may include a silicon oxide film, and the second molding insulating layer ILD2 may include a silicon nitride film. For example, the molding structure MIL may be or include an ON (oxide / nitride) molding structure.

[0090] Multiple semiconductor patterns SP can be disposed on a substrate SUB. The semiconductor patterns SP can be disposed along a second direction D2. Furthermore, the multiple semiconductor patterns SP can be stacked along a third direction D3. The semiconductor patterns SP stacked on the third direction D3 can be spaced apart from each other. The semiconductor patterns SP stacked on the third direction D3 can be disposed between adjacent first molding insulating layers ILD1 or between adjacent second molding insulating layers ILD2. As an example, in a semiconductor memory device according to some exemplary embodiments, the first molding insulating layers ILD1 can be disposed between semiconductor patterns SP that are adjacent to each other in the third direction D3. Furthermore, the second molding insulating layers ILD2 can be disposed between semiconductor patterns SP that are adjacent to each other in the second direction D2. The second molding insulating layers ILD2 can contact the semiconductor patterns SP that are adjacent to each other in the second direction D2.

[0091] For example, a semiconductor pattern SP may include a first semiconductor pattern and a second semiconductor pattern disposed along a second direction D2. Each of the first and second semiconductor patterns may include a first impurity region SP_A, a second impurity region SP_C, and a channel region SP_CH between the first impurity region SP_A and the second impurity region SP_C. The channel region SP_CH and the second impurity region SP_C of the first semiconductor pattern may be spaced apart from the channel region SP_CH and the second impurity region SP_C of the second semiconductor pattern along the second direction D2. Furthermore, the first impurity region SP_A of the first semiconductor pattern and the first impurity region SP_A of the second semiconductor pattern may be connected to each other. The first and second semiconductor patterns may share the first impurity region SP_A extending along the second direction D2. Each of the first and second semiconductor patterns may include a channel region SP_CH and a second impurity region SP_C, each of the channel region SP_CH and the second impurity region SP_C having a form in which closed loops are connected.

[0092] Semiconductor patterns SP can include semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, metal oxides, or two-dimensional materials.

[0093] In a semiconductor memory device according to some example embodiments, the channel region SP_CH of the semiconductor pattern SP can be formed of an undoped semiconductor material or a semiconductor material doped with p-type impurities, or may include an undoped semiconductor material or a semiconductor material doped with p-type impurities. When the channel region SP_CH is formed of or includes a semiconductor material doped with p-type impurities, the concentration of p-type impurities in the channel region SP_CH is lower than the concentration of p-type impurities in the first impurity region SP_A, for example, at least one order of magnitude lower.

[0094] Each of the first gate structure GS1 and the second gate structure GS2 can be disposed on the substrate SUB. Each of the first gate structure GS1 and the second gate structure GS2 can extend long in the third direction D3. Each of the first gate structure GS1 and the second gate structure GS2 can penetrate the channel region SP_CH. Each of the first gate structure GS1 and the second gate structure GS2 can penetrate the molded structure MIL.

[0095] At least a portion of each of the first gate structure GS1 and the second gate structure GS2 may be surrounded by a channel region SP_CH. In a semiconductor memory device according to some example embodiments, in the region where the first gate structure GS1 and the semiconductor pattern SP intersect each other, the channel region SP_CH may completely surround the sidewall of the first gate structure GS1 extending in the third direction D3. In the region where the second gate structure GS2 and the semiconductor pattern SP intersect each other, the channel region SP_CH may completely surround the sidewall of the second gate structure GS2 extending in the third direction D3.

[0096] The first gate structure GS1 may include a first gate electrode GE1 and a first gate insulating film GI_1. The first gate electrode GE1 may extend on the third direction D3 and penetrate the channel region SP_CH. The first gate insulating film GI_1 may be disposed between the first gate electrode GE1 and the semiconductor pattern SP.

[0097] The second gate structure GS2 may include a second gate electrode GE2 and a second gate insulating film GI_2. The second gate electrode GE2 may extend on the third-direction D3 and penetrate (e.g., completely penetrate or pass through) the channel region SP_CH. The second gate insulating film GI_2 may be disposed between the second gate electrode GE2 and the semiconductor pattern SP.

[0098] Although the first gate electrode GE1 and the second gate electrode GE2 are shown as a single film, this is only for ease of description, and the example implementation is not limited thereto. As an example, each of the first gate electrode GE1 and the second gate electrode GE2 may include a work function regulating film. To make the threshold potentials of the first gate electrode GE1 and the second gate electrode GE2 different from each other, the work function regulating film of the first gate electrode GE1 and the work function regulating film of the second gate electrode GE2 may include different materials. Alternatively or additionally, the work function regulating film of the first gate electrode GE1 and the work function regulating film of the second gate electrode GE2 may include the same material of different thicknesses.

[0099] The first gate electrode GE1 and the second gate electrode GE2 may each include at least one of a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0100] In a semiconductor device according to some example embodiments, the first gate insulating film GI_1 and the second gate insulating film GI_2 may include at least one of silicon oxide, silicon oxide nitride and silicon nitride, and may include materials that are the same as or different from each other.

[0101] The first gate insulating film GI_1 and the second gate insulating film GI_2 can have the same thickness or different thicknesses.

[0102] Unlike the configuration shown, the first gate insulating film GI_1 may extend between the first gate electrode GE1 and the first molded insulating layer ILD1, and the second gate insulating film GI_2 may extend between the second gate electrode GE2 and the first molded insulating layer ILD1.

[0103] The first conductive connection line EL_A can be connected to the first impurity region SP_A of the semiconductor pattern SP. The first conductive connection line EL_A can extend in the second direction D2. The first conductive connection line EL_A can be parallel to the top surface of the substrate SUB. The first conductive connection line EL_A can be connected to a first semiconductor pattern and a second semiconductor pattern disposed along the second direction D2.

[0104] First conductive connection lines EL_A can be disposed between first molded insulating layers ILD1 spaced apart from each other along a third direction D3. Adjacent first conductive connection lines EL_A on the third direction D3 are separated from each other by the first molded insulating layers ILD1 and a first electrode separation pattern ESL1. The first electrode separation pattern ESL1 can extend in a second direction D2. The first electrode separation pattern ESL1 may include insulating material.

[0105] The second conductive connection line EL_C can extend on the third direction D3 and can penetrate the second impurity region SP_C. The second conductive connection line EL_C contacts the semiconductor pattern SP. The second conductive connection line EL_C can be electrically connected to the second impurity region SP_C.

[0106] In the region where the second conductive connection line EL_C intersects with the semiconductor pattern SP, the second impurity region SP_C can completely surround the sidewall of the second conductive connection line EL_C extending in the third direction D3.

[0107] The first conductive connection line EL_A and the second conductive connection line EL_C may each include at least one of conductive metal nitride, metal, and metal-semiconductor compound.

[0108] In a semiconductor memory device according to some example embodiments, the first conductive connection line EL_A and the second conductive connection line EL_C may have an intersection point (XP) structure.

[0109] Figure 8A and Figure 8B This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 9 and Figure 10 This is a diagram used to illustrate a semiconductor device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 3 and Figures 5 to 7 The key points described are different.

[0110] Reference Figure 8A and Figure 8B In a semiconductor memory device according to some example embodiments, the first gate insulating film GI_1 includes a first interface insulating film GI_11 and a first high dielectric constant film GI_12, and the second gate insulating film GI_2 may include a second interface insulating film GI_21 and a second high dielectric constant film GI_22.

[0111] A first high dielectric constant film GI_12 may be disposed between the first gate electrode GE1 and the semiconductor pattern SP, and between the first gate electrode GE1 and the first molded insulating layer ILD1. A second high dielectric constant film GI_22 may be disposed between the second gate electrode GE2 and the semiconductor pattern SP, and between the second gate electrode GE2 and the first molded insulating layer ILD1.

[0112] When the semiconductor pattern SP includes silicon, the first interface insulating film GI_11 and the second interface insulating film GI_21 may include, for example, silicon oxide. However, as the materials included in the semiconductor pattern SP change, the materials included in the first interface insulating film GI_11 and the second interface insulating film GI_21 may also change. The first high dielectric constant film GI_12 and the second high dielectric constant film GI_22 may include, for example, high dielectric constant insulating films.

[0113] exist Figure 8A In this process, the first high dielectric constant film GI_12 and the second high dielectric constant film GI_22 may not be disposed between the bottom surface of the first gate electrode GE1 and the top surface of the substrate SUB, or between the bottom surface of the second gate electrode GE2 and the top surface of the substrate SUB.

[0114] On the other hand, Figure 8B In this process, the first high dielectric constant film GI_12 and the second high dielectric constant film GI_22 can be respectively disposed between the bottom surface of the first gate electrode GE1 and the top surface of the substrate SUB, and between the bottom surface of the second gate electrode GE2 and the top surface of the substrate SUB.

[0115] Reference Figure 9 and Figure 10 The semiconductor memory device according to some example embodiments may also include a fill insulating pattern FIP that fills at least one of a space defined by a first gate electrode GE1, a space defined by a second gate electrode GE2, and a space defined by a second conductive connection line EL_C.

[0116] The sidewalls of the FIP filled with insulating pattern can be covered by the first gate electrode GE1, the second gate electrode GE2, and the second conductive connection line EL_C.

[0117] The filled insulating pattern FIP may include at least one of, for example, silicon oxide film, silicon nitride film, silicon nitride film, carbon-containing silicon oxide film, carbon-containing silicon nitride film, and carbon-containing silicon nitride film.

[0118] Unlike the configuration shown, the filler insulating pattern FIP can be disposed in one or both of the first gate electrode GE1, the second gate electrode GE2, and the second conductive connection line EL_C.

[0119] Figure 11 and Figure 12 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 13 and Figure 14 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 15 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 16A and Figure 16B This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 3 and Figures 5 to 7 The key points described are different.

[0120] Reference Figures 11 to 15 In a semiconductor memory device according to some example embodiments, the channel region SP_CH may include an n-type base channel portion SP_CHN and a p-type base channel portion SP_CHP.

[0121] The n-type base channel portion SP_CHN can contact the first impurity region SP_A, and the p-type base channel portion SP_CHP can contact the second impurity region SP_C. The n-type base channel portion SP_CHN can be located between the first impurity region SP_A and the p-type base channel portion SP_CHP.

[0122] The n-type base channel portion SP_CHN can be formed from a semiconductor material doped with n-type impurities. The concentration of n-type impurities in the n-type base channel portion SP_CHN is lower than the concentration of n-type impurities in the second impurity region SP_C. The p-type base channel portion SP_CHP can be formed from a semiconductor material doped with p-type impurities. The concentration of p-type impurities in the p-type base channel portion SP_CHP is lower than the concentration of p-type impurities in the first impurity region SP_A.

[0123] exist Figures 11 to 15In the illustration, the n-type base channel portion SP_CHN is shown in contact with the second gate insulating film GI_2, but the example embodiment is not limited to this. Of course, a portion of the p-type base channel portion SP_CHP can be interposed between the n-type base channel portion SP_CHN and the second gate insulating film GI_2.

[0124] Furthermore, a portion of the n-type base channel portion SP_CHN is shown recessed into the p-type base channel portion SP_CHP, but the implementation is not limited to this. The forms of the n-type base channel portion SP_CHN and the p-type base channel portion SP_CHP can, of course, vary depending on the order in which they are manufactured.

[0125] exist Figure 11 and Figure 12 In the process, the first gate electrode GE1 can penetrate the n-type base channel portion SP_CHN of the channel region SP_CH. The second gate electrode GE2 can penetrate the p-type base channel portion SP_CHP of the channel region SP_CH.

[0126] exist Figure 13 and Figure 14 In this configuration, the first gate structure GS1 can be replaced by a vertically insulating structure VIP. That is, the vertically insulating structure VIP can penetrate the n-type base channel portion SP_CHN of the channel region SP_CH. The vertically insulating structure VIP can extend onto the third direction D3. The vertically insulating structure VIP can include at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, and a carbon-containing silicon oxide nitride film.

[0127] Unlike the configuration shown, the vertically insulated structure VIP can replace the second gate structure GS2.

[0128] exist Figure 15 In this configuration, a gate structure penetrating the channel region SP_CH may not be required between the first conductive connection line EL_A and the second conductive connection line EL_C. That is, the vertical insulating structure VIP can penetrate both the n-type base channel portion SP_CHN and the p-type base channel portion SP_CHP.

[0129] Reference Figure 16A and Figure 16B In a semiconductor device according to some example embodiments, a portion of the outer wall of the second conductive connection line EL_C may be recessed in the central direction of the second conductive connection line EL_C.

[0130] The portion of the second conductive connection line EL_C facing the second gate electrode GE2 can be recessed in the center direction of the second conductive connection line EL_C.

[0131] The second impurity region SP_C can have a cylindrical shape extending in the third direction D3. The second impurity region SP_C can surround the outer wall of the second conductive connection line EL_C.

[0132] Figure 17 and Figure 18 This is a diagram used to illustrate a semiconductor device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 3 and Figures 5 to 7 The key points described are different.

[0133] Reference Figure 17 and Figure 18 The semiconductor memory device according to some example embodiments may also include a third gate structure GS3 that penetrates the channel region SP_CH.

[0134] The third gate structure GS3 can be disposed on the substrate SUB. The third gate structure GS3 can extend a long distance on the third direction D3. Each third gate structure GS3 can penetrate the molded structure MIL.

[0135] At least a portion of the third gate structure GS3 may be surrounded by the channel region SP_CH. In the region where the third gate structure GS3 and the semiconductor pattern SP intersect each other, the channel region SP_CH may completely surround the sidewalls of the third gate structure GS3 extending on the third-direction D3.

[0136] The first to third gate structures GS1, GS2 and GS3 can be arranged sequentially on the first direction D1 based on the first conductive connection line EL_A.

[0137] The third gate structure GS3 may include a third gate electrode GE3 and a third gate insulating film GI_3. The third gate electrode GE3 may extend on the third-direction D3 and penetrate the channel region SP_CH. The third gate insulating film GI_3 may be disposed between the third gate electrode GE3 and the semiconductor pattern SP. The third gate insulating film GI_3 may be disposed between the third gate electrode GE3 and the channel region SP_CH. The third gate electrode GE3 may correspond to... Figure 1B Selecting transistor T SEL The gate electrode.

[0138] The third gate electrode GE3 may each include at least one of a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0139] Figure 19 and Figure 20 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 17 and Figure 18 The key points described are different.

[0140] Reference Figure 19 and Figure 20 In a semiconductor memory device according to some example embodiments, the channel region SP_CH may include an n-type base channel portion SP_CHN, a p-type base channel portion SP_CHP, and an undoped base channel portion SP_CHI.

[0141] The n-type base channel portion SP_CHN is in contact with the first impurity region SP_A. The undoped base channel portion SP_CHI can be in contact with the second impurity region SP_C. The p-type base channel portion SP_CHP is disposed between the n-type base channel portion SP_CHN and the undoped base channel portion SP_CHI. The p-type base channel portion SP_CHP is in contact with the n-type base channel portion SP_CHN and the undoped base channel portion SP_CHI.

[0142] The n-type base channel portion SP_CHN can be formed from a semiconductor material doped with n-type impurities. The concentration of n-type impurities in the n-type base channel portion SP_CHN is lower than the concentration of n-type impurities in the second impurity region SP_C. The p-type base channel portion SP_CHP can be formed from a semiconductor material doped with p-type impurities. The concentration of p-type impurities in the p-type base channel portion SP_CHP is lower than the concentration of p-type impurities in the first impurity region SP_A.

[0143] As an example, the undoped base channel portion SP_CHI can be formed from undoped semiconductor material.

[0144] As another example, the base channel portion SP_CHI can be formed from a semiconductor material doped with p-type impurities. In this case, the concentration of p-type impurities in the base channel portion SP_CHI is lower than the concentration of p-type impurities in the p-type base channel portion SP_CHP.

[0145] Figure 21 and Figure 22 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 17 and Figure 18 The key points described are different.

[0146] Reference Figure 21 and Figure 22 In a semiconductor memory device according to some example embodiments, the second impurity region SP_C, like the first impurity region SP_A, can extend long in the second direction D2.

[0147] Multiple semiconductor patterns SP arranged in the second direction D2 can share a first impurity region SP_A and a second impurity region SP_C. The channel region SP_CH between the first impurity region SP_A and the second impurity region SP_C can be arranged to be spaced apart from each other in the second direction D2.

[0148] The second conductive connection line EL_C can be a conductive plate electrode EL_PC with a plate shape. The conductive plate electrode EL_PC does not penetrate the semiconductor pattern SP. The conductive plate electrode EL_PC is in contact with one end of the semiconductor pattern SP. The conductive plate electrode EL_PC is in contact with the second impurity region SP_C.

[0149] When the semiconductor pattern SP includes a first semiconductor pattern and a second semiconductor pattern disposed along the second direction D2, the conductive plate electrode EL_PC can contact one end of the first semiconductor pattern and one end of the second semiconductor pattern (e.g., direct contact).

[0150] The conductive plate electrode EL_PC can also be connected to second impurity regions SP_C spaced apart from each other on the third direction D3. The conductive plate electrode EL_PC also covers the sidewalls of the first molded insulating layer ILD1 between the second impurity regions SP_C. The conductive plate electrode EL_PC is separated by a second electrode separator pattern ESL2. The second electrode separator pattern ESL2 can extend long in the second direction D2. The second electrode separator pattern ESL2 may include an insulating material.

[0151] Figure 23 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 21 and Figure 22 The key points described are different.

[0152] Reference Figure 23 In a semiconductor memory device according to some example embodiments, the channel region SP_CH may include an n-type base channel portion SP_CHN, a p-type base channel portion SP_CHP, and an undoped (e.g., intrinsic) base channel portion SP_CHI.

[0153] The explanation and use of the n-type base channel portion SP_CHN, the p-type base channel portion SP_CHP, and the undoped base channel portion SP_CHI Figure 19 and Figure 20 The descriptions are essentially the same, so no further explanation will be provided below.

[0154] Figure 24 and Figure 25 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 26This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 3 and Figures 5 to 7 The key points described are different.

[0155] Reference Figures 24 to 26 In a semiconductor memory device according to some example embodiments, semiconductor patterns SP and a first molded insulating layer ILD1 alternately stacked on a third-direction D3 can be separated by a vertical insulating structure VIP.

[0156] The vertical insulating structure VIP can extend in the first direction D1. The vertical insulating structure VIP is disposed on the substrate SUB and can extend in the third direction D3. The vertical insulating structure VIP can pass through the semiconductor pattern SP and the first molded insulating layer ILD1.

[0157] The semiconductor pattern SP arranged on the first direction D1 and the third direction D3 can be defined by a vertical insulating structure VIP. In the semiconductor pattern SP, the channel region SP_CH and the second impurity region SP_C can be defined by the vertical insulating structure VIP.

[0158] The semiconductor pattern SP and the first molded insulating layer ILD1 can contact the vertical insulating structure VIP.

[0159] exist Figure 24 and Figure 25 In this configuration, the vertical insulating structure VIP does not cut the first impurity region SP_A of the semiconductor pattern SP. That is, the channel region SP_CH and the second impurity region SP_C, which are separated from each other by the vertical insulating structure VIP in the second direction D2, can be connected through the first impurity region SP_A.

[0160] exist Figure 26 In this configuration, the vertical insulating structure VIP can also cut the first impurity region SP_A. The vertical insulating structure VIP can completely separate the semiconductor pattern SP in the second direction D2.

[0161] Figure 27 and Figure 28 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 29 and Figure 30 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 31 and Figure 32 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 3 and Figures 5 to 7 The key points described are different.

[0162] Reference Figure 27and Figure 28 In a semiconductor memory device according to some example embodiments, a vertical insulating pattern VIP can be cut between a molded structure MIL between semiconductor patterns SP arranged in a second direction D2.

[0163] The vertical insulation pattern VIP can define the area in the second direction D2 in which the channel region SP_CH is formed. When the channel region SP_CH is formed, the vertical insulation pattern VIP can prevent adjacent channel regions SP_CH in the second direction D2 from contacting each other.

[0164] Reference Figure 29 and Figure 30 According to some example embodiments, the semiconductor memory device may also include an air gap AG, which is disposed between semiconductor patterns SP that are adjacent to each other in the second direction D2.

[0165] The air gap AG can be disposed between adjacent first semiconductor patterns and second semiconductor patterns in the second direction D2. The air gap AG can also be disposed between adjacent channel regions SP_CH and adjacent second impurity regions SP_C in the second direction D2.

[0166] The air gap AG can be defined by the air gap cover film AIR_CAP, the first molded insulating layer ILD1, the semiconductor pattern SP, and the substrate SUB.

[0167] Reference Figure 31 and Figure 32 According to some example embodiments, the semiconductor memory device may also include a shielding pattern MET_SH disposed between semiconductor patterns SP that are adjacent to each other in the second direction D2.

[0168] The shielding pattern MET_SH can extend long in the first direction D1. The shielding pattern MET_SH can penetrate the molded structure MIL.

[0169] The shielding pattern MET_SH can be disposed between adjacent first and second semiconductor patterns in the second direction D2. The shielding pattern MET_SH can also be disposed between adjacent channel regions SP_CH in the second direction D2 and between adjacent second impurity regions SP_C in the second direction D2.

[0170] The shielding pattern MET_SH may include a conductive material. The shielding pattern MET_SH may include at least one of a conductive metal nitride, a metal, and a metal-semiconductor compound. A constant voltage may be applied to the shielding pattern MET_SH.

[0171] Figure 33This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. For ease of description, the main description will focus on its use. Figure 31 and Figure 32 The key points described are different.

[0172] Reference Figure 33 In a semiconductor device according to some example embodiments, the second conductive connection line EL_C may be a conductive plate electrode EL_PC with a plate shape.

[0173] The conductive plate electrode EL_PC can be connected to the shielding pattern MET_SH. The second impurity regions SP_C can be separated from each other in the second direction D2 by the shielding pattern MET_SH.

[0174] Figures 34 to 36 These are diagrams used to illustrate semiconductor memory devices according to some example embodiments. For ease of description, the main focus will be on their use. Figure 3 and Figures 5 to 7 The key points described are different.

[0175] Reference Figure 34 and Figure 35 , refer to Figure 3 The cell array region CA and the peripheral circuit region PER described herein can be provided on the substrate SUB. The cell array region CA and the peripheral circuit region PER can be stacked on a third-party D3.

[0176] exist Figure 34 In this configuration, a peripheral circuit region (PER) can be provided between the cell array region (CA) and the substrate (SUB). The peripheral circuit region (PER) may include peripheral circuits (PTR, PIL, and PCNT) for operating the cell array region (CA), and may include transistors such as planar transistors. At least some of the peripheral circuits (PTR, PIL, and PCNT) may be formed in a peripheral circuit insulating film (ILD).

[0177] For example, the etch stop layer (ESL) can be additionally interposed between the cell array region (CA) and the peripheral circuit region (PER). As another example, the etch stop layer (ESL) may not be interposed between the cell array region (CA) and the peripheral circuit region (PER).

[0178] Specifically, the peripheral circuitry formed in the peripheral circuitry region PER may include a peripheral transistor PTR, a peripheral wiring PIL on the peripheral transistor PTR, and a peripheral contact PCNT perpendicularly connected to the peripheral wiring PIL. As an example, the first gate electrode GE1, the second gate electrode GE2, and the second conductive connection line EL_C penetrate the etch stop layer ESL and can be electrically connected to the peripheral wiring PIL. Although not shown, the first conductive connection line EL_A can be connected to the peripheral wiring PIL via a through electrode or the like.

[0179] As referenced above Figure 4A The semiconductor memory device described in some example embodiments may have a cell-on-periphery (COP) structure in which memory cells are provided on a peripheral circuit region. By three-dimensionally stacking the peripheral circuit region PER and the cell array region CA, the area of ​​the semiconductor memory chip can be reduced and a high degree of circuit integration can be achieved.

[0180] exist Figure 35 In this configuration, the cell array region CA can be provided on the substrate SUB. The upper substrate SUB2 can be provided on the cell array region CA. The peripheral circuit region PER can be provided on the upper substrate SUB2. The peripheral circuit region PER may include peripheral circuitry for operating the cell array region CA.

[0181] The formation of a semiconductor memory device according to some example embodiments may include forming a cell array region CA on a substrate SUB, forming a peripheral circuit region PER on an upper substrate SUB2, and attaching the upper substrate SUB2 to the cell array region CA by wafer bonding.

[0182] As referenced above Figure 4B The semiconductor memory device described in some example embodiments may include a peripheral circuit region (PER) provided on the periphery-on-cell (POC) structure of the memory cell. By three-dimensionally stacking the cell array region (CA) and the peripheral circuit region (PER), the area of ​​the semiconductor memory chip can be reduced and a high degree of circuit integration can be achieved.

[0183] Reference Figure 36 In a semiconductor memory device according to some example embodiments, the channel region SP_CH and the first impurity region SP_A may be disposed around the second impurity region SP_C.

[0184] The channel regions SP_CH, which are spaced apart from each other in the first direction D1, can share the second impurity region SP_C. By placing the two channel regions SP_CH, which are spaced apart from each other in the first direction D1, between the first impurity regions SP_A, which are adjacent to each other in the first direction D1, the area of ​​the semiconductor memory chip can be reduced and a high degree of circuit integration can be achieved.

[0185] Figure 37 and Figure 38 This is a diagram used to illustrate a semiconductor memory device according to some example embodiments. Figure 37 This is a plan view used to illustrate a semiconductor memory device according to some example embodiments. Figure 38 It is along Figure 37 The sectional view taken by the CC line.

[0186] The component separator layer (DTI) can extend long in the fourth direction (D4). The component separator layer (DTI) can be formed in the substrate (SUB). The component separator layer (DTI) can be used to separate adjacent memory cells in the fifth direction (D5). The component separator layer (DTI) can include at least one of, for example, silicon oxide, silicon nitride, and silicon oxide nitride.

[0187] The first impurity region SP_A and the first conductive connection line EL_A in contact with the first impurity region SP_A can be disposed between adjacent component separator layers DTI. The first impurity region SP_A and the first conductive connection line EL_A can be disposed in the substrate SUB. The first conductive connection line EL_A can be in the form of a line or a pillar.

[0188] The first impurity region SP_A can be formed along the sidewall and bottom surface of the anode hole T_A. The first conductive connection line EL_A can fill the space defined by the first impurity region SP_A.

[0189] The second impurity region SP_C can extend extensively in the fifth direction D5. A plate-shaped second conductive connection line EL_PC extending in the fifth direction D5 can be disposed on the second impurity region SP_C.

[0190] The second impurity region SP_C can be formed along the sidewalls and bottom surface of the cathode trench T_C. The second conductive connection line EL_PC can fill the space defined by the second impurity region SP_C.

[0191] The first conductive connection line EL_A can be spaced apart from the second conductive connection line EL_PC in the fourth direction D4.

[0192] The fourth to sixth gate structures GS4, GS5, and GS6, buried in the substrate SUB, can be disposed between the first impurity region SP_A and the second impurity region SP_C. Each of the fourth to sixth gate structures GS4, GS5, and GS6 can extend in the fifth direction D5. The fourth to sixth gate structures GS4, GS5, and GS6 can be arranged in the fourth direction D4.

[0193] The fourth to sixth gate structures GS4, GS5, and GS6 can pass through the composite channel region SP_CCH, which is defined between the first impurity region SP_A and the second impurity region SP_C. The composite channel region SP_CCH can be defined between adjacent element separator layers DTI in the fifth direction D5.

[0194] The composite channel region SP_CCH may include a portion of the substrate SUB and a deposited semiconductor film DP_CH. The portion of the substrate SUB may include a p-type semiconductor material. The deposited semiconductor film DP_CH may be formed from undoped semiconductor material or p-type semiconductor material. Even if the composite channel region SP_CCH has p-type electrical characteristics, the concentration of p-type impurities in the substrate SUB and the deposited semiconductor film DP_CH is lower than the concentration of p-type impurities in the first conductive connection line EL_A.

[0195] The fourth to sixth gate structures GS4, GS5, and GS6 can each include fourth to sixth gate electrodes GE4, GE5, and GE6, and fourth to sixth gate insulating films GI_4, GI_5, and GI_6, respectively. The fourth gate electrode GE4 can be... Figure 1B The first control transistor T1's gate electrode, and the fifth gate electrode GE5 can be... Figure 1B The gate electrode of the second control transistor T2. The sixth gate electrode GE6 can be Figure 1B Selecting transistor T SEL The gate electrode.

[0196] The fourth to sixth gate insulating films GI_4, GI_5 and GI_6 can surround the periphery of the fourth to sixth gate electrodes GE4, GE5 and GE6 between the fourth to sixth gate electrodes GE4, GE5 and GE6 and the composite channel region SP_CCH, respectively.

[0197] In the regions where the fourth to sixth gate structures GS4, GS5, and GS6 intersect with the composite channel region SP_CCH, some of each of the fourth to sixth gate structures GS4, GS5, and GS6 may be surrounded by the composite channel region SP_CCH. Each of the fourth to sixth gate structures GS4, GS5, and GS6 is stacked on a third-direction D3 within the substrate SUB. For example, the deposited semiconductor film DP_CH, which serves as the channel for the fourth to sixth gate structures GS4, GS5, and GS6, does not cover the top surfaces of the fourth to sixth gate electrodes GE4, GE5, and GE6. The fourth to sixth gate insulating films GI_4, GI_5, and GI_6 cover the top surfaces of the fourth to sixth gate electrodes GE4, GE5, and GE6, respectively. Since the deposited semiconductor film DP_CH used as the channel does not cover the top surface of the fourth to sixth gate electrodes GE4, GE5 and GE6, the composite channel region SP_CCH does not completely surround the fourth to sixth gate structures GS4, GS5 and GS6 in the region where the fourth to sixth gate structures GS4, GS5 and GS6 intersect with the composite channel region SP_CCH.

[0198] The fourth gate structure GS4, stacked on the third-direction D3, can be disposed in the fourth gate trench T_G4. The fifth gate structure GS5, stacked on the third-direction D3, can be disposed in the fifth gate trench T_G5. The sixth gate structure GS6, stacked on the third-direction D3, can be disposed in the sixth gate trench T_G6. The deposited semiconductor film DP_CH can be formed in the fourth to sixth gate trenches T_G4, T_G5, and T_G6.

[0199] In a semiconductor memory device according to some example embodiments, the fourth direction D4 and the fifth direction D5 intersect with the third direction D3, which is the thickness direction of the substrate SUB.

[0200] Figures 39A to 48 This is an intermediate stage diagram used to illustrate a method for manufacturing a semiconductor memory device according to some example embodiments.

[0201] Reference Figure 39A and Figure 39B A molded structure MIL can be formed on a substrate SUB. The molded structure MIL may include a plurality of first molded insulating layers ILD1 and a plurality of second molded insulating layers ILD2 stacked vertically and alternately, and can be formed by chemical vapor deposition (CVD) processes such as plasma enhanced CVD (PECVD).

[0202] Reference Figure 40A and Figure 40B The first to fourth holes TH1, TH2, TH3, and TH4 of the through-molded structure MIL can be formed, for example, by dry etching and / or wet etching processes. The first to third holes TH1, TH2, and TH3 can be in contact form, and the fourth hole TH4 can be in the form of a long line extending in the second direction D2. The first to third holes TH1, TH2, and TH3 can be arranged sequentially in the first direction D1. The fourth hole TH4 is adjacent to the first hole TH1.

[0203] Next, the first sacrificial pattern SDP1 can be formed in the first to fourth holes TH1, TH2, TH3 and TH4.

[0204] Reference Figure 41 The first sacrificial pattern SDP1, which fills the first hole TH1 and the second hole TH2, is removed. Next, the second molded insulating layer ILD2 exposed by the first hole TH1 and the second hole TH2 can be partially etched to form the channel recess CH_R.

[0205] Reference Figure 42A channel region SP_CH is formed to fill the channel recess CH_R. Furthermore, a first gate insulating film GI_1 and a second gate insulating film GI_2 can be formed on the channel region SP_CH exposed by the first hole TH1 and the second hole TH2. Next, a second sacrificial pattern SDP2 can be formed in the first hole TH1 and the second hole TH2.

[0206] Reference Figure 43 The first sacrificial pattern SDP1, which fills the third via TH3, is removed. Next, the second molded insulating layer ILD2, exposed by the third via TH3, can be partially etched to form the source recess SO_R. The channel region SP_CH is then exposed by the source recess SO_R.

[0207] Reference Figure 44 This forms the second impurity region SP_C, which fills the source recess SO_R. Next, the second sacrificial pattern SDP2 can be formed in the third via TH3.

[0208] Reference Figure 45 The first sacrificial pattern SDP1, which fills the fourth hole TH4, is removed. Next, the second molded insulating layer ILD2, exposed by the fourth hole TH4, can be partially etched to form the drain recess DR_R. The drain recess DR_R exposes the channel region SP_CH.

[0209] Reference Figure 46 This forms a first impurity region SP_A that partially fills the drain recess DR_R. The first impurity region SP_A can be formed using an ion implantation process; however, the example implementation is not limited thereto.

[0210] Reference Figure 47 Remove the second sacrificial pattern SDP2 from the first to third holes TH1, TH2 and TH3.

[0211] Reference Figure 48 A first conductive connection line EL_A is formed to fill the remaining portion of the drain recess DR_R. A first gate electrode GE1 and a second gate electrode GE2 are formed in the first hole TH1 and the second hole TH2, respectively. A second conductive connection line EL_C is formed in the third hole TH3. Next, a first electrode separation pattern ESL1 can be formed in the fourth hole TH4.

[0212] Unlike the configuration shown, the formation order of the first impurity region SP_A, the channel region SP_CH, and the second impurity region SP_C can vary.

[0213] Figures 49A to 57B This is an intermediate stage diagram used to illustrate a method for manufacturing a semiconductor memory device according to some example embodiments.

[0214] Reference Figure 49A and Figure 49B A pre-molded structure MIL_1 can be formed on the substrate SUB. The pre-molded structure MIL_1 may include multiple sacrificial insulating layers ILD_SC and multiple second molding insulating layers ILD2 stacked vertically and alternately. A fifth hole TH5 and a sixth hole TH6 are formed penetrating the pre-molded structure MIL_1. The fifth hole TH5 may have a shape in which multiple circles are joined together. The sixth hole TH6 may have a line form extending long in the second direction D2.

[0215] Reference Figure 50A and Figure 50B A third sacrificial pattern SDP3 is formed to fill a portion of the fifth hole TH5. The third sacrificial pattern SDP3 is formed in the fifth hole TH5 and can define the fifth hole TH51. The third sacrificial pattern SDP3 is also formed in the sixth hole TH6.

[0216] Reference Figure 51A and Figure 51B A pre-channel region SP_PCH is formed in the fifth hole TH51. From a plan view perspective, the pre-channel region SP_PCH can have a shape in which closed loops are connected. A first gate insulating film GI_1 and a second gate insulating film GI_2 can be formed on the inner sidewall of the pre-channel region SP_PCH. Subsequently, a fourth sacrificial pattern SDP4 is formed to fill the space defined by the first gate insulating film GI_1 and the second gate insulating film GI_2.

[0217] Reference Figure 52A and Figure 52B Remove the third sacrificial pattern SDP3 from the sixth hole TH6. Then, the sacrificial insulating layer ILD_SC can be removed using the sixth hole TH6. The sacrificial insulating layer ILD_SC can be removed to expose the pre-channel region SP_PCH between the second molded insulating layers ILD2.

[0218] Reference Figure 53A and Figure 53B The channel region SP_CH can be formed by removing the pre-channel region SP_PCH exposed between the second molded insulating layers ILD2. Unlike the configuration shown, the first gate insulating film GI_1 and the second gate insulating film GI_2 exposed between the second molded insulating layers ILD2 can be removed.

[0219] Reference Figure 54A and Figure 54BA first molding insulating layer ILD1 can be formed between the second molding insulating layers ILD2, between the bottommost second molding insulating layer ILD2 and the substrate SUB, and on the topmost second molding insulating layer ILD2. The first molding insulating layer ILD1 can fill the space from which the sacrificial insulating layer ILD_SC has been removed. Next, a fourth sacrificial pattern SDP4 is formed in the sixth hole TH6.

[0220] Reference Figure 55A and Figure 55B The third sacrificial pattern SDP3 is removed from the fifth hole TH5. A second impurity region SP_C can then be formed in the fifth hole TH5 from which the third sacrificial pattern SDP3 has been removed. From a planar view perspective, the second impurity region SP_C can have a closed ring shape. Next, a fourth sacrificial pattern SDP4 is formed to fill the space defined by the second impurity region SP_C.

[0221] Reference Figure 56A and Figure 56B The fourth sacrificial pattern SDP4 in the sixth hole TH6 is removed. The drain recess DR_R is formed by removing the second molded insulating layer ILD2 exposed by the sixth hole TH6. The channel pattern SP_CH is exposed by the drain recess DR_R.

[0222] Reference Figure 57A and Figure 57B This forms a first impurity region SP_A, which fills a portion of the drain recess DR_R. The first impurity region SP_A is in contact with the channel region SP_CH.

[0223] exist Figure 16A and Figure 16B In the process, after removing the fourth sacrificial pattern SDP4 surrounded by the channel region SP_CH and the second impurity region SP_C, the first gate electrode GE1 and the second gate electrode GE2, as well as the first conductive connection line EL_A and the second conductive connection line EL_C are formed.

[0224] Figures 58 to 63 This is an intermediate stage diagram used to illustrate a method for manufacturing a semiconductor memory device according to some example embodiments.

[0225] Reference Figure 58 A component separation layer DTI extending in the fourth direction D4 is formed in the substrate SUB.

[0226] Reference Figure 59A and Figure 59BUsing a mask formed on a substrate SUB, fourth to sixth gate trenches T_G4, T_G5, and T_G6 are formed in the substrate SUB. The fourth to sixth gate trenches T_G4, T_G5, and T_G6 can extend along the fifth direction D5. The fourth to sixth gate trenches T_G4, T_G5, and T_G6 can also be formed in the device separator layer DTI.

[0227] Reference Figure 60 The fourth to sixth gate structures GS4, GS5, and GS6 can be formed in the fourth to sixth gate trenches T_G4, T_G5, and T_G6, respectively. The fourth to sixth gate electrodes GE4, GE5, and GE6 can be formed on the fourth to sixth gate insulating films GI_4, GI_5, and GI_6, respectively. Subsequently, some of the fourth to sixth gate insulating films GI_4, GI_5, and GI_6, and some of the fourth to sixth gate electrodes GE4, GE5, and GE6, are removed. Then, the fourth to sixth gate insulating films GI_4, GI_5, and GI_6 can be additionally formed on the exposed fourth to sixth gate electrodes GE4, GE5, and GE6, respectively.

[0228] The fourth gate structure GS4 fills a portion of the fourth gate trench T_G4. The fifth gate structure GS5 fills a portion of the fifth gate trench T_G5. The sixth gate structure GS6 fills a portion of the sixth gate trench T_G6. Next, a pre-semiconductor film DP_PCH is formed, extending along the sidewalls of the fourth to sixth gate trenches T_G4, T_G5, and T_G6, and the top surface of the fourth to sixth gate structures GS4, GS5, and GS6.

[0229] Reference Figure 61 The fourth to sixth gate insulating films GI_4, GI_5, and GI_6, and the fourth to sixth gate electrodes GE4, GE5, and GE6 can be formed on the pre-semiconductor film DP_PCH. Subsequently, some of the pre-semiconductor film DP_PCH, the fourth to sixth gate insulating films GI_4, GI_5, and GI_6, and the fourth to sixth gate electrodes GE4, GE5, and GE6 can be removed. The fourth to sixth gate insulating films GI_4, GI_5, and GI_6 can be additionally formed on the exposed fourth to sixth gate electrodes GE4, GE5, and GE6, respectively. By repeating the aforementioned process, the fourth to sixth gate structures GS4, GS5, and GS6 stacked on the third-direction D3 and the deposited semiconductor film DP_CH can be formed in the fourth to sixth gate trenches T_G4, T_G5, and T_G6. Subsequently, the mask on the substrate SUB can be removed.

[0230] Reference Figure 62An anode hole T_A is formed in the substrate SUB. A first impurity region SP_A is formed along the sidewall and bottom surface of the anode hole T_A. A first conductive connection line EL_A filling the anode hole T_A is formed on the first impurity region SP_A.

[0231] Reference Figure 63 A cathode trench T_C is formed in the substrate SUB.

[0232] Next, a second impurity region SP_C is formed along the sidewalls and bottom surface of the cathode trench T_C. A second conductive connection line EL_C, filling the cathode trench T_C, is then formed on the second impurity region SP_C.

[0233] In concluding this detailed description, those skilled in the art will recognize that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the exemplary embodiments. Therefore, the preferred embodiments disclosed herein are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor memory device, comprising: A first semiconductor pattern includes a first impurity region, a second impurity region, and a channel region. The first impurity region is spaced apart from the substrate in a first direction and has a first conductivity type. The second impurity region has a second conductivity type different from the first conductivity type. The channel region is located between the first impurity region and the second impurity region. A first conductive connection line is connected to the first impurity region and extends in a second direction different from the first direction; and A first gate structure extends in the first direction and includes a first gate electrode and a first gate insulating film. Wherein the first gate electrode penetrates the channel region, and The first gate insulating film is located between the first gate electrode and the first semiconductor pattern.

2. The semiconductor memory device according to claim 1, further comprising: The second gate structure penetrates the channel region and includes a second gate electrode and a second gate insulating film.

3. The semiconductor memory device according to claim 2, further comprising: The third gate structure penetrates the channel region and includes a third gate electrode and a third gate insulating film.

4. The semiconductor memory device according to claim 1, further comprising: The second conductive connection line penetrates the second impurity region. The second conductive connection line contacts the first semiconductor pattern.

5. The semiconductor memory device according to claim 1, further comprising: The conductive plate electrode is connected to the second impurity region. The conductive plate electrode contacts one end of the first semiconductor pattern.

6. The semiconductor memory device according to claim 1, further comprising: A second semiconductor pattern, spaced apart from the first semiconductor pattern in the second direction and connected to the first conductive connection line, is provided. The second semiconductor pattern is electrically connected to the second impurity region and the channel region through the first impurity region.

7. The semiconductor memory device according to claim 1, further comprising: A second semiconductor pattern is spaced apart from the first semiconductor pattern in the second direction and connected to the first conductive connection line; and An air gap is located between the first semiconductor pattern and the second semiconductor pattern.

8. The semiconductor memory device according to claim 1, further comprising: The shielding pattern extends upward along the channel region and the second impurity region in a third direction different from the first and second directions. The shielding pattern includes conductive material.

9. The semiconductor memory device of claim 8, wherein the shielding pattern is electrically connected to the second impurity region.

10. The semiconductor memory device of claim 1, wherein... The channel region includes a first base portion having the second conductivity type and a second base portion having the first conductivity type. The first base portion is located between the first impurity region and the second base portion. The concentration of impurities in the first base region is less than the concentration of impurities in the second impurity region, and The concentration of impurities in the second base region is less than the concentration of impurities in the first impurity region.

11. A semiconductor memory device, comprising: A semiconductor pattern includes a first impurity region, a second impurity region, and a channel region. The first impurity region is spaced apart from the substrate in a first direction and has a first conductivity type. The second impurity region has a second conductivity type different from the first conductivity type. The channel region is located between the first impurity region and the second impurity region. A first conductive connection line is connected to the first impurity region and extends in a second direction different from the first direction; as well as The second conductive connection electrode extends in the first direction, penetrates the second impurity region, and contacts the semiconductor pattern.

12. The semiconductor memory device of claim 11, further comprising: One or more gate structures penetrate the channel region and include a gate electrode and a gate insulating film.

13. The semiconductor memory device of claim 12, wherein... The channel region includes a first base portion having the second conductivity type and a second base portion having the first conductivity type. The first base portion is located between the first impurity region and the second base portion. The concentration of impurities in the first base region is less than the concentration of impurities in the second impurity region, and The concentration of impurities in the second base region is less than the concentration of impurities in the first impurity region.

14. The semiconductor memory device of claim 12, wherein the channel region comprises an undoped semiconductor material.

15. The semiconductor memory device of claim 11, wherein... The channel region includes a first base portion having the second conductivity type and a second base portion having the first conductivity type. The first base portion is located between the first impurity region and the second base portion. The concentration of impurities in the first base region is lower than the concentration of impurities in the second impurity region. The concentration of impurities in the second base region is lower than the concentration of impurities in the first impurity region. The semiconductor memory device does not include a gate electrode that penetrates the channel region.

16. A semiconductor memory device, comprising: Peripheral circuit area on the substrate; and The cell array region is stacked together with the peripheral circuit region in the first direction. The peripheral circuit area includes peripheral circuitry configured to control the cell array area. The unit array region includes Multiple semiconductor patterns are stacked on the substrate in the first direction. Each semiconductor pattern includes a first impurity region having a first conductivity type, a second impurity region having a second conductivity type different from the first conductivity type, and a channel region between the first impurity region and the second impurity region. A first conductive connection line is connected to the first impurity region and extends in a second direction different from the first direction, and A first gate structure extends in the first direction and includes a gate electrode and a gate insulating film. Each of the first conductive connection line and the gate electrode contacts the peripheral circuit, and The gate electrode penetrates the channel region.

17. The semiconductor memory device of claim 16, further comprising: The second conductive connection line penetrates the second impurity region. The second conductive connection line contacts the semiconductor pattern.

18. The semiconductor memory device of claim 16, further comprising: The conductive plate electrode is connected to the second impurity region. The conductive plate electrode contacts one end of the semiconductor pattern.

19. The semiconductor memory device of claim 16, wherein the peripheral circuit region is between the substrate and the cell array region.

20. The semiconductor memory device of claim 16, wherein the cell array region is between the substrate and the peripheral circuit region.

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