Semiconductor structure and method of manufacturing the same
By forming a temporary support layer to cover the chip after hybrid bonding and using the temporary support layer to avoid lateral shear stress during polishing, the problem of chip breakage/peeling in the hybrid bonding process is solved, and the product yield is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ADVANCED SEMICON ENG INC
- Filing Date
- 2021-07-13
- Publication Date
- 2026-06-19
AI Technical Summary
In existing hybrid bonding processes, when using Pillar First or Pillar Last methods, there are problems such as increased roughness in the chip bonding area or uneven coating thickness, leading to hybrid bonding failure or chip breakage/peeling.
After hybrid bonding, a temporary support layer is formed to cover the chip. The temporary support layer is used to avoid lateral shear stress during polishing. After the interconnect structure is formed, the temporary support layer is removed to prevent the chip from cracking/peeling.
This effectively avoids chip breakage/peeling caused by lateral shear stress during the grinding process, thus improving product yield.
Smart Images
Figure CN113594115B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor structures and their manufacturing methods. Background Technology
[0002] Direct bonding, such as hybrid bonding technology, can refer to wafer-to-wafer bonding, chip-to-chip bonding, or wafer-to-chip bonding. Currently, hybrid bonding package structures formed by hybrid bonding processes, if using tall pillars to guide signals, typically employ two methods: "pillar first" and "pillar last".
[0003] If Pillar First is used, chemical mechanical polishing (CMP) needs to be performed on the bottom wafer first, and then photoresist coating is applied to protect the die bonding area before opening and electroplating to form the Pillar. However, subsequent processes such as photoresist coating and seed layer removal will increase the roughness of the die bonding area (roughness > 0.3 nm), making it impossible to perform hybrid bonding (such as die to wafer bonding) in the future.
[0004] While using Pillar Last can avoid the increased roughness caused by photolithography, photoresist coating must be performed after hybrid bonding. However, the thickness of the top die cannot be less than 25µm (currently 75µm), resulting in uneven photoresist coating and making subsequent Pillar Last processes impossible. Furthermore, if hybrid bonding is followed by grinding to reduce the die thickness, the excessive lateral shear stress generated during the grinding process can lead to die cracking / peeling. Summary of the Invention
[0005] This disclosure provides semiconductor structures and methods for manufacturing the same.
[0006] In a first aspect, this disclosure provides a semiconductor structure comprising:
[0007] A first electronic component and a second electronic component, the first electronic component and the second electronic component being connected by a bonding structure, the second electronic component including a conductive pad for external connection;
[0008] An interconnect structure is electrically connected to the conductive pad, and a seed layer is provided between the conductive pad and the interconnect structure.
[0009] In some alternative implementations, the seed layer covers the ends of the interconnect structure.
[0010] In some alternative implementations, the interconnect structure is a conductive pillar.
[0011] In some alternative implementations, the thickness of the first electronic component is less than 75 micrometers.
[0012] In some alternative embodiments, a dielectric layer is provided between the conductive pad and the interconnect structure, and the ends of the interconnect structure are embedded in the dielectric layer.
[0013] In some alternative embodiments, a first material layer is provided between the sidewall of the first electronic component and the dielectric layer.
[0014] In some alternative implementations, the first material layer includes a molding material.
[0015] In some alternative embodiments, the semiconductor structure further includes:
[0016] A redistribution layer electrically connected to the interconnect structure, the redistribution layer comprising opposing first and second surfaces.
[0017] In some alternative embodiments, the semiconductor structure further includes:
[0018] A molding layer is disposed between the first electronic component and the first surface.
[0019] In some alternative embodiments, the semiconductor structure further includes:
[0020] An external electrical connector is disposed on the second surface and electrically connected to the redistribution layer.
[0021] In some optional embodiments, the bonding structure includes a first metal layer, a second metal layer, a first dielectric layer, and a second dielectric layer, wherein the first metal layer and the second metal layer are in contact to form a metal bond, and the first dielectric layer and the second dielectric layer are in contact to form a dielectric bond.
[0022] Secondly, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising:
[0023] A hybrid bonding package structure is provided, the hybrid bonding package structure including a first electronic component and a second electronic component, the first electronic component and the second electronic component being connected by a bonding structure, the second electronic component including a conductive pad for external connection, and the width of the second electronic component being greater than the width of the first electronic component;
[0024] A temporary support layer is formed on the second electronic component to cover the first electronic component;
[0025] Thin the first electronic component;
[0026] The conductive pads are formed into interconnect structures using photolithography.
[0027] In some alternative embodiments, before the second electronic element forms a temporary support layer covering the first electronic element, the method further includes:
[0028] A temporary protective layer is formed on the second electronic component to cover the conductive pad.
[0029] In some alternative implementations, the temporary protective layer is a water-washable adhesive.
[0030] In some alternative implementations, the temporary support layer is a molding material.
[0031] In some alternative embodiments, prior to forming the interconnect structure on the conductive pad using photolithography, the method further includes:
[0032] Remove the temporary support layer and the temporary protective layer.
[0033] In some alternative implementations, the temporary support layer is removed by laser.
[0034] In some alternative implementations, the temporary protective layer is removed by washing with water.
[0035] In some alternative implementations, the interconnect structure is a conductive pillar.
[0036] In some optional implementations, the method further includes:
[0037] A rewiring layer is formed that is electrically connected to the interconnect structure.
[0038] In some alternative implementations, the redistribution layer forming an electrical connection with the interconnect structure includes:
[0039] A molding layer is formed on the second electronic component;
[0040] A rewiring layer electrically connected to the interconnect structure is formed in the molding layer.
[0041] To address the issue of excessive lateral shear stress during the grinding process, which can lead to chip breakage / peeling, when directly grinding the chip after hybrid bonding, this disclosure provides a semiconductor structure and manufacturing method. After hybrid bonding, a temporary support layer is first formed to cover the chip. Then, the entire chip is ground on top of this temporary support layer. Because the temporary support layer surrounds the chip during grinding, the lateral shear stress generated during grinding is effectively avoided, preventing chip breakage / peeling and improving product yield. Attached Figure Description
[0042] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0043] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;
[0044] Figures 2A to 2J This is a schematic diagram of the manufacturing process of the semiconductor structure according to the present disclosure.
[0045] Symbol explanation:
[0046] 1-First electronic component, 2-Second electronic component, 3-Bonding structure, 31-First metal layer, 32-Second metal layer, 33-First dielectric layer, 34-Second dielectric layer, 4-Conductive pad, 5-Interconnection structure, 6-Seed layer, 7-Dielectric layer, 8-First material layer, 9-Rewiring layer, 10-Molding layer, 11-External electrical connector, 12-Temporary support layer, 13-Temporary protective layer, 14-Adhesive layer, 15-Wire, 16-Substrate. Detailed Implementation
[0047] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0048] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.
[0049] Furthermore, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Reference will be made below. Figure 1 This disclosure will be described in detail with reference to the embodiments.
[0050] Please refer to Figure 1 , Figure 1 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.
[0051] like Figure 1 As shown, the semiconductor structure includes a first electronic component 1, a second electronic component 2, and an interconnect structure 5. The first electronic component 1 can be connected to the second electronic component 2 via a bonding structure 3. The second electronic component 2 includes a conductive pad 4 for external connection. The interconnect structure 5 can be disposed on the conductive pad 4 and electrically connected to the conductive pad 4. A seed layer 6 can be provided between the conductive pad 4 and the interconnect structure 5. The seed layer 6 can cover the upper end of the interconnect structure 5. A dielectric layer 7 can be provided between the conductive pad 4 and the interconnect structure 5. The upper end of the interconnect structure 5 can be embedded in the dielectric layer 7. A first material layer 8 can be included between the sidewall of the first electronic component 1 and the dielectric layer 7.
[0052] In this embodiment, the first electronic component 1 may be, for example, a chip or a wafer. The thickness of the first electronic component 1 may be less than 75 micrometers.
[0053] In this embodiment, the second electronic component 2 may be, for example, a chip or a wafer.
[0054] In this embodiment, the interconnection structure 5 may be, for example, a conductive pillar.
[0055] In this embodiment, the bonding structure 3 may include a first metal layer 31, a second metal layer 32, a first dielectric layer 33 and a second dielectric layer 34. The first metal layer 31 and the second metal layer 32 are in contact to form a metal bond, and the first dielectric layer 33 and the second dielectric layer 34 are in contact to form a dielectric bond.
[0056] In this embodiment, the first material layer 8 may include a molding compound, such as an epoxy molding compound (EMC). Here, in the manufacturing process (refer to...) Figure 2D and Figure 2E During the removal of the temporary support layer 12, the temporary support layer 12 was not completely removed, and the remaining material layer 8 was formed.
[0057] In this embodiment, the dielectric layer 7 can be used to reinforce the upper end of the supporting interconnect structure 5.
[0058] In this embodiment, the semiconductor structure may further include a redistribution layer 9, a molding layer 10, and an external electrical connector 11. The redistribution layer 9 may be electrically connected to the interconnect structure 5. The redistribution layer 9 may include opposing first and second surfaces. The molding layer 10 may be disposed between the first electronic component 1 and the first surface. The external electrical connector 11 may be disposed on the second surface and electrically connected to the redistribution layer 9.
[0059] Please refer to Figures 2A to 2J , Figures 2A to 2J A schematic diagram of the manufacturing process of the semiconductor structure according to the present disclosure is shown.
[0060] like Figure 2A As shown, the provided hybrid bonding package structure may include a first electronic component 1 and a second electronic component 2. The first electronic component 1 can be connected to the second electronic component 2 via a bonding structure 3. The second electronic component 2 may include a conductive pad 4 for external connection. The width of the second electronic component 2 may be greater than the width of the first electronic component 1. The bonding structure 3 may include a first metal layer 31, a second metal layer 32, a first dielectric layer 33, and a second dielectric layer 34. The first metal layer 31 can contact the second metal layer 32 to form a metal bond. The first dielectric layer 33 and the second dielectric layer 34 can contact each other to form a dielectric bond.
[0061] like Figure 2B As shown, a temporary protective layer 13 covering the conductive pad 4 can be formed on the second electronic component 2 by a coating process. The temporary protective layer 13 can be, for example, a water-washable adhesive.
[0062] like Figure 2C As shown, a temporary support layer 12 covering the first electronic component 1 can be formed on the second electronic component 2 by a molding process. The temporary support layer 12 can be, for example, a molding material.
[0063] like Figure 2D As shown, the first electronic component 1 is thinned. Here, a grinding process can be used to thin both the temporary support layer 12 and the first electronic component 1 as a whole.
[0064] like Figure 2E As shown, the temporary support layer 12 and the temporary protective layer 13 are removed. The remaining temporary support layer 12 can be removed by laser treatment or CF4 plasma treatment. The temporary protective layer 13 can be removed by solvent dissolution. If the temporary protective layer 13 is a water-washable adhesive, it can be removed by washing. Because the temporary support layer 12 was not completely removed during the removal process, some residue remains, forming the first material layer 8.
[0065] like Figure 2F As shown, an interconnect structure 5 is formed on the conductive pad 4 using a photolithography process. Specifically, a dielectric layer 7 can be formed on the conductive pad 4, an opening can be formed on the dielectric layer 7, a seed layer 6 can be formed in the opening, and the interconnect structure 5 can be formed on the seed layer 6. The interconnect structure 5 can be a conductive pillar.
[0066] like Figure 2G As shown, a molding layer 10 covering the interconnect structure 5 is formed on the second electronic component 2, and the interconnect structure 5 can be exposed from the molding layer 10 by a polishing process.
[0067] like Figure 2H As shown, a redistribution layer 9 electrically connected to the interconnection structure 5 is formed on the molding layer 10.
[0068] like Figure 2I As shown, an external electrical connector 11 is formed on the redistribution layer 9. The external electrical connector 11 may be, for example, a solder ball.
[0069] like Figure 2J The semiconductor structure shown is in Figure 2E Based on the semiconductor structure shown, an adhesive layer 14 (e.g., a die attaching film (DAF)) is first formed, and then the adhesive layer 14 is bonded to the substrate 16. Wire bonding is used to electrically connect the two ends of the wire 15 to the conductive pad 4 and the substrate 16, respectively, and finally, a molding layer 10 is formed.
[0070] Figure 2J The semiconductor structure shown is similar to Figure 2I Compared to the semiconductor structure shown, Figure 2I The semiconductor structure shown uses interconnect structure 5 (conductive pillars) to export signals for external electrical connection. Figure 2J The semiconductor structure shown uses wire 15 to guide the signal for external electrical connection. Additionally, in Figure 2EBased on the semiconductor structure shown, signals can be exported not only by means of interconnect structure 5 (conductive pillars) or wire 15, but also by other electrical connection structures (e.g., which may include an under bump metallization (UBM) layer and solder balls).
[0071] The semiconductor structure and manufacturing method disclosed herein involve coating a temporary protective layer 13 onto the area (conductive pad 4) of the pre-formed interconnect structure 5 (e.g., conductive pillars) for protection, molding a first electronic component 1 (e.g., a chip) with a temporary support layer 12, and then thinning the first electronic component 1 to the required thickness (e.g., less than 5 μm) through a polishing process. Because the temporary support layer 12 surrounds the first electronic component 1 during polishing, lateral shear stress generated during polishing can be effectively avoided, thus preventing chip breakage / peeling and other problems. After polishing, the residual temporary support layer 12 is removed by laser or CF4 plasma treatment, and the temporary protective layer 13 is removed using a solvent (e.g., a water washing process), and then the interconnect structure 5 is formed to achieve signal output.
[0072] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.
Claims
1. A semiconductor structure, comprising: A first electronic component and a second electronic component are connected by a bonding structure. The second electronic component includes a conductive pad for external connection. The conductive pad and the first electronic component are located on the same side of the second electronic component. The thickness of the first electronic component is ground thinned to less than 5 micrometers to allow interconnection structures to be formed on the conductive pad by photolithography. The interconnect structure is electrically connected to the conductive pad, and a seed layer is provided between the conductive pad and the interconnect structure. The interconnect structure is a conductive pillar formed on the seed layer by photolithography, and the height of the conductive pillar is greater than the height of the first electronic component. A dielectric layer is provided between the conductive pad and the interconnect structure. A first material layer is included between the sidewall of the first electronic component and the dielectric layer. The first material layer is a molding material. The first material layer is used to surround the first electronic component during polishing to prevent the first electronic component from breaking or peeling off due to the lateral shear stress generated during polishing.
2. The semiconductor structure according to claim 1, wherein, The seed layer covers the ends of the interconnect structure.
3. The semiconductor structure according to claim 1 or 2, wherein, The ends of the interconnect structure are embedded in the dielectric layer, and the dielectric layer is not disposed above the first electronic component.
4. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A redistribution layer electrically connected to the interconnect structure, the redistribution layer including opposing first and second surfaces; A molding layer is disposed between the first electronic component and the first surface; An external electrical connector is disposed on the second surface and electrically connected to the redistribution layer.
5. The semiconductor structure according to claim 1, wherein, The bonding structure includes a first metal layer, a second metal layer, a first dielectric layer, and a second dielectric layer. The first metal layer and the second metal layer are in contact to form a metal bond, and the first dielectric layer and the second dielectric layer are in contact to form a dielectric bond.
6. A method for manufacturing a semiconductor structure, comprising: A hybrid bonding package structure is provided, the hybrid bonding package structure including a first electronic component and a second electronic component, the first electronic component and the second electronic component being connected by a bonding structure, the second electronic component including a conductive pad for external connection, the conductive pad and the first electronic component being located on the same side of the second electronic component; A temporary support layer is formed on the second electronic component to cover the first electronic component, and the temporary support layer is a molding material; The first electronic component is thinned by a grinding process. During grinding, the temporary support layer surrounds the first electronic component to prevent the lateral shear stress generated during grinding from causing the first electronic component to break or peel off. After thinning, the thickness of the first electronic component is reduced to less than 5 micrometers to allow the formation of interconnect structures on the conductive pad by photolithography. Conductive pillars are formed on the conductive pad using photolithography as an interconnect structure, and the height of the conductive pillars is greater than the height of the first electronic component.
7. The method according to claim 6, wherein, Before forming a temporary support layer covering the first electronic component on the second electronic component, the method further includes: A temporary protective layer is formed on the second electronic component to cover the conductive pad.
8. The method according to claim 7, wherein, The temporary protective layer is a water-washable adhesive.
9. The method according to claim 7, wherein, Before forming the interconnect structure on the conductive pad using photolithography, the method further includes: Remove the temporary support layer and the temporary protective layer.
10. The method according to claim 9, wherein, The temporary support layer is removed by laser.
11. The method according to claim 9, wherein, The temporary protective layer is removed by washing with water.
12. The method according to claim 6, wherein, The method further includes: A rewiring layer is formed that is electrically connected to the interconnect structure.
13. The method according to claim 12, wherein, The redistribution layer that forms an electrical connection with the interconnect structure includes: A molding layer is formed on the second electronic component; A rewiring layer electrically connected to the interconnect structure is formed on the molding layer.