Memory array including epitaxial source lines and bit lines

Abstract

The present disclosure relates to a memory array including epitaxial source lines and bit lines. A 3D memory array and a method for forming the same are disclosed, wherein epitaxial source / drain regions that are merged horizontally and not merged vertically are used as source lines and bit lines. In an embodiment, a memory array includes: a first channel region, above a semiconductor substrate; a first epitaxial region, electrically coupled to the first channel region; a second epitaxial region, located directly above the first epitaxial region in a direction perpendicular to a main surface of the semiconductor substrate; a dielectric material, between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric, surrounding the first channel region; and a gate electrode, surrounding the gate dielectric.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and, in particular, to memory arrays including epitaxial source lines and bit lines. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a storage array is provided, comprising: a first channel region on a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to a main surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, wherein the second epitaxial region is isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first channel region above a semiconductor substrate; a second channel region located directly above the first channel region in a vertical direction; a first gate structure surrounding the first channel region and the second channel region; a third channel region adjacent to the first channel region in a horizontal direction; a first source / drain region electrically coupled to the first channel region and the third channel region; and a second source / drain region electrically coupled to the second channel region and isolated from the first source / drain region, wherein a first dielectric material extends between the first source / drain region and the second source / drain region.

[0006] According to another embodiment of the present disclosure, a method is provided, comprising: forming a multilayer stack on a semiconductor substrate, the multilayer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; patterning the multilayer stack to form a first plurality of nanostructures comprising the first semiconductor material and a second plurality of nanostructures comprising the second semiconductor material, the second plurality of nanostructures comprising a first nanostructure, a second nanostructure and a third nanostructure, the second nanostructure being adjacent to the first nanostructure in a direction parallel to a major surface of the semiconductor substrate, and the third nanostructure being located directly above the first nanostructure in a direction perpendicular to the major surface of the semiconductor substrate; forming a gate structure on the multilayer stack; etching the multilayer stack to form a first recess adjacent to the gate structure; and epitaxially growing source / drain regions from the second plurality of nanostructures, wherein, after epitaxially growing the source / drain regions, the first source / drain region epitaxially grown from the first nanostructure and the second source / drain region epitaxially grown from the second nanostructure merge with each other, and wherein the third source / drain region epitaxially grown from the third nanostructure is isolated from the first source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A and Figure 1B A perspective view and circuit diagram of a memory array according to some embodiments are shown.

[0009] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A Figure 6B Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Figure 8 , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.14A , Fig. 14B Figure 14C Fig.14D , Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig.15F Figure 16A Fig. 16B , Fig. 16C , Fig.16D , Fig.17A , Fig. 17B , Fig. 17C , Fig.17D Figure 18A Fig.18B , Fig.18C , Fig.18D , Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig. 20A , Fig. 20B , Fig. 20C , Fig.20D , Fig.21A , Fig.21B , Fig. 21C , Fig.21D Figure 22A Fig. 22B , Fig. 22C , Fig.22D and Fig.23 Various views of fabricating a semiconductor device including a memory array are shown in accordance with some embodiments.

[0010] Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.26C , Fig.27A , Fig.27B , Fig.27C , Fig.28A , Fig.28B , Fig.28C , Fig.29A Figure 29B Fig.29C , Fig.29D , Fig. 30A , Fig. 30B , Fig. 30C , Fig.30D , Fig.31A Figure 31B Fig. 31C , Fig.31D and Fig.32 Various views of fabricating a semiconductor device including a memory array are shown in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] Various embodiments provide a 3D memory array and a method for forming the same, in which epitaxially grown source / drain regions are merged in the horizontal direction and isolated in the vertical direction. The method may include forming a channel region, which may be a nanostructure, etc. Some portions of the channel region may be etched, and the source / drain region may be epitaxially grown from the rest of the channel region. The channel region may be formed so that adjacent source / drain regions in the horizontal direction merge with each other while adjacent source / drain regions in the vertical direction remain unmerged. The source / drain region may then be etched to form a staircase structure so that each group of merged source / drain regions may be individually connected. The source / drain region may be used as a source line and a bit line in a 3D memory array. The method for forming a 3D memory array is compatible with existing nanostructure field effect transistor (nanoFET) processes and allows the formation of a 3D memory array in a reduced area, thereby increasing device density and reducing costs.

[0014] Embodiments are described below in a specific context, namely, a die including nanoFETs. However, various embodiments may be applied to dies including other types of transistors (eg, fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanoFETs.

[0015] Figure 1A and Figure 1B An example of a memory array 200 is shown in accordance with some embodiments. Figure 1A shows an example of a portion of a storage array 200 of a three-dimensional view in accordance with some embodiments, Figure 1B A circuit diagram of a memory array 200 is shown. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. The memory cells 202 may be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. In some embodiments, the memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array 200 may be disposed in an interconnect layer of a semiconductor die, for example, above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0016] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array, etc. Each memory cell 202 may include a transistor 204 having a gate dielectric layer 100. The gate dielectric layer 100 may be used as a gate dielectric. In some embodiments, the gate electrode 102 of each transistor 204 may correspond to or be electrically coupled to a corresponding word line. The first epitaxial source / drain region 92 of each transistor 204 may correspond to or be electrically coupled to a corresponding bit line, and the second epitaxial source / drain region 92 of each transistor 204 may correspond to or be electrically coupled to a corresponding source line. The memory cells 202 in the memory array 200 of the same horizontal row may share a common epitaxial source / drain region 92 corresponding to a common source line and a common epitaxial source / drain region 92 corresponding to a common bit line, while the memory cells 202 in the memory array 200 of the same vertical column may share a common gate electrode 102 corresponding to a common word line.

[0017] The memory array 200 includes a plurality of vertically stacked epitaxial source / drain regions 92, wherein a first ILD 96 is disposed between vertically adjacent epitaxial source / drain regions 92. The epitaxial source / drain regions 92 extend in a direction parallel to the major surface of the underlying substrate 50. The epitaxial source / drain regions 92 may have a stepped configuration such that a lower epitaxial source / drain region 92 is longer than an upper epitaxial source / drain region 92 and extends laterally beyond the end point of the upper epitaxial source / drain region 92. For example, in Figure 1A , multiple stacked layers of epitaxial source / drain regions 92 are shown, where the topmost epitaxial source / drain region 92 is the shortest and the bottommost epitaxial source / drain region 92 is the longest. The respective lengths of the epitaxial source / drain regions 92 may increase in a direction toward the underlying substrate. In this way, a portion of each epitaxial source / drain region 92 may be accessed from above the memory array 200, and conductive contact may be made to the exposed portion of each epitaxial source / drain region 92.

[0018] The memory array 200 also includes a plurality of gate electrodes 102. The gate electrodes 102 may each extend in a direction perpendicular to the epitaxial source / drain regions 92. A dielectric material 106 is disposed between and isolates adjacent gate electrodes 102. The pairs of epitaxial source / drain regions 92 and the intersecting gate electrodes 102 define the boundaries of each memory cell 202, and the dielectric material 106 is disposed between and isolates adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the alternating stacks of epitaxial source / drain regions 92 may be electrically connected to ground and a voltage source.

[0019] The memory array 200 may further include a nanostructure 54. The nanostructure 54 may provide a channel region for a transistor 204 of the memory cell 202. For example, when a suitable voltage (e.g., higher than a corresponding threshold voltage (V th )), the nanostructure 54 intersecting the gate electrode 102 can allow current to flow from the first epitaxial source / drain region 92 on the first side of the nanostructure 54 to the second epitaxial source / drain region 92 on the second side of the nanostructure 54 opposite to the first side of the nanostructure 54.

[0020] The gate dielectric layer 100 is disposed between the gate electrode 102 and the nanostructure 54, and the gate dielectric layer 100 provides a gate dielectric of the transistor 204. In some embodiments, the gate dielectric layer 100 includes a ferroelectric (FE) material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc. Therefore, the memory array 200 may be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the gate dielectric layer 100 may be a multi-layer structure, different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc. Using ferroelectric materials for the gate dielectric layer 100 may shift the threshold voltage (Vt) and provide storage reliability and improved performance.

[0021] In an embodiment where the gate dielectric layer 100 includes a FE material, the gate dielectric layer 100 can be polarized in one of two different directions. The polarization direction can be changed by applying an appropriate voltage difference on the gate dielectric layer 100 and generating an appropriate electric field. Depending on the polarization direction of a specific gate dielectric layer 100, the threshold voltage of the corresponding transistor 204 changes and a digital value (e.g., 0 or 1) can be stored. For example, when the gate dielectric layer 100 has a first electrical polarization direction, the corresponding transistor 204 can have a relatively low threshold voltage, and when the gate dielectric layer 100 has a second electrical polarization direction, the corresponding transistor 204 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding storage cell 202.

[0022] In order to perform a write operation on the memory cell 202, a write voltage is applied to the gate dielectric layer 100 corresponding to the memory cell 202. The write voltage can be applied, for example, by applying an appropriate voltage to the gate electrode 102 (e.g., through the corresponding word line) and the corresponding epitaxial source / drain region 92 (e.g., through the corresponding bit line and source line). By applying the write voltage on the gate dielectric layer 100, the polarization direction of the gate dielectric layer 100 can be changed. As a result, the corresponding threshold voltage of the corresponding transistor 204 can be switched from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value can be stored in the memory cell 202. Since the gate electrode 102 intersects the epitaxial source / drain region 92, each memory cell 202 can be selected for a write operation.

[0023] To perform a read operation on a memory cell 202, a read voltage (e.g., a voltage between a low threshold voltage and an upper threshold voltage) is applied to a corresponding gate electrode 102 (e.g., through a corresponding word line). Depending on the polarization direction of the corresponding gate dielectric layer 100, the transistor 204 of the memory cell 202 may or may not be turned on. As a result, the corresponding epitaxial source / drain region 92 (e.g., a corresponding epitaxial source / drain region electrically coupled to a source line) may (or may not) be discharged through the corresponding epitaxial source / drain region 92 (e.g., a corresponding source / drain region electrically coupled to ground), and the digital value stored in the memory cell 202 may be determined. Because the gate electrode 102 intersects the epitaxial source / drain region 92, individual memory cells 202 may be selected for a read operation.

[0024] Figure 1AReference cross sections of the memory array 200 used in subsequent figures are also shown. Cross section AA' is along the longitudinal axis of the nanostructure 54 and in a direction parallel to the direction of current flowing through the nanostructure 54 of the transistor 204. Cross section BB' is perpendicular to cross section AA' and extends through the gate electrode 102 in a direction parallel to the longitudinal axis of the epitaxial source / drain region 92. Cross section CC' is parallel to cross section BB' and extends through the epitaxial source / drain region 92. For clarity, subsequent figures refer to these reference cross sections.

[0025] Some embodiments discussed herein are discussed in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices (e.g., planar FETs) or fin field effect transistors (FinFETs).

[0026] Figures 2 to 32 are cross-sectional and top views of intermediate stages in the fabrication of memory array 200 according to some embodiments. Figure 2 , Figure 3 , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Figure 8 , Fig.9A Figure 9B Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A Figure 17A Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.24A , Fig.25A Figure 26A Fig.27A , Fig.28A , Fig.29A , Fig. 30A and Fig.31A Shows Figure 1A Reference section AA' is shown. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Fig. 10B , Fig. 11B , Fig. 12B Figure 13B Fig. 14B , Fig. 15B , Fig.15E , Fig.15F , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B Figure 29B Fig. 30B and Fig.31B Shows Figure 1A Reference section BB' is shown. Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.29C , Fig. 30C and Fig. 31C Shows Figure 1A Reference section CC' shown in . Figure 4C , Figure 5C , Figure 6C , Figure 7C , Fig. 10D , Fig.11D , Fig.12D , Fig.13D , Fig.14D , Fig.15D , Fig.16D , Fig.17D , Fig.18D , Fig.19D , Fig.20D , Fig.21D , Fig.22D , Fig.23 , Fig.24C , Fig.25C , Fig.26C , Fig.27C , Fig.28C Figure 29D Fig.30D , Fig.31D and Fig.32 A top view is shown.

[0027] exist Figure 2In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be an integrated circuit die, such as a logic die, a memory die, an ASIC die, etc. The substrate 50 may be a complementary metal oxide semiconductor (CMOS) die, and may be referred to as a CMOS under array (CUA). The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations of the foregoing.

[0028] Figure 2 Further shown is a circuit that can be formed on the substrate 50. The circuit includes a transistor located on the top surface of the substrate 50. The transistor may include a gate dielectric layer 302 on the top surface of the substrate 50, and a gate electrode 304 on the gate dielectric layer 302. Source / drain regions 306 are provided in the substrate 50 on opposite sides of the gate dielectric layer 302 and the gate electrode 304. Gate spacers 308 are formed along the sidewalls of the gate dielectric layer 302 and separate the source / drain regions 306 from the gate electrode 304 by an appropriate lateral distance. The transistor may include a fin field effect transistor (FinFET), a nanostructure (e.g., nanosheet, nanowire, gate all around, etc.) FET (nanoFET), a planar FET, etc., or a combination thereof, and may be formed by a gate first process or a gate last process.

[0029] The first ILD 310 surrounds and isolates the source / drain regions 306, the gate dielectric layer 302, and the gate electrode 304, and the second ILD 312 is above the first ILD 310. The source / drain contacts 314 extend through the second ILD 312 and the first ILD 310 and are electrically connected to the source / drain regions 306, and the gate contact 316 extends through the second ILD 312 and is electrically connected to the gate electrode 304. Above the second ILD 312, the source / drain contacts 314, and the gate contact 316 is an interconnect structure 320, which includes one or more stacked dielectric layers 324 and conductive features 322 formed in the one or more dielectric layers 324. The interconnect structure 320 can be electrically connected to the gate contact 316 and the source / drain contacts 314 to form a functional circuit. In some embodiments, the functional circuits formed by the interconnect structure 320 may include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, etc., or a combination of the foregoing. Figure 2 Transistors formed on the substrate 50 are discussed, but other active devices (e.g., diodes, etc.) and / or passive devices (e.g., capacitors, resistors, etc.) may also be formed as part of the functional circuit. For the purpose of simplicity and clarity, transistors, ILDs, and interconnect structures 320 formed on the substrate 50 may be omitted in subsequent figures. The substrate 50 and transistors (e.g., source / drain regions 306, gate dielectric layer 302, and gate electrode 304), gate spacers 308, first ILD 310, second ILD 312, and interconnect structures 320 may be CMOS under array (CUA), logic die, etc.

[0030] In some embodiments, substrate 50 may include an n-type region and a p-type region (not shown separately). The n-type region may be used to form an n-type device such as an NMOS transistor, for example, an n-type nanoFET, and the p-type region may be used to form a p-type device such as a PMOS transistor, for example, a p-type nanoFET. The n-type region may be physically separate from the p-type region, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region and the p-type region. Any number of n-type regions and p-type regions may be provided.

[0031] exist Figure 3 in Figure 2The multilayer stack 64 is formed on the structure of FIG. 3. For simplicity and clarity, transistors, ILDs, and interconnect structures 320 may be omitted in subsequent figures. Although the multilayer stack 64 is shown as contacting the substrate 50, any number of intermediate layers may be provided between the substrate 50 and the multilayer stack 64. For example, one or more interconnect layers may be provided between the substrate 50 and the multilayer stack 64, and the interconnect layers may include conductive features in an insulating layer (e.g., a low-k dielectric layer). In some embodiments, the conductive features may be patterned to provide a conductive layer for the substrate 50 and / or the memory array 200 (see FIG. 3 ). Figure 1A and Figure 1B ) provide power, ground and / or signal lines for active devices on the substrate. In some embodiments, a multilayer stack 64 can be formed directly on the substrate 50.

[0032] The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, as discussed in more detail below, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of the nanoFET in both the p-type region and the n-type region. In some embodiments, the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of the nanoFET in one of the n-type region and the p-type region, or in both the n-type region and the p-type region. In embodiments where the channel region is formed by the first semiconductor layer 51 or the second semiconductor layer 53 in both the n-type region and the p-type region, the channel regions in both the n-type region and the p-type region may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously.

[0033] For example purposes, the multilayer stack 64 is shown as including three layers each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 51 and the second semiconductor layer 53. Each layer in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material such as silicon, silicon carbon, silicon germanium, germanium, etc. In embodiments where the first semiconductor material and the second semiconductor material are formed of silicon germanium, the first semiconductor material and the second semiconductor material may have different silicon concentrations and germanium concentrations from each other, so that the first semiconductor material and the second semiconductor material may be selectively etched relative to each other. For example purposes, the multilayer stack 64 is shown as having one of the first semiconductor layers 51 as the bottommost semiconductor layer. In some embodiments, the multilayer stack 64 may be formed such that the bottommost layer is one of the second semiconductor layers 53.

[0034] The first semiconductor material and the second semiconductor material can be materials having high etching selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment where the second semiconductor layer 53 of the second semiconductor material is removed, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0035] The first semiconductor layer 51 may be formed to have a thickness T in the range of about 100 nm to about 500 nm. l , and the second semiconductor layer 53 may be formed to have a thickness T2 in the range of about 10 nm to about 50 nm. In some embodiments, the ratio of the thickness T1 of the first semiconductor layer 51 to the thickness T2 of the second semiconductor layer 53 may be in the range of about 2 to about 10. Forming the first semiconductor layer 51 and the second semiconductor layer 53 with specified thicknesses may help allow horizontally adjacent subsequently formed epitaxial source / drain regions (e.g., as described below with respect to FIG. 10A to FIG. 10DThe epitaxial source / drain regions 92 discussed above are merged, while the vertically adjacent subsequently formed epitaxial source / drain regions are not merged. This allows the horizontally merged epitaxial source / drain regions to be used as source lines and bit lines, and prevents short circuits between vertically adjacent epitaxial source / drain regions. Using the merged epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0036] exist FIG. 4A to FIG. 4C In some embodiments, nanostructures 55 may be formed in the multilayer stack 64 by etching grooves in the multilayer stack 64. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. Forming the nanostructures 55 by etching the multilayer stack 64 may define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from the first semiconductor layer 51, and may define second nanostructures 54A-C (collectively referred to as second nanostructures 54) from the second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 may be collectively referred to as nanostructures 55.

[0037] The nanostructure 55 can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern the nanostructure 55. Typically, the double patterning or multi-patterning process combines a photolithography process and a self-alignment process, thereby allowing the creation of a pattern with a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed on top of a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure 55.

[0038] In some embodiments, the nanostructures 55 in the n-type region and the p-type region have substantially equal widths; however, the width of the nanostructure 55 may be greater in one of the n-type region or the p-type region. In addition, although each nanostructure 55 is shown as having a uniform width, in some embodiments, the nanostructures 55 may have tapered sidewalls such that the width of each nanostructure 55 increases continuously in a direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0039] The nanostructures 55 may have a width W1 in a range of about 10 nm to about 50 nm. The nanostructures 55 may be separated by a distance D1 in a range of about 50 nm to about 100 nm. Forming the first nanostructure 55 with a specified width and spacing may help allow for horizontally adjacent subsequently formed epitaxial source / drain regions (e.g., as described below with respect to FIG. 10A to FIG. 10D The epitaxial source / drain regions discussed above are merged, while the vertically adjacent subsequently formed epitaxial source / drain regions are not merged. This allows the horizontally merged epitaxial source / drain regions to be used as source lines and bit lines, and prevents short circuits between vertically adjacent epitaxial source / drain regions. Using the merged epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0040] The above about Figures 3 to 4C The process described is only one example of how the nanostructure 55 can be formed. In some embodiments, the nanostructure 55 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above (e.g., a first semiconductor material and a second semiconductor material). In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material can be in-situ doped during growth, which can avoid implantation before and / or after, but in-situ doping and implantation doping can be used together.

[0041] In addition, for exemplary purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as including the same material in the p-type region and the n-type region. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region and the n-type region, or may be formed in a different order.

[0042] Further in FIG. 4A to FIG. 4CIn the embodiment with different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps for n-type regions and p-type regions. For example, a photoresist can be formed over the nanostructure 55 and the substrate 50 in the n-type region and the p-type region. The photoresist is patterned to expose the p-type region. The photoresist can be formed by using a spin coating technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region. The n-type impurity can be phosphorus, arsenic, antimony, etc., which is implanted into the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process. The process can then be repeated to perform a p-type impurity implantation in the n-type region, wherein the photoresist is formed and patterned to substantially prevent the p-type impurity from being implanted into the p-type region. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region, and its concentration is about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After the implantation of the n-type and p-type regions, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may eliminate the implantation, but in-situ doping and implantation doping may be used together.

[0043] exist FIG. 5A to FIG. 5CIn the embodiment of the present invention, a dummy dielectric layer 70 is formed on the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70, and then planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having high etching selectivity relative to etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region and the p-type region. Note that the dummy dielectric layer 70 is shown to cover only the nanostructures 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the substrate 50, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the substrate 50.

[0044] exist FIG. 6A to FIG. 6C In the embodiment, the mask layer 74 may be patterned using acceptable photolithography and etching techniques (see FIG. 5A to FIG. 5C ) to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the nanostructure 55. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from an adjacent dummy gate 76. The dummy gate 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding nanostructure 55.

[0045] Further in FIG. 6A to FIG. 6C , a first spacer 80 is formed over the nanostructure 55 and adjacent to the dummy gate dielectric 71, the dummy gate 76, and the mask 78. The first spacer 80 may be used as a spacer for forming a self-aligned source / drain region. The first spacer 80 may be formed by depositing a first spacer layer (not separately shown) on the top surface of the substrate 50; the top surface and sidewalls of the nanostructure 55 and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric layer 71. The first spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or may be deposited by CVD, ALD, etc.

[0046] After forming the first spacer layer, an implant for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, FIG. 4A to FIG. 4C As discussed in the implantation, a mask (e.g., photoresist) can be formed over the n-type region while exposing the p-type region, and an impurity of an appropriate type (e.g., p-type) can be implanted into the exposed nanostructures 55 in the p-type region. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type region while exposing the n-type region, and an impurity of an appropriate type (e.g., n-type) can be implanted into the exposed nanostructures 55 in the n-type region. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have a density of approximately 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0047] The first spacer layer can then be etched to form first spacers 81. As will be discussed in more detail below, the first spacers 80 are used to self-align subsequently formed source and drain regions, as well as to protect the sidewalls of the nanostructures 55 during subsequent processes. The first spacer layer can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. Fig. 6A As shown, the first spacer 80 may be disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. Figure 6C As shown, the first spacer 80 may be further disposed on the sidewall of the nanostructure 55 .

[0048] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used, additional spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0049] exist 7A to 7C In the embodiment, a first recess 86 is formed in the nanostructure 55. In some embodiments, the first recess 86 may also extend at least partially into the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54. Fig. 7AAs shown, the first recess 86 may extend to the top surface of the substrate 50. The first recess 86 may be formed by etching the nanostructure 55 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the first recess 86, the first spacer 80 and the mask 78 mask some portions of the nanostructure 55. Each layer of the nanostructure 55 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0050] exist Figure 8 In the embodiment, the portion of the sidewalls of each layer of the multilayer stack 64 formed of the first semiconductor material (eg, the first nanostructure 52) exposed by the first recess 86 is etched to form a sidewall recess 88. Figure 8 The sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are shown as straight, but these sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process (e.g., wet etching, etc.). In embodiments where the first nanostructure 52 includes, for example, silicon germanium and the second nanostructure 54 includes, for example, silicon or silicon carbide, the sidewalls of the first nanostructure 52 can be etched using a wet etching process using hydrogen fluoride, another fluorine-based etchant, etc., or a dry etching process.

[0051] exist Fig.9A and Fig. 9B In the embodiment, a first inner spacer 90 is formed in the sidewall groove 88. Figure 8 An internal spacer layer (not shown separately) is deposited over the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 will be replaced with a corresponding gate structure.

[0052] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, for example, a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54, or be recessed relative to the sidewalls of the second nanostructure 54.

[0053] In addition, despite the Fig.9AThe outer side wall of the first inner spacer 90 is shown as straight, but the outer side wall of the first inner spacer 90 can be concave or convex. As an example, Fig. 9B 10A to 10B are shown, wherein the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed relative to the sidewalls of the second nanostructure 54. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 may be used to prevent etching of the source / drain regions (e.g., as described below with respect to FIGS. 10A to 10B ) that are subsequently formed by a subsequent etching process (e.g., an etching process for forming a gate structure). Fig. 10D Damage to the epitaxial source / drain regions 92) discussed.

[0054] exist FIG. 10A to FIG. 10D In the embodiment, epitaxial source / drain regions 92A-C are formed in the first recess 86. The epitaxial source / drain regions 92A-C may be collectively referred to as epitaxial source / drain regions 92. In some embodiments, the epitaxial source / drain regions 92 may exert stress on the second nanostructure 54, thereby improving performance. Fig. 10A As shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 80 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76 by an appropriate lateral distance, and first internal spacers 90 are used to separate the epitaxial source / drain regions 92 from the first nanostructure 52 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed resulting nanoFET.

[0055] like Fig. 10A , Fig. 10C and Fig. 10DAs shown, epitaxial source / drain regions 92A-C (collectively referred to as epitaxial source / drain regions 92) may be epitaxially grown from the second nanostructures 54A-C, respectively. The epitaxial source / drain regions 92 may be grown so that horizontally adjacent epitaxial source / drain regions 92 (e.g., epitaxial source / drain regions 92 adjacent to each other in a direction parallel to the main surface of the substrate 50) merge with each other, which are illustrated by epitaxial source / drain regions 92A.i and 92A.ii, epitaxial source / drain regions 92B.i and 92B.ii, epitaxial source / drain regions 92C.i and 92C.ii, and corresponding dotted lines. On the other hand, vertically adjacent epitaxial source / drain regions 92 (e.g., epitaxial source / drain regions 92 directly above / directly below each other in a direction perpendicular to the main surface of the substrate 50) remain separated from each other, e.g., epitaxial source / drain regions 92A-C. The epitaxial source / drain regions 92 may extend from sidewalls of the second nanostructure 54 and may extend along sidewalls of the first inner spacer 90 and the first spacer 80 .

[0056] The epitaxial source / drain regions 92 may be epitaxially grown to have a thickness T3 in the range of about 30 nm to about 200 nm. The epitaxial source / drain regions 92 may have a height H1 in the range of about 50 nm to about 400 nm and may be separated from each other by a gap 93 having a height H2 in the range of about 50 nm to about 200 nm. The spacing and size of the first nanostructures 52 and the second nanostructures 54 may be selected together with the thickness T3 to allow horizontally adjacent epitaxial source / drain regions 92 to merge with each other while vertically adjacent epitaxial source / drain regions 92 remain unmerged. In some embodiments, this may be achieved by forming a first semiconductor layer 51 having a thickness T1 that is greater than the distance D1 between adjacent nanostructures 55, so that horizontally adjacent second nanostructures 54 are more closely spaced than vertically adjacent second nanostructures 54. Horizontally adjacent second nanostructures 54 may be separated from each other by a distance D1 in the range of about 50 nm to about 200 nm, and vertically adjacent second nanostructures 54 may be separated from each other by a distance D2 that is greater than distance D1 and in the range of about 100 nm to about 500 nm. This allows the horizontally merged epitaxial source / drain regions 92 to be used as source lines and bit lines, and prevents short circuits between vertically adjacent epitaxial source / drain regions 92. Using the merged epitaxial source / drain regions 92 as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0057] Although epitaxial source / drain regions 92 are shown Fig. 10A The cross-sectional view shown has a rectangular shape and Fig. 10CThe epitaxial source / drain regions 92 are shown as having a circular shape in the cross-sectional view, but the epitaxial source / drain regions 92 may have any suitable cross-sectional shape, for example, a hexagon, an octagon, or other shapes. In some embodiments, the epitaxial source / drain regions 92 may have a small facet. In some embodiments, the epitaxial source / drain regions 92 in both the n-type region and the p-type region may include materials such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc.

[0058] The epitaxial source / drain region 92 in the n-type region (e.g., NMOS region) can be formed by masking the p-type region (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphorus, etc.

[0059] The epitaxial source / drain regions 92 in the p-type region (e.g., PMOS region) can be formed by masking the n-type region (e.g., NMOS region). Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recess 86 in the p-type region. The epitaxial source / drain regions 92 can include any acceptable material suitable for p-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can include a material that exerts compressive strain on the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc.

[0060] The epitaxial source / drain regions 92, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions (similar to the process previously discussed for forming lightly doped source / drain regions) and then annealed. The impurity concentration of the source / drain regions may be about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during growth.

[0061] exist FIG. 11A to FIG. 11D In FIG. 10A to FIG. 10DA first interlayer dielectric (ILD) 96 is deposited on the structure shown. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), ALD, etc. The dielectric material may include silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxide, silicon carbide, silicon oxynitride, etc. Other insulating materials formed by any acceptable process may be used. Fig.11A and Fig. 11C As shown, the first ILD 96 may be formed to surround the epitaxial source / drain regions 92 and fill the gap 93. The first ILD 96 may be formed along: top, side, and bottom surfaces of the epitaxial source / drain regions 92; side surfaces of the first inner spacer 90; side and top surfaces of the first spacer 80; and a top surface of the mask 78.

[0062] exist FIG. 12A to FIG. 12D In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and the portion of the first spacer 80 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 80, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 80.

[0063] exist FIG. 13A to FIG. 13D In the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a second recess 98. The portion of the dummy gate dielectric 71 in the second recess 98 may also be removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etch the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 80. Each second recess 98 exposes and / or overlies portions of the nanostructure 55 that serve as channel regions in the subsequently completed nanoFET. Portions of the nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 may serve as an etch stop layer when etching the dummy gate 76. The dummy gate dielectric 71 may then be removed after the dummy gate 76 is removed.

[0064] exist FIG. 14A to FIG. 14D, the first nanostructure 52 is removed, thereby expanding the second recess 98. The first nanostructure 52 may be removed by performing an isotropic etching process (e.g., wet etching, etc.) using an etchant that is selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 58 remain relatively unetched compared to the first nanostructure 52. In an embodiment where the first nanostructure 52 includes, for example, silicon germanium and the second nanostructures 54A-54C include, for example, silicon or silicon carbide, the first nanostructure 52 may be removed using hydrogen fluoride, another fluorine-based etchant, etc. After the first nanostructure 52 is removed, the second nanostructures 54 adjacent in a vertical direction (e.g., a direction perpendicular to the main surface of the substrate 50) may be separated from each other by a distance equal to the thickness of the first nanostructure (e.g., thickness T1).

[0065] exist FIG. 15A to FIG. 15D , a gate dielectric layer 100 and a gate electrode 102 are formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in the second groove 98. The gate dielectric layer 100 may be formed on the top surface of the substrate 50, and the top surface, side surface, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the top surface and side surface of the first spacer 80, and the side surface of the first inner spacer 90. The gate dielectric layer 100 may be deposited by CVD, PVD, ALD, molecular beam deposition (MBD), PECVD, etc.

[0066] In some embodiments, the gate dielectric layer 100 may include a material that can be switched between two different polarization directions by applying an appropriate voltage difference across the gate dielectric layer 100. The gate dielectric layer 100 may be a high-k dielectric material, such as a hafnium (Hf)-based dielectric material, etc. In some embodiments, the gate dielectric layer 100 includes a ferroelectric (FE) material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc. In some embodiments, the gate dielectric layer 100 may include different ferroelectric materials or different types of dielectric materials. In some embodiments, the gate dielectric layer 100 may be a dielectric layer formed between two SiO x Between the layers include SiN x The gate dielectric layer 100 may be a multilayer dielectric structure (e.g., an ONO structure) of a plurality of layers. The structure of the gate dielectric layer 100 may be the same or different in the n-type region and the p-type region. The gate dielectric layer 100 may have a thickness in the range of about 5 nm to about 20 nm. Forming a gate dielectric layer 100 with a thickness less than 5 nm may impair performance, while forming a gate dielectric layer 100 with a thickness greater than 20 nm may take up too much space.

[0067] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remainder of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although in FIGS. 15A to 15B, the gate electrode 102 may be formed of a plurality of metals, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.15D A single layer gate electrode 102 is shown in FIG. 1 , but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50.

[0068] The formation of the gate dielectric layer 100 in the n-type region and the p-type region may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by a different process, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0069] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 100 and the material of the gate electrode 102 that are above the top surfaces of the first ILD 96 and the first spacer 80. The material of the gate electrode 102 and the remaining portions of the gate dielectric layer 100 thus form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0070] Despite Fig. 14B and Fig. 15B The second nanostructure 54 is shown as having a rectangular cross-sectional shape, but after removing the dummy gate dielectric 71, the dummy gate 76, and the first nanostructure 52, the second nanostructure 54 may have a circular, annular, square, or other cross-sectional shape. As an example, Fig.15EFIG. 15A shows an embodiment in which the second nanostructure 54 has a circular shape in a cross-sectional view, and FIG. 15F shows an embodiment in which the second nanostructure 54 has a square shape in a cross-sectional view. The shape of the second nanostructure 54 can be controlled by controlling the thickness of the second semiconductor layer 53, the width of the second nanostructure 54, and the parameters of the etching process for patterning the second nanostructure 54, removing the dummy gate dielectric 71, the dummy gate 76, and the first nanostructure 52. The gate dielectric layer 100 is conformally formed and thus has a cross-sectional shape similar to that of the second nanostructure 54. For example, in Fig.15E In the illustrated embodiment, the gate dielectric layer 100 has a circular shape in cross-sectional view. Fig.15E In the illustrated embodiment, the gate dielectric layer 100 has a square shape in a cross-sectional view.

[0071] exist FIG. 16A to FIG. 16D In the embodiment of the present invention, a trench 104 is patterned through the gate electrode 102, the gate dielectric layer 100, and the first spacer 80. The trench 104 can also be patterned through the second nanostructure 54. The trench 104 can be patterned by a combination of lithography and etching. The etching can be any acceptable etching process, for example, wet or dry etching, RIE, NBE, etc., or a combination thereof. The etching can be anisotropic. The trench 104 can be disposed between the opposite sidewalls of the first ILD 96 and the epitaxial source / drain region 92, and the trench 104 can separate adjacent stacked entities of the memory cell 202 in the memory array 200 (see Figure 1A ). A ladder structure will be formed in the subsequent structure (for example, FIG. 21A to FIG. 21D In the portion of the step structure 110 discussed above, trenches 104 may also be patterned through the gate electrode 102 , the gate dielectric layer 100 , the first spacers 80 , and the second nanostructures 54 .

[0072] exist 17A to 17D, a dielectric material 106 is deposited in the trench 104 and fills the trench 104. The dielectric material 106 may include, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxide, silicon carbide, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The dielectric material 106 may fill the trench 104 and may be deposited along the top surfaces of the first ILD 96, the first spacer 80, the gate dielectric layer 100, the gate electrode 102, and the substrate 50, and along the sidewalls of the gate dielectric layer 100, the gate electrode 102, the first ILD 96, and the epitaxial source / drain regions 92. After deposition, a planarization process (e.g., CMP, etch back, etc.) may be performed to remove excess portions of the dielectric material 106. In the resulting structure, top surfaces of the first ILD 96 , the first spacer 80 , the gate dielectric layer 100 , the gate electrode 102 , and the dielectric material 106 may be substantially flush with one another (eg, within process variations).

[0073] 18A to 21D The first ILD 96 and the epitaxial source / drain regions 92 are patterned to form a stepped structure 110 (in FIG. FIG. 21A to FIG. 21D ). 18A to 18D In the embodiment of the present invention, a photoresist 108 is formed over the first ILD 96, the dielectric material 106, the first spacer 80, the gate dielectric layer 100, and the gate electrode 102. The photoresist 108 can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. The patterned photoresist 108 can expose portions of the first ILD 96 and the dielectric material 106 in the region 111 while masking the remaining portions of the first ILD 96, the dielectric material 106, the first spacer 80, the gate dielectric layer 100, and the gate electrode 102.

[0074] Further in 18A to 18DIn the embodiment of the present invention, the exposed portion of the first ILD 96 in the region 111 is etched using the photoresist 108 as a mask, and the portion of the epitaxial source / drain region 92C under the exposed portion of the first ILD 96 in the region 111 is etched using the first ILD 96 as a mask. The etching can be any acceptable etching process, for example, wet or dry etching, RIE, NBE, etc., or a combination thereof. The etching can be anisotropic. The etching can remove the first ILD 96 and the portion of the epitaxial source / drain region 92C in the region 111 and define the opening 109. Since the first ILD 96 and the epitaxial source / drain region 92C have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, the epitaxial source / drain region 92C is used as an etch stop layer when etching the first ILD 96, and the first ILD 96 is used as an etch stop layer when etching the epitaxial source / drain region 92C. As a result, portions of the first ILD 96 and the epitaxial source / drain regions 92C can be selectively removed without removing the remaining portions of the first ILD 96 and the epitaxial source / drain regions 92, and the opening 109 can be extended to a desired depth. Alternatively, a timed etching process can be used to stop etching the opening 109 after the opening 109 reaches the desired depth. In the resulting structure, a portion of the first ILD 96 above the epitaxial source / drain regions 92B is exposed in the region 111.

[0075] exist FIG. 19A to FIG. 19D 113, the photoresist 108 is trimmed to expose additional portions of the first ILD 96 and the dielectric material 106. Acceptable photolithography techniques may be used to trim the photoresist 108. As a result of the trimming, the width of the photoresist 108 is reduced, and portions of the first ILD 96 and the dielectric material 106 in the regions 111 and 113 are exposed. For example, the top surfaces of the first ILD 96 and the dielectric material 106 in the regions 113 and 111 may be exposed.

[0076] Then, the exposed portions of the first ILD 96 and the epitaxial source / drain regions 92 may be etched using the photoresist 108 and the portions of the first ILD 96 and the epitaxial source / drain regions 92C as masks. The etching may be any suitable etching process, such as wet or dry etching, RIE, NBE, etc., or a combination thereof. The etching process may be anisotropic. The etching may further extend the opening 109 into the first ILD 96 and the epitaxial source / drain regions 92. Since the first ILD 96 and the epitaxial source / drain regions 92 have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, the epitaxial source / drain regions 92B-C are used as an etch stop layer when etching portions of the first ILD 96, and portions of the first ILD 96 are used as an etch stop layer when etching the epitaxial source / drain regions 92B-C. As a result, the first ILD 96 and the epitaxial source / drain regions 92B-C can be selectively etched without etching the rest of the first ILD 96 and the epitaxial source / drain regions 92, and the opening 109 can be extended to a desired depth. Alternatively, a timed etching process can be used to stop etching the opening 109 after the opening 109 reaches the desired depth. In addition, during the etching process, the unetched portions of the first ILD 96 and the epitaxial source / drain regions 92 serve as a mask for the underlying layers, and thus the previous pattern of the first ILD 96 and the epitaxial source / drain regions 92C (see FIG. 1 ) is not etched. 18A to 18D ) can be transferred to the underlying first ILD 96 and the underlying epitaxial source / drain regions 92B. In the resulting structure, a portion of the first ILD 96 above the epitaxial source / drain regions 92A is exposed in region 111, and a portion of the first ILD 96 above the epitaxial source / drain regions 92B is exposed in region 113.

[0077] exist FIG. 20A to FIG. 20D 1, the photoresist 108 is trimmed to expose additional portions of the first ILD 96 and the dielectric material 106. Acceptable photolithography techniques may be used to trim the photoresist 108. As a result of the trimming, the width of the photoresist 108 is reduced, and portions of the first ILD 96 and the dielectric material 106 in the regions 111, 113, and 115 are exposed. For example, the top surfaces of the first ILD 96 and the dielectric material 106 in the regions 115, 113, and 111 may be exposed.

[0078] Then, the exposed portions of the first ILD 96 and the epitaxial source / drain regions 92 may be etched using the photoresist 108, the first ILD 96, the epitaxial source / drain regions 92C, and the epitaxial source / drain regions 92B as masks. The etching may be any suitable etching process, for example, wet or dry etching, RIE, NBE, etc., or a combination thereof. The etching process may be anisotropic. The etching may further extend the opening 109 into the first ILD 96 and the epitaxial source / drain regions 92. Since the first ILD 96 and the epitaxial source / drain regions 92 have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, the epitaxial source / drain regions 92A-C are used as an etch stop layer when etching portions of the first ILD 96, and portions of the first ILD 96 are used as an etch stop layer when etching the epitaxial source / drain regions 92A-C. As a result, the first ILD 96 and the epitaxial source / drain regions 92A-C can be selectively etched without etching the rest of the first ILD 96, and the opening 109 can be extended to a desired depth. Alternatively, a timed etching process can be used to stop etching the opening 109 after the opening 109 reaches the desired depth. In addition, during the etching process, the unetched portions of the first ILD 96 and the epitaxial source / drain regions 92 serve as a mask for the underlying layers, and thus the previous pattern of the first ILD 96 and the epitaxial source / drain regions 92B-C (see FIG. 1 ) is not etched. FIG. 19A to FIG. 19D ) may be transferred to the underlying first ILD 96 and the underlying epitaxial source / drain regions 92A-B. In the resulting structure, a portion of the first ILD 96 above the substrate 50 is exposed in region 111, a portion of the first ILD 96 above the epitaxial source / drain regions 92A is exposed in region 113, and a portion of the first ILD 96 above the epitaxial source / drain regions 92B is exposed in region 115.

[0079] exist FIG. 21A to FIG. 21D In the embodiment, the photoresist 108 is removed by an acceptable ashing or wet stripping process. Thus, a stepped structure 110 is formed. The stepped structure 110 includes a stack of alternating layers of the first ILD 96 and the epitaxial source / drain regions 92. Fig. 21C As shown, the length of epitaxial source / drain regions 92 increases in a direction toward substrate 50, such that epitaxial source / drain regions 92A are longer and extend laterally beyond epitaxial source / drain regions 92B, and epitaxial source / drain regions 92B are longer and extend laterally beyond epitaxial source / drain regions 92C. As a result, conductive contact can be made from above stepped structure 110 to each epitaxial source / drain region 92 in subsequent process steps.

[0080] exist FIG. 22A to FIG. 22DIn the embodiment, the intermetal dielectric (IMD) 112 is deposited on FIG. 21A to FIG. 21D The IMD 112 may be formed along the top surfaces of the first ILD 96, the first spacer 80, the gate dielectric layer 100, the gate electrode 102, the dielectric material 106, and the epitaxial source / drain regions 92A-C, and along the side surfaces of the first ILD 96 and the epitaxial source / drain regions 92A-C. The IMD 112 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, PECVD, flowable CVD (FCVD), etc. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the IMD 112 may include an oxide (e.g., silicon oxide, etc.), a nitride (e.g., silicon nitride, etc.), a combination thereof, etc. Other dielectric materials formed by any acceptable process may be used.

[0081] Further in FIG. 22A to FIG. 22D 1 , contacts 114 and contacts 116 are formed to extend and electrically couple to epitaxial source / drain regions 92 and gate electrode 102, respectively. The stepped shape of epitaxial source / drain regions 92 provides a surface on each epitaxial source / drain region 92 for contact 114 to land on. For example, forming contacts 114 and contacts 116 may include patterning openings in IMD 112 using a combination of photolithography and etching to expose portions of epitaxial source / drain regions 92 and gate electrode 102. In some embodiments, the openings in IMD 112 may be formed by a process having a high etch selectivity to the material of IMD 112. In this way, the openings in IMD 112 may be formed without significantly removing the material of epitaxial source / drain regions 92 and gate electrode 102.

[0082] In some embodiments, the openings exposing each epitaxial source / drain region 92A-C may be formed simultaneously. Due to the variation in thickness of IMD 112 over each epitaxial source / drain region 92A-C, epitaxial source / drain region 92C may be exposed to etching for a longer duration than epitaxial source / drain region 92B, which in turn may be exposed to etching for a longer duration than epitaxial source / drain region 92A. Exposure to etching may cause some material loss, pitting, or other damage in epitaxial source / drain regions 92, such that epitaxial source / drain region 92C is damaged to the greatest extent, epitaxial source / drain region 92B is damaged to a reduced extent, and epitaxial source / drain region 92A is damaged to the least extent. The openings exposing the gate electrodes 102 may be formed simultaneously with the openings exposing the epitaxial source / drain regions 92 , or may be formed by a separate etching process that is similar to or the same as the etching process used to form the openings exposing the epitaxial source / drain regions 92 .

[0083] A liner (not shown separately) such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, etc. Contacts 114 and 116 may be formed simultaneously or separately. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 112. The remaining liner and conductive material form contacts 114 and 116 in the opening. Fig. 22C As shown, a contact 114 may extend to each epitaxial source / drain region 92A-C. Fig. 22B As shown, a contact 116 extends to each gate electrode 102 .

[0084] exist Fig.231, conductive lines 118 and conductive lines 120 are formed on contacts 114 and contacts 116, respectively, and are electrically coupled to contacts 114 and contacts 116, respectively. Conductive lines 118 and conductive lines 120 may be formed on IMD 112. In some embodiments, conductive lines 118 and conductive lines 120 may be formed in additional IMD layers that are formed on IMD 112 by processes and materials that are the same or similar to those used for IMD 112. In some embodiments, conductive lines 118 and conductive lines 120 may be formed using a damascene process, wherein additional IMD layers on IMD 112 are patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of conductive lines 118 and conductive lines 120. An optional diffusion barrier layer and / or an optional adhesion layer may be deposited in the trenches, and then the trenches may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, or other alternatives. Suitable materials for the conductive material include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, combinations thereof, etc. In an embodiment, conductive lines 118 and conductive lines 120 may be formed by depositing a seed layer of copper or copper alloy and filling the trenches using electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the additional IMD layer and planarize the surfaces of conductive lines 118 and conductive lines 120 and the additional IMD layer for subsequent processes.

[0085] like Fig.23 As shown, the gate electrodes 102 adjacent in a direction perpendicular to the length direction of the epitaxial source / drain regions 92 may be electrically coupled to different conductive lines 120. Each contact 114 may be electrically coupled to one of the conductive lines 118. In some embodiments, the gate electrode 102 may be a word line, which is connected to a word signal through the contact 116 and the conductive line 120. The epitaxial source / drain regions 92 on the first side of the stepped structure 110 may be a source line, which is electrically coupled to a voltage source through the contact 114 and the conductive line 118, and the epitaxial source / drain regions 92 on the second side of the stepped structure 110 may be a bit line, which is electrically coupled to ground through the contact 114 and the conductive line 118.

[0086] Forming epitaxial source / drain regions 92 horizontally merged and vertically isolated from one another allows individual connections to be made to each epitaxial source / drain region 92A-C in stepped structure 110. This increases the number of devices that can be provided in a given area (eg, increases device density) and reduces cost.

[0087] FIG. 24A to FIG. 32 An embodiment is shown in which the second nanostructures 54 of adjacent gate structures are staggered with respect to each other. FIG. 24A to FIG. 24Cshows that after having executed Figure 3 4C and after steps similar or identical to those discussed above. The nanostructure 55 may be formed to have the same Figures 3 to 4C For example, the nanostructures 55 may have a width W2 in the range of about 10 nm to about 50 nm. The nanostructures 55 may be separated by a distance D3 in the range of about 20 nm to about 300 nm. Forming the first nanostructure 55 with a specified width and spacing may help allow for horizontally adjacent subsequently formed epitaxial source / drain regions (e.g., as described below with respect to FIG. 29A to FIG. 29D The epitaxial source / drain regions discussed above are merged, while the vertically adjacent subsequently formed epitaxial source / drain regions are not merged. This allows the horizontally merged epitaxial source / drain regions to be used as source lines and bit lines, and prevents short circuits between vertically adjacent epitaxial source / drain regions. Using the merged epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0088] The nanostructures 55 may include first nanostructures 52A-C (collectively referred to as first nanostructures 52) and second nanostructures 54A-C (collectively referred to as second nanostructures 54) similar or identical to those described above. The first nanostructures 52 may be formed to have a height H3 in the range of about 100 nm to about 500 nm, and the second nanostructures 54 may be formed to have a height H4 in the range of about 10 nm to about 50 nm. In some embodiments, the ratio of the height H3 of the first nanostructures 52 to the height H4 of the second nanostructures 54 may be in the range of about 2 to about 10. Forming the first nanostructures 52 and the second nanostructures 54 with a specified thickness may help allow horizontally adjacent subsequently formed epitaxial source / drain regions (e.g., as described below with respect to FIG. 29A to FIG. 29D The epitaxial source / drain regions discussed above are merged, while the vertically adjacent subsequently formed epitaxial source / drain regions are not merged. This allows the horizontally merged epitaxial source / drain regions to be used as source lines and bit lines, and prevents short circuits between vertically adjacent epitaxial source / drain regions. Using the merged epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0089] exist FIG. 25A to FIG. 25C In the embodiment, the nanostructures 55 are patterned to form gaps 130 in each nanostructure 55. The gaps 130 may extend through the second nanostructures 54A-C and the first nanostructures 52A-C and may expose the surface of the substrate 50. FIG. 4A to FIG. 4CThe nanostructures 55 may be patterned using the same or similar processes discussed above. In some embodiments, the nanostructures 55 may be formed and patterned to form the gaps 130 in a single process step. Fig.25C As shown, the gaps 130 formed in adjacent nanostructures 55 can be staggered, and the remaining portions of adjacent nanostructures 55 can also be staggered. Portions of the remaining portions of adjacent nanostructures 55 can overlap each other. Forming nanostructures 55 in a staggered configuration can simplify the connection with the second nanostructure 54 in subsequent steps, reduce costs and reduce device defects. After patterning of nanostructures 55, portions of nanostructures 55 that subsequently form the channel region of transistor 204 can be separated from each other by a distance D4 in the range of about 50 nm to about 200 nm in a direction perpendicular to the longitudinal axis of nanostructures 55.

[0090] exist FIG. 26A to FIG. 26C In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having high etching selectivity relative to etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed on the n-type region and the p-type region. Note that the dummy dielectric layer 70 is shown to cover only the nanostructures 55 for exemplary purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the substrate 50, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the substrate 50.

[0091] exist FIG. 27A to FIG. 27C In the embodiment, the mask layer 74 may be patterned using acceptable photolithography and etching techniques (see FIG. 26A to FIG. 26C) to form mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70, respectively, to form dummy gate 76 and dummy gate dielectric 71. Dummy gate 76 covers the corresponding channel region of nanostructure 55. The pattern of mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. Dummy gate 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding nanostructure 55.

[0092] Further in FIG. 27A to FIG. 27C , a first spacer 80 is formed over the nanostructure 55, the adjacent dummy gate dielectric 71, the dummy gate 76, and the mask 78. The first spacer 80 can be used as a spacer for forming a self-aligned source / drain region. The first spacer 80 can be formed by depositing a first spacer layer (not separately shown) on the top surface of the substrate 50; the top surface and sidewalls of the nanostructure 55 and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. The first spacer layer can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or can be deposited by CVD, ALD, etc.

[0093] The first spacer layer can then be etched to form first spacers 81. As will be discussed in more detail below, the first spacers 80 are used to self-align subsequently formed source and drain regions, as well as to protect the sidewalls of the nanostructures 55 during subsequent processes. The first spacer layer can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. Fig.27A As shown, the first spacer 80 may be disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. Fig.27C As shown, the first spacer 80 may be further disposed on the sidewall of the nanostructure 55 .

[0094] like Fig.27A As shown, the first spacer 80 may be formed to extend along the end surfaces of the first nanostructure 52 and the second nanostructure 54. In some embodiments, the dummy gate 76 may be formed to extend along the end surfaces of the first nanostructure 52 and the second nanostructure 54, and the first spacer 80 may be formed on the second nanostructure 54C.

[0095] Although the nanostructure 55 is described as being patterned to form the gap 130 before forming and patterning the dummy gate 76, the dummy gate dielectric 71, and the mask 78, in some embodiments, the nanostructure 55 may be patterned to form the gap 130 after forming and patterning the dummy gate 76, the dummy gate dielectric 71, and the mask 78. In addition, the nanostructure 55 may be patterned to form the gap 130 before or after forming the first spacer 80.

[0096] exist FIG. 28A to FIG. 28C In the embodiment, a first recess 86 is formed in the nanostructure 55. In some embodiments, the first recess 86 may also extend at least partially into the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54. Fig.28A As shown, the first recess 86 may extend to the top surface of the substrate 50. The first recess 86 may be formed by etching the nanostructure 55 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the first recess 86, the first spacer 80 and the mask 78 mask portions of the nanostructure 55. Each layer of the nanostructure 55 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0097] Further in FIG. 28A to FIG. 28C In the embodiment, the portion of the sidewall of the first nanostructure 52 exposed by the first groove 86 is replaced by the first inner spacer 90. Figure 8 The first nanostructure 52 may then be etched using the same or similar process discussed above. Fig.9A or Fig. 9B The first inner spacer 90 may be formed using the same or similar processes and materials discussed above.

[0098] exist FIG. 29A to FIG. 29D In the embodiment, epitaxial source / drain regions 92A-C are formed in the first recess 86. The epitaxial source / drain regions 92A-C may be collectively referred to as epitaxial source / drain regions 92. In some embodiments, the epitaxial source / drain regions 92 may exert stress on the second nanostructure 54, thereby improving performance. Fig.29AAs shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 80 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76 by an appropriate lateral distance, and first internal spacers 90 are used to separate the epitaxial source / drain regions 92 from the first nanostructure 52 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed resulting nanoFET.

[0099] like Fig.29A , Fig.29C and Fig.29D As shown, epitaxial source / drain regions 92A-C may be epitaxially grown from second nanostructures 54A-C, respectively. Epitaxial source / drain regions 92 may be grown so that horizontally adjacent epitaxial source / drain regions 92 (e.g., epitaxial source / drain regions 92 adjacent to each other in a direction parallel to the main surface of substrate 50) merge with each other, for example, epitaxial source / drain regions 92A.i and 92A.ii, epitaxial source / drain regions 92B.i and 92B.ii, epitaxial source / drain regions 92C.i and 92C.ii, and corresponding dotted lines. On the other hand, vertically adjacent epitaxial source / drain regions 92 (e.g., epitaxial source / drain regions 92 directly above / directly below each other in a direction perpendicular to the main surface of substrate 50) remain separated from each other, for example, epitaxial source / drain regions 92A-C. The epitaxial source / drain regions 92 may extend from sidewalls of the second nanostructure 54 and may extend along sidewalls of the first inner spacer 90 and the first spacer 80 .

[0100] The epitaxial source / drain regions 92 may be epitaxially grown to have a thickness T4 in the range of about 30 nm to about 200 nm. The epitaxial source / drain regions 92 may have a height H5 in the range of about 50 nm to about 400 nm and may be separated from each other by a gap 93 having a height H6 in the range of about 50 nm to about 200 nm. The spacing and size of the first nanostructures 52 and the second nanostructures 54 may be selected together with the thickness T4 to allow horizontally adjacent epitaxial source / drain regions 92 to merge with each other while vertically adjacent epitaxial source / drain regions 92 remain unmerged. In some embodiments, this may be achieved by forming a first nanostructure 52 having a height H3 that is greater than the distance D4 between adjacent nanostructures 55 so that horizontally adjacent second nanostructures 54 are more closely spaced than vertically adjacent second nanostructures 54. Horizontally adjacent second nanostructures 54 may be separated from each other by a distance D4 in the range of about 50 nm to about 200 nm, and vertically adjacent second nanostructures 54 may be separated from each other by a distance D5 that is greater than distance D4 and in the range of about 100 nm to about 500 nm. This allows the horizontally merged epitaxial source / drain regions 92 to be used as source lines and bit lines, and prevents short circuits between vertically adjacent epitaxial source / drain regions 92. Using the merged epitaxial source / drain regions 92 as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0101] Although epitaxial source / drain regions 92 are shown Fig.29A The cross-sectional view shown has a rectangular shape and Fig.29C The epitaxial source / drain regions 92 are shown as having a circular shape in the cross-sectional view, but the epitaxial source / drain regions 92 may have any suitable cross-sectional shape, for example, a hexagon, an octagon, or other shapes. In some embodiments, the epitaxial source / drain regions 92 may have a small facet. In some embodiments, the epitaxial source / drain regions 92 in both the n-type region and the p-type region may include materials such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc.

[0102] The epitaxial source / drain region 92 in the n-type region (e.g., NMOS region) can be formed by masking the p-type region (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphorus, etc.

[0103] The epitaxial source / drain regions 92 in the p-type region (e.g., PMOS region) can be formed by masking the n-type region (e.g., NMOS region). Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recess 86 in the p-type region. The epitaxial source / drain regions 92 can include any acceptable material suitable for p-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can include a material that exerts compressive strain on the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc.

[0104] The epitaxial source / drain regions 92, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The impurity concentration of the source / drain regions may be about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during growth.

[0105] FIG. 30A to FIG. 30D This shows that the above has been executed FIG. 11A to FIG. 21D Specifically, a first ILD 96 is formed around the epitaxial source / drain regions 92, a dummy gate structure is replaced with a gate structure including a gate electrode 102 and a gate dielectric layer 100, a portion of the gate structure is replaced with a dielectric material 106, and a stepped structure 110 is formed in the epitaxial source / drain regions 92 and the first ILD 96.

[0106] exist FIG. 31A to FIG. 31D In the embodiment, the intermetal dielectric (IMD) 112 is deposited on FIG. 30A to FIG. 30DThe IMD 112 may be formed along the top surfaces of the first ILD 96, the first spacer 80, the gate dielectric layer 100, the gate electrode 102, the dielectric material 106, and the epitaxial source / drain regions 92A-C, and along the side surfaces of the first ILD 96 and the epitaxial source / drain regions 92A-C. The IMD 112 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, PECVD, flowable CVD (FCVD), etc. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the IMD 112 may include an oxide (e.g., silicon oxide, etc.), a nitride (e.g., silicon nitride, etc.), a combination thereof, etc. Other dielectric materials formed by any acceptable process may be used.

[0107] Further in FIG. 31A to FIG. 31D 1 , contacts 114 and contacts 116 are formed to extend and electrically couple to epitaxial source / drain regions 92 and gate electrode 102, respectively. The stepped shape of epitaxial source / drain regions 92 provides a surface on each epitaxial source / drain region 92 for contact 114 to land on. For example, forming contacts 114 and contacts 116 may include patterning openings in IMD 112 using a combination of photolithography and etching to expose portions of epitaxial source / drain regions 92 and gate electrode 102. In some embodiments, the openings in IMD 112 may be formed by a process having a high etch selectivity to the material of IMD 112. In this way, the openings in IMD 112 may be formed without significantly removing the material of epitaxial source / drain regions 92 and gate electrode 102.

[0108] In some embodiments, the openings exposing each epitaxial source / drain region 92A-C may be formed simultaneously. Due to the variation in thickness of IMD 112 over each epitaxial source / drain region 92A-C, epitaxial source / drain region 92C may be exposed to etching for a longer duration than epitaxial source / drain region 92B, which in turn may be exposed to etching for a longer duration than epitaxial source / drain region 92A. Exposure to etching may cause some material loss, pitting, or other damage in epitaxial source / drain regions 92, such that epitaxial source / drain region 92C is damaged to the greatest extent, epitaxial source / drain region 92B is damaged to a reduced extent, and epitaxial source / drain region 92A is damaged to the least extent. The openings exposing the gate electrodes 102 may be formed simultaneously with the openings exposing the epitaxial source / drain regions 92 , or may be formed by a separate etching process that is similar to or the same as the etching process used to form the openings exposing the epitaxial source / drain regions 92 .

[0109] A liner (not shown separately) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, etc. Contacts 114 and 116 may be formed simultaneously or separately. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 112. The remaining liner and conductive material form contacts 114 and 116 in the opening. Fig.31C As shown, a contact 114 may extend to each epitaxial source / drain region 92A-C. Fig.31B As shown, a contact 116 extends to each gate electrode 102 .

[0110] exist Fig.32 1, conductive lines 118 and conductive lines 120 are formed on contacts 114 and contacts 116, respectively, and are electrically coupled to contacts 114 and contacts 116, respectively. Conductive lines 118 and conductive lines 120 may be formed on IMD 112. In some embodiments, conductive lines 118 and conductive lines 120 may be formed in additional IMD layers that are formed on IMD 112 by processes and materials that are the same or similar to those used for IMD 112. In some embodiments, conductive lines 118 and conductive lines 120 may be formed using a damascene process, wherein additional IMD layers on IMD 112 are patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of conductive lines 118 and conductive lines 120. An optional diffusion barrier layer and / or an optional adhesion layer may be deposited in the trenches, and then the trenches may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, or other alternatives. Suitable materials for the conductive material include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, combinations thereof, etc. In an embodiment, conductive lines 118 and conductive lines 120 may be formed by depositing a seed layer of copper or copper alloy and filling the trenches using electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the additional IMD layer and planarize the surfaces of conductive lines 118 and conductive lines 120 and the additional IMD layer for subsequent processes.

[0111] like Fig.32 As shown, each stack of the first nanostructure 52 ( FIG. 24A to FIG. 24CThe gate electrodes 102 formed by the first nanostructures 52 may be electrically coupled to the same conductive line 120. The gate electrodes 102 formed by adjacent first nanostructures 52 are connected to adjacent conductive lines 120. Each contact 114 may be electrically coupled to one of the conductive lines 118. In some embodiments, the gate electrode 102 may be a word line, which is connected to a word signal through the contact 116 and the conductive line 120. The epitaxial source / drain region 92 on the first side of the stepped structure 110 may be a source line, which is electrically coupled to a voltage source through the contact 114 and the conductive line 118, and the epitaxial source / drain region 92 on the second side of the stepped structure 110 may be a bit line, which is electrically coupled to ground through the contact 114 and the conductive line 118. FIG. 25A to FIG. 25C Forming the nanostructures 55 in a staggered configuration allows a single conductive line 120 to be electrically coupled to the gate electrode 102 formed by each stack of first nanostructures 52, which simplifies connection layout, reduces cost, and reduces device defects.

[0112] Embodiments can achieve various advantages. For example, forming epitaxial source / drain regions 92 that are horizontally merged and vertically isolated from each other allows individual connections to be made to each epitaxial source / drain region 92A-C in the stepped structure 110. This increases the number of devices that can be provided in a given area (e.g., increases device density) and reduces cost.

[0113] According to one embodiment, a memory array includes: a first channel region on a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric. In one embodiment, the memory array also includes: a second channel region located directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, the second channel region electrically coupled to the second epitaxial region, and the gate dielectric also surrounding the second channel region. In one embodiment, the ratio of the distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate to the height of the first channel region and the second channel region is 2 to 10. In one embodiment, the memory array further comprises: a second channel region located directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region; and a third channel region adjacent to the first channel region in a direction parallel to the main surface of the semiconductor substrate, the third channel region being electrically coupled to the first epitaxial region. In one embodiment, the distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate is greater than the distance between the first channel region and the third channel region in a direction parallel to the main surface of the semiconductor substrate. In one embodiment, the distance between the second epitaxial region and the semiconductor substrate is greater than the distance between the first epitaxial region and the semiconductor substrate, and the length of the second epitaxial region is less than the length of the first epitaxial region. In one embodiment, the gate dielectric comprises a ferroelectric material.

[0114] According to another embodiment, a semiconductor device includes: a first channel region on a semiconductor substrate; a second channel region located directly above the first channel region in a vertical direction; a first gate structure surrounding the first channel region and the second channel region; a third channel region adjacent to the first channel region in a horizontal direction; a first source / drain region electrically coupled to the first channel region and the third channel region; and a second source / drain region electrically coupled to the second channel region and isolated from the first source / drain region, and a first dielectric material extending between the first source / drain region and the second source / drain region. In one embodiment, the second gate structure surrounds the third channel region, and the second gate structure is separated from the first gate structure by a second dielectric material. In one embodiment, the length of the second source / drain region is less than the length of the first source / drain region. In one embodiment, the first source / drain region and the second source / drain region are bit lines or source lines, and the first gate structure is a word line. In one embodiment, the memory array further includes: a third source / drain region electrically coupled to the first channel region and the third channel region, the third source / drain region being disposed on a side of the first channel region and the third channel region opposite to the first source / drain region, the first source / drain region being a source line, and the third source / drain region being a bit line. In one embodiment, the memory array further includes: a fourth channel region electrically coupled to the first source / drain region, the longitudinal axis of the fourth channel region being aligned with the longitudinal axis of the first channel region; a second gate structure surrounding the fourth channel region; a first conductive line electrically coupled to the first gate structure, the first conductive line being disposed on a first side of the first channel region and the fourth channel region in a horizontal direction; and a second conductive line electrically coupled to the second gate structure, the second conductive line being disposed on a second side of the first channel region and the fourth channel region opposite to the first side in a horizontal direction. In one embodiment, the memory array further includes: a fourth channel region electrically coupled to a first source / drain region opposite to the first channel region, a longitudinal axis of the fourth channel region being aligned with the first gate structure; and a second gate structure surrounding the fourth channel region, a longitudinal axis of the first channel region being aligned with the second gate structure.

[0115] According to yet another embodiment, a method includes: forming a multilayer stack on a semiconductor substrate, the multilayer stack including alternating layers of a first semiconductor material and a second semiconductor material; patterning the multilayer stack to form a first plurality of nanostructures including the first semiconductor material and a second plurality of nanostructures including the second semiconductor material, the second plurality of nanostructures including a first nanostructure, a second nanostructure adjacent to the first nanostructure in a direction parallel to a major surface of the semiconductor substrate, and a third nanostructure located directly above the first nanostructure in a direction perpendicular to the major surface of the semiconductor substrate; forming a gate structure on the multilayer stack; etching the multilayer stack to form a first recess adjacent to the gate structure; and epitaxially growing source / drain regions from the second plurality of nanostructures, after epitaxially growing the source / drain regions, the first source / drain region epitaxially grown from the first nanostructure and the second source / drain region epitaxially grown from the second nanostructure merge with each other, and the third source / drain region epitaxially grown from the third nanostructure is isolated from the first source / drain region. In one embodiment, the longitudinal axes of the first plurality of nanostructures and the longitudinal axes of the second plurality of nanostructures extend parallel to the first direction, and after patterning the multilayer stack, the first plurality of nanostructures and the second plurality of nanostructures form a first stack and a second stack, the second stack being separated from the first stack in the first direction. In one embodiment, after patterning the multilayer stack, the first plurality of nanostructures and the second plurality of nanostructures also form a third stack, the third stack being separated from the first stack and the second stack in a second direction perpendicular to the first direction, the first end surface of the third stack being located between the opposite end surfaces of the first stack in the first direction, and the second end surface of the third stack being opposite to the first end surface being located between the opposite end surfaces of the second stack in the first direction. In one embodiment, the method further includes: removing the first plurality of nanostructures and the gate structure to form a second recess; and forming a replacement gate structure in the second recess. In one embodiment, the method further includes: patterning the replacement gate structure to form a third recess, the third recess separating the first replacement gate structure from the second replacement gate structure; and forming a dielectric material in the third recess. In one embodiment, the method further includes: forming a dielectric material between the first source / drain region and the third source / drain region, the dielectric material isolating the first source / drain region from the third source / drain region.

[0116] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0117] Example 1. A storage array comprising:

[0118] a first channel region on the semiconductor substrate;

[0119] a first epitaxial region electrically coupled to the first channel region;

[0120] a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate;

[0121] a dielectric material between the first epitaxial region and the second epitaxial region, wherein the second epitaxial region is isolated from the first epitaxial region by the dielectric material;

[0122] a gate dielectric surrounding the first channel region; and

[0123] A gate electrode surrounds the gate dielectric.

[0124] Example 2. The storage array according to Example 1 further includes a second channel region, which is located directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, and the second channel region is electrically coupled to the second epitaxial region, wherein the gate dielectric also surrounds the second channel region.

[0125] Example 3. The storage array of Example 2, wherein a ratio of a distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate to a height of the first channel region and the second channel region is 2 to 10.

[0126] Example 4. The storage array of Example 2 further comprising:

[0127] a second channel region located directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region; and

[0128] A third channel region is adjacent to the first channel region in a direction parallel to the main surface of the semiconductor substrate, and the third channel region is electrically coupled to the first epitaxial region.

[0129] Example 5. A storage array according to Example 4, wherein a distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate is greater than a distance between the first channel region and the third channel region in a direction parallel to the main surface of the semiconductor substrate.

[0130] Example 6. A storage array according to Example 1, wherein the distance between the second epitaxial region and the semiconductor substrate is greater than the distance between the first epitaxial region and the semiconductor substrate, and wherein the length of the second epitaxial region is less than the length of the first epitaxial region.

[0131] Example 7. The memory array of Example 1, wherein the gate dielectric comprises a ferroelectric material.

[0132] Example 8. A semiconductor device comprising:

[0133] a first channel region on the semiconductor substrate;

[0134] a second channel region located directly above the first channel region in a vertical direction;

[0135] a first gate structure surrounding the first channel region and the second channel region;

[0136] a third channel region, adjacent to the first channel region in a horizontal direction;

[0137] a first source / drain region electrically coupled to the first channel region and the third channel region; and

[0138] A second source / drain region is electrically coupled to the second channel region and isolated from the first source / drain region, wherein a first dielectric material extends between the first source / drain region and the second source / drain region.

[0139] Example 9. The semiconductor device of Example 8, wherein a second gate structure surrounds the third channel region, the second gate structure being separated from the first gate structure by a second dielectric material.

[0140] Example 10. The semiconductor device of Example 8, wherein a length of the second source / drain region is less than a length of the first source / drain region.

[0141] Example 11. The semiconductor device of Example 8, wherein the first source / drain region and the second source / drain region are bit lines or source lines, and wherein the first gate structure is a word line.

[0142] Example 12. The semiconductor device according to Example 8 further includes: a third source / drain region electrically coupled to the first channel region and the third channel region, the third source / drain region being arranged on a side of the first channel region and the third channel region opposite to the first source / drain region, wherein the first source / drain region is a source line, and wherein the third source / drain region is a bit line.

[0143] Example 13. The semiconductor device according to Example 8, further comprising:

[0144] a fourth channel region electrically coupled to the first source / drain region, wherein a longitudinal axis of the fourth channel region is aligned with a longitudinal axis of the first channel region;

[0145] a second gate structure surrounding the fourth channel region;

[0146] a first conductive line electrically coupled to the first gate structure, the first conductive line being disposed at a first side of the first channel region and the fourth channel region in the horizontal direction; and

[0147] A second conductive line is electrically coupled to the second gate structure, and the second conductive line is disposed on a second side of the first channel region and the fourth channel region opposite to the first side in the horizontal direction.

[0148] Example 14. The semiconductor device according to Example 8, further comprising:

[0149] a fourth channel region electrically coupled to the first source / drain region opposite the first channel region, wherein a longitudinal axis of the fourth channel region is aligned with the first gate structure; and

[0150] A second gate structure surrounds the fourth channel region, wherein a longitudinal axis of the first channel region is aligned with the second gate structure.

[0151] Example 15. A method comprising:

[0152] forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating layers of a first semiconductor material and a second semiconductor material;

[0153] Patterning the multilayer stack to form a first plurality of nanostructures comprising the first semiconductor material and a second plurality of nanostructures comprising the second semiconductor material, the second plurality of nanostructures comprising a first nanostructure, a second nanostructure, and a third nanostructure, the second nanostructure being adjacent to the first nanostructure in a direction parallel to a major surface of the semiconductor substrate, the third nanostructure being located directly above the first nanostructure in a direction perpendicular to the major surface of the semiconductor substrate;

[0154] forming a gate structure over the multilayer stack;

[0155] etching the multilayer stack to form a first recess adjacent to the gate structure; and

[0156] Epitaxially growing source / drain regions from the second plurality of nanostructures, wherein, after epitaxially growing the source / drain regions, a first source / drain region epitaxially grown from the first nanostructures and a second source / drain region epitaxially grown from the second nanostructures merge with each other, and wherein a third source / drain region epitaxially grown from the third nanostructures is isolated from the first source / drain region.

[0157] Example 16. A method according to Example 15, wherein the longitudinal axes of the first plurality of nanostructures and the longitudinal axes of the second plurality of nanostructures extend parallel to a first direction, and wherein, after patterning the multilayer stack, the first plurality of nanostructures and the second plurality of nanostructures form a first stack and a second stack, and the second stack is separated from the first stack in the first direction.

[0158] Example 17. A method according to Example 16, wherein, after patterning the multilayer stack, the first plurality of nanostructures and the second plurality of nanostructures further form a third stack, and the third stack is separated from the first stack and the second stack in a second direction perpendicular to the first direction, wherein a first end surface of the third stack is located between opposite end surfaces of the first stack in the first direction, and wherein a second end surface of the third stack opposite to the first end surface is located between opposite end surfaces of the second stack in the first direction.

[0159] Example 18. The method according to Example 15, further comprising:

[0160] removing the first plurality of nanostructures and the gate structure to form a second recess; and

[0161] A replacement gate structure is formed in the second recess.

[0162] Example 19. The method according to Example 18, further comprising:

[0163] patterning the replacement gate structure to form a third recess separating the first replacement gate structure from the second replacement gate structure; and

[0164] A dielectric material is formed in the third recess.

[0165] Example 20. The method according to Example 15 further includes: forming a dielectric material between the first source / drain region and the third source / drain region, wherein the dielectric material isolates the first source / drain region from the third source / drain region.

Claims

1. A storage array, comprising: a first channel region on the semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, wherein the second epitaxial region is isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; a gate electrode surrounding the gate dielectric; a second channel region located directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region; and A third channel region is adjacent to the first channel region in a direction parallel to the main surface of the semiconductor substrate, and the third channel region is electrically coupled to the first epitaxial region.

2. The storage array according to claim 1, wherein: The gate dielectric also surrounds the second channel region.

3. The storage array according to claim 2, wherein: A ratio of a distance between the first channel region and the second channel region in a direction perpendicular to a main surface of the semiconductor substrate to a height of the first channel region and the second channel region is 2 to 10.

4. The storage array according to claim 1, wherein: A distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate is greater than a distance between the first channel region and the third channel region in a direction parallel to the main surface of the semiconductor substrate.

5. The storage array according to claim 1, wherein: A distance between the second epitaxial region and the semiconductor substrate is greater than a distance between the first epitaxial region and the semiconductor substrate, and a length of the second epitaxial region is less than a length of the first epitaxial region.

6. The storage array according to claim 1, wherein: The gate dielectric includes a ferroelectric material.

7. A semiconductor device comprising: a first channel region on the semiconductor substrate; a second channel region located directly above the first channel region in a vertical direction; a first gate structure surrounding the first channel region and the second channel region; a third channel region, adjacent to the first channel region in a horizontal direction; a first source / drain region electrically coupled to the first channel region and the third channel region; as well as A second source / drain region is electrically coupled to the second channel region and isolated from the first source / drain region, wherein a first dielectric material extends between the first source / drain region and the second source / drain region.

8. The semiconductor device according to claim 7, wherein: A second gate structure surrounds the third channel region, and the second gate structure is separated from the first gate structure by a second dielectric material.

9. The semiconductor device according to claim 7, wherein: The length of the second source / drain region is shorter than the length of the first source / drain region.

10. The semiconductor device according to claim 7, wherein: The first source / drain region and the second source / drain region are bit lines or source lines, and wherein the first gate structure is a word line.

11. The semiconductor device according to claim 7, further comprising: a third source / drain region electrically coupled to the first channel region and the third channel region, the third source / drain region being disposed on a side of the first channel region and the third channel region opposite to the first source / drain region, wherein the first source / drain region is a source line, and wherein the third source / drain region is a bit line.

12. The semiconductor device according to claim 7, further comprising: a fourth channel region electrically coupled to the first source / drain region, wherein a longitudinal axis of the fourth channel region is aligned with a longitudinal axis of the first channel region; a second gate structure surrounding the fourth channel region; a first conductive line electrically coupled to the first gate structure, the first conductive line being disposed at a first side of the first channel region and the fourth channel region in the horizontal direction; and A second conductive line is electrically coupled to the second gate structure, and the second conductive line is disposed on a second side of the first channel region and the fourth channel region opposite to the first side in the horizontal direction.

13. The semiconductor device according to claim 7, further comprising: a fourth channel region electrically coupled to the first source / drain region opposite the first channel region, wherein a longitudinal axis of the fourth channel region is aligned with the first gate structure; and A second gate structure surrounds the fourth channel region, wherein a longitudinal axis of the first channel region is aligned with the second gate structure.

14. A method for forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; Patterning the multilayer stack to form a first plurality of nanostructures comprising the first semiconductor material and a second plurality of nanostructures comprising the second semiconductor material, the second plurality of nanostructures comprising a first nanostructure, a second nanostructure, and a third nanostructure, the second nanostructure being adjacent to the first nanostructure in a direction parallel to a major surface of the semiconductor substrate, the third nanostructure being located directly above the first nanostructure in a direction perpendicular to the major surface of the semiconductor substrate; forming a gate structure over the multilayer stack; etching the multilayer stack to form a first recess adjacent to the gate structure; as well as Epitaxially growing source / drain regions from the second plurality of nanostructures, wherein, after epitaxially growing the source / drain regions, a first source / drain region epitaxially grown from the first nanostructures and a second source / drain region epitaxially grown from the second nanostructures merge with each other, and wherein a third source / drain region epitaxially grown from the third nanostructures is isolated from the first source / drain region.

15. The method according to claim 14, wherein: The longitudinal axes of the first plurality of nanostructures and the longitudinal axes of the second plurality of nanostructures extend parallel to a first direction, and wherein, after patterning the multilayer stack, the first plurality of nanostructures and the second plurality of nanostructures form a first stack and a second stack, the second stack being separated from the first stack in the first direction.

16. The method according to claim 15, wherein: After patterning the multilayer stack, the first plurality of nanostructures and the second plurality of nanostructures also form a third stack, and the third stack is separated from the first stack and the second stack in a second direction perpendicular to the first direction, wherein a first end surface of the third stack is located between opposite end surfaces of the first stack in the first direction, and wherein a second end surface of the third stack opposite to the first end surface is located between opposite end surfaces of the second stack in the first direction.

17. The method according to claim 14, further comprising: removing the first plurality of nanostructures and the gate structure to form a second groove; as well as A replacement gate structure is formed in the second recess.

18. The method according to claim 17, further comprising: patterning the replacement gate structure to form a third recess, the third recess separating the first replacement gate structure from the second replacement gate structure; as well as A dielectric material is formed in the third recess.

19. The method according to claim 14, further comprising: A dielectric material is formed between the first source / drain region and the third source / drain region, the dielectric material isolating the first source / drain region from the third source / drain region.

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