Display device and method of manufacturing the same

Abstract

The present application is a display device and a manufacturing method thereof, which prevents surface damage of an insulating layer in which a pixel electrode is arranged, prevents occurrence of degradation of a light emitting element caused by damage of a thin film encapsulation layer, protects a surface of a pad portion and prevents surface damage of the pad portion, and provides a display device including: a substrate including a display region and a peripheral region surrounding the display region; a thin film transistor arranged on the substrate corresponding to the display region; a pad portion arranged on the substrate corresponding to the peripheral region; a first insulating layer including a first portion arranged on the thin film transistor and a second portion extending from the first portion, the first insulating layer exposing the pad portion; and a light emitting element arranged on the first portion of the first insulating layer and electrically connected to the thin film transistor, an upper surface of the first insulating layer having a step between the first portion and the second portion.

Description

Technical Field

[0001] This invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] A display device is a device for visually displaying data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] Such a display device includes a substrate divided into display areas and non-display areas, in which gate lines and data lines are insulated from each other. Multiple pixel regions are defined within the display areas, and pixels disposed in these pixel regions emit light by receiving electrical signals from the intersecting gate lines and data lines in order to display an image externally. Each pixel region (or each of pixel regions) includes a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor, and a common counter electrode is provided in the pixel regions. The non-display areas may include: various wirings for transmitting electrical signals to the pixels within the display area; a gate driving section; and pads for connecting the data driving section and the control section.

[0004] Recently, the applications of display devices have become more diverse. Furthermore, display devices have become thinner and lighter, thus expanding their range of uses. Recently, various designs have been explored to improve the quality of display devices. Summary of the Invention

[0005] This invention addresses various problems and aims to provide a display device and its manufacturing method that prevent surface damage to the insulating layer where pixel electrodes are disposed, prevent degradation of the light-emitting element caused by damage to the thin-film encapsulation layer, and form openings to expose the pad portions after the etching process for forming the pixel electrodes, thereby protecting the surface of the pad portions and preventing surface damage. However, such problems are exemplary and the scope of the invention is not limited thereto.

[0006] According to one aspect of the present invention, a display device is provided, comprising: a substrate including a display area and a peripheral area surrounding the display area; a thin-film transistor disposed on the substrate corresponding to the display area; a pad portion disposed on the substrate corresponding to the peripheral area; a first insulating layer including a first portion disposed on the thin-film transistor and a second portion extending from the first portion, the first insulating layer exposing the pad portion; and a light-emitting element disposed on the first portion of the first insulating layer and electrically connected to the thin-film transistor, wherein a step is provided on the surface of the first insulating layer between the first portion and the second portion.

[0007] As one example, the vertical distance from the substrate to the top of the first portion may be greater than the vertical distance from the substrate to the top of the second portion.

[0008] According to one example, the display device may further include: a second insulating layer disposed in the peripheral region and containing the same material as the first insulating layer; the pad portion includes: a pad electrode; and a pad connection electrode disposed on the pad electrode and in contact with at least a portion of the pad electrode; the second insulating layer is disposed between the pad electrode and the pad connection electrode and overlaps at least a portion of the pad connection electrode.

[0009] In one example, the surface of the second insulating layer that overlaps with the pad connection electrode may be inclined.

[0010] According to one example, the display device may further include: a third insulating layer disposed between the second insulating layer and the pad electrode, and having a contact hole that partially exposes the pad electrode, wherein a portion of the pad connecting electrode contacts the pad electrode within the contact hole.

[0011] As one example, the width of the pad connection electrode along one direction may be wider than the width of the pad electrode exposed through the contact hole.

[0012] According to one example, the pad portion may further include a pad protection layer disposed between the pad electrode and the pad connection electrode.

[0013] As one example, the light-emitting element may include a pixel electrode, an intermediate layer, and a counter electrode, wherein at least a portion of the pad-connecting electrode and the pixel electrode contain the same material.

[0014] As one example, the pixel electrode may have a three-layer film, and the pad connection electrode may have a single-layer film.

[0015] As one example, the pixel electrode may be configured to overlap only with the first portion.

[0016] According to another aspect of the present invention, a method for manufacturing a display device is provided, comprising: preparing a substrate including a display area and a peripheral area surrounding the display area; forming a thin-film transistor on the display area; forming pad electrodes on the peripheral area; forming an inorganic protective layer and a first insulating layer to cover the thin-film transistor and the pad electrodes; patterning the first insulating layer using a first mask; forming a first contact hole partially exposing the thin-film transistor and a second contact hole partially exposing the pad electrodes on the inorganic protective layer using the first insulating layer; forming a pixel electrode layer electrically connected to the thin-film transistor through the first contact hole on a first portion of the first insulating layer; forming a first photoresist pattern on the pixel electrode layer; etching the pixel electrode layer using the first photoresist pattern; and partially etching a second portion extending from the first portion of the first insulating layer using the first photoresist pattern.

[0017] As an example, the first mask could be a half-tone mask or a slit mask.

[0018] According to one example, the method of manufacturing the display device may further include: forming a pad connection electrode electrically connected to the pad electrode through the second contact hole; forming a second photoresist pattern on the pad connection electrode; and etching the pad connection electrode using the second photoresist pattern.

[0019] According to one example, the method of manufacturing the display device may further include the step of using the second photoresist pattern to partially etch a third portion of the first insulating layer corresponding to the peripheral region.

[0020] According to one example, the method of manufacturing the display device may further include the step of removing the second photoresist pattern, and the step of removing the second photoresist pattern and the step of partially etching the third portion are performed simultaneously.

[0021] As one example, the surface of the remaining portion of the third part of the first insulating layer, excluding the etched portion, may be inclined.

[0022] In one example, the steps of forming the first photoresist pattern and forming the second photoresist pattern can be performed simultaneously using a second mask.

[0023] As an example, the second mask could be a half-tone mask or a slit mask.

[0024] As an example, the thickness of the first photoresist pattern may be greater than the thickness of the second photoresist pattern.

[0025] According to one example, the method of manufacturing the display device may further include the steps of forming the pad connection electrode into a three-layer film and removing the two films of the three-layer film of the pad connection electrode other than the film adjacent to the pad electrode.

[0026] According to another aspect of the present invention, a display device is provided, comprising: a substrate including a display area and a peripheral area surrounding the display area; a thin-film transistor disposed on the substrate corresponding to the display area; a pad portion disposed on the substrate corresponding to the peripheral area; a first insulating layer disposed on the thin-film transistor and exposing the pad portion; a light-emitting element disposed on the first insulating layer and electrically connected to the thin-film transistor, and including a pixel electrode, an intermediate layer and a counter electrode; and a pixel defining film disposed on the first insulating layer and covering the edge of the pixel electrode, wherein the side surface of the first insulating layer and the side surface of the pixel defining film are located on the same etched surface.

[0027] As one example, the first insulating layer may include a first portion and a second portion extending from the first portion, with a step between the first portion and the second portion on the upper surface of the first insulating layer.

[0028] As one example, the vertical distance from the substrate to the top of the first portion may be greater than the vertical distance from the substrate to the top of the second portion.

[0029] As one example, the side of the first portion may be located on the same etched surface as the outer side of the pixel defining film.

[0030] In one example, the pixel electrode and the pixel defining film may be configured corresponding to the first part.

[0031] According to one example, the pad portion may include: a pad electrode; and a pad connection electrode disposed on the pad electrode and in contact with at least a portion of the pad electrode.

[0032] According to one example, the display device may further include: a second insulating layer disposed in the peripheral region and containing the same material as the first insulating layer, the second insulating layer being disposed between the pad electrode and the pad connection electrode and overlapping at least a portion of the pad connection electrode.

[0033] In one example, the surface of the second insulating layer that overlaps with the pad connection electrode may be inclined.

[0034] According to one example, the display device may further include: a third insulating layer disposed on the pad electrode and having a contact hole exposing a portion of the pad electrode, wherein a portion of the pad connecting electrode contacts the upper surface of the third insulating layer.

[0035] As one example, the width of the pad connection electrode along one direction may be wider than the width of the pad electrode exposed through the contact hole.

[0036] As one example, the pixel electrode may have a three-layer film, and the pad connection electrode may have a single-layer film.

[0037] According to one example, the display device may further include: a dam portion, configured corresponding to the peripheral area, and including a first peripheral insulating layer, a second peripheral insulating layer disposed on the first peripheral insulating layer, and a peripheral electrode layer between the first peripheral insulating layer and the second peripheral insulating layer.

[0038] In one example, the side surface of the first peripheral insulating layer and the side surface of the second peripheral insulating layer may be located on the same etched surface.

[0039] According to another aspect of the present invention, a method for manufacturing a display device is provided, comprising: preparing a substrate including a display area and a peripheral area surrounding the display area; forming a thin-film transistor on the display area; sequentially forming a first insulating layer, a pixel electrode material layer, and a pixel defining film material layer on the thin-film transistor; patterning the pixel defining film material layer using a first mask to form a pre-pixel defining film on a first portion of the first insulating layer; etching the pixel electrode material layer using the pre-pixel defining film to form a pixel electrode; and partially etching a second portion extending from the first portion of the first insulating layer using the pre-pixel defining film.

[0040] According to one example, the method of manufacturing the display device may further include: the step of forming a pad electrode on the peripheral region; the step of forming an inorganic protective layer on the pad electrode having a contact hole that exposes a portion of the pad electrode; and the step of forming a pad connection electrode electrically connected to the pad electrode through the contact hole.

[0041] According to one example, the step of forming the pad connection electrode may include: forming a pad connection electrode material layer on the pad electrode; forming a photoresist pattern on the pad connection electrode material layer; and etching the pad connection electrode material layer using the photoresist pattern.

[0042] In one example, the photoresist pattern can be formed by patterning the pixel-defining film material layer corresponding to the surrounding area using the first mask.

[0043] As one example, the thickness of the pre-pixel defining film may be greater than the thickness of the photoresist pattern.

[0044] According to one example, the method of manufacturing the display device may further include the step of using the photoresist pattern to partially etch a third portion of the first insulating layer corresponding to the peripheral area.

[0045] According to one example, the method of manufacturing the display device may further include a step of removing the photoresist pattern, wherein the step of removing the photoresist pattern and the step of partially etching the third portion are performed simultaneously.

[0046] According to one example, the method of manufacturing the display device may further include the steps of forming the pad connection electrode into a three-layer film and removing the two films of the three-layer film of the pad connection electrode other than the film adjacent to the pad electrode.

[0047] According to one example, the pre-pixel defining film may include: a first pre-pixel defining film covering the edge of the pixel electrode; and a second pre-pixel defining film surrounded by the first pre-pixel defining film, the first pre-pixel defining film being thicker than the second pre-pixel defining film.

[0048] According to one example, the method of manufacturing the display device may further include the step of removing the second preliminary pixel delimiting film to form a pixel delimiting film.

[0049] According to one example, the method of manufacturing the display device may further include the step of forming the pre-pixel defining film to contact the side of the pixel electrode.

[0050] As an example, the first mask could be a half-tone mask or a slit mask.

[0051] According to another aspect of the present invention, a display device is provided, comprising: a substrate including a display area and a peripheral area surrounding the display area; a thin-film transistor disposed on the substrate corresponding to the display area; a pad portion disposed on the substrate corresponding to the peripheral area; an inorganic insulating layer disposed on the thin-film transistor and the pad portion, and having an opening exposing the upper surface of the pad portion; and a light-emitting element disposed on the inorganic insulating layer and electrically connected to the thin-film transistor, and including a pixel electrode, an intermediate layer, and a counter electrode.

[0052] As one example, the width of the pad portion along one direction may be less than or equal to the width of the opening.

[0053] According to one example, the pad portion may include: a pad electrode; and a pad protective layer disposed on the pad electrode, the top of the pad protective layer being exposed through the opening.

[0054] As one example, the width of the pad protection layer along one direction may be less than or equal to the width of the opening.

[0055] As one example, the side of the pad electrode may be aligned with the side of the pad protective layer.

[0056] In one example, the side of the pad electrode may be partially exposed through the opening.

[0057] According to one example, the display device may further include: an electrode layer disposed on and electrically connected to the thin-film transistor, the inorganic insulating layer further having a first contact hole exposing a portion of the electrode layer.

[0058] According to one example, the display device may further include: an insulating layer disposed on the inorganic insulating layer and having a second contact hole corresponding to the first contact hole; and a pixel defining film disposed on the insulating layer with the pixel electrode placed therebetween, the pixel electrode being electrically connected to the electrode layer through the first contact hole and the second contact hole.

[0059] As one example, the side of the insulating layer adjacent to the peripheral region may be aligned with the side of the pixel defining film.

[0060] According to one example, the insulating layer may include: a first portion; and a second portion extending from the first portion toward the peripheral region side, the upper surface of the insulating layer having a step between the first portion and the second portion.

[0061] As one example, the vertical distance from the substrate to the top of the first portion may be greater than the vertical distance from the substrate to the top of the second portion.

[0062] According to one example, the display device may further include: a dam portion, configured corresponding to the surrounding area, and including a first peripheral insulating layer and a second peripheral insulating layer configured corresponding to the first peripheral insulating layer.

[0063] In one example, the sides of the first peripheral insulating layer and the sides of the second peripheral insulating layer may be aligned.

[0064] According to another aspect of the present invention, a method for manufacturing a display device is provided, comprising: preparing a substrate including a display area and a peripheral area surrounding the display area; forming a thin-film transistor on the display area; forming a pad portion on the peripheral area; forming an inorganic insulating layer on the pad portion; forming a preliminary pixel defining film on the inorganic insulating layer having a first opening exposing at least a portion of the inorganic insulating layer on the pad portion; and etching the first portion of the inorganic insulating layer exposed through the first opening using the preliminary pixel defining film.

[0065] According to one example, the step of forming the pad portion may include: forming a pad electrode on the peripheral region; and forming a pad protective layer on the pad electrode.

[0066] According to one example, the step of etching a first portion of the inorganic insulating layer may be a step of exposing the top of the pad protective layer.

[0067] According to one example, the method of manufacturing the display device may further include the step of removing the pre-pixel demarcation film corresponding to the peripheral area.

[0068] According to one example, the method of manufacturing the display device may further include: forming an electrode layer disposed on and electrically connected to the thin-film transistor; forming a preliminary insulating layer between the electrode layer and the preliminary pixel defining film and having a first contact hole corresponding to a portion of the electrode layer; and using the preliminary insulating layer to etch a second portion of the inorganic insulating layer corresponding to the first contact hole.

[0069] According to one example, the method of manufacturing the display device may further include the step of removing the pre-insulating layer corresponding to the peripheral area.

[0070] According to one example, the manufacturing method of the display device may further include the step of removing the pre-pixel defining film corresponding to the peripheral region, wherein the steps of removing the pre-pixel defining film corresponding to the peripheral region and removing the pre-insulating layer corresponding to the peripheral region are performed simultaneously.

[0071] Other aspects, features, and advantages beyond those foregoing will become clear from the following detailed description of the invention, the claims, and the accompanying drawings.

[0072] (Invention Effects)

[0073] According to an embodiment of the present invention configured as described above, a display device and its manufacturing method can be realized, preventing surface damage to the insulating layer on which pixel electrodes are disposed, preventing deterioration of the light-emitting element caused by damage to the thin-film encapsulation layer, and forming an opening to expose the pad portion after the etching process for forming the pixel electrodes, thereby protecting the surface of the pad portion and preventing surface damage to the pad portion. Of course, the scope of the present invention is not limited to such effects. Attached Figure Description

[0074] Figure 1 This is a plan view that briefly illustrates a display device according to an embodiment of the present invention.

[0075] Figure 2 This is a plan view that briefly illustrates a display panel according to an embodiment of the present invention.

[0076] Figure 3 This is a simplified equivalent circuit diagram illustrating any pixel of a display panel according to an embodiment of the present invention.

[0077] Figure 4 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0078] Figure 5 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0079] Figure 6a This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0080] Figure 6b This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0081] Figures 7a to 7g These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0082] Figures 8a to 8g These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0083] Figure 9 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0084] Figure 10 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0085] Figure 11 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0086] Figures 12a to 12hThese are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0087] Figures 13a to 13g These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0088] Figures 14a to 14i These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0089] Figures 15a to 15g These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0090] Figure 16 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0091] Figure 17 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0092] Figure 18 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0093] Figure 19 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0094] Figure 20a This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0095] Figure 20b This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0096] Figure 21 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0097] Figures 22a to 22j These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0098] Figures 23a to 23d These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0099] Figure 24 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0100] Figure 25 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0101] (Explanation of reference numerals in the attached diagram)

[0102] 1: Display device 10: Display panel

[0103] 117: Planarization layer; 117p: Preparatory planarization layer

[0104] 117a: Part One; 117b: Part Two

[0105] 117c: Part 3 118: Insulation layer

[0106] 119: Pixel boundary layer; 119p: Preparatory pixel boundary layer

[0107] ST: Stepped PR: Photoresist pattern

[0108] OP: Opening; PVX: Inorganic protective layer

[0109] M1, M2, M3, M4, M5, M6: Masks 1 through 6 Detailed Implementation

[0110] This invention can be modified in various ways and can have various embodiments, with specific embodiments illustrated in the accompanying drawings and described in detail in the accompanying description. (Referring to the accompanying drawings...) Figure 1 The effects and features of the invention, as well as the methods for implementing them, will become clear from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0111] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, the same or corresponding constituent elements will be given the same reference numerals, and repeated descriptions of them will be omitted.

[0112] In the following embodiments, the terms "first," "second," etc., are not used in a restrictive sense, but are used for the purpose of distinguishing one constituent element from other constituent elements.

[0113] In the following embodiments, the singular expression includes the plural expression unless explicitly represented differently in context.

[0114] In the following embodiments, the terms "including" or "having" mean the presence of the features or constituent elements described in the specification, and do not preclude the possibility of adding more than one other feature or constituent element.

[0115] In the following embodiments, when referring to a membrane, region, constituent element, or other part on or on other parts, it includes not only cases where it is directly on other parts, but also cases where other membranes, regions, constituent elements, etc. are interspersed therein.

[0116] In the accompanying drawings, the dimensions of the constituent elements may be enlarged or reduced for ease of explanation. For example, the dimensions and thicknesses of the various components shown in the drawings are arbitrarily illustrated for ease of explanation, and therefore the invention is not necessarily limited to the illustrations.

[0117] Where a particular embodiment can be implemented differently, the specific process sequence may also be performed differently than the described sequence. For example, two processes described consecutively may be performed substantially simultaneously, or in the reverse order of the description.

[0118] In this specification, "A and / or B" means A, or B, or A and B. Additionally, "at least one of A and B" means A, or B, or A and B.

[0119] In the following embodiments, when referring to the connection of membranes, regions, constituent elements, etc., it includes the case where the membranes, regions, constituent elements are directly connected, and / or the case where they are indirectly connected by other membranes, regions, constituent elements, etc., intervening in the connection. For example, in this specification, when referring to the electrical connection of membranes, regions, constituent elements, etc., it means the case where the membranes, regions, constituent elements, etc. are directly electrically connected, and / or the case where they are indirectly electrically connected by other membranes, regions, constituent elements, etc., intervening in the connection.

[0120] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system; they can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0121] Figure 1 This is a plan view that briefly illustrates a display device according to an embodiment of the present invention.

[0122] Reference Figure 1 The display device 1 includes a display area DA for displaying an image and a peripheral area PA disposed around the display area DA. The display device 1 can provide an image to the outside using light emitted from the display area DA. Of course, since the display device 1 includes a substrate 100, it can also be said that the substrate 100 has such a display area DA and a peripheral area PA.

[0123] The substrate 100 can be made of various materials such as glass, metal, or plastic. According to one embodiment, the substrate 100 may include a flexible material. Here, a flexible material refers to a substrate that can be easily bent, folded, or rolled. Such a flexible material substrate 100 can be made of ultra-thin glass, metal, or plastic.

[0124] The display area DA on the substrate 100 can be configured with pixels PX, which are equipped with various display elements such as organic light-emitting diodes (OLEDs). Multiple pixels PX can be configured in various ways, such as stripe arrangement, five-grid arrangement, or mosaic arrangement, to realize an image.

[0125] When the display area DA is viewed in a planar shape, the display area DA can be as follows: Figure 1 That would give it a rectangular shape. As another embodiment, the display area DA can have a polygonal shape such as a triangle, pentagon, or hexagon, or a circular shape, elliptical shape, or irregular shape.

[0126] The peripheral region PA of the substrate 100, which is disposed around the display area DA, can be an area where no image is displayed. The peripheral region PA can surround all or part of the display area DA. Various wirings for transmitting electrical signals to be applied to the display area DA, and pads PADs on which printed circuit boards or driver IC chips are attached can be provided in the peripheral region PA.

[0127] Figure 2 This is a plan view that briefly illustrates a display panel according to an embodiment of the present invention.

[0128] Reference Figure 2 The display panel 10 includes a display area DA and a peripheral area PA, and includes a plurality of pixels PX disposed in the display area DA. Each of the plurality of pixels PX may include a display element such as an organic light-emitting diode (OLED). Each pixel PX can emit light, for example, red, green, blue, or white, through the OLED. Hereinafter, in this specification, each pixel PX may refer to a sub-pixel that emits light of a different color from each other, and each pixel PX may be, for example, one of a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. The display area DA may be covered by an encapsulation component to protect it from external gases or moisture.

[0129] Each pixel PX can be electrically connected to peripheral circuitry configured in the peripheral region PA. The peripheral region PA may be configured with a first gate drive circuit 130, a second gate drive circuit 140, a pad portion PAD, a data drive circuit 150, a first power supply wiring 160, and a second power supply wiring 170.

[0130] The first gate driving circuit 130 and the second gate driving circuit 140 may each include a scan driving circuit and a light emission control driving circuit. The scan driving circuit included in the first gate driving circuit 130 and the second gate driving circuit 140 can provide a scan signal to each pixel PX through the scan line SL. In addition, the light emission control driving circuit included in the first gate driving circuit 130 and the second gate driving circuit 140 can provide a light emission control signal to each pixel PX through the light emission control line EL.

[0131] The second gate driving circuit 140 can be arranged side-by-side with the first gate driving circuit 130, with the display area DA positioned between them. A portion of the pixels PX disposed in the display area DA can be electrically connected to the first gate driving circuit 130, while the remainder can be connected to the second gate driving circuit 140. As another embodiment, the second gate driving circuit 140 can be omitted.

[0132] The pad portion (PAD) can be disposed on one side of the substrate 100. The pad portion (PAD) can be exposed without being covered by an insulating layer, thereby electrically connecting to the printed circuit board (PCB). The terminal portion (PCB-P) of the printed circuit board (PCB) can be electrically connected to the pad portion (PAD) of the display panel 10. The printed circuit board (PCB) transmits signals or power from the control unit (not shown) to the display panel 10.

[0133] The control signals generated by the control unit can be transmitted to the first and second gate drive circuits 130 and 140 respectively via the printed circuit board (PCB). The control unit can provide first and second power supply voltages to the first and second power supply wirings 160 and 170 respectively via the first and second connection wirings 161 and 171. Specifically, the first power supply voltage can be provided to each pixel PX via the drive voltage line PL connected to the first power supply wiring 160, and the second power supply voltage can be provided to the counter electrode 330 of each pixel PX connected to the second power supply wiring 170 (see below). Figure 5 ).

[0134] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 can be provided to each pixel PX through the connection wiring 151 connected to the pad part PAD and the data line DL connected to the connection wiring 151. Figure 2 The data driving circuit 150 is shown disposed on a printed circuit board (PCB), but as another embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the pad portion (PAD) and the first power supply wiring 160.

[0135] The first power supply cabling 160 may include a first sub-cabling 162 and a second sub-cabling 163 extending side-by-side along the x-direction, with the display area DA positioned between them. The second power supply cabling 170 may partially surround the display area DA in a loop shape with one side open.

[0136] Figure 3 This is a simplified equivalent circuit diagram illustrating any pixel of a display panel according to an embodiment of the present invention.

[0137] Reference Figure 3 Each pixel PX includes: a pixel circuit PC connected to the scan line SL and the data line DL; and an organic light-emitting diode OLED connected to the pixel circuit PC.

[0138] The pixel circuit PC includes a driving thin-film transistor (TFT) T1, a switching thin-film transistor (TFT) T2, and a storage capacitor Cst. The switching TFT T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving TFT T1 according to the scan signal Sn input through the scan line SL.

[0139] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores a voltage equivalent to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0140] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and controls the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) according to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a predetermined brightness through the driving current.

[0141] exist Figure 3 The previous description included a pixel circuit PC comprising two thin-film transistors and one storage capacitor, but the invention is not limited thereto. For example, the pixel circuit PC may include three or more thin-film transistors and / or two or more storage capacitors. As one embodiment, the pixel circuit PC may also include seven thin-film transistors and one storage capacitor.

[0142] Figure 4 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0143] Reference Figure 4 Display device 1 (refer to) Figure 1The display unit DU includes a display unit DU and a color filter unit CU disposed opposite to the display unit DU. The display unit DU may include a first pixel PX1, a second pixel PX2, and a third pixel PX3 disposed on a substrate 100 (hereinafter referred to as the lower substrate). The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be pixels that emit light of different colors on the lower substrate 100. For example, the first pixel PX1 may emit red light Lr, the second pixel PX2 may emit green light Lg, and the third pixel PX3 may emit blue light Lb.

[0144] The first pixel PX1, the second pixel PX2, and the third pixel PX3 may each have a first light-emitting element 300a, a second light-emitting element 300b, and a third light-emitting element 300c, respectively, belonging to an organic light-emitting diode (OLED). In one embodiment, the first light-emitting element 300a, the second light-emitting element 300b, and the third light-emitting element 300c may emit blue light. In another embodiment, the first light-emitting element 300a, the second light-emitting element 300b, and the third light-emitting element 300c may also emit red light Lr, green light Lg, and blue light Lb, respectively.

[0145] The color filter unit CU may include filter sections 500a, 500b, and 500c. Light emitted from the first light-emitting element 300a, the second light-emitting element 300b, and the third light-emitting element 300c can pass through the filter sections 500a, 500b, and 500c and be emitted as red light Lr, green light Lg, and blue light Lb, respectively.

[0146] Filter sections 500a, 500b, and 500c can be directly located on the upper substrate 200. Filter sections 500a, 500b, and 500c can each include components described later. Figure 18 The first quantum dot layer 220a, the first filter layer 210a, the second quantum dot layer 220b, the second filter layer 210b, the transmission layer 220c, and the third filter layer 210c.

[0147] At this point, "directly located on the upper substrate 200" can mean that the first filter layer 210a, the second filter layer 210b, and the third filter layer 210c are directly formed on the upper substrate 200 to fabricate the color filter unit CU. Afterwards, the first filter layer 210a, the second filter layer 210b, and the third filter layer 210c can be positioned facing the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively, to bond the display unit DU and the color filter unit CU.

[0148] exist Figure 4The diagram illustrates the bonding of the display unit DU and the color filter unit CU via an adhesive layer ADH. The adhesive layer ADH can be, for example, an optically clear adhesive (OCA), but is not necessarily limited to this. As another embodiment, the adhesive layer ADH can be omitted.

[0149] exist Figure 4 The filter units 500a, 500b, and 500c are shown disposed on the upper substrate 200, but the filter units 500a, 500b, and 500c can be disposed on the display unit DU.

[0150] As an example, filter units 500a, 500b, and 500c can be configured as described later. Figure 18 The thin-film encapsulation layer 400 shown is provided with a first quantum dot layer 220a, a second quantum dot layer 220b, a transmission layer 220c, a first filter layer 210a, a second filter layer 210b, and a third filter layer 210c. Alternatively, the first quantum dot layer 220a, the second quantum dot layer 220b, and the transmission layer 220c may be disposed on the thin-film encapsulation layer 400 first, then the first filter layer 210a, the second filter layer 210b, and the third filter layer 210c may be disposed on the first quantum dot layer 220a, the second quantum dot layer 220b, and the transmission layer 220c respectively.

[0151] like Figure 4 As shown, the display device 1 may include a lower substrate 100 and an upper substrate 200. The number of substrates included in the display device 1 may be two. Alternatively, the display device 1 may exclude the upper substrate 200 and include only the lower substrate 100. In this case, filter units 500a, 500b, and 500c may be disposed on the lower substrate 100. The number of substrates included in the display device 1 may be one.

[0152] Figure 5 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0153] Reference Figure 5 Display device 1 (refer to) Figure 1 The system includes: a thin-film transistor (TFT) disposed on a substrate 100 corresponding to the display area DA; and a pad portion PAD disposed on the substrate 100 corresponding to the peripheral area PA. As an insulating layer disposed on the TFT and exposing the pad portion PAD, a planarization layer 117 is included. The planarization layer 117 includes a first portion 117a and a second portion 117b extending to one side from the first portion 117a. At this time, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b.

[0154] The following is for reference Figure 5 The structure included in the display device 1 will be described more specifically based on the stacked structure.

[0155] The substrate 100 may comprise glass, ceramic, metallic, or other materials with flexible or bendable properties. When the substrate 100 possesses flexible or bendable properties, it may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0156] The substrate 100 may have a single-layer or multi-layer structure of the material, and in the case of a multi-layer structure, it may also include an inorganic layer. In some embodiments, the substrate 100 may have an organic / inorganic / organic structure.

[0157] The buffer layer 111 can reduce or prevent foreign matter, moisture or external gases from penetrating from below the substrate 100 and can provide a flat surface on the substrate 100. The buffer layer 111 can contain inorganic materials such as oxides or nitrides, or organic materials, or organic-inorganic composites, and can be composed of a single layer or multiple layers of inorganic and organic materials.

[0158] A barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 111. The barrier layer serves to prevent or minimize the penetration of impurities from the substrate 100 and the like into the semiconductor layer A. The barrier layer may contain inorganic materials such as oxides or nitrides, or organic materials, or organic-inorganic composites, and may be composed of a single layer or multiple layers of inorganic and organic materials.

[0159] A semiconductor layer A may be disposed on the buffer layer 111. The semiconductor layer A may comprise an oxide semiconductor material. For example, the semiconductor layer A may comprise an oxide of one or more materials selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0160] As an example, semiconductor layer A can be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, or the like. Oxide semiconductors have a wide bandgap (approximately 3.1 eV), high carrier mobility, and low leakage current. Therefore, even with long driving times, the voltage drop is not significant, offering the advantage of minimal brightness change due to voltage drop even at low-frequency driving.

[0161] Semiconductor layer A may include a channel region C and a source region S and a drain region D disposed on one side and the other side of the channel region C, respectively. Semiconductor layer A may be composed of a single layer or multiple layers.

[0162] A conductive layer BML may be disposed between the substrate 100 and the buffer layer 111. The conductive layer BML may be configured to overlap with the channel region C of the semiconductor layer A. The conductive layer BML may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer containing said material. As an example, the conductive layer BML may be formed in a Ti / Al / Ti multilayer structure.

[0163] The conductive layer BML can be configured to overlap with the semiconductor layer A containing an oxide semiconductor material. The semiconductor layer A containing the oxide semiconductor material has the characteristic of being less susceptible to light; therefore, the conductive layer BML can prevent changes in the device characteristics of the thin-film transistor (TFT) containing the oxide semiconductor material from being induced by external light incident from the substrate 100 side. Additionally, the conductive layer BML can be connected to the drain region D. Although in Figure 5 The diagram shows the conductive layer BML connected to the drain region D, but the conductive layer BML can also be connected to the source region S.

[0164] A gate insulating layer 113 may be disposed on semiconductor layer A. The gate insulating layer 113 may comprise silicon oxide (SiO2) or silicon nitride (SiN). X Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) are included.

[0165] like Figure 5 As shown, the gate insulating layer 113 can be patterned to overlap a portion of the semiconductor layer A. That is, the gate insulating layer 113 can be patterned to expose the source region S and the drain region D.

[0166] The region where the gate insulating layer 113 overlaps with the semiconductor layer A can be understood as the channel region C. After the source region S and drain region D undergo a conductor-enhancing process using plasma treatment or the like, the portion of the semiconductor layer A that overlaps with the gate insulating layer 113 (i.e., the channel region C) is not exposed to plasma treatment and thus has properties different from the source region S and drain region D. Specifically, it is possible to use the gate electrode G, which is located above the gate insulating layer 113 during plasma treatment of the semiconductor layer A, as a self-aligning mask to form the untreated channel region C at the location overlapping with the gate insulating layer 113, and to form the plasma-treated source region S and drain region D on either side of the channel region C, respectively.

[0167] In another embodiment, the gate insulating layer 113 may not be patterned to overlap a portion of the semiconductor layer A, and may be disposed on the entire surface of the substrate 100 to cover the semiconductor layer A.

[0168] A gate electrode G may be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer A. Additionally, a first electrode CE1 of the storage capacitor Cst and an auxiliary pad electrode SPE may be disposed on the gate insulating layer 113. The gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be formed in single or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0169] In one embodiment, the storage capacitor Cst can be configured with a first electrode CE1 and a second electrode CE2, and as follows: Figure 5 As shown, it exists independently without overlapping with the thin-film transistor (TFT). In contrast, the storage capacitor Cst can overlap with the TFT. For example, the gate electrode G of the TFT can function as the first electrode CE1 of the storage capacitor Cst.

[0170] An interlayer insulating layer 115 may be provided to cover the semiconductor layer A, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. The interlayer insulating layer 115 may comprise silicon oxide (SiO2) or silicon nitride (SiN). X Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) are included.

[0171] On top of the interlayer insulating layer 115, a source electrode, a drain electrode, a data line (not shown), a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE can be disposed.

[0172] The source electrode, drain electrode, data line, second electrode CE2 of storage capacitor Cst, and pad electrode PE can contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and can be formed as a multilayer or a single layer containing said materials. As one example, the source electrode, drain electrode, data line, second electrode CE2 of storage capacitor Cst, and pad electrode PE can be formed as a Ti / Al / Ti multilayer structure. As another example, the source electrode, drain electrode, data line, second electrode CE2 of storage capacitor Cst, and pad electrode PE can be formed as a Ti / Cu multilayer structure.

[0173] The source electrode and drain electrode can be connected to the source region S or drain region D of the semiconductor layer A through contact holes. In addition, the conductive layer BML and the source region S or drain region D of the semiconductor layer A can be connected through contact holes formed in the buffer layer 111 and the interlayer insulating layer 115.

[0174] The second electrode CE2 of the storage capacitor Cst overlaps with the first electrode CE1 by placing the interlayer insulating layer 115 between them, thus forming a capacitor. In this case, the interlayer insulating layer 115 can function as the dielectric layer of the storage capacitor Cst.

[0175] The pad electrode PE can be connected to the auxiliary pad electrode SPE through contact holes formed in the interlayer insulating layer 115. Figure 5 The diagram shows three contact holes connecting the PE pad electrode and the SPE auxiliary pad electrode, but there could be more or fewer. Additionally, in... Figure 5 The auxiliary pad electrode SPE is shown, but the auxiliary pad electrode SPE can be omitted.

[0176] It is possible that an electrode protection layer EPL is configured on the source electrode, drain electrode, and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL is configured on the pad electrode PE.

[0177] The electrode protective layer (EPL) and the pad protective layer (PPL) may be selected from one or more materials selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0178] The source electrode, drain electrode, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE can be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Therefore, separate masks are not required for patterning the electrode protection layer EPL and the pad protection layer PPL, thus reducing the number of masks.

[0179] The source electrode, drain electrode, data line, second electrode CE2 of storage capacitor Cst, and pad electrode PE can be covered by an inorganic protective layer PVX. The inorganic protective layer PVX can be an inorganic insulating film formed from inorganic materials. Suitable inorganic materials include polysiloxanes, silicon nitride, silicon oxide, and silicon oxynitride. Alternatively, the inorganic protective layer PVX can be silicon nitride (SiN). X ) and silicon dioxide (SiO) X A single-layer or multi-layer film. The inorganic protective layer PVX may be introduced to cover and protect a portion of the wiring disposed on the interlayer insulation layer 115.

[0180] The planarization layer 117 is configured to cover the source electrode, drain electrode, data line, and the second electrode CE2 of the storage capacitor Cst. The planarization layer 117 includes contact holes for connecting the thin-film transistor TFT and the pixel electrode 310.

[0181] The planarization layer 117 can be formed from a single layer or multiple layers of a film made of organic material, providing a planar surface. Such a planarization layer 117 may include general-purpose polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylyl polymers, vinyl alcohol polymers, or mixtures thereof.

[0182] The planarization layer 117 may include a first portion 117a disposed on the thin-film transistor TFT and a second portion 117b extending to one side from the first portion 117a. In this case, the upper surface of the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b. That is, the vertical distance d1 from the substrate 100 to the upper surface of the first portion 117a and the vertical distance d2 from the substrate 100 to the upper surface of the second portion 117b may be different. As an example, such as... Figure 5 As shown, the vertical distance d1 from the substrate 100 to the top of the first portion 117a can be greater than the vertical distance d2 from the substrate 100 to the top of the second portion 117b.

[0183] The planarization layer 117 can be configured to expose the pad portion (PAD). That is, the planarization layer 117 may not be configured in the surrounding area PA and may not overlap with the pad portion (PAD).

[0184] As a comparative example, the planarization layer may remain and be disposed in the peripheral area of ​​the display panel. In this case, the residual planarization layer in the peripheral area of ​​the display panel may act as a moisture permeation path from the outside, posing a risk of reliability problems such as degradation of the light-emitting elements.

[0185] A light-emitting element 300 is disposed on the planarization layer 117. The light-emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light-emitting layer, and a counter electrode 330.

[0186] The pixel electrode 310 can be a (semi-)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 310 may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or compounds thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may have one or more of the following materials selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, such as Figure 5 As shown, the pixel electrode 310 can have a three-layer film. As an example, the three-layer film of the pixel electrode 310 can be ITO / Ag / ITO.

[0187] In one embodiment, the pixel electrode 310 may be configured to overlap only with a first portion 117a of the planarization layer 117. The aforementioned planarization layer 117 may have a step ST between the first portion 117a and a second portion 117b extending from the first portion 117a. Figure 5 As shown, not only the second portion 117b extending towards the peripheral region PA side, but also a step ST can be formed between the second portion 117b and the first portion 117a of the planarization layer 117 extending towards the display region DA side. That is, the first portion 117a may correspond to the portion of the planarization layer 117 that is relatively far in vertical distance from the substrate 100 to the top of the planarization layer 117, and a pixel electrode 310 may be disposed above such a first portion 117a.

[0188] A pixel defining film 119 may be disposed on the planarization layer 117. In addition, the pixel defining film 119 can prevent electric arcs from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

[0189] The pixel defining film 119 can be formed by spin coating or other methods using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0190] The intermediate layer 320 can be disposed within the opening formed by the pixel defining film 119 and includes an organic light-emitting layer. The organic light-emitting layer can contain an organic material containing a fluorescent or phosphorescent substance that emits red, green, blue, or white light. The organic light-emitting layer can be a low-molecular-weight organic material or a high-molecular-weight organic material. Selectively, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may also be disposed below and above the organic light-emitting layer.

[0191] The counter electrode 330 can be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 330 can be a transparent or translucent electrode and can be formed using a metal thin film with a low work function containing Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 can be disposed on top of the metal thin film. The counter electrode 330 can be disposed across the display area DA and above the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 can be integrally formed among multiple light-emitting elements 300 to correspond to multiple pixel electrodes 310.

[0192] Such organic light-emitting elements may be easily damaged by external factors such as moisture or oxygen. Therefore, an encapsulation layer (not shown) can cover and protect these organic light-emitting elements. Such an encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0193] Figure 6a as well as Figure 6b This is a simplified cross-sectional view illustrating a display device according to an embodiment of the present invention. Figure 6a as well as Figure 6b In, with Figure 5 The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0194] Reference Figure 6a The display device 1 includes: a thin-film transistor (TFT) and a storage capacitor (Cst) disposed on a substrate 100 corresponding to the display area DA; and a pad portion (PAD) disposed on the substrate 100 corresponding to the peripheral area PA.

[0195] and Figure 5 Different, such as Figure 6aAs shown, a pad connection electrode PCE can be disposed on the pad electrode PE. The pad connection electrode PCE may have one or more materials selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The pad connection electrode PCE may contain at least a portion of the same material as the pixel electrode 310. In one embodiment, the pixel electrode 310 may have a three-layer film, and the pad connection electrode PCE may have a single-layer film. As an example, the three-layer film of the pixel electrode 310 may be ITO / Ag / ITO, and the single-layer film of the pad connection electrode PCE may be ITO.

[0196] The pad-connecting electrode PCE can contact at least a portion of the pad electrode PE. This can be achieved by forming a contact hole (CNT) in the inorganic protective layer PVX that exposes at least a portion of the pad electrode PE, with a portion of the pad-connecting electrode PCE contacting the pad electrode PE within the contact hole (CNT). In one embodiment, as... Figure 6a As shown, the width W2 of the pad connection electrode PCE along one direction can be wider than the width W1 of the pad electrode PE exposed through the contact hole CNT.

[0197] As in Figure 2 As described, the pad portion PAD and the terminal portion PCB-P of the printed circuit board PCB can be electrically connected. In this case, the contact width between the pad portion PAD and the terminal portion PCB-P increases from the width W1 of the pad electrode PE exposed through the contact hole CNT to the width W2 of the pad connection electrode PCE. That is, the contact area between the pad portion PAD and the terminal portion PCB-P increases. Therefore, poor contact between the pad portion PAD and the terminal portion PCB-P can be reduced, and the risk of malfunctions during the operation of the display device 1 can be reduced.

[0198] It may also include an insulating layer 118 disposed on the inorganic protective layer PVX corresponding to the surrounding area PA and containing the same material as the planarization layer 117.

[0199] An insulating layer 118 may be disposed between the pad electrode PE and the pad connection electrode PCE, and may overlap at least partially with the pad connection electrode PCE. The surface of the insulating layer 118 overlapping with the pad connection electrode PCE may be inclined. The surface of the inorganic protective layer PVX, which is parallel to the substrate 100, and the surface of the insulating layer 118 may have a certain angle. In addition, the surface of the pad connection electrode PCE overlapping with the insulating layer 118 may also be inclined along the insulating layer 118.

[0200] Despite Figure 6a The electrode protective layer (EPL) and the pad protective layer (PPL) are omitted, but as in Figure 5 As described in the text, refer to Figure 6b The pad portion (PAD) may also include a pad protection layer (PPL) disposed between the pad electrode (PE) and the pad connection electrode (PCE). Additionally, an electrode protection layer (EPL) may be disposed on the source electrode, drain electrode, and the second electrode (CE2) of the storage capacitor (Cst).

[0201] So far, only the display device has been described in detail, but the present invention is not limited thereto. For example, the method for manufacturing such a display device also falls within the scope of the present invention.

[0202] Figures 7a to 7g These are cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment of the present invention. Specifically, based on... Figure 5 Cross-sectional views of a method for manufacturing a display device according to an embodiment of the present invention are shown in sequence. Figures 7a to 7g In, with Figure 5 The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0203] Reference Figure 7a First, a conductive layer BML, a buffer layer 111, a semiconductor layer A, a gate insulating layer 113, a gate electrode G, a first electrode CE1 and a second electrode CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protection layer PVX are sequentially formed on a substrate 100.

[0204] The conductive layer BML can be formed by patterning a pre-conductive layer (not shown). The pre-conductive layer may contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or a single layer containing said material.

[0205] Buffer layer 111 can be made of silicon oxide (SiO2) or silicon nitride (SiN). XIt can be set up and formed by vapor deposition methods such as chemical vapor deposition (CVD) and sputtering.

[0206] A semiconductor layer A may be disposed on the buffer layer 111. The semiconductor layer A may be formed by patterning a pre-semiconductor layer (not shown). The pre-semiconductor layer may be formed using an oxide semiconductor and may be deposited by chemical vapor deposition.

[0207] Alternatively, a gate insulating layer 113 and a gate electrode G may be disposed on a semiconductor layer A, and a gate insulating layer 113, a first electrode CE1 of a storage capacitor Cst, and an auxiliary pad electrode SPE may be disposed on a buffer layer 111.

[0208] The gate insulating layer 113, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE can be formed by patterning the pre-gate insulating layer (not shown) and the pre-metal layer (not shown).

[0209] The pre-gate insulating layer can be made of silicon oxide (SiO2) or silicon nitride (SiN). X It can be made of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), and can be formed by vapor deposition methods such as chemical vapor deposition (CVD) and sputtering, and is not limited to these.

[0210] The preparation - metal layer can be formed by one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) in single or multiple layers, and can be formed by evaporation methods such as chemical vapor deposition, plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and is not limited to these methods.

[0211] During the patterning of the pre-gate insulating layer, plasma processing is performed, and a portion of the semiconductor layer A that is exposed and does not overlap with the gate electrode G undergoes a conductive process using plasma processing. As a result, the source region S and drain region D exposed during plasma processing become conductive, and the channel region C that overlaps with the gate electrode G has different properties from the source region S and drain region D.

[0212] An interlayer insulating layer 115 is formed on the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. After forming the interlayer insulating layer 115, contact holes are formed that penetrate the interlayer insulating layer 115 and expose a portion of the conductive layer BML, the semiconductor layer A, and the auxiliary pad electrode SPE, respectively.

[0213] An electrode layer E, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE are formed on the interlayer insulating layer 115. Additionally, an electrode protection layer EPL and a pad protection layer PPL are formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The electrode layer E, the second electrode CE2 of the storage capacitor Cst, the pad electrode PE, the electrode protection layer EPL, and the pad protection layer PPL can be integrally deposited on the interlayer insulating layer 115 as a pre-electrode layer (not shown) and a pre-protection layer (not shown), and formed through a mask process and an etching process. That is, the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE can be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Therefore, a separate mask is not required for patterning the electrode protection layer EPL and the pad protection layer PPL, thus reducing the number of masks.

[0214] An inorganic protective layer PVX is formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The inorganic protective layer PVX can be an inorganic insulating film formed from inorganic materials, and can be formed by vapor deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and is not limited to these methods.

[0215] Reference Figure 7bA planarization material layer 117' can be disposed on the inorganic protective layer PVX. The planarization material layer 117' can be formed as a single layer or multiple layers of a film made of organic or inorganic substances. After the planarization material layer 117' is formed, chemical mechanical polishing can be performed to provide a flat surface.

[0216] The planarization layer 117' may contain positive photoresist, which can be formed by applying positive photoresist liquid (not shown) onto the inorganic protective layer PVX using various methods such as spin-coating, spraying, or dipping. Before applying the planarization layer 117' onto the inorganic protective layer PVX, a polishing process may be additionally performed on the surface of the inorganic protective layer PVX to which the planarization layer 117' is to be applied.

[0217] A first mask M1 can be disposed on the planarization layer 117'. The first mask M1 can adjust the amount of exposure applied to the planarization layer 117' according to each region. For example, compared with the second region AR2 and the fifth region AR5 of the first mask M1, the fourth region AR4 of the first mask M1 can be adjusted to a smaller amount of light exposure applied to the planarization layer 117'. In addition, compared with the second region AR2 and the fifth region AR5 of the first mask M1, the sixth region AR6 of the first mask M1 can be adjusted to a smaller amount of exposure applied to the planarization layer 117'. As an example, the first mask M1 can be a half-tone mask or a slit mask. In some embodiments, the first region AR1 and the third region AR3 of the first mask M1 can be masked to prevent exposure of the planarization layer 117'.

[0218] The planarization layer 117' can be exposed using a first mask M1 with different exposure levels for each region, and a portion of the planarization layer 117' can be removed using a developing process. The amount of planarization layer 117' removed varies depending on the exposure level, thus allowing planarization layers 117 with different thicknesses for each region to be formed in a single step. That is, as... Figure 7c As shown, the thickness of the planarization layer 117 corresponding to the display area DA can be thicker than the thickness of the planarization layer 117 corresponding to the peripheral area PA. Then, the adhesion to the inorganic protective layer PVX can be increased through a curing and drying process of the planarization layer 117. At this time, the curing and drying process may include a heat treatment process.

[0219] exist Figure 7bThe planarization layer 117' is given as an example of containing positive photoresist, but the planarization layer 117' may also contain negative photoresist. In this case, contrary to when the planarization layer 117' contains positive photoresist, the more exposure applied to the planarization layer 117', the thicker the planarization layer 117' remains after the development process.

[0220] Reference Figure 7c as well as Figure 7d Using a patterned planarization layer 117, a first contact hole CNT1 partially exposes the electrode layer E, and a second contact hole CNT2 partially exposes the pad electrode PE, forming on the inorganic protective layer PVX. The first contact hole CNT1 and the second contact hole CNT2 are formed by a partial etching process of the inorganic protective layer PVX. As an example, the partial etching process of the inorganic protective layer PVX can be dry etching. Although in Figure 7d It is not shown in the figure, but a portion of the planarization layer 117 can also be removed together to reduce the overall thickness of the planarization layer 117.

[0221] Reference Figure 7e A pixel electrode 310 is formed above the planarization layer 117. The pixel electrode 310 can be applied to the pre-pixel electrode layer 310' (see reference). Figure 8b The pixel electrode 310 is formed by patterning. This can be achieved by depositing a pre-pixel electrode layer 310' onto the planarization layer 117, forming a photoresist pattern PR on the pre-pixel electrode layer 310', and then etching the pre-pixel electrode layer 310' using the photoresist pattern PR. In other words, the pixel electrode 310 can be formed by depositing the pre-pixel electrode layer 310' and then performing a masking process and an etching process. As an example, the etching process can be wet etching.

[0222] A third contact hole CNT3 is formed in the planarization layer 117 to partially expose the electrode layer E. The pixel electrode 310 can be connected to the thin film transistor TFT through the first contact hole CNT1 and the third contact hole CNT3.

[0223] After forming the pixel electrode 310, the photoresist pattern PR can be used without removing it, and an etching process can be performed using the photoresist pattern PR to remove the planarization layer 117 of the surrounding area PA. As an example, the etching process can be dry etching.

[0224] Reference Figure 7fIt can be seen that the first portion 117a of the planarization layer 117 corresponds to the portion protected by the photoresist pattern PR during the etching process, and the second portion 117b of the planarization layer 117 corresponds to the portion not protected by the photoresist pattern PR during the etching process. Through the photoresist pattern PR, the top surface of the planarization layer 117 can have a step ST between the first portion 117a and the second portion 117b. That is, the vertical distance d1 from the substrate 100 to the top surface of the first portion 117a can be greater than the vertical distance d2 from the substrate 100 to the top surface of the second portion 117b. Furthermore, through the etching process, a portion of the photoresist pattern PR can be etched, and the thickness t of the photoresist pattern PR also becomes thinner.

[0225] On the other hand, such as Figure 7e As shown, the pixel electrode 310 is formed using a photoresist pattern PR as an etching mask, such as Figure 7f As shown, the first portion 117a of the planarization layer 117 is also formed using the photoresist pattern PR as an etching mask. Therefore, the planar shape of the pixel electrode 310 and the planar shape of the first portion 117a substantially correspond to the planar shape of the photoresist pattern PR. Furthermore, as... Figure 7f As shown, the edge of the pixel electrode 310 and the sidewall of the first part 117a also correspond to each other.

[0226] As a comparative example, an etching process for removing the planarization layer in the surrounding area can be performed before forming the pixel electrode. If impurities are present on the surface of the planarization layer, steps may form between the impurity-containing and impurity-free areas during the etching process. If a light-emitting element is placed on the surface of the planarization layer with these steps, a short circuit between the pixel electrode and the counter electrode may be induced, resulting in a dark spot on the display panel. Furthermore, the surface of the planarization layer is not protected during the etching process, thus increasing its surface roughness. If a pixel electrode is placed on the surface of a planarization layer with increased roughness, a decrease in reflectivity due to external light may occur, potentially reducing luminous efficiency.

[0227] However, as in one embodiment of the present invention, after forming the pixel electrode 310, the etching process for removing the planarization layer 117 of the peripheral area PA can be performed without removing the photoresist pattern PR. In this case, the surface of the planarization layer 117 on which the pixel electrode 310 is disposed can be protected by the photoresist pattern PR. Therefore, steps caused by surface impurities in the planarization layer 117 are not formed, and the surface roughness of the planarization layer 117 does not increase. That is, no dark spots are generated in the display panel, no decrease in reflectivity caused by external light occurs, and thus the luminous efficiency is not reduced. In addition, since the planarization layer 117 is not left in the peripheral area PA by the etching process, the moisture permeation path from the outside is blocked, thereby reducing the risk of reliability problems such as degradation of the light-emitting element.

[0228] Reference Figure 7g After removing the photoresist pattern PR, a pixel defining film 119 is integrally formed on the planarization layer 117, covering the edge of the pixel electrode 310 and having an opening exposing the central portion. The pixel defining film 119 can be formed by spin coating or other methods using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0229] An intermediate layer 320 is formed on the pixel electrode 310, that is, inside the opening of the pixel defining film 119. The intermediate layer 320 may contain a low molecular weight or polymer material. The intermediate layer 320 may be formed by vacuum evaporation, screen printing or inkjet printing, laser induced thermal imaging (LITI), etc.

[0230] The intermediate layer 320 of the light-emitting element 300 may include an organic light-emitting layer. The organic light-emitting layer may contain an organic material that emits fluorescent or phosphorescent substances that emit red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. Selectively, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be disposed below and above the organic light-emitting layer. The intermediate layer 320 may be configured corresponding to each of the multiple pixel electrodes 310. However, it is not limited to this. The intermediate layer 320 may include a layer integrally formed across multiple pixel electrodes 310, and various modifications are possible.

[0231] Subsequently, counter electrodes 330 are formed to correspond to the plurality of light-emitting elements 300. The counter electrodes 330 can be formed by an opening mask to cover the display area DA of the substrate 100. The counter electrodes 330 can be formed by vapor deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD).

[0232] Figures 8a to 8g These are cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment of the present invention. Specifically, based on... Figure 5 Cross-sectional views of a method for manufacturing a display device according to an embodiment of the present invention are shown in sequence. Figures 8a to 8g In, with Figures 7a to 7g The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0233] Reference Figure 8a , such as in Figure 7b As described, the planarization material layer 117' can be exposed using a first mask M1 with different exposure amounts for each region, and a portion of the planarization material layer 117' can be removed by a development process. The amount of planarization material layer 117' removed varies depending on the exposure amount, thus planarization layers 117 with different thicknesses for each region can be formed in a single step. That is, the planarization layer 117 can be patterned. Using the patterned planarization layer 117, a first contact hole CNT1 that partially exposes the electrode layer E and a second contact hole CNT2 that partially exposes the pad electrode PE can be formed in the inorganic protective layer PVX.

[0234] Reference Figure 8b A pre-pixel electrode layer 310' and a photoresist layer PR' are sequentially formed on the planarization layer 117.

[0235] The photoresist layer PR' may contain positive photoresist, and the photoresist layer PR' can be formed by applying positive photoresist liquid (not shown) onto the pre-pixel electrode layer 310' by various methods such as spin-coating, spraying or dipping.

[0236] A second mask M2 can be disposed on the photoresist layer PR'. The second mask M2 can adjust the exposure applied to the photoresist layer PR' for each region. For example, compared to the first region AR1, the third region AR3, and the fifth region AR5 of the second mask M2, the fourth region AR4 of the second mask M2 can be adjusted to have a smaller exposure applied to the photoresist layer PR'. As an example, the second mask M2 can be a half-tone mask or a slit mask. In some embodiments, the second region AR2 of the second mask M2 can be masked to prevent exposure of the photoresist layer PR'.

[0237] The photoresist layer PR' can be exposed using a second mask M2 with different exposure amounts for each region, and a portion of the photoresist layer PR' can be removed using a development process. The amount of photoresist layer PR' removed varies depending on the exposure amount, thus allowing the formation of a first photoresist pattern PR1 and a second photoresist pattern PR2 with different thicknesses for each region in a single step. That is, as shown... Figure 8c As shown, the thickness t1 of the first photoresist pattern PR1 corresponding to the display area DA can be thicker than the thickness t2 of the second photoresist pattern PR2 corresponding to the peripheral area PA.

[0238] exist Figure 8b The example given is that the photoresist layer PR' contains positive photoresist, but the photoresist layer PR' can also contain negative photoresist. In this case, contrary to the case where the photoresist layer PR' contains positive photoresist, the more exposure is applied to the photoresist layer PR', the thicker the residual photoresist layer PR' will be after the development process.

[0239] Reference Figure 8c as well as Figure 8d A pixel electrode 310 and a pad connection electrode PCE are formed above the planarization layer 117. The pixel electrode 310 and the pad connection electrode PCE can be formed by patterning the pre-pixel electrode layer 310'. The pre-pixel electrode layer 310' is deposited integrally on the planarization layer 117, and a first photoresist pattern PR1 and a second photoresist pattern PR2 are formed on the pre-pixel electrode layer 310'. At this time, the first photoresist pattern PR1 is disposed in the display area DA, and the second photoresist pattern PR2 is disposed in the peripheral area PA.

[0240] Subsequently, using the first photoresist pattern PR1 and the second photoresist pattern PR2, the pre-pixel electrode layer 310' is etched to form the pixel electrode 310 and the pad connection electrode PCE. That is, the pixel electrode 310 and the pad connection electrode PCE can be formed by vapor deposition of the pre-pixel electrode layer 310' and through a masking process and an etching process. As an example, the etching process can be wet etching.

[0241] After forming the pixel electrode 310 and the pad connection electrode PCE, without removing the first photoresist pattern PR1 and the second photoresist pattern PR2, an etching process is performed using the first photoresist pattern PR1 and the second photoresist pattern PR2 to remove the planarization layer 117 of the peripheral area PA. As an example, the etching process can be dry etching.

[0242] Reference Figure 8e It can be seen that the first portion 117a of the planarization layer 117 corresponds to the portion protected by the first photoresist pattern PR1 during the etching process, and the second portion 117b of the planarization layer 117 corresponds to the portion not protected by the first photoresist pattern PR1 or the second photoresist pattern PR2 during the etching process. Through the first photoresist pattern PR1, the planarization layer 117 can have a step ST between the first portion 117a and the second portion 117b. That is, the vertical distance d1 from the substrate 100 to the top of the first portion 117a can be greater than the vertical distance d2 from the substrate 100 to the top of the second portion 117b. Furthermore, through the etching process, a portion of the first photoresist pattern PR1 is etched, and the thickness t1 of the first photoresist pattern PR1 can also be reduced.

[0243] The portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral region PA that is not protected by the second photoresist pattern PR2 is removed. In contrast, the portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral region PA that is protected by the second photoresist pattern PR2 remains. Additionally, as... Figure 8e As shown, the second photoresist pattern PR2 can also be completely etched away during the etching process. That is, the step of locally etching the third portion 117c of the planarization layer 117 and the step of removing the second photoresist pattern PR2 can be performed simultaneously.

[0244] As a comparative example, an etching process for removing the planarization layer in the surrounding area can be performed before forming the pixel electrode. If impurities are present on the surface of the planarization layer, a step can be formed between the impurity-containing and impurity-free areas during the etching process. If a light-emitting element is placed on the surface of the planarization layer with the formed step, a short circuit between the pixel electrode and the counter electrode may be induced, resulting in a dark spot on the display panel. Furthermore, the surface of the planarization layer is not protected during the etching process, thus increasing its surface roughness. If a pixel electrode is placed on the surface of the planarization layer with increased roughness, a decrease in reflectivity due to external light may occur, potentially reducing luminous efficiency.

[0245] However, as in one embodiment of the present invention, after forming the pixel electrode 310, the etching process for removing the planarization layer 117 of the peripheral region PA can be performed without removing the first photoresist pattern PR1 and the second photoresist pattern PR2. In this case, the surface of the planarization layer 117 on which the pixel electrode 310 is disposed can be protected by the first photoresist pattern PR1. Therefore, steps caused by surface impurities in the planarization layer 117 are not formed, and the surface roughness of the planarization layer 117 does not increase. That is, no dark spots are generated in the display panel, and no decrease in reflectivity caused by external light occurs, thereby maintaining the luminous efficiency. In addition, since the etching process leaves no planarization layer 117 remaining in the peripheral region PA, the path for moisture penetration from the outside is blocked, reducing the risk of reliability problems such as degradation of the light-emitting element.

[0246] Subsequently, the etching process can be performed without removing the first photoresist pattern PR1. For example, the etching process can be wet etching.

[0247] Reference Figure 8f The two films of the pad connection electrode PCE, which is formed as a three-layer film, can be removed by etching. The other two films are the film adjacent to the pad electrode PE. The pad connection electrode PCE can be a single-layer film.

[0248] As a comparative example, the pad connection electrode can be maintained as a three-layer film. In the case of a three-layer film pad connection electrode, it can be formed as ITO / Ag / ITO. The pad connection electrode can be exposed without being covered by an insulating layer. In this case, the highly reactive silver (Ag) is exposed, posing a risk of short circuit to adjacent electrodes.

[0249] However, in the case of removing two of the three films of the pad connection electrode PCE as in one embodiment of the present invention, only ITO is present in the exposed pad connection electrode PCE, and the risk of short circuit with adjacent electrodes is eliminated.

[0250] In one embodiment, such as Figure 8f As shown, the width W2 of the pad connection electrode PCE along one direction can be wider than the width W1 of the pad electrode PE exposed through the second contact hole CNT2. In such a case, as in Figure 6a As described above, the contact area between the pads (PAD) and the PCB-P (terminal) is increased. Therefore, poor contact between the pads (PAD) and the PCB-P (terminal) can be reduced, thus decreasing the risk of malfunctions during the operation of the display device 1.

[0251] Reference Figure 8gAfter removing the first photoresist pattern PR1, a pixel defining film 119 is integrally formed on the planarization layer 117, covering the edge of the pixel electrode 310 and having an opening exposing the central portion. The pixel defining film 119 can be formed by spin coating or other methods using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0252] An intermediate layer 320 is formed on the pixel electrode 310, that is, inside the opening of the pixel defining film 119. The intermediate layer 320 may contain a low molecular weight or polymer material. The intermediate layer 320 may be formed by vacuum evaporation, screen printing or inkjet printing, laser induced thermal imaging (LITI), etc.

[0253] The intermediate layer 320 of the light-emitting element 300 may include an organic light-emitting layer. The organic light-emitting layer may contain an organic material that emits fluorescent or phosphorescent substances that emit red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. Selectively, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be disposed below and above the organic light-emitting layer. The intermediate layer 320 may be configured corresponding to each of the multiple pixel electrodes 310. However, it is not limited to this. The intermediate layer 320 may include a layer integrally formed across multiple pixel electrodes 310, and various modifications are possible.

[0254] Subsequently, counter electrodes 330 are formed to correspond to the plurality of light-emitting elements 300. The counter electrodes 330 can be formed by an opening mask to cover the display area DA of the substrate 100. The counter electrodes 330 can be formed by vapor deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD).

[0255] Figure 9 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0256] Reference Figure 9 Display device 1 (refer to) Figure 1 The system includes: a thin-film transistor (TFT) disposed on a substrate 100 corresponding to the display area DA; and a pad portion PAD disposed on the substrate 100 corresponding to the peripheral area PA. As an insulating layer disposed on the TFT and exposing the pad portion PAD, a planarization layer 117 is included. The planarization layer 117 includes a first portion 117a and a second portion 117b extending to one side from the first portion 117a. At this time, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b.

[0257] A pixel defining film 119 may be disposed on the planarization layer 117. In this case, the side surfaces of the planarization layer 117 and the side surfaces of the pixel defining film 119 may be etched surfaces of the same plane. The side surfaces of the first portion 117a of the planarization layer 117 and the side surfaces of the pixel defining film 119 may also be etched surfaces of the same plane.

[0258] The following is for reference Figure 9 The structure included in the display device 1 will be described more specifically based on the stacked structure.

[0259] The substrate 100 may comprise glass, ceramic, metallic, or other materials with flexible or bendable properties. The substrate 100 may have a single-layer or multi-layer structure, and in the case of a multi-layer structure, it may also include an inorganic layer. In some embodiments, the substrate 100 may have an organic / inorganic / organic structure.

[0260] The buffer layer 111 can reduce or prevent foreign matter, moisture or external gas from penetrating from under the substrate 100 and can provide a flat surface on the substrate 100.

[0261] A barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 111. The barrier layer can prevent or minimize the penetration of impurities from the substrate 100 and the like into the semiconductor layer A.

[0262] A semiconductor layer A may be disposed on the buffer layer 111. The semiconductor layer A may comprise an oxide semiconductor material. For example, the semiconductor layer A may comprise an oxide of one or more materials selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0263] As an example, semiconductor layer A can be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. Oxide semiconductors have a wide band gap (approximately 3.1 eV), high carrier mobility, and low leakage current. Therefore, even with long driving times, the voltage drop is not significant, and they have the advantage of minimal brightness change due to voltage drop even at low-frequency driving.

[0264] Semiconductor layer A may include a channel region C and a source region S and a drain region D disposed on one side and the other side of the channel region C, respectively. Semiconductor layer A may be composed of a single layer or multiple layers.

[0265] A conductive layer BML may be disposed between the substrate 100 and the buffer layer 111. The conductive layer BML may be configured to overlap with the channel region C of the semiconductor layer A.

[0266] The conductive layer BML can be configured to overlap with the semiconductor layer A containing an oxide semiconductor material. The semiconductor layer A containing the oxide semiconductor material has the characteristic of being less susceptible to light; therefore, the conductive layer BML can prevent changes in the device characteristics of the thin-film transistor (TFT) containing the oxide semiconductor material from being induced by external light incident from the substrate 100 side. Additionally, the conductive layer BML can be connected to the drain region D. Although in Figure 9 The diagram shows the conductive layer BML connected to the drain region D, but the conductive layer BML can also be connected to the source region S.

[0267] A gate insulating layer 113 may be disposed on semiconductor layer A. The gate insulating layer 113 may comprise silicon oxide (SiO2) or silicon nitride (SiN). X Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) are included.

[0268] like Figure 9 As shown, the gate insulating layer 113 can be patterned to overlap a portion of the semiconductor layer A. That is, the gate insulating layer 113 can be patterned to expose the source region S and the drain region D.

[0269] The region where the gate insulating layer 113 overlaps with the semiconductor layer A can be understood as the channel region C. After the source region S and drain region D undergo a conductor-enhancing process using plasma treatment or the like, the portion of the semiconductor layer A that overlaps with the gate insulating layer 113 (i.e., the channel region C) is not exposed to plasma treatment and thus has properties different from the source region S and drain region D. Specifically, it is possible to use the gate electrode G, which is located above the gate insulating layer 113 during plasma treatment of the semiconductor layer A, as a self-aligning mask to form the untreated channel region C at the location overlapping with the gate insulating layer 113, and to form the plasma-treated source region S and drain region D on either side of the channel region C, respectively.

[0270] In another embodiment, the gate insulating layer 113 may not be patterned to overlap a portion of the semiconductor layer A, and may be disposed on the entire surface of the substrate 100 to cover the semiconductor layer A.

[0271] A gate electrode G can be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer A. Additionally, a first electrode CE1 of the storage capacitor Cst and an auxiliary pad electrode SPE can be disposed on the gate insulating layer 113.

[0272] In one embodiment, the storage capacitor Cst can be configured with a first electrode CE1 and a second electrode CE2, and as follows: Figure 9 As shown, it exists independently without overlapping with the thin-film transistor (TFT). In contrast, the storage capacitor Cst can overlap with the TFT. For example, the gate electrode G of the TFT can function as the first electrode CE1 of the storage capacitor Cst.

[0273] It may have an interlayer insulating layer 115 to cover the semiconductor layer A, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE.

[0274] On top of the interlayer insulating layer 115, a source electrode, a drain electrode, a data line (not shown), a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE can be disposed.

[0275] The source electrode and drain electrode can be connected to the source region S or drain region D of the semiconductor layer A through contact holes. In addition, the conductive layer BML and the source region S or drain region D of the semiconductor layer A can be connected through contact holes formed in the buffer layer 111 and the interlayer insulating layer 115.

[0276] The second electrode CE2 of the storage capacitor Cst overlaps with the first electrode CE1 by placing the interlayer insulating layer 115 between them, thus forming a capacitor. In this case, the interlayer insulating layer 115 can function as the dielectric layer of the storage capacitor Cst.

[0277] The pad electrode PE can be connected to the auxiliary pad electrode SPE through contact holes formed in the interlayer insulating layer 115. Figure 9 The diagram shows three contact holes connecting the PE pad electrode and the SPE auxiliary pad electrode, but there could be more or fewer. Additionally, in... Figure 9 The auxiliary pad electrode SPE is shown, but the auxiliary pad electrode SPE can be omitted.

[0278] It is possible that an electrode protection layer EPL is configured on the source electrode, drain electrode, and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL is configured on the pad electrode PE.

[0279] The source electrode, drain electrode, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE can be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Therefore, separate masks are not required for patterning the electrode protection layer EPL and the pad protection layer PPL, thus reducing the number of masks.

[0280] The source electrode, drain electrode, data line, second electrode CE2 of storage capacitor Cst, and pad electrode PE can be covered by the inorganic protective layer PVX.

[0281] The planarization layer 117 is configured to cover the source electrode, drain electrode, data line, and the second electrode CE2 of the storage capacitor Cst. The planarization layer 117 includes contact holes for connecting the thin-film transistor TFT and the pixel electrode 310.

[0282] The planarization layer 117 can be formed by a single layer or multiple layers of a membrane made of organic material, and provides a flat surface.

[0283] The planarization layer 117 may include a first portion 117a disposed on the thin-film transistor TFT and a second portion 117b extending to one side from the first portion 117a. In this case, the upper surface of the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b. That is, the vertical distance d1 from the upper surface of the substrate 100 to the upper surface of the first portion 117a and the vertical distance d2 from the upper surface of the substrate 100 to the upper surface of the second portion 117b may be different. As an example, such as... Figure 9 As shown, the vertical distance d1 from the top of the substrate 100 to the top of the first portion 117a can be greater than the vertical distance d2 from the top of the substrate 100 to the top of the second portion 117b.

[0284] The planarization layer 117 can be configured to expose the pad portion (PAD). That is, the planarization layer 117 may not be configured in the surrounding area PA and may not overlap with the pad portion (PAD).

[0285] As a comparative example, the planarization layer may remain and be disposed in the peripheral area of ​​the display panel. In this case, the residual planarization layer in the peripheral area of ​​the display panel may act as a moisture permeation path from the outside, posing a risk of reliability problems such as degradation of the light-emitting elements.

[0286] A light-emitting element 300 is disposed on the planarization layer 117. The light-emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light-emitting layer, and a counter electrode 330.

[0287] In one embodiment, the pixel electrode 310 may be configured to overlap only with a first portion 117a of the planarization layer 117. The aforementioned planarization layer 117 may have a step ST between the first portion 117a and a second portion 117b extending from the first portion 117a. Figure 9 As shown, not only the second portion 117b extending towards the peripheral region PA side, but also a step ST can be formed between the second portion 117b and the first portion 117a of the planarization layer 117 extending towards the display region DA side. That is, the first portion 117a may correspond to the portion of the planarization layer 117 that is relatively far in vertical distance from the substrate 100 to the top of the planarization layer 117, and a pixel electrode 310 may be disposed above such a first portion 117a.

[0288] A pixel defining film 119 may be disposed on the planarization layer 117. The pixel defining film 119 may cover the edge of the pixel electrode 310 and have an opening that exposes a portion of the pixel electrode 310. The pixel defining film 119 can prevent the generation of electric arcs at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

[0289] In one embodiment, such as Figure 9 As shown, the planarization layer 117 and the pixel defining film 119 can have the same etched surfaces s and s'. For example, in Figure 12g As described later, the planarization layer 117 and the pixel defining film 119 can be formed simultaneously using the same etching process and can include the same etching surfaces s and s'. A portion of the planarization layer 117 can be etched using the pixel defining film 119 as a mask, and the outer surface of the pixel defining film 119 and the side surface of the planarization layer 117 can be located on the same etching surfaces s and s'. The outer surface of the pixel defining film 119 and the side surface of the first portion 117a of the planarization layer 117 can be located on the same etching surfaces s and s'.

[0290] The outer surface of the pixel defining film 119 and the side surface of the planarization layer 117 can be located on the same plane. The outer surface of the pixel defining film 119 and the side surface of the first portion 117a of the planarization layer 117 can be located on the same plane. The outer surface of the pixel defining film 119 and the side surface of the planarization layer 117 can be formed without steps. The outer surface of the pixel defining film 119 and the side surface of the planarization layer 117 can be formed without boundaries.

[0291] The pixel defining film 119 can be configured to overlap with the first portion 117a of the planarization layer 117. On the plane, the boundary of the pixel defining film 119 can correspond to the boundary of the first portion 117a of the planarization layer 117.

[0292] When the pixel defining film 119 and the first portion 117a of the planarization layer 117 have the same etched surfaces s and s', the pixel defining film 119 can be configured corresponding to the first portion 117a. The pixel defining film 119 can be configured corresponding to the first portion 117a but not configured in the second portion 117b. The pixel defining film 119 can be removed from the portion corresponding to the second portion 117b. The insulating layer formed of organic matter can be removed by adding the thickness t of the pixel defining film 119 to the step ST of the planarization layer 117 (t+(d1-d2)). In this case, a portion of the pixel defining film 119 and the planarization layer 117 adjacent to the light-emitting element 300 are removed, thereby reducing the volume of organic matter within the display device 1 and minimizing the outgassing of organic matter. Therefore, even if the display device 1 is exposed to sunlight for a long time, the decomposition of organic matter caused by sunlight can be prevented or minimized, thus preventing defects such as pixel shrinkage caused by outgassing. The reliability of the display device 1 can be improved.

[0293] The intermediate layer 320 can be disposed within the opening formed by the pixel defining film 119 and includes an organic light-emitting layer. The organic light-emitting layer can contain an organic material containing a fluorescent or phosphorescent substance that emits red, green, blue, or white light. The organic light-emitting layer can be a low-molecular-weight organic material or a high-molecular-weight organic material. Selectively, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may also be disposed below and above the organic light-emitting layer.

[0294] The counter electrode 330 can be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 330 can be a transparent or translucent electrode and can be formed using a metal thin film with a low work function containing Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 can be disposed on top of the metal thin film. The counter electrode 330 can be disposed across the display area DA and above the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 can be integrally formed among multiple light-emitting elements 300 to correspond to multiple pixel electrodes 310.

[0295] Such organic light-emitting elements are easily damaged by external factors such as moisture or oxygen, therefore, in Figure 18 As described later, the thin-film encapsulation layer 400 can cover and protect the organic light-emitting elements. The thin-film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430. As described above, the insulating layer formed of organic material can be removed from the portion corresponding to the second portion 117b of the planarization layer 117. The amount of insulating layer removed from the organic encapsulation layer 420 can be further configured. The thickness of the organic encapsulation layer 420 can increase the amount of insulating layer removed, thus making it difficult for foreign matter or the like to reach the counter electrode 330. If foreign matter or the like reaches the counter electrode 330, the light-emitting element 300 may deteriorate. By thickening the organic encapsulation layer 420, the deterioration of the light-emitting element 300 can be prevented. That is, the thin-film encapsulation layer 400 can be prevented from being damaged by foreign matter or the like, and the light-emitting element 300 can be prevented from deteriorating due to damage to the thin-film encapsulation layer 400.

[0296] Figure 10 as well as Figure 11 This is a simplified cross-sectional view illustrating a display device according to an embodiment of the present invention. Figure 10 as well as Figure 11 In, with Figure 9 The same reference numerals are used to refer to the same parts, and repeated descriptions of them are omitted.

[0297] Reference Figure 10 The display device 1 includes: a thin-film transistor (TFT) and a storage capacitor (Cst) disposed on a substrate 100 corresponding to the display area DA; and a pad portion (PAD) disposed on the substrate 100 corresponding to the peripheral area PA.

[0298] and Figure 9 Different, such as Figure 10As shown, a pad connection electrode PCE can be configured on the pad electrode PE. The pad connection electrode PCE can be one or more selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0299] The pad connection electrode PCE may contain at least a portion of the same material as the pixel electrode 310. In one embodiment, the pixel electrode 310 may have a three-layer film, and the pad connection electrode PCE may have a single-layer film. As an example, the three-layer film of the pixel electrode 310 may be ITO / Ag / ITO, and the single-layer film of the pad connection electrode PCE may be ITO.

[0300] The pad-connecting electrode PCE can make at least partial contact with the pad electrode PE. Figure 10 The diagram shows that the pad connection electrode PCE and the pad electrode PE are electrically connected through the pad protector layer PPL. However, the pad protector layer PPL can be omitted, and the pad connection electrode PCE and the pad electrode PE can be in direct contact. Alternatively, a contact hole CNT can be formed in the inorganic protector layer PVX, exposing at least a portion of the pad electrode PE, and a portion of the pad connection electrode PCE contacts the pad electrode PE within the contact hole CNT. In one embodiment, as... Figure 10 As shown, the width W2 of the pad connection electrode PCE along one direction can be wider than the width W1 of the pad electrode PE exposed through the contact hole CNT.

[0301] As in Figure 1 As described, the pad portion PAD can be attached to a printed circuit board or a driver IC chip. In this case, the contact width between the pad portion PAD and the printed circuit board or driver IC chip is increased from the width W1 of the pad electrode PE exposed through the contact hole CNT to the width W2 of the pad connection electrode PCE. That is, the area where the pad portion PAD can contact the printed circuit board or driver IC chip is increased. Therefore, poor contact between the pad portion PAD and the printed circuit board or driver IC chip can be reduced, and the risk of malfunctions during the operation of the display device 1 can be reduced.

[0302] In one embodiment, such as Figure 10As shown, a portion of the pad-connecting electrode PCE can contact the top of the inorganic protective layer PVX. The portion of the pad-connecting electrode PCE can contact the top of the inorganic protective layer PVX and is formed according to the shape of the top of the inorganic protective layer PVX.

[0303] In another embodiment, such as Figure 11 As shown, the display device 1 may also include an insulating layer 118 disposed on an inorganic protective layer PVX corresponding to the surrounding area PA and containing the same material as the planarization layer 117.

[0304] An insulating layer 118 may be disposed between the pad electrode PE and the pad connection electrode PCE, and may overlap at least partially with the pad connection electrode PCE. The surface of the insulating layer 118 overlapping with the pad connection electrode PCE may be inclined. The surface of the inorganic protective layer PVX, which is parallel to the substrate 100, and the surface of the insulating layer 118 may have a certain angle. In addition, the surface of the pad connection electrode PCE overlapping with the insulating layer 118 may also be inclined along the insulating layer 118.

[0305] exist Figure 10 as well as Figure 11 The electrode protection layer (EPL) and the pad protection layer (PPL) are shown, but the electrode protection layer (EPL) and the pad protection layer (PPL) can also be omitted.

[0306] So far, only the display device has been described in detail, but the present invention is not limited thereto. For example, the method for manufacturing such a display device also falls within the scope of the present invention.

[0307] Figures 12a to 12h These are cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment of the present invention. Specifically, based on... Figure 9 Cross-sectional views of a method for manufacturing a display device according to an embodiment of the present invention are shown in sequence. Figures 12a to 12h In, with Figure 9 The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0308] Reference Figure 12a First, a conductive layer BML, a buffer layer 111, a semiconductor layer A, a gate insulating layer 113, a gate electrode G, a first electrode CE1 and a second electrode CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protection layer PVX are sequentially formed on a substrate 100.

[0309] The conductive layer BML can be formed by patterning a pre-conductive layer (not shown). The pre-conductive layer may contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or a single layer containing said material.

[0310] Buffer layer 111 can be made of silicon oxide (SiO2) or silicon nitride (SiN). X It can be set up and formed by vapor deposition methods such as chemical vapor deposition (CVD) and sputtering.

[0311] A semiconductor layer A may be disposed on the buffer layer 111. The semiconductor layer A may be formed by patterning a pre-semiconductor layer (not shown). The pre-semiconductor layer may be formed using an oxide semiconductor and may be deposited by chemical vapor deposition.

[0312] Alternatively, a gate insulating layer 113 and a gate electrode G may be disposed on a semiconductor layer A, and a gate insulating layer 113, a first electrode CE1 of a storage capacitor Cst, and an auxiliary pad electrode SPE may be disposed on a buffer layer 111.

[0313] The gate insulating layer 113, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE can be formed by patterning the pre-gate insulating layer (not shown) and the pre-metal layer (not shown).

[0314] The pre-gate insulating layer can be made of silicon oxide (SiO2) or silicon nitride (SiN). X It can be made of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), and can be formed by vapor deposition methods such as chemical vapor deposition (CVD) and sputtering, and is not limited to these.

[0315] The preparation - metal layer can be formed in single or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). It can be formed by vapor deposition methods such as chemical vapor deposition, plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and is not limited to these methods.

[0316] During the patterning of the pre-gate insulating layer, plasma processing is performed, and a portion of the semiconductor layer A that is exposed and does not overlap with the gate electrode G undergoes a conductive process using plasma processing. As a result, the source region S and drain region D exposed during plasma processing become conductive, and the channel region C that overlaps with the gate electrode G has different properties from the source region S and drain region D.

[0317] An interlayer insulating layer 115 is formed on the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. After forming the interlayer insulating layer 115, contact holes are formed that penetrate the interlayer insulating layer 115 and expose a portion of the conductive layer BML, the semiconductor layer A, and the auxiliary pad electrode SPE, respectively.

[0318] An electrode layer E, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE are formed on the interlayer insulating layer 115. Additionally, an electrode protection layer EPL and a pad protection layer PPL are formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The electrode layer E, the second electrode CE2 of the storage capacitor Cst, the pad electrode PE, the electrode protection layer EPL, and the pad protection layer PPL can be integrally deposited on the interlayer insulating layer 115 as a pre-electrode layer (not shown) and a pre-protection layer (not shown), and formed through a mask process and an etching process. That is, the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE can be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Therefore, a separate mask is not required for patterning the electrode protection layer EPL and the pad protection layer PPL, thus reducing the number of masks.

[0319] An inorganic protective layer PVX is formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The inorganic protective layer PVX can be an inorganic insulating film formed from inorganic materials, and can be formed by vapor deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and is not limited to these methods.

[0320] After the inorganic protective layer PVX is formed, the first contact hole CNT1 and the second contact hole CNT2, which locally expose the electrode protective layer EPL and the pad protective layer PPL, can be formed using a separate mask.

[0321] Reference Figure 12b A planarization layer 117' can be disposed on the inorganic protective layer PVX. The planarization layer 117' may contain positive photoresist, and the planarization layer 117' can be formed by applying positive photoresist liquid (not shown) to the inorganic protective layer PVX by various methods such as spin-coating, spraying, or dipping. Before applying the planarization layer 117' to the inorganic protective layer PVX, a polishing process can be additionally performed on the surface of the inorganic protective layer PVX to which the planarization layer 117' is to be applied.

[0322] A first mask M1 can be disposed on the planarization material layer 117'. The first region AR1 and the third region AR3 of the first mask M1 can be masked to prevent exposure of the planarization material layer 117', while the second region AR2 and the fourth region AR4 of the first mask M1 can be left unmasked to expose the planarization material layer 117'.

[0323] The planarization material layer 117' can be exposed to each region using a first mask M1, and a portion of the planarization material layer 117' can be removed by a developing process to form the planarization layer 117. The planarization layer 117 can be formed as a single layer or multiple layers of a film made of organic or inorganic materials. The adhesion to the inorganic protective layer PVX can be increased by a curing and drying process of the planarization layer 117. In this case, the curing and drying process may include a heat treatment process. After the planarization layer 117 is formed, chemical mechanical polishing can be performed to provide a flat surface.

[0324] exist Figure 12bThe planarization layer 117' is given as an example of containing positive photoresist, but the planarization layer 117' may also contain negative photoresist. In this case, unlike when the planarization layer 117' contains positive photoresist, the exposed areas in the planarization layer 117' remain after the development process.

[0325] Reference Figure 12c The planarization layer 117 may have a third contact hole CNT3 that partially exposes the electrode protective layer EPL corresponding to the portion exposed through the second region AR2 of the first mask M1. The planarization layer 117 may be formed to expose the pad portion PAD corresponding to the portion exposed through the fourth region AR4 of the first mask M1. After the planarization layer 117 is formed, a pixel electrode material layer 310' is formed above the planarization layer 117.

[0326] Reference Figure 12d A pixel defining film material layer 119' is formed above the pixel electrode material layer 310'. The pixel defining film material layer 119' may contain positive photoresist, and the pixel defining film material layer 119' can be formed by applying positive photoresist solution onto the pixel electrode material layer 310' by various methods such as spin-coating, spraying, or dipping.

[0327] A second mask M2 can be disposed on the pixel-defining film material layer 119'. The second mask M2 can adjust the amount of exposure applied to the pixel-defining film material layer 119' for each region. For example, compared to the first region AR1 and the fifth region AR5 of the second mask M2, the third region AR3 of the second mask M2 can be adjusted to have a smaller amount of light exposure applied to the pixel-defining film material layer 119'. As an example, the second mask M2 can be a half-tone mask or a slit mask. In some embodiments, the second region AR2 and the fourth region AR4 of the second mask M2 can be masked to prevent exposure of the pixel-defining film material layer 119'.

[0328] The pixel defining film material layer 119' can be exposed using a second mask M2 with different exposure levels for each region, and a portion of the pixel defining film material layer 119' can be removed using a development process. The amount of pixel defining film material layer 119' removed varies depending on the exposure level, thus allowing a pre-pixel defining film 119p with different thicknesses for each region to be formed in a single step.

[0329] For example, such as Figure 12eAs shown, the pre-pixel defining film 119p may include a first pre-pixel defining film 119pa and a second pre-pixel defining film 119pb surrounded by the first pre-pixel defining film 119pa. The first pre-pixel defining film 119pa corresponds to the portion of the pixel defining film material layer 119' that is not exposed and is not removed by the second region AR2 and the fourth region AR4 of the second mask M2. The second pre-pixel defining film 119pb corresponds to the portion of the pixel defining film material layer 119' that is partially removed by the third region AR3 of the second mask M2 after an adjusted exposure is applied. The thickness t1 of the first pre-pixel defining film 119pa may be thicker than the thickness t2 of the second pre-pixel defining film 119pb.

[0330] exist Figure 12d The example given is that the pixel defining film material layer 119' contains positive photoresist, but the pixel defining film material layer 119' may also contain negative photoresist. In this case, contrary to the case where the pixel defining film material layer 119' contains positive photoresist, the more exposure applied to the pixel defining film material layer 119', the thicker the pixel defining film material layer 119' remains after the development process.

[0331] Reference Figure 12e as well as Figure 12f The pixel electrode 310 is formed by etching the pixel electrode material layer 310' using the pre-pixel defining film 119p formed on the pixel electrode material layer 310'. That is, the pixel electrode 310 can be formed by vapor deposition of the pixel electrode material layer 310' through a masking process and an etching process. As an example, the etching process can be wet etching.

[0332] Depending on the conditions of the etching process, the number of etching operations can be varied. For example, the etching process may include a single etching operation and a double etching operation. The etching process can be performed a total of two times. After the single etching operation, the pixel electrode material layer 310' not protected by the pre-defined pixel boundary film 119p can remain as a single-layer film or a double-layer film. After the double etching operation, the pixel electrode material layer 310' not protected by the pre-defined pixel boundary film 119p can be removed. As another example, the etching process may also remove the pixel electrode material layer 310' by performing only a single etching operation.

[0333] A third contact hole CNT3 is formed in the planarization layer 117 to partially expose the electrode layer E. The pixel electrode 310 can be electrically connected to the thin film transistor TFT through the first contact hole CNT1 and the third contact hole CNT3.

[0334] Reference Figure 12fThis allows for the curing process of the 119p pre-pixel defining film. Figure 12d In this process, after forming the pre-pixel defining film 119p, a first curing process can be performed, and after forming the pixel electrode 310, a second curing process can be performed. The conditions for the first and second curing processes can be different.

[0335] When the pre-pixel defining film 119p is cured under single-stage curing conditions, the pre-pixel defining film 119p can still maintain fluidity after the curing process. Therefore, after patterning the pixel electrode 310, if the curing process conditions are changed to perform a second curing process on the pre-pixel defining film 119p, then as... Figure 12g As shown, a pre-defined pixel delimiting film 119p surrounds the side of the pixel electrode 310. Through a curing process, a portion of the pre-defined pixel delimiting film 119p is reflowed to surround the side of the pixel electrode 310. The side of the pixel electrode 310 is not exposed to the outside through the pre-defined pixel delimiting film 119p, thus preventing the highly reducing silver (Ag) contained in the pixel electrode 310 from reacting with external particles.

[0336] Reference Figure 12g as well as Figure 12h To expose a portion of the pixel electrode 310, an etching process is performed to remove the second preliminary pixel defining film 119pb. The second preliminary pixel defining film 119pb can be removed from the preliminary pixel defining film 119p to form the pixel defining film 119. As an example, the etching process can be dry etching.

[0337] It can be seen that the first portion 117a of the planarization layer 117 corresponds to the portion protected by the pre-defined pixel boundary film 119p during the etching process, and the second portion 117b of the planarization layer 117 corresponds to the portion not protected by the pre-defined pixel boundary film 119p during the etching process. Through the pre-defined pixel boundary film 119p, the planarization layer 117 can have a step ST between the first portion 117a and the second portion 117b.

[0338] When etching the second pre-pixel defining film 119pb, the first pre-pixel defining film 119pa and the first portion 117a of the planarization layer 117 can be locally etched together. As a result, the planarization layer 117 and the pixel defining film 119 can have the same etch surfaces s and s'. The outer surface of the pixel defining film 119 and the side surface of the planarization layer 117 can be located on the same etch surfaces s and s'.

[0339] On the other hand, such as Figure 12f As shown, the pixel electrode 310 is formed using a pre-defined pixel boundary film 119p as an etching mask, such as Figure 12g as well as Figure 12h As shown, the first portion 117a of the planarization layer 117 is also formed using the pre-defined pixel film 119p as an etching mask. Therefore, the planar shape of the pixel electrode 310 and the planar shape of the first portion 117a substantially correspond to the planar shape of the pixel film 119p. Furthermore, as... Figure 12h As shown, the edge of the pixel electrode 310 and the sidewall of the first portion 117a also correspond to each other. The edge of the pixel electrode 310 and the sidewall of the pixel defining film 119 also correspond to each other.

[0340] Reference Figure 12h An intermediate layer 320 is formed on the pixel electrode 310, that is, inside the opening of the pixel defining film 119. The intermediate layer 320 may contain a low molecular weight or polymer material. The intermediate layer 320 may be formed by vacuum evaporation, screen printing or inkjet printing, laser induced thermal imaging (LITI), etc.

[0341] The intermediate layer 320 of the light-emitting element 300 may include an organic light-emitting layer. The organic light-emitting layer may contain an organic material that emits fluorescent or phosphorescent substances that emit red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. Selectively, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be disposed below and above the organic light-emitting layer. The intermediate layer 320 may be configured corresponding to each of the multiple pixel electrodes 310. However, it is not limited to this. The intermediate layer 320 may include a layer integrally formed across multiple pixel electrodes 310, and various modifications are possible.

[0342] Subsequently, counter electrodes 330 are formed to correspond to the plurality of light-emitting elements 300. The counter electrodes 330 can be formed by an opening mask to cover the display area DA of the substrate 100. The counter electrodes 330 can be formed by vapor deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD).

[0343] Figures 13a to 13g These are cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment of the present invention. Specifically, based on... Figure 10 Cross-sectional views of a method for manufacturing a display device according to an embodiment of the present invention are shown in sequence. Figures 13a to 13g In, with Figure 10 The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0344] Reference Figure 13a A pixel electrode material layer 310' and a pixel defining film material layer 119' are sequentially formed above the planarization layer 117. Before the sequential formation of the pixel electrode material layer 310' and the pixel defining film layer 119', the formation processes of the thin-film transistor (TFT), the pad electrode (PE), the planarization layer 117, etc., can be synchronized with... Figure 12a as well as Figure 12b same.

[0345] A third mask M3 can be disposed on the pixel-defining film material layer 119'. The third mask M3 can adjust the exposure applied to the pixel-defining film material layer 119' for each region. For example, compared to the first region AR1, the fifth region AR5, and the seventh region AR7 of the third mask M3, the third region AR3 and the sixth region AR6 of the third mask M3 can be adjusted to have a smaller exposure applied to the pixel-defining film material layer 119'. Compared to the sixth region AR6 of the third mask M3, the third region AR3 of the third mask M3 can be adjusted to have a smaller exposure applied to the pixel-defining film material layer 119'. The exposure applied to the pixel-defining film material layer 119' corresponding to the third region AR3 of the third mask M3 can be minimized. As an example, the third mask M3 can be a half-tone mask or a slit mask. In some embodiments, the second region AR2 and the fourth region AR4 of the third mask M3 can be masked to prevent exposure of the pixel-defining film material layer 119'.

[0346] The pixel defining film material layer 119' can be exposed using a third mask M3 with different exposure levels for each region, and a portion of the pixel defining film material layer 119' can be removed using a development process. The amount of pixel defining film material layer 119' removed varies depending on the exposure level, thus allowing the formation of a pre-pixel defining film 119p and a photoresist pattern PR with different thicknesses for each region in a single step.

[0347] For example, such as Figure 13bAs shown, a pre-pixel defining film 119p can be formed in the display area DA, and a photoresist pattern PR can be formed in the peripheral area PA. The pre-pixel defining film 119p can include a first pre-pixel defining film 119pa and a second pre-pixel defining film 119pb surrounded by the first pre-pixel defining film 119pa. The photoresist pattern PR can be formed simultaneously with the pixel defining film material layer 119' and the pre-pixel defining film 119p, and therefore can contain the same material as the pre-pixel defining film 119p.

[0348] The first pre-pixel defining film 119pa corresponds to the portion of the pixel defining film material layer 119' that is not exposed and is not removed by the second region AR2 and the fourth region AR4 of the third mask M3. The second pre-pixel defining film 119pb corresponds to the portion of the pixel defining film material layer 119' that is minimally exposed by the third region AR3 of the third mask M3 and is minimally removed. The photoresist pattern PR corresponds to the portion of the pixel defining film material layer 119' that is exposed by the sixth region AR6 of the third mask M3 with more exposure than the third region AR3 of the third mask M3, and corresponds to the portion of the pixel defining film material layer 119' that is more removed compared to the second pre-pixel defining film 119pb.

[0349] The thickness t1 of the first pre-pixel defining film 119pb can be thicker than the thickness t2 of the second pre-pixel defining film 119pb. The thickness t2 of the second pre-pixel defining film 119pb can be thicker than the thickness t3 of the photoresist pattern PR. That is, the thicknesses t1 and t2 of the pre-pixel defining films 119p can be thicker than the thickness t3 of the photoresist pattern PR.

[0350] exist Figure 13a The example given is that the pixel defining film material layer 119' contains positive photoresist, but the pixel defining film material layer 119' may also contain negative photoresist. In this case, contrary to the case where the pixel defining film material layer 119' contains positive photoresist, the more exposure applied to the pixel defining film material layer 119', the thicker the pixel defining film material layer 119' remains after the development process.

[0351] Reference Figure 13b as well as Figure 13c Using the pre-defined pixel boundary film 119p and photoresist pattern PR formed on the pixel electrode material layer 310', the pixel electrode material layer 310' is etched to form the pixel electrode 310 and the pad connection electrode PCE. That is, the pixel electrode 310 and the pad connection electrode PCE can be formed by vapor deposition of the pixel electrode material layer 310' through a masking process and an etching process. As an example, the etching process can be wet etching.

[0352] Reference Figure 13c as well as Figure 13d The curing process for the pre-pixel delimiting film 119p can be performed. After patterning the pixel electrode 310, if the curing process for the pre-pixel delimiting film 119p is performed, then... Figure 13d As shown, a pre-defined pixel delimiting film 119p surrounds the side of the pixel electrode 310. Through a curing process, a portion of the pre-defined pixel delimiting film 119p is reflowed to surround the side of the pixel electrode 310. The side of the pixel electrode 310 is not exposed to the outside through the pre-defined pixel delimiting film 119p, thus preventing the highly reducing silver (Ag) contained in the pixel electrode 310 from reacting with external particles.

[0353] Although the pre-defined pixel boundary film 119p was used as an example, the photoresist pattern PR can also be cured together. A portion of the photoresist pattern PR is reflowed around the side of the bonding pad connecting electrode PCE.

[0354] Reference Figure 13d as well as Figure 13e An etching process is then performed to remove the photoresist pattern (PR). For example, this etching process could be dry etching.

[0355] It can be seen that the first portion 117a of the planarization layer 117 corresponds to the portion protected by the pre-defined pixel boundary film 119p during the etching process, and the second portion 117b of the planarization layer 117 corresponds to the portion not protected by the pre-defined pixel boundary film 119p during the etching process. Through the pre-defined pixel boundary film 119p, the planarization layer 117 can have a step ST between the first portion 117a and the second portion 117b. Furthermore, through the etching process, a portion of the pre-defined pixel boundary film 119p can be etched, and the overall thickness of the pre-defined pixel boundary film 119p also becomes thinner.

[0356] Subsequently, the etching process can be performed without removing the pre-defined pixel layer 119p. For example, the etching process can be wet etching.

[0357] Reference Figure 13f The three-layer film of the pad connection electrode PCE (excluding the film adjacent to the pad electrode PE) can be removed by etching. The pad connection electrode PCE can then become a single-layer film.

[0358] As a comparative example, the pad connection electrode can be maintained as a three-layer film. In the case of a three-layer film pad connection electrode, it can be formed as ITO / Ag / ITO. The pad connection electrode can be exposed without being covered by an insulating layer. In this case, the highly reactive silver (Ag) is exposed, posing a risk of short circuit to adjacent electrodes.

[0359] However, in the case of removing two of the three films of the pad connection electrode PCE as in one embodiment of the present invention, only ITO is present in the exposed pad connection electrode PCE, and the risk of short circuit with adjacent electrodes is eliminated.

[0360] Next, an etching process is performed to remove the second preliminary pixel defining film 119pb to expose a portion of the pixel electrode 310. The second preliminary pixel defining film 119pb can be removed from the preliminary pixel defining film 119p to form the pixel defining film 119. As an example, the etching process can be dry etching.

[0361] When etching the second pre-pixel defining film 119pb, the first pre-pixel defining film 119pa and the first portion 117a of the planarization layer 117 can be locally etched together. As a result, the planarization layer 117 and the pixel defining film 119 can have the same etch surfaces s and s'. The outer surface of the pixel defining film 119 and the side surface of the planarization layer 117 can be located on the same etch surfaces s and s'.

[0362] On the other hand, such as Figure 13c As shown, the pixel electrode 310 is formed using a pre-defined pixel boundary film 119p as an etching mask, such as Figure 13f as well as Figure 13g As shown, the first portion 117a of the planarization layer 117 is also formed using the pre-defined pixel film 119p as an etching mask. Therefore, the planar shape of the pixel electrode 310 and the planar shape of the first portion 117a substantially correspond to the planar shape of the pixel film 119p. Furthermore, as... Figure 13g As shown, the edge of the pixel electrode 310 and the sidewall of the first portion 117a also correspond to each other. The edge of the pixel electrode 310 and the sidewall of the pixel defining film 119 also correspond to each other.

[0363] Subsequently, an intermediate layer 320 is formed inside the opening of the pixel defining film 119, and a counter electrode 330 is formed on the intermediate layer 320.

[0364] Figures 14a to 14i These are cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment of the present invention. Specifically, based on... Figure 9 Cross-sectional views of a method for manufacturing a display device according to an embodiment of the present invention are shown in sequence. Figures 14a to 14i In, with Figure 9 as well as Figures 12a to 12h The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0365] Reference Figure 14a First, a conductive layer BML, a buffer layer 111, a semiconductor layer A, a gate insulating layer 113, a gate electrode G, a first electrode CE1 and a second electrode CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protective layer PVX are sequentially formed on a substrate 100. The process of forming the inorganic protective layer PVX from the conductive layer BML is similar to that in... Figure 12a The same applies as described in [the document]. However, it is possible that after forming the inorganic protective layer PVX, contact holes for separately exposing the electrode protective layer EPL and the pad protective layer PPL are not formed using a separate mask, as shown in [the document]. Figure 14b as well as Figure 14c As shown, contact holes are formed using planarization layer 117. As a result, contact holes formed in the inorganic protective layer PVX can be formed without a separate mask.

[0366] Reference Figure 14b A planarization layer 117' can be disposed on the inorganic protective layer PVX. A fourth mask M4 can be disposed on the planarization layer 117'. The fourth mask M4 can adjust the exposure applied to the planarization layer 117' according to each region. For example, compared with the second region AR2 and the fifth region AR5 of the fourth mask M4, the fourth region AR4 of the fourth mask M4 can be adjusted to a smaller exposure applied to the planarization layer 117'. In addition, compared with the second region AR2 and the fifth region AR5 of the fourth mask M4, the sixth region AR6 of the fourth mask M4 can be adjusted to a smaller exposure applied to the planarization layer 117'. As an example, the fourth mask M4 can be a half-tone mask or a slit mask. In some embodiments, the first region AR1 and the third region AR3 of the fourth mask M4 can be masked to prevent exposure of the planarization layer 117'.

[0367] The planarization layer 117' can be exposed using a fourth mask M4 with different exposure levels for each region, and a portion of the planarization layer 117' can be removed using a developing process. The amount of planarization layer 117' removed varies depending on the exposure level, thus allowing planarization layers 117 with different thicknesses for each region to be formed in a single step. That is, as... Figure 14cAs shown, the thickness of the planarization layer 117 corresponding to the display area DA can be thicker than the thickness of the planarization layer 117 corresponding to the peripheral area PA. Then, the adhesion to the inorganic protective layer PVX can be increased through a curing and drying process of the planarization layer 117. At this time, the curing and drying process may include a heat treatment process.

[0368] exist Figure 14b The planarization layer 117' is given as an example of containing positive photoresist, but the planarization layer 117' may also contain negative photoresist. In this case, contrary to when the planarization layer 117' contains positive photoresist, the more exposure applied to the planarization layer 117', the thicker the planarization layer 117' remains after the development process.

[0369] Reference Figure 14c as well as Figure 14d Using a patterned planarization layer 117, a first contact hole CNT1 partially exposes the electrode layer E, and a second contact hole CNT2 partially exposes the pad electrode PE, forming on the inorganic protective layer PVX. The first contact hole CNT1 and the second contact hole CNT2 are formed by a partial etching process of the inorganic protective layer PVX. As an example, the partial etching process of the inorganic protective layer PVX can be dry etching. Although in Figure 14d It is not shown in the figure, but a portion of the planarization layer 117 can also be removed together to reduce the overall thickness of the planarization layer 117.

[0370] Reference Figures 14e to 14i A pixel electrode material layer 310' and a pixel defining film material layer 119' are sequentially formed on the planarization layer 117. Figure 14e A pre-pixel defining film 119p with different thicknesses for each region can be formed in one step using a fifth mask M5 disposed on the pixel defining film material layer 119'. Figure 14f Then, using the pre-defined pixel demarcation film 119p formed on the pixel electrode material layer 310', the pixel electrode material layer 310' is etched to form the pixel electrode 310. Figure 14f as well as Figure 14g The pre-pixel defining film 119p can be configured to surround the side of the pixel electrode 310 by performing a curing process. Figure 14g as well as Figure 14h An etching process is performed to remove a portion of the second pre-pixel defining film 119pb used to expose the pixel electrode 310. Figure 14h The second preliminary pixel delimiting film 119pb can be etched to form the pixel delimiting film 119. Details are already available in [the relevant section]. Figures 12d to 12h It was described, therefore in Figures 14e to 14iRepeated explanations are omitted.

[0371] It can be seen that the first portion 117a of the planarization layer 117 corresponds to the portion protected by the pre-pixel delimiting film 119p during the etching process of the second pre-pixel delimiting film 119pb, and the second portion 117b of the planarization layer 117 corresponds to the portion not protected by the pre-pixel delimiting film 119p during the etching process of the second pre-pixel delimiting film 119pb. Through the pre-pixel delimiting film 119p, the planarization layer 117 can have a step ST between the first portion 117a and the second portion 117b on its upper surface. Furthermore, the planarization layer 117 and the pixel delimiting film 119 can have the same etched surface. The planarization layer 117 corresponding to the peripheral region PA cannot be protected by the pre-pixel delimiting film 119p during the etching process and can therefore be removed.

[0372] Figures 15a to 15g These are cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment of the present invention. Specifically, based on... Figure 11 Cross-sectional views of a method for manufacturing a display device according to an embodiment of the present invention are shown in sequence. Figures 15a to 15g In, with Figure 11 as well as Figures 13a to 13g The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0373] Reference Figure 15a A pixel electrode material layer 310' and a pixel defining film material layer 119' are sequentially formed above the planarization layer 117. Before the sequential formation of the pixel electrode material layer 310' and the pixel defining film layer 119', the formation processes of the thin-film transistor (TFT), the pad electrode (PE), the planarization layer 117, etc., can be synchronized with... Figures 14a to 14d same.

[0374] Reference Figures 15a to 15g A pre-pixel defining film 119p and a photoresist pattern PR with different thicknesses for each region can be formed in one step using a sixth mask M6 disposed on the pixel defining film material layer 119'. Figure 15b Subsequently, the pixel electrode material layer 310' is etched using the pre-pixel defining film 119p and the photoresist pattern PR formed on the pixel electrode material layer 310', to form the pixel electrode 310 and the pad connection electrode PCE. Figure 15b as well as Figure 15c The pre-pixel defining film 119p can be configured to surround the side of the pixel electrode 310 by performing a curing process. Figure 15c as well as Figure 15d An etching process is performed to remove the photoresist pattern PR. Figure 15e ).

[0375] During the etching process, the planarization layer 117 may have a step ST. Additionally, the portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral region PA that is not protected by the photoresist pattern PR is removed. Conversely, the portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral region PA that is protected by the photoresist pattern PR remains. Furthermore, as... Figure 15e As shown, during the etching process, the photoresist pattern PR can also be completely etched away. That is, the step of locally etching the third portion 117c of the planarization layer 117 and the step of removing the photoresist pattern PR can be performed simultaneously.

[0376] Subsequently, with the pre-pixel defining film 119p still in place, an etching process is performed to make the pad-connecting electrode PCE a single-layer film. Figure 15e as well as Figure 15f An etching process is performed to remove the second pre-pixel defining film 119pb to expose a portion of the pixel electrode 310. Figure 15f as well as Figure 15g The second preliminary pixel delimiting film 119pb can be removed to form the pixel delimiting film 119. Figures 13a to 13g The above has been described, therefore details are omitted. Figures 15a to 15g Detailed information.

[0377] Figure 16 as well as Figure 17 This is a simplified cross-sectional view of a display device according to an embodiment of the present invention. Figure 16 as well as Figure 17 Equivalent to Figure 9 as well as Figure 11 A portion of the modified embodiments. In Figure 16 as well as Figure 17 In, with Figure 9 as well as Figure 11 The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0378] Reference Figure 16 Display device 1 (refer to) Figure 1 The system includes: a thin-film transistor (TFT) disposed on a substrate 100 corresponding to a display area DA; and a pad portion PAD disposed on the substrate 100 corresponding to a peripheral area PA. As an insulating layer disposed on the TFT and exposing the pad portion PAD, a planarization layer 117 is included. The planarization layer 117 includes a first portion 117a and a second portion 117b extending to one side from the first portion 117a. At this time, the upper surface of the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b.

[0379] A pixel defining film 119 may be disposed on the planarization layer 117. In this case, the side surfaces of the planarization layer 117 and the side surfaces of the pixel defining film 119 may be etched surfaces of the same plane. The side surfaces of the first portion 117a of the planarization layer 117 and the side surfaces of the pixel defining film 119 may also be etched surfaces of the same plane.

[0380] The following is for reference Figure 16 The structure included in the display device 1 will be described more specifically based on the stacked structure.

[0381] A buffer layer 111 may be disposed on the substrate 100. A barrier layer may also be included between the substrate 100 and the buffer layer 111. A conductive layer BML, an electrode layer E, a first electrode CE1 of a storage capacitor Cst, and an auxiliary pad electrode SPE may be disposed between the substrate 100 and the buffer layer 111. Figure 9 as well as Figure 11 Unlike the example shown, the electrode layer E is not disposed on a different layer from the conductive layer BML. The conductive layer BML, electrode layer E, first electrode CE1, and auxiliary pad electrode SPE are disposed on the same layer; therefore, the conductive layer BML, electrode layer E, the first electrode CE1 of the storage capacitor Cst, and auxiliary pad electrode SPE can be patterned on a single metal layer and formed simultaneously. This reduces the number of masks used in manufacturing the display device 1.

[0382] A semiconductor layer A can be disposed on the buffer layer 111. A gate insulating layer 113 can be disposed on the semiconductor layer A. Figure 16 As shown, the gate insulating layer 113 can be patterned to overlap with a portion of the semiconductor layer A.

[0383] A gate electrode G may be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer A. In addition, a first bridge electrode BE1, a second bridge electrode BE2, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE may be disposed on the gate insulating layer 113.

[0384] The first bridging electrode BE1 can be connected to the conductive layer BML and the semiconductor layer A through contact holes formed in the gate insulating layer 113 and the buffer layer 111, respectively. The conductive layer BML and the semiconductor layer A can be electrically connected through the first bridging electrode BE1.

[0385] The second bridging electrode BE2 can be connected to the electrode layer E and the semiconductor layer A through contact holes formed in the gate insulating layer 113 and the buffer layer 111, respectively. The electrode layer E and the semiconductor layer A can be electrically connected through the second bridging electrode BE2.

[0386] The first electrode CE1 and the second electrode CE2 of the storage capacitor Cst can overlap each other by placing the gate insulating layer 113 and the buffer layer 111 between them. The gate insulating layer 113 and the buffer layer 111 can function as the dielectric layer of the storage capacitor Cst. Figure 16 The second electrode CE2 of the storage capacitor Cst shown is made of the same material as the gate electrode G, but the second electrode CE2 of the storage capacitor Cst may also be made of the same material as the semiconductor layer A. The second electrode CE2 of the storage capacitor Cst may also be disposed in the same layer as the semiconductor layer A.

[0387] It is possible that an electrode protection layer EPL is disposed on the gate electrode G, the first bridging electrode BE1, the second bridging electrode BE2 and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL is disposed on the pad electrode PE.

[0388] The gate electrode G, the first bridging electrode BE1, the second bridging electrode BE2, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE can be covered by the inorganic protective layer PVX.

[0389] A planarization layer 117 is disposed on the inorganic protective layer PVX. The planarization layer 117 includes contact holes for connecting the thin-film transistor TFT and the pixel electrode 310. The planarization layer 117 can be configured to expose the pad portion PAD. That is, the planarization layer 117 may not be disposed in the peripheral area PA and may not overlap with the pad portion PAD.

[0390] A light-emitting element 300 is disposed on the planarization layer 117. The light-emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light-emitting layer, and a counter electrode 330.

[0391] A pixel defining film 119 may be disposed on the planarization layer 117. The pixel defining film 119 may cover the edge of the pixel electrode 310 and have an opening that exposes a portion of the pixel electrode 310. The planarization layer 117 and the pixel defining film 119 may have the same etched surfaces s, s'.

[0392] In one embodiment, such as Figure 17 As shown, a pad connection electrode PCE can be disposed on the pad electrode PE. The display device 1 may also include an insulating layer 118 disposed on the inorganic protective layer PVX corresponding to the peripheral region PA and containing the same material as the planarization layer 117. The insulating layer 118 can be disposed between the pad electrode PE and the pad connection electrode PCE, and at least partially overlaps with the pad connection electrode PCE. The surface of the insulating layer 118 overlapping the pad connection electrode PCE may be inclined.

[0393] When manufacturing according to Figure 16 as well as Figure 17 The display device 1 shown in one embodiment can be similarly applied to [other applications]. Figures 14b to 14i , Figures 15a to 15g The manufacturing method of the display device described in the text.

[0394] Figure 18 This is a simplified cross-sectional view illustrating a display device according to an embodiment of the present invention. Figure 18 In, with Figure 9 The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0395] Reference Figure 18 In a display device 1 according to an embodiment of the present invention (refer to...) Figure 1 The display area DA can be configured with at least one thin-film transistor TFT and a display element connected to the thin-film transistor TFT.

[0396] The display area DA of the display device 1 according to this embodiment includes first to third pixels PX1, PX2, and PX3. Of course, this is exemplary, and the display device 1 may have more pixels. Furthermore, in Figure 18 The diagram shows that the first to third pixels PX1, PX2, and PX3 are adjacent to each other, but the invention is not limited to this. That is, other wiring or other structural elements may be present between the first to third pixels PX1, PX2, and PX3. Therefore, for example, the first pixel PX1 and the second pixel PX2 may not be pixels arranged adjacent to each other. Furthermore, in... Figure 18 The cross sections of the first to third pixels PX1, PX2, and PX3 do not have to be cross sections in the same direction.

[0397] The first to third pixels PX1, PX2, and PX3 each include a light-emitting region EA. The light-emitting region EA can be a region that generates light and emits it outwards. Alternatively, a non-light-emitting region NEA can be disposed between the light-emitting regions EA, with the light-emitting regions EA divided by the non-light-emitting regions NEA.

[0398] The first to third pixels, PX1, PX2, and PX3, can emit different colors. For example, the first pixel PX1 can emit red light, the second pixel PX2 can emit green light, and the third pixel PX3 can emit blue light. When viewed on a plane, the emitting area EA can be in various polygonal or circular shapes, and can be arranged in various patterns such as stripes or five-square grids.

[0399] On the other hand, the display device 1 according to this embodiment may have a first quantum dot layer 220a, a second quantum dot layer 220b, and a transmissive layer 220c corresponding to the light-emitting region EA. The first quantum dot layer 220a, the second quantum dot layer 220b, and the transmissive layer 220c may include quantum dots and metal nanoparticles.

[0400] For example, the first pixel PX1 may include a first quantum dot layer 220a, the second pixel PX2 may include a second quantum dot layer 220b, and the third pixel PX3 may include a transmissive layer 220c.

[0401] In this embodiment, the average size of the quantum dots included in the first quantum dot layer 220a and the second quantum dot layer 220b may be different from each other.

[0402] Hereinafter, a display device 1 according to an embodiment of the present invention will be described. Figure 18 The stacking order shown will be explained in detail.

[0403] The substrate 100 (hereinafter referred to as the lower substrate) may comprise a glass material, a ceramic material, a metallic material, or a material with flexible or bendable properties. A barrier layer (not shown) may also be included between the lower substrate 100 and the buffer layer 111.

[0404] Alternatively, a conductive layer BML may be disposed on the lower substrate 100, and a semiconductor layer A may be disposed on the buffer layer 111. On the semiconductor layer A, the gate electrode G may be configured such that a gate insulating layer 113 is placed between it and at least partially overlaps with the semiconductor layer A.

[0405] An interlayer insulating layer 115 can be provided to cover the gate electrode G. An active electrode and a drain electrode, etc., can be disposed above the interlayer insulating layer 115.

[0406] Alternatively, a planarization layer 117 may be disposed on the source electrode and the drain electrode, and first to third light-emitting elements 300a, 300b, and 300c may be disposed on the planarization layer 117. Each of the first to third light-emitting elements 300a, 300b, and 300c may commonly include a pixel electrode 310, an intermediate layer 320 including an organic light-emitting layer, and a counter electrode 330.

[0407] A pixel defining film 119 may be disposed on the planarization layer 117. In one embodiment, such as Figure 18As shown, the planarization layer 117 and the pixel defining film 119 can have the same etched surfaces s and s'. The planarization layer 117 and the pixel defining film 119 can be formed simultaneously using the same etching process and can include the same etched surfaces s and s'. A portion of the planarization layer 117 can be etched using the pixel defining film 119 as a mask, and the outer side surface of the pixel defining film 119 and the side surface of the planarization layer 117 can be located on the same etched surfaces s and s'. The outer side surface of the pixel defining film 119 and the side surface of the first portion 117a of the planarization layer 117 can be located on the same etched surfaces s and s'.

[0408] When the pixel defining film 119 and the first portion 117a of the planarization layer 117 have the same etched surfaces s and s', the pixel defining film 119 can be configured corresponding to the first portion 117a. The pixel defining film 119 can be configured corresponding to the first portion 117a but not configured in the second portion 117b. The pixel defining film 119 can be removed from the portion corresponding to the second portion 117b. The insulating layer formed of organic material can be removed by adding the thickness t of the pixel defining film 119 to the step ST of the planarization layer 117. In this case, a portion of the pixel defining film 119 and the planarization layer 117 adjacent to the light-emitting element 300 are removed, thereby reducing the volume of organic material within the display device 1 and minimizing the outgassing of the organic material. Therefore, even if the display device 1 is exposed to sunlight for a long time, the decomposition of organic material caused by sunlight can be prevented or minimized, thus preventing defects such as pixel shrinkage caused by outgassing. The reliability of the display device 1 can be improved.

[0409] The first to third light-emitting elements 300a, 300b, and 300c may be easily damaged by external moisture or oxygen, and therefore can be protected by covering them with a thin-film encapsulation layer 400. The thin-film encapsulation layer 400 can cover the display area DA and extend beyond the display area DA. The thin-film encapsulation layer 400 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin-film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0410] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and includes silicon oxide, silicon nitride, and / or silicon trioxide, etc. Although not shown, other layers such as a capping layer may also be interposed between the first inorganic encapsulation layer 410 and the counter electrode 330 as needed. The first inorganic encapsulation layer 410 is formed along the structure below it, and therefore its surface is not flat. An organic encapsulation layer 420 may cover such a first inorganic encapsulation layer 410 and, unlike the first inorganic encapsulation layer 410, its surface is generally flat.

[0411] Even if cracks occur within the thin-film encapsulation layer 400, the aforementioned multilayer structure ensures that such cracks do not connect between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420, or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. This prevents or minimizes the formation of pathways that allow external moisture or oxygen to penetrate into the display area DA.

[0412] As described above, the insulating layer formed with organic material can be removed from the portion corresponding to the second portion 117b of the planarization layer 117. The organic encapsulation layer 420 can be further configured to increase the amount of insulating layer removed. The thickness t4 of the organic encapsulation layer 420 can increase the amount of insulating layer removed, thus making it difficult for foreign matter flowing in from the outside to reach the counter electrode 330, thereby preventing the degradation of the light-emitting element 300. It is possible to prevent the thin-film encapsulation layer 400 from being damaged by foreign matter flowing in from the outside, and to prevent the degradation of the light-emitting element 300 due to damage to the thin-film encapsulation layer 400.

[0413] The upper substrate 200 is located above the lower substrate 100, and the counter electrode 330 is positioned between the upper substrate 200 and the lower substrate 100. The upper substrate 200 may comprise glass, metal, or polymer resin. If the upper substrate 200 has flexible or bendable properties, it may comprise, for example, polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Alternatively, the upper substrate 200 may have a multilayer structure comprising two layers, each containing such a polymer resin, and a barrier layer containing inorganic materials (such as silicon oxide, silicon nitride, or silicon oxynitride) between these layers, allowing for various deformations.

[0414] A light-shielding layer 230 is disposed on the underside of the upper substrate 200 in the direction of the lower substrate 100. The light-shielding layer 230 includes openings corresponding to the first to third light-emitting elements 300a, 300b, and 300c, respectively, and the first to third filter layers 210a, 210b, and 210c are respectively located within the openings. The light-shielding layer 230 serves as a black matrix and can be a layer used to enhance color vividness and contrast. The light-shielding layer 230 may contain at least one of black pigment, black dye, or black particles. In some embodiments, the light-shielding layer 230 may contain Cr or CrO. X Cr / CrO X Cr / CrO X / CrN Y Materials include resins (carbon pigments, RGB mixed pigments), graphite, and non-Cr-based materials.

[0415] Alternatively, the first filter layer 210a can allow only light with wavelengths between 630nm and 780nm to pass through, the second filter layer 210b can allow only light with wavelengths between 495nm and 570nm to pass through, and the third filter layer 210c can allow only light with wavelengths between 450nm and 495nm to pass through. The first to third filter layers 210a, 210b, and 210c can reduce external light reflection in the display device 1.

[0416] A first upper insulating layer 240 is disposed on the light-shielding layer 230. The first upper insulating layer 240 includes a first opening 241a corresponding to the first light-emitting element 300a, a first opening 241b corresponding to the second light-emitting element 300b, and a first opening 241c corresponding to the third light-emitting element 300c. A first quantum dot layer 220a is located within the first opening 241a, a second quantum dot layer 220b is located within the first opening 241b, and a transmissive layer 220c is located within the first opening 241c. The first quantum dot layer 220a and the second quantum dot layer 220b can be formed by inkjet printing.

[0417] The first upper insulating layer 240 may, for example, contain an organic material. Depending on the application, the first upper insulating layer 240 may contain a light-shielding material to function as a light-shielding layer. The light-shielding material may, for example, contain at least one of black pigment, black dye, black particles, or metal particles. In one embodiment, the first upper insulating layer 240 may be blue.

[0418] The first quantum dot layer 220a can convert light of a first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into light of a second wavelength band. For example, if light with a wavelength of 450 nm to 495 nm is generated from the intermediate layer 320 on the pixel electrode 310, the first quantum dot layer 220a can convert that light into light with a wavelength of 630 nm to 780 nm. Thus, in the first pixel PX1, light with a wavelength of 630 nm to 780 nm is emitted to the outside through the upper substrate 200.

[0419] The second quantum dot layer 220b can convert light of the first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into light of the third wavelength band. For example, if light with a wavelength of 450 nm to 495 nm is generated from the intermediate layer 320 on the pixel electrode 310, the second quantum dot layer 220b can convert this light into light with a wavelength of 495 nm to 570 nm. Thus, in the second pixel PX2, light with a wavelength of 495 nm to 570 nm is emitted to the outside through the upper substrate 200.

[0420] The first quantum dot layer 220a and the second quantum dot layer 220b can each have quantum dots dispersed within a resin. Quantum dots include semiconductor materials such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or indium phosphide (InP). The size of the quantum dots can be several nanometers, and the wavelength of the converted light varies depending on the size of the quantum dots. The resin containing the first quantum dot layer 220a and the second quantum dot layer 220b can be any transparent material. For example, polymer resins such as acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO) can be used as the materials for forming the first quantum dot layer 220a and the second quantum dot layer 220b.

[0421] In the third pixel PX3, light of the first wavelength generated from the intermediate layer 320 can be emitted outward without wavelength change. Therefore, the third pixel PX3 may not have a quantum dot layer. Thus, a quantum dot layer is not required within the first-third opening 241c, and a transmissive layer 220c formed of a light-transmitting resin can be configured. The transmissive layer 220c may contain acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). Of course, depending on the circumstances, it may also contain... Figure 18 The difference shown is that the transmission layer 220c is absent in the first-third opening 241c.

[0422] In this display device according to the present embodiment, a second band of light is emitted outward from the first pixel PX1, a third band of light is emitted outward from the second pixel PX2, and a first band of light is emitted outward from the third pixel PX3. Therefore, the display device 1 according to the present embodiment can display a full-color image.

[0423] A second upper insulating layer 250 is disposed on the first upper insulating layer 240. The second upper insulating layer 250 includes a second-1 opening 251a corresponding to the first-1 opening 241a, a second-2 opening 251b corresponding to the first-2 opening 241b, and a second-3 opening 251c corresponding to the first-3 opening 241c.

[0424] The first quantum dot layer 220a and the second quantum dot layer 220b, located within the first-1 opening 241a and the first-2 opening 241b respectively, can be formed by inkjet printing. The second-1 opening 251a and the second-2 opening 251b can be channels through which ink ejected from the nozzle falls during inkjet printing. The ink moving through the second upper insulating layer 250 including the second-1 opening 251a and the second-2 opening 251b can reach the first-1 opening 241a and the first-2 opening 241b respectively, forming the first quantum dot layer 220a and the second quantum dot layer 220b.

[0425] The second upper insulating layer 250 may contain a light-shielding material. For example, the light-shielding material may contain at least one of black pigment, black dye, black particles, or metal particles. Alternatively, in one embodiment, the second upper insulating layer 250 may be blue. As described above, the first upper insulating layer 240 may also contain a light-shielding material, but the materials constituting the first upper insulating layer 240 and the second upper insulating layer 250 may be different in order to form the first quantum dot layer 220a and the second quantum dot layer 220b by inkjet printing.

[0426] As an example, the second upper insulating layer 250, which is the channel through which ink travels via the nozzle during inkjet printing, may contain a substance that has no affinity for ink. Alternatively, the first upper insulating layer 240, which forms the first quantum dot layer 220a and the second quantum dot layer 220b by accumulating ink, may contain a substance that has an affinity for ink.

[0427] exist Figure 18 The first upper insulating layer 240 and the second upper insulating layer 250 are both shown in the diagram, but the second upper insulating layer 250 may be omitted, or only the first upper insulating layer 240 may be disposed on the upper substrate 200.

[0428] A filler 600 may be disposed between the lower substrate 100 and the upper substrate 200. The filler 600 can act as a buffer against external pressure. The filler 600 can be formed from organic substances such as methyl silicone, phenylsilicone, and polyimide. However, it is not limited to these; the filler 600 can also be formed from polyurethane resin, epoxy resin, acrylic resin as an organic sealant, or silicone as an inorganic sealant.

[0429] Figure 19 This is a simplified cross-sectional view illustrating a display device according to an embodiment of the present invention. Specifically, Figure 19 It is Figure 1 An exemplary cross-sectional view of the display device taken along I-I' and II-II'. Figure 19 In, with Figure 9 The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0430] Reference Figure 19 The display device 1 includes a display area DA and a peripheral area PA. The substrate 100 may have areas corresponding to the display area DA and the peripheral area PA.

[0431] Reference Figure 19 The display area DA can have a conductive layer BML, a thin-film transistor (TFT), and a light-emitting element 300 disposed on the substrate 100. Detailed information regarding this is available in [link to relevant documentation]. Figure 9 The text is described in the middle.

[0432] A thin-film encapsulation layer 400 may be disposed on the light-emitting element 300. The thin-film encapsulation layer 400 may be configured to cover the entire display area DA and extend towards the peripheral area PA to cover a portion of the peripheral area PA. The thin-film encapsulation layer 400 may extend to the outside of the common voltage supply line CVL.

[0433] The thin-film encapsulation layer 400 may include a first inorganic encapsulation layer 410, a second inorganic encapsulation layer 430, and an organic encapsulation layer 420 located between them.

[0434] A portion 330a of the counter electrode 330 may extend toward the peripheral region PA side and overlap with the common voltage supply line CVL. A connection wiring CL may be configured between the portion 330a of the counter electrode 330 and the common voltage supply line CVL. The connection wiring CL can electrically connect the common voltage supply line CVL and the counter electrode 330, so that the common voltage can be transmitted to the counter electrode 330.

[0435] Despite Figure 19Although not shown, a drive circuit region is disposed on the peripheral region PA. For example, a gate drive circuit section may be disposed in the drive circuit region. The gate drive circuit section may include a thin-film transistor and include wiring connected to the thin-film transistor.

[0436] The buffer layer 111, the interlayer insulation layer 115, and the inorganic protective layer PVX can extend to the surrounding area PA.

[0437] A first dam section DAM1, a second dam section DAM2, and a mask support MS can be configured on the inorganic protective layer PVX corresponding to the surrounding area PA. The first dam section DAM1, the second dam section DAM2, and the mask support MS can be configured to surround the periphery of the display area DA in a plane. That is, the first dam section DAM1 can be configured to surround the periphery of the display area DA, the second dam section DAM2 can be configured to surround the periphery of the first dam section DAM1, and the mask support MS can be configured to surround the periphery of the second dam section DAM2.

[0438] The first dam section DAM1 and the second dam section DAM2 serve to prevent the organic encapsulation layer 420 of the thin-film encapsulation layer 400 from overflowing onto the outside of the substrate 100. The mask support MS serves to support the opening mask used when forming the counter electrode 330, etc.

[0439] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 in the thin-film encapsulation layer 400 can partially overlap with the first dam section DAM1 and the second dam section DAM2. This differs from other methods, such as... Figure 19 As shown, the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may not overlap with the mask support MS.

[0440] The first dam section DAM1, the second dam section DAM2, and the mask support MS can be configured in a double-layer structure. Each of the first dam section DAM1, the second dam section DAM2, and the mask support MS can include peripheral insulating layers 117s and 119s containing the same material as the planarization layer 117 and the pixel defining film 119. The peripheral insulating layers 117s and 119s forming the first dam section DAM1, the second dam section DAM2, and the mask support MS can be disposed on the same layer as the planarization layer 117 and the pixel defining film 119.

[0441] Peripheral electrode layers 310a, 310b, and 310c may be interposed between the peripheral insulating layers 117s and 119s that respectively form the first dam section DAM1, the second dam section DAM2, and the mask support MS. Each peripheral electrode layer 310a, 310b, and 310c may contain the same material as the pixel electrode 310. Each peripheral electrode layer 310a, 310b, and 310c may be disposed in the same layer as the pixel electrode 310. Each peripheral electrode layer 310a, 310b, and 310c may be surrounded by the second peripheral insulating layer 119s.

[0442] The first peripheral insulating layer 117s and the second peripheral insulating layer 119s may have the same etched surface. The side surfaces of the first peripheral insulating layer 117s and the second peripheral insulating layer 119s may be located on the same etched surface.

[0443] The width of the mask support MS can be wider than the width of the first dam section DAM1. The width of the mask support MS can be wider than the width of the second dam section DAM2. As an example, the width of the mask support MS can be approximately 4 to 6 times the width of the first dam section DAM1.

[0444] The pixel defining film 119 and planarization layer 117 included in the display device 1 according to an embodiment of the present invention may have the same etched surface. The thickness t4 of the organic encapsulation layer 420 in the thin-film encapsulation layer 400 can increase the amount removed by etching the pixel defining film 119 and planarization layer 117, thus making it difficult for foreign matter flowing in from the outside to reach the counter electrode 330, thereby preventing deterioration of the light-emitting element 300. This prevents damage to the thin-film encapsulation layer 400 by foreign matter flowing in from the outside, and prevents deterioration of the light-emitting element 300 due to damage to the thin-film encapsulation layer 400.

[0445] In addition, the volume of organic matter inside the display device 1 can be reduced to minimize the release of organic matter.

[0446] Figure 20a This is a simplified cross-sectional view of a display device according to an embodiment of the present invention.

[0447] Reference Figure 20a Display device 1 (refer to) Figure 1 It includes: a thin-film transistor (TFT) disposed on a substrate 100 corresponding to the display area DA; and a pad portion (PAD) disposed on a substrate 100 corresponding to the peripheral area PA.

[0448] The display device 1 includes a planarization layer 117 as an insulating layer disposed on a thin-film transistor (TFT) and exposing the pad portion (PAD), and includes a pixel defining film 119 disposed on the planarization layer 117. In this case, the side surfaces of the planarization layer 117 adjacent to the peripheral region (PA) and the pixel defining film 119 can be aligned. This means that the side surfaces of the planarization layer 117 adjacent to the peripheral region (PA) and the pixel defining film 119 are located on the same surface. The side surfaces of the planarization layer 117 adjacent to the peripheral region (PA) and the pixel defining film 119 can be etched surfaces of the same surface formed by the same etching process.

[0449] Hereinafter, referring to 20a, the structure included in the display device 1 will be described in more detail according to the stacked structure.

[0450] The substrate 100 may comprise a glass material, a ceramic material, a metallic material, or a material with flexible or bendable properties. The substrate 100 may have a single-layer or multi-layer structure of said material, and in the case of a multi-layer structure, it may also include an inorganic layer. In some embodiments, the substrate 100 may have an organic / inorganic / organic structure.

[0451] The buffer layer 111 can reduce or prevent foreign matter, moisture or external gas from penetrating from under the substrate 100 and can provide a flat surface on the substrate 100.

[0452] A barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 111. The barrier layer can prevent or minimize the penetration of impurities from the substrate 100 and the like into the semiconductor layer A.

[0453] A semiconductor layer A may be disposed on the buffer layer 111. The semiconductor layer A may comprise an oxide semiconductor material. For example, the semiconductor layer A may comprise an oxide of one or more materials selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0454] As an example, semiconductor layer A can be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc.

[0455] Semiconductor layer A may include a channel region C and a source region S and a drain region D disposed on one side and the other side of the channel region C, respectively. Semiconductor layer A may be composed of a single layer or multiple layers.

[0456] A conductive layer BML may be disposed between the substrate 100 and the buffer layer 111. The conductive layer BML may be configured to overlap with the channel region C of the semiconductor layer A. The conductive layer BML may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer containing said material. As an example, the conductive layer BML may be formed in a Ti / Al / Ti multilayer structure.

[0457] The conductive layer BML can be configured to overlap with the semiconductor layer A containing an oxide semiconductor material. The semiconductor layer A containing the oxide semiconductor material has the characteristic of being less susceptible to light; therefore, the conductive layer BML can prevent changes in the device characteristics of the thin-film transistor (TFT) containing the oxide semiconductor material from being induced by external light incident from the substrate 100 side. Additionally, the conductive layer BML can be connected to the drain region D. Although in Figure 20a The diagram shows the conductive layer BML connected to the drain region D, but the conductive layer BML can also be connected to the source region S.

[0458] A gate insulating layer 113 may be disposed on semiconductor layer A. The gate insulating layer 113 may comprise silicon oxide (SiO2) or silicon nitride (SiN). X Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) are included.

[0459] like Figure 20a As shown, the gate insulating layer 113 can be patterned to overlap a portion of the semiconductor layer A. That is, the gate insulating layer 113 can be patterned to expose the source region S and the drain region D.

[0460] The region where the gate insulating layer 113 overlaps with the semiconductor layer A can be understood as the channel region C. After the source region S and drain region D undergo a conductor-enhancing process using plasma treatment or the like, the portion of the semiconductor layer A that overlaps with the gate insulating layer 113 (i.e., the channel region C) is not exposed to plasma treatment and thus has properties different from the source region S and drain region D. Specifically, it is possible to use the gate electrode G, which is located above the gate insulating layer 113 during plasma treatment of the semiconductor layer A, as a self-aligning mask to form the untreated channel region C at the location overlapping with the gate insulating layer 113, and to form the plasma-treated source region S and drain region D on either side of the channel region C, respectively.

[0461] In another embodiment, the gate insulating layer 113 may not be patterned to overlap a portion of the semiconductor layer A, and may be disposed on the entire surface of the substrate 100 to cover the semiconductor layer A.

[0462] A gate electrode G may be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer A. Additionally, a first electrode CE1 of the storage capacitor Cst and an auxiliary pad electrode SPE may be disposed on the gate insulating layer 113.

[0463] In one embodiment, the storage capacitor Cst can be configured with a first electrode CE1 and a second electrode CE2, and as follows: Figure 20a As shown, it exists independently without overlapping with the thin-film transistor (TFT). In contrast, the storage capacitor Cst can overlap with the TFT. For example, the gate electrode G of the TFT can function as the first electrode CE1 of the storage capacitor Cst.

[0464] It may have an interlayer insulating layer 115 to cover the semiconductor layer A, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE.

[0465] An electrode layer E, a second electrode CE2 of a storage capacitor Cst, and a pad electrode PE can be disposed above the interlayer insulating layer 115. The electrode layer E can be a source electrode, a drain electrode, a data line, etc.

[0466] The electrode layer E can be connected to the source region S or drain region D of the semiconductor layer A through contact holes. In addition, the conductive layer BML and the source region S or drain region D of the semiconductor layer A can be connected through contact holes formed in the buffer layer 111 and the interlayer insulating layer 115.

[0467] The second electrode CE2 of the storage capacitor Cst overlaps with the first electrode CE1 by placing the interlayer insulating layer 115 between them, thus forming a capacitor. In this case, the interlayer insulating layer 115 can function as the dielectric layer of the storage capacitor Cst.

[0468] The pad electrode PE can be connected to the auxiliary pad electrode SPE through contact holes formed in the interlayer insulating layer 115. Figure 20a The diagram shows three contact holes connecting the PE pad electrode and the SPE auxiliary pad electrode, but there could be more or fewer. Additionally, in... Figure 20a The auxiliary pad electrode SPE is shown, but the auxiliary pad electrode SPE can be omitted.

[0469] It is possible that an electrode protection layer EPL is configured on the electrode layer E and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL is configured on the pad electrode PE.

[0470] The electrode protective layer (EPL) and the pad protective layer (PPL) may be selected from one or more materials selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0471] The electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE can be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Therefore, separate masks are not required for patterning the electrode protection layer EPL and the pad protection layer PPL, thus reducing the number of masks.

[0472] The pad electrode PE and the pad protector layer PPL can be patterned together, so the sides of the pad electrode PE and the sides of the pad protector layer PPL can be aligned. The pad electrode PE and the pad protector layer PPL can be formed simultaneously using the same etching process and can include the same etched surface. The sides of the pad electrode PE and the sides of the pad protector layer PPL can be located on the same etched surface. Although the pad electrode PE and the pad protector layer PPL are illustrated as an example, the electrode layer E and the electrode protector layer EPL, and the second electrode CE2 of the storage capacitor Cst and the electrode protector layer EPL can also be applied in the same way.

[0473] The electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE can be covered with an inorganic insulating layer (hereinafter, inorganic protective layer) PVX. The inorganic protective layer PVX can be an inorganic insulating film formed from inorganic materials. As inorganic materials, polysiloxanes, silicon nitride, silicon oxide, silicon oxynitride, etc., can be used. Alternatively, the inorganic protective layer PVX can be silicon nitride (SiN). X ) and silicon dioxide (SiO) X It can be a single-layer or multi-layer film. The inorganic protective layer PVX can be used to cover and protect a portion of the wiring disposed on the interlayer insulation layer 115.

[0474] The inorganic protective layer PVX may include: a first contact hole CNT1 for connecting the thin-film transistor TFT and the pixel electrode 310; and an opening OP for exposing the pad portion PAD.

[0475] The width W1 of the pad portion PAD along one direction can be the same as the width W2 of the opening OP. Specifically, the width W1 of the pad protectant layer PPL along one direction can be the same as the width W2 of the opening OP. The top of the pad protectant layer PPL can be exposed through the opening OP formed in the inorganic protectant layer PVX. For example... Figure 20a As shown, the entire top of the pad protection layer PPL can be exposed through the opening OP.

[0476] As in Figure 1 As described, the pad portion (PAD) can be attached to a printed circuit board or a driver IC chip. In this case, the contact width between the pad portion (PAD) and the printed circuit board or driver IC chip can be varied according to the size of the opening (OP) formed in the inorganic protective layer (PVX). Figure 20a As shown, when the pad protective layer PPL is fully exposed through the opening OP, the contact area between the pad portion PAD and the printed circuit board or driver IC chip can be maximized. Therefore, poor contact between the pad portion PAD and the printed circuit board or driver IC chip can be reduced, and the risk of malfunctions during the driving of the display device 1 can be decreased.

[0477] The planarization layer 117 is configured to cover the electrode layer E and the second electrode CE2 of the storage capacitor Cst. The planarization layer 117 includes a second contact hole for connecting the thin film transistor TFT and the pixel electrode 310.

[0478] The planarization layer 117 can be formed from a single layer or multiple layers of a film made of an organic substance, providing a flat top surface. The planarization layer 117 can be configured to expose the pad portion (PAD). That is, the planarization layer 117 may not be disposed in the peripheral area (PA) and may not overlap with the pad portion (PAD).

[0479] As a comparative example, the planarization layer may remain and be disposed in the peripheral area of ​​the display panel. In this case, the residual planarization layer in the peripheral area of ​​the display panel may act as a moisture permeation path from the outside, posing a risk of reliability problems such as degradation of the light-emitting elements.

[0480] A light-emitting element 300 is disposed on the planarization layer 117. The light-emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light-emitting layer, and a counter electrode 330.

[0481] A pixel defining film 119 may be disposed on the planarization layer 117. The pixel defining film 119 may cover the edge of the pixel electrode 310 and have an opening that exposes a portion of the pixel electrode 310. In addition, the pixel defining film 119 can prevent the generation of electric arcs or the like at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

[0482] In one embodiment, such as Figure 20a As shown, the planarization layer 117 and the pixel defining film 119 can have the same etched surface s. (As in...) Figure 22i as well as Figure 22j As described later, the planarization layer 117 and the pixel defining film 119 can be formed simultaneously by the same etching process and can include the same etched surface s.

[0483] The side surfaces of the planarization layer 117 adjacent to the peripheral region PA and the outer surface surfaces of the pixel defining film 119 can be located on the same etched surface s. In other words, the side surfaces of the planarization layer 117 adjacent to the peripheral region PA and the outer surface surfaces of the pixel defining film 119 can be located on the same surface. Furthermore, the side surfaces of the planarization layer 117 adjacent to the peripheral region PA and the outer surface surfaces of the pixel defining film 119 can be formed without steps and without boundaries. The side surfaces of the planarization layer 117 adjacent to the peripheral region PA and the outer surface surfaces of the pixel defining film 119 can be aligned.

[0484] The intermediate layer 320 may be disposed within an opening formed by the pixel defining film 119 and includes an organic light-emitting layer.

[0485] The counter electrode 330 can be a semi-transparent electrode or a reflective electrode. In some embodiments, the counter electrode 330 can be a transparent or semi-transparent electrode and can be formed using a metal thin film with a low work function containing Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 can be disposed on top of the metal thin film. The counter electrode 330 can be disposed across the display area DA and above the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 can be integrally formed among multiple light-emitting elements 300 to correspond to multiple pixel electrodes 310.

[0486] Such organic light-emitting elements are easily damaged by external factors such as moisture or oxygen, therefore, in Figure 24 As described later, the thin-film encapsulation layer 400 can cover and protect the organic light-emitting elements. The thin-film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0487] Figure 20b as well as Figure 21 This is a simplified cross-sectional view illustrating a display device according to an embodiment of the present invention. Figure 20b as well as Figure 21 In, with Figure 20aThe same reference numerals refer to the same parts, and repeated descriptions of them are omitted. Figure 20b As Figure 20a The modified embodiments differ in the structure of the planarization layer 117. Additionally, Figure 21 As Figure 20a The modified embodiments differ in the structure of the inorganic protective layer PVX. Hereinafter, repeated content will be used... Figure 20a Instead of using descriptive terms, the explanation will focus on the key differences.

[0488] Reference Figure 20b The planarization layer 117 may include a first portion 117a disposed on the thin-film transistor TFT and a second portion 117b extending from the first portion 117a toward the peripheral region PA side. In this case, the top surface of the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b.

[0489] The vertical distance d1 from the top of the substrate 100 to the top of the first portion 117a and the vertical distance d2 from the top of the substrate 100 to the top of the second portion 117b can be different. For example, ... Figure 20b As shown, the vertical distance d1 from the top of the substrate 100 to the top of the first portion 117a can be greater than the vertical distance d2 from the top of the substrate 100 to the top of the second portion 117b.

[0490] The first portion 117a of the planarization layer 117 and the pixel defining film 119 can have the same etched surface. For example... Figure 23c As described later in 23d, the first portion 117a of the planarization layer 117 and the pixel defining film 119 can be formed simultaneously by the same etching process and may include the same etched surface.

[0491] The side surface of the first portion 117a of the planarization layer 117 adjacent to the peripheral region PA and the outer surface of the pixel defining film 119 can be located on the same etched surface. In other words, the side surface of the first portion 117a of the planarization layer 117 adjacent to the peripheral region PA and the outer surface of the pixel defining film 119 can be located on the same surface. Furthermore, the side surface of the first portion 117a of the planarization layer 117 adjacent to the peripheral region PA and the outer surface of the pixel defining film 119 can be formed without steps and without boundaries. The side surface of the first portion 117a of the planarization layer 117 adjacent to the peripheral region PA and the outer surface of the pixel defining film 119 can be aligned.

[0492] Reference Figure 21 The width W1 of the pad portion PAD along one direction can be smaller than the width W3 of the opening OP. Specifically, the width W1 of the pad protector layer PPL along one direction can be smaller than the width W3 of the opening OP.

[0493] The top and sides of the pad protective layer PPL can be exposed through openings OP formed in the inorganic protective layer PVX. For example... Figure 21 As shown, the top and sides of the pad protector layer PPL can be fully exposed through the opening OP. Additionally, the sides of the pad electrode PE can be partially exposed through the opening OP.

[0494] As in Figure 1 As described, the pad portion (PAD) can be attached to a printed circuit board or a driver IC chip. In this case, the contact width between the pad portion (PAD) and the printed circuit board or driver IC chip can be varied according to the size of the opening (OP) formed in the inorganic protective layer (PVX). Figure 21 As shown, when the top and sides of the pad protective layer PPL are fully exposed through the opening OP, the contact area between the pad portion PAD and the printed circuit board or driver IC chip can be maximized. Therefore, poor contact between the pad portion PAD and the printed circuit board or driver IC chip can be reduced, and the risk of malfunctions during the driving of the display device 1 can be decreased.

[0495] So far, only the display device has been described in detail, but the present invention is not limited thereto. For example, the method for manufacturing such a display device also falls within the scope of the present invention.

[0496] Figures 22a to 22j These are cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figures 22a to 22j In, with Figure 20a The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0497] Reference Figure 22a First, a conductive layer BML, a buffer layer 111, a semiconductor layer A, a gate insulating layer 113, a gate electrode G, a first electrode CE1 and a second electrode CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protection layer PVX are sequentially formed on a substrate 100.

[0498] The conductive layer BML can be formed by patterning a pre-conductive layer (not shown). The pre-conductive layer may contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or a single layer containing said material.

[0499] Buffer layer 111 can be made of silicon oxide (SiO2) or silicon nitride (SiN). XIt can be set up and formed by vapor deposition methods such as chemical vapor deposition (CVD) and sputtering.

[0500] A semiconductor layer A may be disposed on the buffer layer 111. The semiconductor layer A may be formed by patterning a pre-semiconductor layer (not shown). The pre-semiconductor layer may be formed using an oxide semiconductor and may be deposited by chemical vapor deposition.

[0501] Alternatively, a gate insulating layer 113 and a gate electrode G may be disposed on a semiconductor layer A, and a gate insulating layer 113, a first electrode CE1 of a storage capacitor Cst, and an auxiliary pad electrode SPE may be disposed on a buffer layer 111.

[0502] The gate insulating layer 113, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE can be formed by patterning the pre-gate insulating layer (not shown) and the pre-metal layer (not shown).

[0503] The pre-gate insulating layer can be made of silicon oxide (SiO2) or silicon nitride (SiN). X It can be made of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), and can be formed by vapor deposition methods such as chemical vapor deposition (CVD) and sputtering, and is not limited to these.

[0504] The preparation - metal layer can be formed in single or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). It can be formed by vapor deposition methods such as chemical vapor deposition, plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and is not limited to these methods.

[0505] During the patterning of the pre-gate insulating layer, plasma processing is performed, and a portion of the semiconductor layer A that is exposed and does not overlap with the gate electrode G undergoes a conductive process using plasma processing. As a result, the source region S and drain region D exposed during plasma processing become conductive, and the channel region C that overlaps with the gate electrode G has different properties from the source region S and drain region D.

[0506] An interlayer insulating layer 115 is formed on the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. After forming the interlayer insulating layer 115, contact holes are formed that penetrate the interlayer insulating layer 115 and expose a portion of the conductive layer BML, the semiconductor layer A, and the auxiliary pad electrode SPE, respectively.

[0507] An electrode layer E, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE are formed on the interlayer insulating layer 115. Additionally, an electrode protection layer EPL and a pad protection layer PPL are formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE.

[0508] Electrode layer E, the second electrode CE2 of storage capacitor Cst, pad electrode PE, electrode protective layer EPL, and pad protective layer PPL can be integrally deposited on interlayer insulating layer 115 by sequentially vapor-depositing a pre-electrode layer (not shown) and a pre-protective layer (not shown), and formed by masking and etching processes. That is, electrode layer E, the second electrode CE2 of storage capacitor Cst, and pad electrode PE can be patterned together with electrode protective layer EPL and pad protective layer PPL. Therefore, a separate mask is not required for patterning electrode protective layer EPL and pad protective layer PPL, thus reducing the number of masks.

[0509] An inorganic protective layer PVX is formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The inorganic protective layer PVX can be an inorganic insulating film formed from inorganic materials, and can be formed by vapor deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and is not limited to these methods.

[0510] Reference Figure 22bA planarization layer 117' can be disposed on the inorganic protective layer PVX. A first mask M1 can be disposed on the planarization layer 117'. The first mask M1 can adjust the amount of light exposure applied to the planarization layer 117' for each region. For example, the fourth region AR4 of the first mask M1 can be adjusted to a smaller amount of light exposure applied to the planarization layer 117' compared to the second region AR2 of the first mask M1. As an example, the first mask M1 can be a half-tone mask or a slit mask. In some embodiments, the first region AR1 and the third region AR3 of the first mask M1 can be masked to prevent exposure of the planarization layer 117'.

[0511] The planarization material layer 117' can be exposed using a first mask M1 with different exposure amounts for each region, and a portion of the planarization material layer 117' can be removed by a developing process. The amount of planarization material layer 117' removed varies depending on the exposure amount, thus a pre-insulating layer (hereinafter, pre-planarization layer) 117p with different thicknesses for each region can be formed in one step.

[0512] Reference Figure 22c The pre-planarization layer 117p may include a first pre-planarization layer 117pa corresponding to the display area DA and a second pre-planarization layer 117pb corresponding to the peripheral area PA. The thickness of the first pre-planarization layer 117pa may be greater than the thickness of the second pre-planarization layer 117pb.

[0513] After removing a portion of the planarization material layer 117' to form a pre-planarization layer 117p, a curing and drying process for the pre-planarization layer 117p can be performed. The curing and drying process of the pre-planarization layer 117p can increase its adhesion to the inorganic protective layer PVX. At this time, the curing and drying process may include a heat treatment process.

[0514] exist Figure 22b The planarization layer 117' is given as an example of containing positive photoresist, but the planarization layer 117' may also contain negative photoresist. In this case, contrary to when the planarization layer 117' contains positive photoresist, the more exposure applied to the planarization layer 117', the thicker the remaining pre-planarization layer 117p will be after the development process.

[0515] Reference Figure 22c as well as Figure 22dUsing a patterned pre-planarization layer 117p, contact holes (CNTs) are formed on the inorganic protective layer PVX to partially expose the electrode layer E. The contact holes (CNTs) are formed through an etching process that partially etches the inorganic protective layer PVX. As an example, the etching process for partially etching the inorganic protective layer PVX can be dry etching. Although in Figure 22d It is not shown in the figure, but a portion of the pre-planarization layer 117p can also be removed together to reduce the overall thickness of the pre-planarization layer 117p.

[0516] Reference Figure 22e A pixel electrode material layer 310' and a photoresist layer PR' are sequentially formed on the pre-planarization layer 117p.

[0517] The photoresist layer PR' may contain positive photoresist, and the photoresist layer PR' can be formed by applying positive photoresist liquid (not shown) onto the pixel electrode material layer 310' by various methods such as spin-coating, spraying or dipping.

[0518] A second mask M2 can be disposed on the photoresist layer PR'. The second mask M2 can adjust the exposure amount applied to the photoresist layer PR' according to each region. For example, the second region AR2 of the second mask M2 can be masked to prevent exposure of the photoresist layer PR'. The first region AR1 and the third region AR3 of the second mask M2 can be left unmasked to expose the photoresist layer PR'.

[0519] The photoresist layer PR' corresponding to the first region AR1 and the third region AR3 can be exposed through the second mask M2, and a portion of the photoresist layer PR' can be removed through a development process, such as... Figure 22f As shown, a photoresist pattern PR can be formed.

[0520] exist Figure 22e The example given is that the photoresist layer PR' contains positive photoresist, but the photoresist layer PR' can also contain negative photoresist. In this case, contrary to when the photoresist layer PR' contains positive photoresist, the unexposed portion of the photoresist layer PR' corresponds to the portion removed after the development process.

[0521] Reference Figure 22f as well as Figure 22g The pixel electrode 310 is formed by etching the pixel electrode material layer 310' using a photoresist pattern PR formed on the pixel electrode material layer 310'. That is, the pixel electrode 310 can be formed by vapor deposition of the pixel electrode material layer 310' and by a masking process and an etching process. As an example, the etching process can be wet etching.

[0522] Contact holes for partially exposed electrode layers E are formed in the pre-planarization layer 117p and the inorganic protective layer PVX. The pixel electrode 310 can be electrically connected to the thin-film transistor TFT through the contact holes.

[0523] As a comparative example, when forming contact holes that electrically connect pixel electrodes and thin-film transistors, openings that partially expose the pad portion can be formed. After forming the openings, wet etching for forming the pixel electrodes can be performed. In this case, the pad portion exposed through the openings is affected by the wet etching, and a portion of the pad portion surface may crack or form a fine seam. A portion of the pad portion surface may be damaged. In the case of fine cracks on the pad portion surface, the copper (Cu) and other materials constituting the pad portion may erode, potentially leading to poor contact at the pad portion.

[0524] However, as Figure 22f As shown, during the etching process for forming the pixel electrode 310, the pad protection layer PPL and the pad electrode PE are protected by the pre-planarization layer 117p, thus safely protecting the surface of the pad portion PAD. Therefore, poor contact of the pad portion PAD can be improved. Furthermore, since the pad protection layer PPL and the pad electrode PE are protected by the pre-planarization layer 117p, the pad portion PAD can be protected regardless of whether the etching process for forming the pixel electrode 310 is performed in one, two, or only one step.

[0525] Reference Figure 22g After forming the pixel electrode 310, a pixel defining film material layer 119' is formed above the pixel electrode 310 and the pre-planarization layer 117p. The pixel defining film material layer 119' may contain positive photoresist, and the pixel defining film material layer 119' can be formed by applying positive photoresist solution to the pixel electrode 310 and the pre-planarization layer 117p by various methods such as spin-coating, spraying, or dipping.

[0526] A third mask M3 can be disposed on the pixel-defining film material layer 119'. The third mask M3 can adjust the exposure applied to the pixel-defining film material layer 119' for each region. For example, compared to the fifth region AR5 of the third mask M3, the second region AR2, the fourth region AR4, and the sixth region AR6 of the third mask M3 can adjust the exposure applied to the pixel-defining film material layer 119' to be smaller. As an example, the third mask M3 can be a half-tone mask or a slit mask. In some embodiments, the first region AR1 and the third region AR3 of the third mask M3 can be masked to prevent exposure of the pixel-defining film material layer 119'.

[0527] The pixel defining film material layer 119' can be exposed using a third mask M3 with different exposure levels for each region, and a portion of the pixel defining film material layer 119' can be removed using a development process. The amount of pixel defining film material layer 119' removed varies depending on the exposure level, thus allowing a pre-pixel defining film 119p with different thicknesses for each region to be formed in a single step.

[0528] For example, such as Figure 22h As shown, the pre-pixel defining film 119p may include: a first pre-pixel defining film 119pa; a second pre-pixel defining film 119pb, surrounded by the first pre-pixel defining film 119pa; and a third pre-pixel defining film 119pc, corresponding to the surrounding area PA.

[0529] At this point, the second pre-pixel defining film 119pb can serve to protect the surface of the pixel electrode 310 in subsequent processes. Alternatively, the second pre-pixel defining film 119pb can be omitted. The second region AR2 of the third mask M3 is opened and the maximum exposure is applied to the pixel defining film material layer 119', so that the pixel defining film material layer 119' corresponding to the second region AR2 of the third mask M3 can be completely removed.

[0530] The first pre-pixel defining film 119pa corresponds to the portion of the pixel defining film material layer 119' that is not exposed and is not removed by the first region AR1 and the third region AR3 of the third mask M3. The second pre-pixel defining film 119pb corresponds to the portion of the pixel defining film material layer 119' that is partially removed by applying an adjusted exposure amount through the second region AR2 of the third mask M3. The third pre-pixel defining film 119pc corresponds to the portion of the pixel defining film material layer 119' that is partially removed by applying an adjusted exposure amount through the fourth region AR4 and the sixth region AR6 of the third mask M3.

[0531] The thickness of the first pre-pixel defining film 119pa can be greater than the thickness of the second pre-pixel defining film 119pb. The thickness of the first pre-pixel defining film 119pa can be greater than the thickness of the third pre-pixel defining film 119pc. The thicknesses of the second pre-pixel defining film 119pb and the third pre-pixel defining film 119pc can be the same or different. For example, ... Figure 22h As shown, the thickness of the third pre-pixel defining film 119pc can be thicker than the thickness of the second pre-pixel defining film 119pb.

[0532] The pre-pixel defining film 119p may have a first opening OP1 corresponding to the pad portion PAD. The first opening OP1 is equivalent to applying maximum exposure to the pixel defining film material layer 119' through the fifth region AR5 of the third mask M3, thereby removing all of the pixel defining film material layer 119'.

[0533] exist Figure 22g The example given is that the pixel defining film material layer 119' contains positive photoresist, but the pixel defining film material layer 119' may also contain negative photoresist. In this case, contrary to the case where the pixel defining film material layer 119' contains positive photoresist, the more exposure applied to the pixel defining film material layer 119', the thicker the pixel defining film material layer 119' remains after the development process.

[0534] Reference Figure 22h as well as Figure 22i Using a patterned pre-pixel defining film 119p, a second opening OP2 and a third opening OP3 are formed on the pre-planarization layer 117p and the inorganic protective layer PVX, respectively, to expose the pad portion PAD. The second opening OP2 and the third opening OP3 are formed by a partial etching process of the pre-planarization layer 117p and the inorganic protective layer PVX. As an example, the partial etching process of the pre-planarization layer 117p and the inorganic protective layer PVX can be dry etching. Although in Figure 22i It is not shown in the figure, but a portion of the pre-pixel defining film 119p can also be removed together to reduce the overall thickness of the pre-pixel defining film 119p.

[0535] Reference Figure 22i as well as Figure 22j An etching process is performed to remove the second pre-pixel defining film 119pb, the third pre-pixel defining film 119pc, and the second pre-planarization layer 117pb. As an example, the etching process can be dry etching.

[0536] The second pre-planarization layer 117pb can be removed from the pre-planarization layer 117p to form the planarization layer 117.

[0537] A pixel defining film 119 can be formed by removing the second pre-pixel defining film 119p and the third pre-pixel defining film 119pc. A portion of the pixel electrode 310 can be exposed by removing the second pre-pixel defining film 119p. The pixel defining film 119 may have an opening that exposes a portion of the pixel electrode 310.

[0538] When performing an etching process to remove the second pre-pixel defining film 119pb, the third pre-pixel defining film 119pc, and the second pre-planarization layer 117pb, a portion of the first pre-pixel defining film 119pa and a portion of the first pre-planarization layer 117pa can also be etched together. For example, as Figure 22i As shown, a portion of the first pre-pixel defining film 119pa and a portion of the first pre-planarization layer 117pa located on the peripheral region PA side of the virtual surface s' can be etched together.

[0539] like Figure 22j As shown, the planarization layer 117 and the pixel defining film 119 can have the same etched surface s. The outer side of the pixel defining film 119 adjacent to the peripheral region PA and the side of the planarization layer 117 can be located on the same etched surface s. Here, the same etched surface s can correspond to... Figure 22i The aforementioned virtual surface s'.

[0540] On the other hand, such as Figure 22i As shown, the planarization layer 117 is formed using the pre-defined pixel boundary film 119p as an etching mask, therefore the planar shape of the planarization layer 117 substantially corresponds to the planar shape of the pixel boundary film 119. Furthermore, as... Figure 22j As shown, the sidewalls of the planarization layer 117 and the pixel defining film 119, which are adjacent to the surrounding area PA, also correspond to each other.

[0541] Reference Figure 22j An intermediate layer 320 is formed on the pixel electrode 310, that is, inside the opening of the pixel defining film 119. The intermediate layer 320 may contain a low molecular weight or polymer material. The intermediate layer 320 may be formed by vacuum evaporation, screen printing or inkjet printing, laser induced thermal imaging (LITI), etc.

[0542] The intermediate layer 320 of the light-emitting element 300 may include an organic light-emitting layer. The organic light-emitting layer may contain an organic material that emits fluorescent or phosphorescent substances that emit red, green, blue, or white light.

[0543] Subsequently, counter electrodes 330 are formed to correspond to the plurality of light-emitting elements 300. The counter electrodes 330 can be formed by an opening mask to cover the display area DA of the substrate 100. The counter electrodes 330 can be formed by vapor deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD).

[0544] Figures 23a to 23d These are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention. Figures 23a to 23d As Figures 22g to 22j The modified embodiments differ in the structure of the planarization layer 117. Hereinafter, repeated content will be used... Figures 22g to 22j Instead of using descriptive terms, the explanation will focus on the key differences.

[0545] Reference Figure 23a After forming the pixel electrode 310, a pixel defining film material layer 119' is formed above the pixel electrode 310 and the pre-planarization layer 117p. The pixel defining film material layer 119' may contain positive photoresist, and the pixel defining film material layer 119' can be formed by applying positive photoresist solution to the pixel electrode 310 and the pre-planarization layer 117p by various methods such as spin-coating, spraying, or dipping.

[0546] A fourth mask M4 can be disposed on the pixel-defining film material layer 119'. The fourth mask M4 can adjust the exposure applied to the pixel-defining film material layer 119' according to each region. As an example, the fourth mask M4 can be a half-tone mask or a slit mask. In some embodiments, the first region AR1 and the third region AR3 of the fourth mask M4 can be masked to prevent exposure of the pixel-defining film material layer 119'.

[0547] The pixel defining film material layer 119' can be exposed using a fourth mask M4 with different exposure levels for each region, and a portion of the pixel defining film material layer 119' can be removed using a development process. The amount of pixel defining film material layer 119' removed varies depending on the exposure level, thus allowing a pre-pixel defining film 119p with different thicknesses for each region to be formed in a single step.

[0548] For example, such as Figure 23bAs shown, the pre-pixel defining film 119p may include: a first pre-pixel defining film 119pa; a second pre-pixel defining film 119pb, surrounded by the first pre-pixel defining film 119pa; and a third pre-pixel defining film 119pc, corresponding to the surrounding area PA.

[0549] The thickness of the first pre-pixel defining film 119pa can be greater than the thickness of the second pre-pixel defining film 119pb. The thickness of the first pre-pixel defining film 119pa can be greater than the thickness of the third pre-pixel defining film 119pc. The thicknesses of the second pre-pixel defining film 119pb and the third pre-pixel defining film 119pc can be the same or different. For example, ... Figure 23b As shown, the thickness of the third pre-pixel defining film 119pc can be thicker than the thickness of the second pre-pixel defining film 119pb.

[0550] A step ST' can be formed at the boundary between the first pre-pixel defining film 119pa and the third pre-pixel defining film 119pc. By preparing the planarization layer 117p, the distance from the top surface of the substrate 100 to the top surface of the first pre-pixel defining film 119pa can be different from the distance from the top surface of the substrate 100 to the top surface of the third pre-pixel defining film 119pc, and a step ST' can be formed between the first pre-pixel defining film 119pa and the third pre-pixel defining film 119pc.

[0551] Reference Figure 23b as well as Figure 23c Using a patterned pre-pixel defining film 119p, a second opening OP2 and a third opening OP3 are formed on the pre-planarization layer 117p and the inorganic protective layer PVX, respectively, to expose the pad portion PAD. The second opening OP2 and the third opening OP3 are formed by a partial etching process of the pre-planarization layer 117p and the inorganic protective layer PVX. As an example, the partial etching process of the pre-planarization layer 117p and the inorganic protective layer PVX can be dry etching. Although in Figure 23c It is not shown in the figure, but a portion of the pre-pixel defining film 119p can also be removed together to reduce the overall thickness of the pre-pixel defining film 119p.

[0552] Reference Figure 23c as well as Figure 23d An etching process is performed to remove the second pre-pixel defining film 119pb, the third pre-pixel defining film 119pc, and the second pre-planarization layer 117pb. As an example, the etching process can be dry etching.

[0553] When performing an etching process to remove the second pre-pixel defining film 119pb, the third pre-pixel defining film 119pc, and the second pre-planarization layer 117pb, a portion of the first pre-pixel defining film 119pa and a portion of the first pre-planarization layer 117pa may also be etched together.

[0554] like Figure 23d As shown, the planarization layer 117 includes a first portion 117a disposed on the thin-film transistor TFT and a second portion 117b extending from the first portion 117a toward the peripheral region PA side. In this case, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b on its upper surface.

[0555] The first portion 117a of the planarization layer 117 and the pixel defining film 119 may have the same etched surface. The outer side of the pixel defining film 119 adjacent to the peripheral region PA and the side of the first portion 117a of the planarization layer 117 may be aligned.

[0556] Reference Figure 23d An intermediate layer 320 is formed on the pixel electrode 310, specifically inside the opening of the pixel defining film 119. The intermediate layer 320 of the light-emitting element 300 may include an organic light-emitting layer. Subsequently, a counter electrode 330 is formed to correspond to the plurality of light-emitting elements 300. The counter electrode 330 may be formed by an opening mask to cover the display area DA of the substrate 100.

[0557] Figure 24 This is a simplified cross-sectional view illustrating a display device according to an embodiment of the present invention. Figure 24 In, with Figure 20a The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0558] Reference Figure 24 In a display device 1 according to an embodiment of the present invention (refer to...) Figure 1 The display area DA can be configured with at least one thin-film transistor TFT and a display element connected to the thin-film transistor TFT.

[0559] The display area DA of display device 1 includes first to third pixels PX1, PX2, and PX3. Of course, this is exemplary; display device 1 can have more pixels. Furthermore, in Figure 24 The diagram shows that the first to third pixels PX1, PX2, and PX3 are adjacent to each other, but the invention is not limited to this. That is, other wiring or other structural elements may be present between the first to third pixels PX1, PX2, and PX3. Therefore, for example, the first pixel PX1 and the second pixel PX2 may not be pixels arranged adjacent to each other. Furthermore, in... Figure 24The cross sections of the first to third pixels PX1, PX2, and PX3 do not have to be cross sections in the same direction.

[0560] The first to third pixels PX1, PX2, and PX3 each include a light-emitting region EA. The light-emitting region EA can be a region that generates light and emits it outwards. Alternatively, a non-light-emitting region NEA can be disposed between the light-emitting regions EA, with the light-emitting regions EA divided by the non-light-emitting regions NEA.

[0561] The first to third pixels, PX1, PX2, and PX3, can emit different colors. For example, the first pixel PX1 can emit red light, the second pixel PX2 can emit green light, and the third pixel PX3 can emit blue light. When viewed on a plane, the emitting area EA can be in various polygonal or circular shapes, and can be arranged in various patterns such as stripes or five-square grids.

[0562] On the other hand, the display device 1 may have a first quantum dot layer 220a, a second quantum dot layer 220b, and a transmissive layer 220c corresponding to the light-emitting region EA. The first quantum dot layer 220a, the second quantum dot layer 220b, and the transmissive layer 220c may include quantum dots and metal nanoparticles.

[0563] For example, the first pixel PX1 may include a first quantum dot layer 220a, the second pixel PX2 may include a second quantum dot layer 220b, and the third pixel PX3 may include a transmissive layer 220c.

[0564] In this embodiment, the average size of the quantum dots included in the first quantum dot layer 220a and the second quantum dot layer 220b may be different from each other.

[0565] Hereinafter, a display device 1 according to an embodiment of the present invention will be described. Figure 24 The stacking order shown will be explained in detail.

[0566] The substrate 100 (hereinafter referred to as the lower substrate) may comprise a glass material, a ceramic material, a metallic material, or a material with flexible or bendable properties. A barrier layer (not shown) may also be included between the lower substrate 100 and the buffer layer 111.

[0567] Alternatively, a conductive layer BML may be disposed on the lower substrate 100, and a semiconductor layer A may be disposed on the buffer layer 111. On the semiconductor layer A, the gate electrode G may be configured such that a gate insulating layer 113 is placed between it and at least partially overlaps with the semiconductor layer A.

[0568] An interlayer insulating layer 115 can be provided to cover the gate electrode G. An active electrode and a drain electrode, etc., can be disposed above the interlayer insulating layer 115.

[0569] Alternatively, a planarization layer 117 may be disposed on the source electrode and the drain electrode, and first to third light-emitting elements 300a, 300b, and 300c may be disposed on the planarization layer 117. Each of the first to third light-emitting elements 300a, 300b, and 300c commonly includes a pixel electrode 310, an intermediate layer 320 including an organic light-emitting layer, and a counter electrode 330. A pixel defining film 119 may be disposed on the planarization layer 117.

[0570] The first to third light-emitting elements 300a, 300b, and 300c may be easily damaged by external moisture or oxygen, and therefore can be covered and protected by a thin-film encapsulation layer 400. The thin-film encapsulation layer 400 can cover the display area DA and extend beyond the display area DA. The thin-film encapsulation layer 400 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin-film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0571] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and includes silicon oxide, silicon nitride, and / or silicon trioxide, etc. Although not shown, other layers such as a capping layer may also be interposed between the first inorganic encapsulation layer 410 and the counter electrode 330 as needed. The first inorganic encapsulation layer 410 is formed along the structure below it, and therefore its surface is not flat. An organic encapsulation layer 420 may cover such a first inorganic encapsulation layer 410 and, unlike the first inorganic encapsulation layer 410, its surface is generally flat.

[0572] Even if cracks occur within the thin-film encapsulation layer 400, the aforementioned multilayer structure ensures that such cracks do not connect between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420, or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. This prevents or minimizes the formation of pathways that allow external moisture or oxygen to penetrate into the display area DA.

[0573] The upper substrate 200 is located above the lower substrate 100, and the counter electrode 330 is positioned between the upper substrate 200 and the lower substrate 100.

[0574] A light-shielding layer 230 is disposed on the underside of the upper substrate 200 in the direction of the lower substrate 100. The light-shielding layer 230 includes openings corresponding to the first to third light-emitting elements 300a, 300b, and 300c, respectively, and the first to third filter layers 210a, 210b, and 210c are respectively located within the openings. The light-shielding layer 230 serves as a black matrix and can be a layer used to enhance color vividness and contrast. The light-shielding layer 230 may contain at least one of black pigment, black dye, or black particles. In some embodiments, the light-shielding layer 230 may contain Cr or CrO.X Cr / CrO X Cr / CrO X / CrN Y Materials include resins (carbon pigments, RGB mixed pigments), graphite, and non-Cr-based materials.

[0575] Alternatively, the first filter layer 210a can allow only light with wavelengths between 630nm and 780nm to pass through, the second filter layer 210b can allow only light with wavelengths between 495nm and 570nm to pass through, and the third filter layer 210c can allow only light with wavelengths between 450nm and 495nm to pass through. The first to third filter layers 210a, 210b, and 210c can reduce external light reflection in the display device 1.

[0576] A first upper insulating layer 240 is disposed on the light-shielding layer 230. The first upper insulating layer 240 includes a first opening 241a corresponding to the first light-emitting element 300a, a first opening 241b corresponding to the second light-emitting element 300b, and a first opening 241c corresponding to the third light-emitting element 300c. A first quantum dot layer 220a is located within the first opening 241a, a second quantum dot layer 220b is located within the first opening 241b, and a transmissive layer 220c is located within the first opening 241c. The first quantum dot layer 220a and the second quantum dot layer 220b can be formed by inkjet printing.

[0577] The first upper insulating layer 240 may, for example, contain an organic material. Depending on the application, the first upper insulating layer 240 may contain a light-shielding material to function as a light-shielding layer. The light-shielding material may, for example, contain at least one of black pigment, black dye, black particles, or metal particles. In one embodiment, the first upper insulating layer 240 may be blue.

[0578] The first quantum dot layer 220a can convert light of a first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into light of a second wavelength band. For example, if light with a wavelength of 450 nm to 495 nm is generated from the intermediate layer 320 on the pixel electrode 310, the first quantum dot layer 220a can convert that light into light with a wavelength of 630 nm to 780 nm. Thus, in the first pixel PX1, light with a wavelength of 630 nm to 780 nm is emitted to the outside through the upper substrate 200.

[0579] The second quantum dot layer 220b can convert light of the first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into light of the third wavelength band. For example, if light with a wavelength of 450 nm to 495 nm is generated from the intermediate layer 320 on the pixel electrode 310, the second quantum dot layer 220b can convert this light into light with a wavelength of 495 nm to 570 nm. Thus, in the second pixel PX2, light with a wavelength of 495 nm to 570 nm is emitted to the outside through the upper substrate 200.

[0580] The first quantum dot layer 220a and the second quantum dot layer 220b can each have quantum dots dispersed within a resin. Quantum dots include semiconductor materials such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or indium phosphide (InP). The size of the quantum dots can be several nanometers, and the wavelength of the converted light varies depending on the size of the quantum dots. The resin containing the first quantum dot layer 220a and the second quantum dot layer 220b can be any transparent material. For example, polymer resins such as acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO) can be used as the materials for forming the first quantum dot layer 220a and the second quantum dot layer 220b.

[0581] In the third pixel PX3, light of the first wavelength generated from the intermediate layer 320 can be emitted outward without wavelength change. Therefore, the third pixel PX3 may not have a quantum dot layer. Thus, a quantum dot layer is not required within the first-third opening 241c, and a transmissive layer 220c formed of a light-transmitting resin can be configured. The transmissive layer 220c may contain acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). Of course, depending on the circumstances, it may also contain... Figure 24 Unlike the previous example, the transmission layer 220c is absent within the first-third opening 241c.

[0582] In this display device according to the present embodiment, a second band of light is emitted outward from the first pixel PX1, a third band of light is emitted outward from the second pixel PX2, and a first band of light is emitted outward from the third pixel PX3. Therefore, the display device 1 according to the present embodiment can display a full-color image.

[0583] A second upper insulating layer 250 is disposed on the first upper insulating layer 240. The second upper insulating layer 250 includes a second-1 opening 251a corresponding to the first-1 opening 241a, a second-2 opening 251b corresponding to the first-2 opening 241b, and a second-3 opening 251c corresponding to the first-3 opening 241c.

[0584] The first quantum dot layer 220a and the second quantum dot layer 220b, located within the first-1 opening 241a and the first-2 opening 241b respectively, can be formed by inkjet printing. The second-1 opening 251a and the second-2 opening 251b can be channels through which ink ejected from the nozzle falls during inkjet printing. The ink moving through the second upper insulating layer 250 including the second-1 opening 251a and the second-2 opening 251b can reach the first-1 opening 241a and the first-2 opening 241b respectively, forming the first quantum dot layer 220a and the second quantum dot layer 220b.

[0585] The second upper insulating layer 250 may contain a light-shielding material. For example, the light-shielding material may contain at least one of black pigment, black dye, black particles, or metal particles. Alternatively, in one embodiment, the second upper insulating layer 250 may be blue. As described above, the first upper insulating layer 240 may also contain a light-shielding material, but the materials constituting the first upper insulating layer 240 and the second upper insulating layer 250 may be different in order to form the first quantum dot layer 220a and the second quantum dot layer 220b by inkjet printing.

[0586] As an example, the second upper insulating layer 250, which is the channel through which ink travels via the nozzle during inkjet printing, may contain a substance that has no affinity for ink. Alternatively, the first upper insulating layer 240, which forms the first quantum dot layer 220a and the second quantum dot layer 220b by accumulating ink, may contain a substance that has an affinity for ink.

[0587] exist Figure 24 The first upper insulating layer 240 and the second upper insulating layer 250 are both shown in the diagram, but the second upper insulating layer 250 may be omitted, or only the first upper insulating layer 240 may be disposed on the upper substrate 200.

[0588] A filler 600 may be disposed between the lower substrate 100 and the upper substrate 200. The filler 600 can act as a buffer against external pressure. The filler 600 can be formed from organic substances such as methyl silicone, phenylsilicone, and polyimide. However, it is not limited to these; the filler 600 can also be formed from polyurethane resin, epoxy resin, acrylic resin as an organic sealant, or silicone as an inorganic sealant.

[0589] Figure 25 This is a simplified cross-sectional view illustrating a display device according to an embodiment of the present invention. Specifically, Figure 25 It is Figure 1 An exemplary cross-sectional view of the display device taken along I-I' and II-II'. Figure 25 In, with Figure 20a The same reference numerals refer to the same parts, and repeated descriptions of them are omitted.

[0590] Reference Figure 25 The display device 1 includes a display area DA and a peripheral area PA. The substrate 100 may have areas corresponding to the display area DA and the peripheral area PA.

[0591] Reference Figure 25 The display area DA can have a conductive layer BML, a thin-film transistor (TFT), and a light-emitting element 300 disposed on the substrate 100. Detailed information regarding this is available in [link to relevant documentation]. Figure 20a The text is described in the middle.

[0592] A thin-film encapsulation layer 400 may be disposed on the light-emitting element 300. The thin-film encapsulation layer 400 may be configured to cover the entire display area DA and extend towards the peripheral area PA to cover a portion of the peripheral area PA. The thin-film encapsulation layer 400 may extend to the outside of the common voltage supply line CVL.

[0593] The thin-film encapsulation layer 400 may include a first inorganic encapsulation layer 410, a second inorganic encapsulation layer 430, and an organic encapsulation layer 420 located between them.

[0594] A portion 330a of the counter electrode 330 may extend toward the peripheral region PA side and overlap with the common voltage supply line CVL. A connection wiring CL may be configured between the portion 330a of the counter electrode 330 and the common voltage supply line CVL. The connection wiring CL can electrically connect the common voltage supply line CVL and the counter electrode 330, so that the common voltage can be transmitted to the counter electrode 330.

[0595] Despite Figure 25 Although not shown, a drive circuit region is disposed on the peripheral region PA. For example, a gate drive circuit section may be disposed in the drive circuit region. The gate drive circuit section may include a thin-film transistor and include wiring connected to the thin-film transistor.

[0596] The buffer layer 111, the interlayer insulation layer 115, and the inorganic protective layer PVX can extend to the surrounding area PA.

[0597] A first dam section DAM1, a second dam section DAM2, and a mask support MS can be configured on the inorganic protective layer PVX corresponding to the surrounding area PA. The first dam section DAM1, the second dam section DAM2, and the mask support MS can be configured to surround the periphery of the display area DA in a plane. That is, the first dam section DAM1 can be configured to surround the periphery of the display area DA, the second dam section DAM2 can be configured to surround the periphery of the first dam section DAM1, and the mask support MS can be configured to surround the periphery of the second dam section DAM2.

[0598] The first dam section DAM1 and the second dam section DAM2 serve to prevent the organic encapsulation layer 420 of the thin-film encapsulation layer 400 from overflowing onto the outside of the substrate 100. The mask support MS serves to support the opening mask used when forming the counter electrode 330, etc.

[0599] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 in the thin-film encapsulation layer 400 can partially overlap with the first dam section DAM1 and the second dam section DAM2. This differs from other methods, such as... Figure 25 As shown, the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may not overlap with the mask support MS.

[0600] The first dam section DAM1, the second dam section DAM2, and the mask support MS can be configured with a double-layer structure. Each of the first dam section DAM1, the second dam section DAM2, and the mask support MS can include a first peripheral insulating layer 117s containing the same material as the planarization layer 117 and a second peripheral insulating layer 119s containing the same material as the pixel defining film 119. The first peripheral insulating layer 117s and the second peripheral insulating layer 119s forming the first dam section DAM1, the second dam section DAM2, and the mask support MS can be disposed on the same layer as the planarization layer 117 and the pixel defining film 119, respectively.

[0601] The first peripheral insulating layer 117s and the second peripheral insulating layer 119s can have the same etched surface. The side surfaces of the first peripheral insulating layer 117s and the second peripheral insulating layer 119s can be located on the same etched surface. In other words, the side surfaces of the first peripheral insulating layer 117s and the second peripheral insulating layer 119s can be aligned. The side surfaces of the first peripheral insulating layer 117s and the second peripheral insulating layer 119s can be located on the same surface. In other words, the side surfaces of the first peripheral insulating layer 117s and the second peripheral insulating layer 119s can be formed without steps and can be formed without boundaries.

[0602] The width of the mask support MS can be wider than the width of the first dam section DAM1. The width of the mask support MS can be wider than the width of the second dam section DAM2. As an example, the width of the mask support MS can be approximately 4 to 6 times the width of the first dam section DAM1.

[0603] The invention has been illustrated with reference to the embodiments shown in the accompanying drawings; however, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true scope of protection of the invention should be determined by the technical concept of the appended claims.

Claims

1. A display device, wherein, have: A substrate, including a display area and a peripheral area surrounding the display area; Thin-film transistors are disposed on the substrate corresponding to the display area; The pad portion is disposed on the substrate corresponding to the peripheral region; A first insulating layer includes a first portion disposed on the thin-film transistor and a second portion extending from the first portion, the first insulating layer exposing the pad portion; A second insulating layer is disposed in the peripheral region and contains the same material as the first insulating layer, and is disposed on the same layer as the first insulating layer; as well as A light-emitting element is disposed on the first portion of the first insulating layer and is electrically connected to the thin-film transistor. The first insulating layer has a step on its surface between the first portion and the second portion. The pad portion includes: a pad electrode; And a pad connection electrode, disposed on the pad electrode and in contact with at least a portion of the pad electrode. The second insulating layer is disposed between the pad electrode and the pad connection electrode, and overlaps at least a portion of the pad connection electrode.

2. The display device according to claim 1, wherein, The vertical distance from the substrate to the top of the first portion is greater than the vertical distance from the substrate to the top of the second portion.

3. The display device according to claim 1, wherein, The surface of the second insulating layer that overlaps with the pad connection electrode is inclined.

4. The display device according to claim 1, wherein, The display device further includes: A third insulating layer is disposed between the second insulating layer and the pad electrode, and has contact holes that partially expose the pad electrode. A portion of the pad connecting electrode contacts the pad electrode within the contact hole. The width of the pad connecting electrode along one direction is wider than the width of the pad electrode exposed through the contact hole.

5. The display device according to claim 1, wherein, The pad portion also includes: A pad protection layer is disposed between the pad electrode and the pad connection electrode.

6. The display device according to claim 1, wherein, The light-emitting element includes a pixel electrode, an intermediate layer, and a counter electrode. The pad connecting electrode and at least a portion of the pixel electrode contain the same material.

7. The display device according to claim 6, wherein, The pixel electrode has a three-layer film, and the pad connection electrode has a single-layer film.

8. A display device, wherein, have: A substrate, including a display area and a peripheral area surrounding the display area; Thin-film transistors are disposed on the substrate corresponding to the display area; The pad portion is disposed on the substrate corresponding to the peripheral region; A first insulating layer is disposed on the thin-film transistor and exposes the pad portion; A second insulating layer is disposed in the peripheral region and contains the same material as the first insulating layer, and is disposed on the same layer as the first insulating layer; A light-emitting element is disposed on the first insulating layer and electrically connected to the thin-film transistor, and includes a pixel electrode, an intermediate layer and a counter electrode; as well as A pixel defining film is disposed on the first insulating layer and covers the edge of the pixel electrode. The side surface of the first insulating layer and the side surface of the pixel defining film are located on the same etched surface. The pad portion includes: a pad electrode; And a pad connection electrode, disposed on the pad electrode and in contact with at least a portion of the pad electrode. The second insulating layer is disposed between the pad electrode and the pad connection electrode, and overlaps at least a portion of the pad connection electrode.

9. The display device according to claim 8, wherein, The first insulating layer includes a first portion and a second portion extending from the first portion. The first insulating layer has a step on its surface between the first portion and the second portion.

10. The display device according to claim 9, wherein, The side surface of the first portion is located on the same etched surface as the outer side surface of the pixel defining film.

11. The display device according to claim 9, wherein, The pixel electrode and the pixel defining film are configured corresponding to the first part.

12. The display device according to claim 8, wherein, The surface of the second insulating layer that overlaps with the pad connection electrode is inclined.

13. The display device according to claim 8, wherein, The display device further includes: A third insulating layer is disposed on the pad electrode and has contact holes that expose a portion of the pad electrode. A portion of the pad connecting electrode is in contact with the top of the third insulating layer.

14. The display device according to claim 13, wherein, The width of the pad connecting electrode along one direction is wider than the width of the pad electrode exposed through the contact hole.

15. The display device according to claim 8, wherein, The pixel electrode has a three-layer film, and the pad connection electrode has a single-layer film.

16. The display device according to claim 8, wherein, The display device further includes: The dam section is configured corresponding to the surrounding area and includes a first peripheral insulation layer, a second peripheral insulation layer disposed on the first peripheral insulation layer, and a peripheral electrode layer between the first peripheral insulation layer and the second peripheral insulation layer.

17. The display device according to claim 16, wherein, The side surface of the first peripheral insulating layer and the side surface of the second peripheral insulating layer are located on the same etched surface.

18. A display device, wherein, have: A substrate, including a display area and a peripheral area surrounding the display area; Thin-film transistors are disposed on the substrate corresponding to the display area; The pad portion is disposed on the substrate corresponding to the peripheral region; An inorganic insulating layer is disposed on the thin-film transistor and the pad portion, and has an opening exposing the upper surface of the pad portion; A second insulating layer is disposed in the peripheral region and on the inorganic insulating layer; as well as A light-emitting element is disposed on the inorganic insulating layer and electrically connected to the thin-film transistor, and includes a pixel electrode, an intermediate layer, and a counter electrode. The pad portion includes: a pad electrode; And a pad connection electrode, disposed on the pad electrode and in contact with at least a portion of the pad electrode. The second insulating layer is disposed between the pad electrode and the pad connection electrode, and overlaps at least a portion of the pad connection electrode.

19. The display device according to claim 18, wherein, The width of the pad portion along one direction is less than or equal to the width of the opening.

20. The display device according to claim 18, wherein, The pad portion includes: a pad electrode; and a pad protective layer disposed on the pad electrode. The top of the pad protective layer is exposed through the opening.

21. The display device according to claim 20, wherein, The width of the pad protection layer along one direction is less than or equal to the width of the opening.

22. The display device according to claim 20, wherein, The side of the pad electrode is at least partially exposed through the opening.

23. The display device according to claim 18, wherein, The display device further includes: An electrode layer is disposed on the thin-film transistor and electrically connected to the thin-film transistor; A first insulating layer, disposed on the inorganic insulating layer; and A pixel defining film, wherein the pixel electrodes are placed between the pixel electrodes and disposed on the first insulating layer. The inorganic insulating layer also has a first contact hole that exposes a portion of the electrode layer. The first insulating layer has a second contact hole corresponding to the first contact hole. The pixel electrode is electrically connected to the electrode layer through the first contact hole and the second contact hole.

24. The display device according to claim 23, wherein, The side of the first insulating layer adjacent to the surrounding area is aligned with the side of the pixel defining film.

25. The display device according to claim 23, wherein, The first insulating layer includes: a first portion; and a second portion extending from the first portion toward the peripheral region side. The first insulating layer has a step on its surface between the first portion and the second portion.

26. The display device according to claim 18, wherein, The display device further includes: The dam section is configured corresponding to the surrounding area and includes a first peripheral insulation layer and a second peripheral insulation layer disposed on the first peripheral insulation layer.

27. The display device according to claim 26, wherein, The side surfaces of the first peripheral insulating layer and the second peripheral insulating layer are aligned.

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