Storage device and retraining method of storage device

Abstract

A storage device and a retraining method of a storage device are disclosed. The storage device includes an NVM package and a controller connected to the NVM package through a channel and controlling operations of the NVM package. The NVM package includes an interface chip, a first NVM device connected to the interface chip through a first internal channel, and a second NVM device connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining related to the second internal channel is required and sends a retraining request to the controller when the retraining is required.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0053797, filed on May 6, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the inventive concept generally relate to storage devices and methods for retraining non-volatile memory devices constituting the storage devices (hereinafter, individually or collectively referred to as "NVM"). Background Technology

[0003] The use of various error detection and / or correction techniques is known to be particularly useful for both volatile and non-volatile memory. Many storage devices, including NVMs, are equipped with controllers capable of training (or calibrating) the NVMs within the storage device to detect and / or minimize data errors.

[0004] Typically, the operating frequency of a storage device can vary with power and / or temperature conditions, resulting in signal propagation delays, noise, and / or signal timing skew—all of which degrade data integrity. Therefore, storage devices require retraining operations between the controller and the NVM to better align data signals and compensate for this degradation. Summary of the Invention

[0005] Specific embodiments of the inventive concept provide a storage device capable of retraining NVM without time and / or regional limitations. Other embodiments of the inventive concept provide a method for retraining the storage device.

[0006] According to an embodiment of the inventive concept, a storage device includes: a non-volatile memory (NVM) package; and a controller connected to the NVM package via a channel and configured to control the operation of the NVM package. The NVM package includes an interface chip, a first NVM device, and a second NVM device. The first NVM device is connected to the interface chip via a first internal channel, and the second NVM device is connected to the interface chip via a second internal channel. The interface chip is configured to: select the first internal channel in response to an operation request received from the controller, connect the first internal channel to the channel, determine whether retraining related to the second internal channel is required, and send a retraining request to the controller if retraining is required.

[0007] According to an embodiment of the inventive concept, a storage device includes: a non-volatile memory (NVM) package, the NVM package including an interface chip, a first NVM device, and a second NVM device, the first NVM device being connected to the interface chip via a first internal channel, and the second NVM device being connected to the interface chip via a second internal channel, wherein the interface chip is configured to select one of the first and second internal channels, thereby designating one of the first and second internal channels as the selected internal channel, and designating the other of the first and second internal channels as an unselected internal channel, and the interface chip is further configured to: determine whether retraining of the unselected internal channel is required, and provide a retraining request when it is determined that retraining of the unselected internal channel is required; and a controller connected to the interface chip via a channel, wherein the controller is configured to: send a retraining command to the NVM package in response to the retraining request.

[0008] According to an embodiment of the inventive concept, a method for retraining a storage device includes: determining via an interface chip whether retraining is required for an unselected internal channel; and when it is determined that retraining is required, sending a retraining request from the interface chip to a controller. Attached Figure Description

[0009] The above and other aspects, features and advantages of the inventive concept can be better understood by examining the following detailed embodiments in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the inventive concept;

[0011] Figure 2 This is a diagram illustrating a non-volatile memory device (NVM) according to an embodiment of the inventive concept;

[0012] Figure 3A and Figure 3B These are perspective views of a memory block according to an embodiment of the inventive concept;

[0013] Figure 4 This is a diagram illustrating an interface chip according to an embodiment of the inventive concept;

[0014] Figure 5 This is a diagram illustrating a retraining check of an interface chip according to an embodiment of the inventive concept;

[0015] Figure 6 This is a diagram illustrating the operation of a retraining check circuit implemented as a BIST circuit;

[0016] Figure 7 This is a diagram illustrating the operation of a retraining check circuit implemented as an oscillator;

[0017] Figure 8 This is a diagram illustrating the activation process of the retraining check circuit RCC using DQ / DQS / nRE signals according to an embodiment of the inventive concept;

[0018] Figure 9 This is a diagram illustrating the activation process of the retraining check circuit RCC using write / read command signals according to an embodiment of the inventive concept;

[0019] Figure 10 This is a ladder diagram illustrating the operation of a retraining check of a storage device according to an embodiment of the inventive concept;

[0020] Figure 11 This is a ladder diagram illustrating the operation of a retraining check of a storage device according to an embodiment of the inventive concept;

[0021] Figure 12 This is a diagram illustrating a method for sending a retraining request from an interface chip to a controller according to an embodiment of the inventive concept;

[0022] Figure 13 This is a diagram illustrating a method for sending a retraining request from an interface chip to a controller according to an embodiment of the inventive concept;

[0023] Figure 14 This is a diagram illustrating a non-volatile memory package 100 implemented as a stacked non-volatile memory package according to an embodiment of the inventive concept.

[0024] Figure 15 This is a diagram illustrating a storage device according to an embodiment of the inventive concept;

[0025] Figure 16 This is a diagram illustrating a storage device according to an embodiment of the inventive concept;

[0026] Figure 17 This is a diagram illustrating a storage device according to an embodiment of the inventive concept;

[0027] Figure 18 This is a flowchart outlining a method for operating an interface chip according to an embodiment of the inventive concept;

[0028] Figure 19 It is a flowchart outlining a method for operating a controller according to an embodiment of the inventive concept;

[0029] Figure 20 This is a diagram illustrating a storage device according to an embodiment of the inventive concept;

[0030] Figure 21 This is a block diagram illustrating a computing system according to an embodiment of the inventive concept;

[0031] Figure 22 This is a diagram illustrating a mobile device according to an embodiment of the inventive concept;

[0032] Figure 23 This is a block diagram illustrating an electronic system according to an embodiment of the inventive concept; and

[0033] Figure 24 This is a diagram illustrating a data center using a memory device according to an embodiment of the inventive concept. Detailed Implementation

[0034] In the following description, specific embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0035] Embodiments of the inventive concept include a storage device capable of using unselected channels in a memory input / output (I / O) structure to determine whether retraining is required, and performing retraining using a buffer chip based on that determination.

[0036] Figure 1 This is a block diagram illustrating a storage device 10 according to an embodiment of the inventive concept. (Refer to...) Figure 1 The storage device 10 may include an NVM package (NVM PCKG) 100 and a memory controller (CNTL) 200, the memory controller (CNTL) (hereinafter also referred to as the controller) 200 being configured to control the NVM package 100.

[0037] The NVM package 100 may include an interface chip 110 (e.g., a frequency boost interface chip (FBI) or a buffer chip) and multiple NVMs 120, the multiple NVMs 120 being connected to the interface chip 110 via a first internal channel ICH1 and a second internal channel ICH2. It should be noted that more than two (2) internal channels may be used to connect the NVMs to the interface chip 110.

[0038] Interface chip 110 can be connected to controller 200 via channel CH, so that channel CH can be effectively and flexibly connected to one or more of the available internal channels (e.g., first internal channel ICH1 and / or second internal channel ICH2) via interface chip 110.

[0039] exist Figure 1 In the example shown, the interface chip 110 includes a retraining check circuit (RCC) 111, which is capable of determining whether internal retraining of the NVM is required and, in response to this determination, controlling the execution of a retraining method between the interface chip 110 and the NVM package 100.

[0040] The retraining check circuit (RCC) 111 may be configured to use, for example, an unselected internal channel (hereinafter, "unselected channel") between the first internal channel ICH1 and the second internal channel ICH2 to determine whether retraining is required. For example, the retraining check circuit 111 may include a built-in self-test (BIST) circuit, an oscillator, and / or a delay-locked loop (DLL).

[0041] In fact, the retraining check circuit (RCC) 111 effectively designates one of the available internal channels as the selected internal channel and also designates another of the available internal channels as the unselected internal channel.

[0042] Regardless of the specific implementation and / or configuration, the retraining check circuit 111 can be used to check the alignment status between the test mode data (i.e., the expected data) that has passed through the data transmission path of the unselected channel and the clock signal that has passed through the clock transmission path of the unselected channel. The results of these alignment checks can be used to determine whether retraining of the unselected channel is required.

[0043] Each of the NVM120s can be implemented differently to store single-level data (SLC) and / or multi-level data (MLC). One or more NVM120s can be connected to each of the first internal channel ICH1 and / or the second internal channel ICH2. Figure 1 In this design, four (4) NVMs can be connected to each of the internal channels ICH1 and ICH2, but the number of NVMs connected to the internal channels ICH1 and ICH2 can vary depending on the design.

[0044] At least one of the NVM120s can be used to store a bootloader. In this respect, the bootloader can be used, in whole or in part, as an initializer that can be used to initialize the operation of the storage device 10. Those skilled in the art will recognize that the NVM package 100 can be implemented differently using a lateral and / or vertical stacking arrangement of the NVM120.

[0045] The memory controller (CNTL) 200 can be implemented to control the overall operation of the NVM package 100. The memory controller 200 can define and / or control various functions required for the management of data stored in the NVM package 100 (e.g., address mapping, error detection and / or correction, garbage collection, wear leveling, bad block management, etc.). Such functions can be implemented using hardware, software, and / or firmware.

[0046] Controller 200 may receive a retraining request generated by and transmitted from NVM wrapper 100. In response to the retraining request, controller 200 may issue a retraining command and send the retraining command to NVM wrapper 100. Therefore, NVM wrapper 100 may perform a retraining operation related to the unselected channel.

[0047] The retraining operation may include one or more data training operations (e.g., read training operation and / or write training operation). Here, a read training operation may include the operation of effectively positioning the data strobe signal DQS output from the NVM device connected to an unselected channel at the center of the eye pattern of the read data, and a write training operation may include the operation of aligning the eye pattern of the data written to the NVM using the unselected channel.

[0048] The storage device can perform an initial NVM training operation after power-on to properly obtain optimal alignment between the data and clock signals for performing various operations (such as write and / or read operations). After the initial training operation (e.g., once a predetermined period of time has elapsed), deviations between the data and clock signals may occur due to changes in the storage device's operating environment, for example. Optionally or additionally, if a specific failure condition (e.g., exceeding a specific bit error rate or number of errors) is observed during write and / or read operations, a retraining operation can be performed again to correct the alignment between the data and clock signals.

[0049] Some comparison storage devices can create replica paths from I / O blocks trained using mismatched DQ-DQS to check for the need for retraining to memory inputs and outputs, or can periodically perform retraining using intermediate portions of normal I / O operations. However, these methods may have time and / or region limitations in creating replica paths.

[0050] Conversely, the storage device according to an embodiment of the inventive concept can use the interface chip 110 to check whether retraining is needed without such time and / or regional limitations, and then notify the controller 200 whether NVM needs retraining. For example, Figure 1 The storage device 10 may perform normal read / write operations using a selected internal channel (hereinafter, "selected channel"), but may simultaneously (i.e., at least partially overlap in time) use an unselected channel (or in relation to the unselected channel) to determine whether NVM retraining is required. As a result of this retraining determination, the storage device 10 may perform a retraining operation on the NVM.

[0051] Figure 2This is a block diagram illustrating an exemplary NVM 120 according to an embodiment of the inventive concept. (Refer to...) Figure 2 The NVM 120 includes a memory cell array 121, an address decoder 122, a voltage generation circuit 123, input and output circuits 124, and control logic 125.

[0052] The NVM 120 can be implemented as NAND flash memory, vertical NAND flash memory (VNAND), XOR NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-torque random access memory (STT-RAM). In the following description, it is assumed that the NVM 120 is implemented as a vertical NAND flash memory device.

[0053] The memory cell array 121 may include multiple memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz is connected to the address decoder 122 via a word line WL, at least one string select line SSL, and at least one ground select line GSL, and is connected to the input / output circuitry 124 via a bit line BL. In this example embodiment, the word line WL may have a stacked board structure.

[0054] Memory blocks BLK1 to BLKz may include strings having a three-dimensional structure, which may be arranged according to a first direction and a second direction (different from the first direction) and a third direction (a direction perpendicular to the plane formed in the first and second directions) on the substrate. Each string may include at least one string select transistor, a memory cell, and at least one ground select transistor connected in series between a bit line and a common source line (CSL). Each memory cell may be implemented to store at least one bit at the intersection of word line WL and bit line BL. In one exemplary embodiment, at least one dummy cell may be included between at least one string select transistor and a plurality of memory cells. In another example embodiment, at least one dummy cell may be included between a memory cell and at least one ground select transistor.

[0055] Address decoder 122 may be implemented to select one of memory blocks BLK1 to BLKz in response to an address. Furthermore, address decoder 122 may be connected to memory cell array 121 via word line WL, at least one serial select line SSL, and at least one ground select line GSL. Address decoder 122 may use the decoded row address to select word line WL, serial select line SSL, and ground select line GSL. Additionally, address decoder 122 may decode column addresses from input addresses. The decoded column addresses may be sent to input and output circuitry 124. In one example embodiment, address decoder 122 may include row decoders, column decoders, address buffers, etc.

[0056] The voltage generation circuit 123 can be implemented to generate the voltages required for its operation (programming voltage, pass voltage, read voltage, read pass voltage, verification voltage, erase voltage, common source voltage, well voltage, etc.). The voltage generation circuit 123 can generate the word line voltages required for programming / read / erase operations.

[0057] Input and output circuitry 124 can be connected to memory cell array 121 via bit line BL. Input and output circuitry 124 can be implemented to receive a decoded column address from address decoder 122. Input and output circuitry 124 can use the decoded column address to select bit line BL. Input and output circuitry 124 may include page buffers, which can store data to be programmed during a programming operation or data to be read during a read operation. Each page buffer may include multiple latches. During a programming operation, data stored in the page buffers can be programmed into the page corresponding to the selected memory block via bit line BL. During a read operation, data read from the page corresponding to the selected memory block can be stored in the page buffers via bit line BL. Input and output circuitry 124 can read data from a first region of memory cell array 121 and can store the read data in a second region of memory cell array 121. For example, input and output circuitry 124 can be implemented to perform a copy-back.

[0058] Control logic 125 can be implemented to control the overall operation (programming / reading / erasing, etc.) of the non-volatile memory device 100. Control logic 125 can operate in response to the control signal CTRL or commands input from an external entity.

[0059] Figure 3A This is a perspective view illustrating a memory block according to an embodiment of the inventive concept. (Refer to...) Figure 3A The memory block BLK1 can be formed in a direction perpendicular to the substrate SUB. The N+ doped region can be formed on the substrate SUB.

[0060] A gate electrode layer and an insulating layer can be alternately deposited on a substrate SUB. An information storage layer can be formed between the gate electrode layer and the insulating layer. When the gate electrode layer and the insulating layer are patterned vertically, V-shaped pillars can be formed. The pillars can penetrate the gate electrode layer and the insulating layer and can be connected to the substrate SUB. The interior of the pillars can be filled with an insulating material (such as silicon oxide) in a dielectric pattern. The exterior of the pillars can be formed with channel semiconductors in a vertical active pattern.

[0061] The gate electrode layer of memory block BLK1 can be connected to the ground select line GSL, word lines WL1 to WL8, and serial select line SSL. Additionally, the pillars of memory block BLK1 can be connected to bit lines BL1 to BL3. Figure 3A In this context, a single memory block BLK1 may have two select lines GSL and SSL, eight (8) word lines WL1 to WL8 and three (3) bit lines BL1 to BL3, but example embodiments of a single memory block BLK1 are not limited thereto.

[0062] Figure 3B This is a perspective view showing a memory block according to another embodiment of the inventive concept. (Refer to...) Figure 3B For ease of description, it can be assumed that the number of word lines in the memory block BLKb is four (4). The memory block BLKb can be implemented with a bit-cost scalable (BiCS) structure, which pipes the lower ends of adjacent memory cells connected in series. The memory block BLKb may include M×N (M and N are positive integers) strings NS.

[0063] Each string NS may include memory cells connected in series. A first upper end of the memory cell may be connected to a string select transistor (SST), a second upper end of the memory cell may be connected to a ground select transistor (GST), and the lower ends of the memory cells may be piped to each other. The memory cells included in the string NS may be formed by stacking multiple semiconductor layers. Each string NS may include a first pillar PL11, a second pillar PL12, and a pillar connection PL13, the pillar connection PL13 being used to connect the first pillar PL11 to the second pillar PL12. The first pillar PL11 may be connected to a bit line (e.g., BL1) and the pillar connection PL13, and may be formed by penetrating the region between the string select line SSL and word lines WL5 to WL8. The second pillar PL12 may be connected to the common source line CSL and the pillar connection PL13, and may be formed by penetrating the region between the ground select line GSL and word lines WL1 to WL4. Figure 3B As shown, the string NS can be implemented in the shape of a U-shaped column.

[0064] In one example embodiment, the back gate BG may be formed on the substrate, and the pillar connection PL13 may be implemented in the back gate BC. In one example embodiment, the back gate BG may coexist in block BLKb. The back gate (BG) may be configured to be separate from the back gate of another block.

[0065] Figure 4 A block diagram of an interface chip 110 according to an example embodiment of the inventive concept is further shown in one example. (Refer to...) Figure 4The interface chip 110 may include a retraining check circuit 111, a state decision logic 112, and a retraining circuit 114. Figure 4 In this context, it is assumed that interface chip 110 is suitable as an interface for NAND flash memory devices.

[0066] The retraining check circuit 111 can receive a read enable signal (RE / nRE), a data strobe signal (DQS / nDQS), a write command, or a read command, and can be implemented to determine whether a retraining operation is required via an unselected channel. That is, the retraining check circuit 111 can be activated using the read enable signal RE / nRE, the data strobe signal DQS / nDQS, the write command signal, or the read command signal. However, those skilled in the art will recognize that the retraining check circuit 111 can be activated in other ways.

[0067] The state decision logic 112 may use at least one control signal (e.g., one or more of nCE[n:1], nRE, ALE / CLE, nWE, DQS / nDQS) and / or a data signal (DQ[k:1], where “n” and “k” are integers greater than 1) to generate at least one selection signal that determines the operating mode (e.g., receive (RX) mode or transmit (TX) mode) of the retraining circuit 114.

[0068] The retraining circuit 114 can be implemented to select an operating mode in response to a selection signal output from the state decision logic 112, and to adjust the timing of the data signal DQ[k:1] or the data strobe signal DQS / nDQS to suit the selected operating mode.

[0069] The retraining circuit 114 may include at least one clock-based sampler and a delay-locked loop (DLL) circuit that generates a clock input to the sampler. Optionally, the retraining circuit 114 may include at least one clock-based sampler and a delay unit that generates a clock input to the sampler. However, the retraining circuit 114 may be implemented differently to adjust the signal timing.

[0070] In this respect, the retraining circuit 114 can be implemented to reduce training time by using a self-training circuit to search for a reference voltage. For example, the self-training circuit can reduce training time by simultaneously searching for the corresponding reference voltage of the NVM through different input and output pads (or solder pads) of the NVM package 100.

[0071] The retraining circuit 114 may include a duty cycle correction circuit to address jitter caused by distortion of the duty cycle from the DQS of the NVM. In this regard, the retraining circuit 114 may use ZQ calibration to calibrate the drive strength of the NVM.

[0072] Reference Figure 4 The connections between the pads in the exemplary layout may include the following: A data pad for inputting and outputting data signals DQ[k:1] may be connected via retraining circuitry 114 to one of a first internal data pad for inputting and outputting a first internal data signal DQ1[k:1] and a second internal data pad for inputting and outputting a second internal data signal DQ2[k:1]. A data gating pad may be connected to one of a first internal data gating pad for inputting and outputting a first data gating signal DQS1 / nDQS1 and a second internal data gating pad for inputting and outputting a second data gating signal DQS2 / nDQS2, wherein the data gating signals DQS / nDQS are input and output via the data gating pad.

[0073] The pad that receives the read enable signal RE / nRE from the controller 200 can be connected via an output driver (DRV) to a first read enable pad for outputting the first read enable signal RE1 / nRE1, and via an output driver to a second internal read enable pad for outputting the second read enable signal RE2 / nRE2 to the non-volatile memory.

[0074] The chip enable signal nCE[n:1] can be received simultaneously in the interface chip 110 and NVM through wire bonding.

[0075] The address latch enable / command latch enable pad can be connected via state decision logic 112 to an internal address latch enable / command latch enable pad that outputs the address latch enable signal ALE / command latch enable signal CLE to the NVM. The address latch enable / command latch enable pad can receive the address latch enable signal ALE / command latch enable signal CLE from the controller 200.

[0076] The write enable pad can be connected via state decision logic 112 to an internal write enable pad for outputting a write enable signal (nWE) to the NVM. The write enable pad can receive the write enable signal nWE from the controller 200.

[0077] like Figure 4 As shown, the state decision logic 112 can use the DQ / DQS signal to send pass / fail information to the controller 200, and the state decision logic 112 can receive the read enable signal nRE.

[0078] The controller 200 can send a status read command to the status decision logic 112 using the data signal DQ or the write enable signal nWE. Additionally, the controller 200 can send a read enable signal nRE to the status decision logic 112. The retraining check circuit 111 can latch the status read data using the read enable signal nRE and can send the status read data to the controller 200 via the data signal DQ or the data strobe signal DQS.

[0079] The status read data can be divided into interface chip 110 status read data and NAND status read data.

[0080] The status read data can be selected as either interface chip status read data or NAND status read data. In the example embodiment, the interface chip status read data may include the determined result value of the retraining check circuit 111.

[0081] Those skilled in the art will recognize that, regarding Figure 4 The connection relationship of the pads shown in the interface chip 110 is merely exemplary.

[0082] Figure 5 This is a block diagram of an interface chip 110 according to an embodiment of the inventive concept, as shown in one example.

[0083] Reference Figure 5 The interface chip 110 may include at least one chip enable pad 116, a data pad 117, a first data pad 118, and a second data pad 119. Data pad 117 corresponds to channel CH between the controller 200 and the interface chip 110, the first data pad 118 corresponds to the first internal channel ICH1, and the second data pad 119 corresponds to the second internal channel ICH2. Here, for ease of description, the first internal channel ICH1 is assumed to be an unselected channel, and the second internal channel ICH2 is assumed to be a selected channel.

[0084] The retraining check circuit (RCC) 111 can be activated by receiving chip selection information from the chip enable signal decoder (nCE DEC) 113 and at least one operation information from the selected channel ICH2. The operation information may be related to a write operation (or programming operation), an erase operation, and / or a read operation.

[0085] The retraining check circuit 111 can send test data to the data pad 118 using the transmit path corresponding to the unselected channel (e.g., the first internal channel ICH1), and can receive test data from the data pad 118 using the receive path corresponding to the unselected channel ICH1, and can determine whether retraining is required. The sensing portion of the retraining check circuit 111 can be related to the transmit and receive paths of the unselected channel ICH1.

[0086] The internal channel selector 115 can determine whether to connect a channel (CH) to the first internal channel (ICH1) or the second internal channel (ICH2) based on chip selection information from the chip enable signal decoder 113.

[0087] The interface chip 110 can be used to check, using the retraining check circuit 111, whether retraining is required for unselected paths while the selected channel continues to be used for normal operation (e.g., read, write, and / or erase operations). Furthermore, the interface chip 110 can be used to send information about whether retraining is required to the controller 200 via a status read operation or via a dedicated pin. Therefore, the interface chip 110 can automatically respond to timing changes caused by variations in frequency, voltage, temperature, etc.

[0088] In a particular embodiment, the retraining check circuit 111 may be implemented as a built-in self-test (BIST) circuit or a DQS oscillator.

[0089] Figure 6 This is a block diagram illustrating the retraining check circuit 111 implemented using BIST circuit 111a in one example. (See also...) Figure 6 The retraining check circuit 111 can use the matching between the DQ signal and the DQS signal output from the BIST circuit 111a to check for pass / fail. For example, a flip-flop (DFF) 111b can be used to latch the data signal DQ from the data strobe pad to the data pad in response to the data strobe signal DQS. Comparison logic 111c can receive the latched value from the flip-flop 111b and output a pass / fail signal (P / F) corresponding to the necessity of the retraining operation. After the DQ signal and DQS signal generated in the BIST circuit 111a are transmitted through the transmit and receive paths, the retraining check circuit 111 can generate a pass / fail signal based on the matching of the DQ signal and the DQS signal.

[0090] Figure 7 This is a block diagram showing a retraining check circuit 111 implemented with an oscillator 111d in one example. (See also...) Figure 7 The count value DQS_OSC_CNT, based on the input and output of the DQS signal, can be output via an unselected channel relative to the clock output from oscillator 111d. The retraining check circuit 111 can use the output count value DQS_OSC_CNT provided by counter 111e to generate a pass / fail signal.

[0091] As described above, the retraining check circuit 111 can be activated in different ways. For example, the retraining check circuit 111 can be activated using the read enable signal nRE.

[0092] Figure 8This is a block diagram illustrating one method of activating the retraining check circuit (RCC) 111 using DQ / DQS / nRE (or write / read command) signals. (See also...) Figure 8 The chip enable signal decoder 111f receives the chip enable signal nCE from the controller and outputs chip selection information. The activation signal generator EN GNRT 111-1 receives the chip selection information from the chip enable signal decoder 111f and outputs the activation signal EN in response to the read enable signal nRE. The activation signal EN can be used to activate the retraining check circuit (RCC) 111. For example, when the chip selection information is not selected and the read enable signal nRE is high, the activation signal generator 111-1 can output the activation signal EN to check whether retraining is required for the unselected channel.

[0093] Alternatively, the activation signal generator in the example embodiment may also output the activation signal EN in response to a write command or read command signal instead of the read enable signal nRE.

[0094] Figure 8 The retraining check circuit RCC shown can be activated non-periodically in response to a read enable signal nRE. However, example embodiments of the retraining check circuit RCC are not limited thereto.

[0095] Figure 9 This is a block diagram illustrating another method for activating the retraining check circuit RCC 111 using write / read commands (or DQ / DQS / nRE). See reference. Figure 9 Counter 111-2 outputs an activation signal EN by counting the write command signal or read command signal and comparing the count value with a reference value. The reference value can be stored in a reference value storage device 111-3. In an example embodiment, the reference value storage device 111-3 can be implemented as volatile memory or non-volatile memory. For example, when the write command signal or read command signal has been counted 1000 times, a retraining check circuit can check whether retraining is required.

[0096] In the example embodiment, the retraining check circuit can output an activation signal by counting the read enable signal nRE instead of counting the write command signal or the read command signal and comparing the count value with a reference value.

[0097] The retraining check circuit RCC 111 can be implemented using an internal oscillator or using nRE / RE or DQS / nDQS.

[0098] Figure 10 It is shown Figure 1 The concept (ladder flow) diagram of the execution of the retraining check operation in the storage device 10.

[0099] Reference Figure 1 and Figure 10 The controller 200 can send a write request to the interface chip 110 (S11). The write request may include a write command, a write address, and write data. The interface chip 110 can send the write request received from the controller 200 to the selected NVM via the selected channel (S12). Thereafter, the selected NVM can perform the write operation corresponding to the write request (S13).

[0100] When a write operation is performed, the interface chip 110 can activate the retraining check circuit (RCC) 111 (S14). Thereafter, the retraining check circuit 111 can send the expected data to the unselected NVM via the unselected channel (S15), and can receive sampled data corresponding to the unselected NVM via the unselected channel (S16). The retraining check circuit 111 can determine whether retraining is needed by comparing the expected data with the sampled data (S17). When retraining is needed, the retraining check circuit 111 can send a retraining request to the controller 200 (S18).

[0101] Then, the selected NVM can complete the write operation and send the completion information to the controller 200 (S19).

[0102] It is worth noting that, Figure 10 The retraining check operation can be performed simultaneously with the write operation.

[0103] Figure 11 It is shown Figure 1 Another conceptual diagram of the execution of the retraining check operation in the storage device 10.

[0104] Reference Figure 1 and Figure 11 The controller 200 can send a read request to the interface chip 110 (S21). The read request may include a read command and a read address. The interface chip 110 can send the read request received from the controller 200 to the selected NVM through the selected channel (S22). Thereafter, the selected NVM can perform the read operation corresponding to the read request (S23). Then, the NVM can send the read data to the controller 200 (S24).

[0105] When a read operation is performed, the interface chip 110 can activate the retraining check circuit (RCC) 111 (S25). Thereafter, the retraining check circuit 111 can send the expected data to the unselected NVM via the unselected channel (S26), and can receive the corresponding sampled data from the unselected non-volatile memory device via the unselected channel (S27). The retraining check circuit 111 can determine whether retraining is needed by comparing the expected data with the sampled data (S28). When retraining is needed, the retraining check circuit 111 can send a retraining request to the controller 200 (S29).

[0106] It is worth noting that, Figure 11 The retraining check operation can be performed simultaneously with the read operation.

[0107] Figure 12 This is a block diagram illustrating a method of sending a retraining request from interface chip 110 to controller 200. (See also...) Figure 12 A state read operation can be used to send a request for retraining. That is, a state read operation can be performed in response to a state read command provided by controller 200. Optionally, a state read operation can be performed in an NVM connected to an unselected channel in response to at least one operation signal related to normal operation performed using the selected channel.

[0108] Interface chip 110 can send a result value to controller 200 as status read information. The result value is obtained by performing an OR operation on a pass / fail result value provided by retraining check circuitry (RCC) 111 and a status value provided by status decision logic (e.g., status determination logic) 112. In one example embodiment, the status read information may include at least one of status read information related to the interface chip and status read information related to non-volatile memory. Controller 200 can issue a retraining command in response to the status read information received from interface chip 110 and can send the retraining command to interface chip 110.

[0109] Figure 13 This is a block diagram illustrating another method for sending a retraining request from interface chip 110 to controller 200. (See also...) Figure 13 Interface chip 110 can send a retraining request corresponding to an unselected channel to controller 200 via a dedicated pin (EXP). Controller 200 can periodically receive retraining requests from interface chip 110 via the dedicated pin. The retraining request may include a pass / fail result value of retraining check circuit (RCC) 111. Controller 200 can send a retraining command to interface chip 110 in response to a retraining request received via pin EXP.

[0110] As described above, the NVM package 100 of a particular embodiment of the inventive concept may include vertically stacked NVMs. Figure 14 The block diagram shows an example of this variant.

[0111] Reference Figure 14 The NVM package (NVM PKG) 100 includes an interface chip 110 (e.g., an I / O buffer) and vertically stacked NVMs (e.g., NVM1 to NVM8) 120. A first internal channel ICH1 can connect the first stacked NVMs (e.g., NVM1 to NVM4) to the interface chip 110, and a second internal channel ICH2 can connect the second stacked NVMs (e.g., NVM5 to NVM8) to the interface chip 110.

[0112] Figure 14 The interface chip 110 is shown as being physically adjacent to the bottommost one (e.g., NVM1) of the stacked NVMs 120. However, the interface chip 110 may be located between the first stacked NVMs and the second stacked NVMs, or adjacent to the topmost one (e.g., NVM8) of the stacked NVMs.

[0113] Figure 14 The first internal channel ICH1 and the second internal channel ICH2 shown can be implemented at least partially using wire channels.

[0114] However, those skilled in the art will recognize that the foregoing examples are merely illustrative.

[0115] Figure 15 This is a block diagram illustrating a storage device 20 according to an embodiment of the inventive concept. (Refer to...) Figure 15 The storage device 20 may include a plurality of NVM memory packages (e.g., 100a-1 to 100a-i, where "i" is an integer greater than 1) and a controller 200a for controlling the NVM packages 100a-1 to 100a-i differently.

[0116] Here, similar to Figure 1 In the embodiment shown, the first NVM package 100a-1 can be connected to the memory controller 200a via a first internal channel CH1. Similarly, each of the remaining NVM packages 100a-i can be connected to the controller 200a via a corresponding internal channel CHi.

[0117] Such as about Figures 1 to 14As described in the embodiments, each of the NVM packages 100a-1 to 100a-i may be implemented to include a retraining check circuit RCC 111. The retraining check circuit RCC 111 may be located in the corresponding interface chips 111a-1 to 111a-i, respectively. Therefore, each of the NVM packages 100a-1 to 100a-i may operate according to the method implemented by the retraining check circuit RCC 111 in their various embodiments.

[0118] In a particular embodiment of the inventive concept, the memory controller 200a may include a plurality of NVM managers 201 to 20i, each NVM manager being used to independently control corresponding NVM packages 100a-1 to 100a-i that respectively include a plurality of NVMs 120a-1 to 120a-i.

[0119] In this regard, (such as) Figure 15 The separate circuits shown can be used to implement NVM managers 201 to 20i respectively, or (as shown) Figure 16 The single controller (or processor) 201 and associated software / firmware shown can be used to implement the functions of the various NVM managers 201 to 20i. For example, Figure 16 The controller 200b may consist of only one NVM manager 201.

[0120] exist Figures 1 to 16 In the embodiments shown in different ways, a single-layer interface chip 110 can be used to perform channel branching. However, the inventive concept is not limited to this, and a multi-layer interface chip can be used to perform channel branching.

[0121] Figure 17 This is a block diagram illustrating a storage device 40 according to an embodiment of the inventive concept. (Refer to...) Figure 17 The storage device 40 may include an NVM package 100c and a controller 200c configured to control the NVM package 100c.

[0122] The NVM package 100c may include an interface circuit 110c and a plurality of NVMs connected via a first internal channel ICH1 to a fourth internal channel ICH4 respectively. The interface circuit 110c includes multi-layer interface chips (e.g., FBI-1, FBI-2 and FBI-3).

[0123] The interface circuit 110c may include a first interface chip FBI-1 in the first layer, and a second interface chip FBI-2 and a third interface chip FBI-3 in the second layer. The first interface chip FBI-1 can branch the first channel CH1 into two branch channels DCH1 and DCH2. The second interface chip FBI-2 and the third interface chip FBI-3 can be respectively branched into two internal channels ICH1 to ICH2 and ICH3 to ICH4 corresponding to the branch channels DCH1 and DCH2.

[0124] In one example embodiment, the first interface chip FBI-1, the second interface chip FBI-2, and the third interface chip FBI-3 can be implemented in the same manner. In one example embodiment, each of the first interface chip FBI-1, the second interface chip FBI-2, and the third interface chip FBI-3 may include a reference. Figures 1 to 14 The circuit described is used to check whether a retraining operation is required, and the retraining check circuit RCC that implements this operation.

[0125] The controller 200c can command a retraining operation on the corresponding channel in response to a retraining request received from at least one of the first interface chip FBI-1, the second interface chip FBI-2, and the third interface chip FBI-3.

[0126] Figure 18 This is a flowchart outlining a method for operating an interface chip according to an embodiment of the inventive concept. (See also...) Figure 1 and Figure 18 The interface chip 110 can operate as follows: In normal mode, the interface chip 110 can use an unselected channel to determine whether a retraining operation is required (S110). When a retraining operation is required, the interface chip 110 can send a retraining request to the controller 200 using a status read operation or via a dedicated pin (S120).

[0127] In a particular embodiment, the interface chip 110 may use a selected channel to send a write request or a read request to the corresponding NVM.

[0128] Here, the steps to determine whether retraining is required may include: activating the retraining check circuit in response to a read enable signal, outputting expected data to an unselected channel, receiving sampled data from the unselected channel, comparing the expected data with the sampled data, and generating a retraining request based on the comparison result.

[0129] Optionally, the step of determining whether retraining is required may include: counting the DQS signals of the unselected channels, comparing the count values ​​with reference values, and generating a retraining request based on the comparison results.

[0130] Here, the step of sending a retraining request to the controller may include: performing an OR calculation on the state read value corresponding to the state read command and the retraining request corresponding to the determined result, and sending the calculated value to the controller.

[0131] Optionally, the step of sending a retraining request to the controller may include sending a retraining request corresponding to the determined result to the controller via at least one dedicated pin.

[0132] Figure 19 This is another flowchart outlining a method for operating a controller according to an embodiment of the inventive concept. (See also...) Figure 1 and Figure 19 The controller 200 can operate as follows: The controller 200 can send an operation command to the interface chip (FBI chip) 110. The operation command can be a write command or a read command (S210). Thereafter, the controller 200 can receive a retraining request from the interface chip via a status read operation or via a dedicated pin (S220). In response to the received retraining request, the controller 200 can send a retraining command to the interface chip (S230).

[0133] Figure 20 This is a block diagram illustrating a storage device 1000 according to an embodiment of the inventive concept. (Refer to...) Figure 20 The storage device 1000 may include at least one NVM package (NVM PCKG) 1100 and a memory controller 1200.

[0134] The non-volatile memory package 1100 can be implemented as an execution reference. Figures 1 to 19 The described retraining check and retraining operations are intended to improve data reliability. Furthermore, the non-volatile memory package 1100 may include at least one retraining check circuit (RCC) for determining whether retraining is required. In one example embodiment, the non-volatile memory device may be optionally provided with an external high voltage (Vpp).

[0135] The memory controller 1200 can be connected to the non-volatile memory package 1110. The memory controller 1200 may include at least one processor (CPU) 1210, a buffer memory 1220, an error correction circuit (ECC) 1230, a code memory 1240, a host interface 1250, and a non-volatile memory interface 1260.

[0136] The processor 1210 can be implemented to control the overall operation. The processor 1210 can be implemented by a central processing unit (CPU) or an application processor (AP).

[0137] The buffer memory 1220 can be implemented to temporarily store data required for the operation of the memory controller 1200. Although Figure 20 The buffer memory 1220 shown is disposed within the memory controller 1200, but the example embodiment of the buffer memory 1220 is not limited thereto. The buffer memory 1220 in the example embodiment may be disposed outside the memory controller 1200 as a separate intellectual property (IP) block.

[0138] Error correction circuit 1230 can calculate the error correction code value of the data to be programmed during a write operation, and can correct errors in the data read during a read operation based on the error correction code value, and can correct errors in the data recovered from the non-volatile memory package 1100 during a data recovery operation. Error correction circuit 1230 can use coding modulation (such as low-density parity-check (LDPC) codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc.) to correct errors. Code memory 1240 can store code data required to operate the memory controller 1200. Code memory can be implemented as a non-volatile memory device.

[0139] The host interface 1250 may be implemented to provide connectivity with an external device. The non-volatile memory interface 1260 may be implemented to provide connectivity with a non-volatile memory package 1100. Although not shown, the memory controller 1200 may include wireless communication capabilities (e.g., Wi-Fi).

[0140] In the example embodiment, the storage device 1000 can periodically or non-periodically perform retraining operations on unselected channels while performing normal operations through selected channels, thereby improving system performance.

[0141] Figure 21 This is a block diagram illustrating a computing system 2000 according to an embodiment of the inventive concept. (Refer to...) Figure 21 The computing system 2000 may include at least one memory module (DIMM) 2100, at least one non-volatile memory module (NVDIMM) 2200, and at least one processor 2300. Each of the at least one memory module 2100 and the at least one non-volatile memory module 2200 may include a retraining check circuit (RCC) capable of performing the retraining check operations described above.

[0142] The example implementation can be applied to various types of computing systems (e.g., central processing unit (CPU) / graphics processing unit (GPU) / neural processor (NPU) platforms).

[0143] Figure 22 This is a block diagram illustrating a mobile device 3000 according to an embodiment of the inventive concept. (Refer to...) Figure 22 The mobile device 3000 may include an application processor (AP, 3100), at least one buffer memory 3200, at least one storage device 3300, at least one sensor 3400, and a display / touch module 3500. For example, the mobile device 3000 may be implemented as a laptop computer, mobile phone, smartphone, tablet PC, or wearable computer.

[0144] The application processor (AP, 3100) can be implemented to control the overall operation of the mobile device 3000. The application processor 3100 can execute applications that provide internet browsers, games, and videos. In one example embodiment, the application processor 3100 may include a single core or multiple cores. In one example embodiment, the application processor 3100 may also include cache memory disposed internally or externally to the application processor 3100. Furthermore, the application processor 3100 may optionally include a controller, a neural processing unit (NPU), etc.

[0145] In one example embodiment, the application processor 3100 may be implemented as a system-on-a-chip (SoC). The kernel of the operating system running on the SoC may include an input / output scheduler and a device driver for controlling the storage device 3300. The device driver may control the access performance of the storage device 3300 by referring to the number of synchronization queues managed by the input / output scheduler, or it may control the CPU mode, DVFS level, etc. in the SoC.

[0146] The buffer memory 3200 can be implemented to store data required for the operation of the application processor 3100. For example, the buffer memory 3200 can temporarily store operating system (OS) and application data, or it can be used as execution space for various software codes. Furthermore, the buffer memory 3200 can store data related to artificial intelligence calculations. In one example embodiment, the buffer memory 3200 can be implemented as DRAM or PRAM.

[0147] Storage device 3300 may be implemented to store user data. Storage device 3300 may be included in mobile device 3000 in an embedded form. In another example embodiment, storage device 3300 may be included in mobile device 3000 in a detachable manner.

[0148] Storage device 3300 can store data collected from at least one sensor, or it can store network data, augmented reality (AR) / virtual reality (VR) data, and high-definition (HD) content. Storage device 3300 may include solid-state drives (SSDs), embedded multimedia cards (eMMC), etc.

[0149] At least one sensor 3400 can be implemented to perform various sensing operations.

[0150] The display / touch module 3500 can be implemented to output or input data via touch. For example, the display / touch module 3500 can use at least one sensor to output sensed image data, or it can use an application processor 3100 to output calculated data. Furthermore, the display / touch module 3500 can recognize user touches.

[0151] Figure 23 This is a block diagram illustrating an electronic system 4000 according to an embodiment of the inventive concept. (Refer to...) Figure 23 The electronic system 4000 for the vehicle may include an electronic control unit (ECU) 4100, a memory device 4200, at least one dynamic range sensor (DVS) 4300, a display device 4400, a communication processor (4500), and a safety ECU (not shown).

[0152] ECU 4100 can be implemented to control overall operation. ECU 4100 can process image data received from DVS 4300. ECU 4100 may include a neural processor (NPU). The NPU can quickly derive the optimal image for driving by comparing the images received from DVS 4300 with a learned model.

[0153] Memory device 4200 may be implemented to store a learning model related to the operation of the NPU. Memory device 4200 may include a volatile memory device or a non-volatile memory device. For example, memory device 4200 may be implemented as DRAM, PRAM, NAND flash memory, etc. The memory device 4200 in the example embodiment may be implemented to execute reference... Figures 1 to 19 The description includes the retraining check operation and the retraining operation.

[0154] The DVS 4300 can be implemented to sense the external environment of a vehicle. The DVS 4300 can output an event signal in response to changes in relative light intensity. The DVS 4300 may include a pixel array and an address event processor; the pixel array includes multiple DVS pixels.

[0155] The display device 4400 can be configured to display images processed by the ECU 4100 or images transmitted by the communication processor 4500.

[0156] For example, the communication processor 4500 can be implemented to send processed images to an external device (such as an external vehicle) or to receive images from an external vehicle. Therefore, the communication processor 4500 can be implemented to communicate with external devices in a wired or wireless manner.

[0157] Figure 24 This is a diagram illustrating a data center employing a memory device according to an embodiment of the inventive concept. (Refer to...) Figure 24 Data center 7000 can be implemented as a facility capable of collecting various types of data and providing services, and can be referred to as a data storage center. Data center 7000 can be implemented as a system for operating search engines and databases, and can be implemented as a computing system used in a company (such as a bank or government organization). Data center 7000 may include application servers 7100 to 7100n and storage servers 7200 to 7200m. In an example embodiment, the number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m can vary, and the number of application servers 7100 to 7100n may differ from the number of storage servers 7200 to 7200m.

[0158] Application server 7100 or storage server 7200 may include at least one of processors 7110 and 7210 and memories 7120 and 7220. Referring to storage server 7200 as an example, processor 7210 may control the overall operation of storage server 7200 and may access memory 7220 and execute commands and / or data loaded in memory 7220. Memory 7220 may be implemented as double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVMDIMM). In example embodiments, the number of processors 7210 and the number of memories 7220 included in storage server 7200 may be varied. In one example embodiment, processors 7210 and memory 7220 may provide a processor-memory pair. In one example embodiment, the number of processors 7210 may differ from the number of memories 7220. Processor 7210 may include a single-core processor or a multi-core processor. The above description of storage server 7200 can be similarly applied to application server 7100. In an example embodiment, application server 7100 may not include storage device 7150. Storage server 7200 may include at least one or more storage devices 7250. In an example embodiment, the number of storage devices 7250 included in storage server 7200 may vary.

[0159] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300. Network 7300 can be implemented using Fibre Channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission, and a high-performance / high-availability optical switch can be used. Depending on the access method of network 7300, storage servers 7200 to 7200m can be provided as file storage devices, block storage devices, or object storage devices.

[0160] In one example embodiment, network 7300 may be implemented as a network specifically for storage (such as a storage area network (SAN)). For example, the SAN may be implemented as an FC-SAN using an FC network and implemented according to the FC protocol (FCP). As another example, the SAN may be implemented as an IP-SAN using a TCP / IP network and implemented according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In another example embodiment, network 7300 may be implemented as a general-purpose network (such as a TCP / IP network). For example, network 7300 may be implemented according to protocols such as FC over Ethernet (FCoE), network-attached storage (NAS), NVMe over a network (NVMe-oF), etc.

[0161] The following description will primarily focus on application server 7100 and storage server 7200. The description of application server 7100 can be applied to other application servers 7100n, and the description of storage server 7200 can be applied to other storage servers 7200m.

[0162] Application server 7100 can store data requested by users or clients and stored in one of storage servers 7200 to 7200m via network 7300. Furthermore, application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be implemented as a web server or a database management system (DBMS).

[0163] Application server 7100 can access memory 7120n or storage device 7150n included in other application servers 7100n via network 7300, or access memory 7220 to 7220m or storage device 7250 to 7250m included in storage servers 7200 to 7200m via network 7300. Therefore, application server 7100 can perform various operations on data stored in application servers 7100 to 7100n and / or storage servers 7200 to 7200m. For example, application server 7100 can execute commands for moving or copying data between application servers 7100 to 7100n and / or storage servers 7200 to 7200m. In this scenario, data can be moved from storage devices 7250 to 7250m of storage servers 7200 to 7200m to memory devices 7220 to 7220m of storage servers 7200 to 7200m and memory devices 7120 to 7120n of application servers 7100 to 7100n. For security or privacy, data moved over network 7300 can be encrypted.

[0164] Referring to storage server 7200 as an example, interface (NIC) 7254 provides physical connectivity between processor 7210 and controller 7251, and between NIC 7240 and controller 7251. For example, interface 7254 can be implemented using a Direct Attach Storage (DAS) method, which allows direct connection of storage device 7250 using a dedicated cable. Furthermore, interface 7254 can be implemented using various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), NVM Fast (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), and Compact Flash Memory (CF) card interface. Similarly, application servers 7100 to 7100n can also include NICs 7140 to 7140n respectively.

[0165] Storage server 7200 may also include switch 7230 and NIC 7240. Switch 7230 may selectively connect processor 7210 to storage device 7250 under the control of processor 7210, or selectively connect NIC 7240 to storage device 7250. Similar to storage server 7200, storage server 7200m may include processor 7210m, memory 7220m, switch 7230m, NIC 7240m, and storage device 7250m. Storage device 7250m may include DRAM 7253m, controller 7251m, NIC 7254m, and NAND 7252m.

[0166] In one example embodiment, NIC 7240 may include a network interface card, network adapter, etc. NIC 7240 can connect to network 7300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 7240 may include internal memory, DSP, host bus interface, etc., and can connect to processor 7210 and / or switch 7230 via the host bus interface. The host bus interface may be implemented as one of the examples of interface 7254 described above. In one example embodiment, NIC 7240 may be integrated with at least one of processor 7210, switch 7230, and storage device 7250.

[0167] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can send commands to storage devices 7130 to 7130n and 7250 to 7250m or memories 7120 to 7120n and 7220 to 7220m, and can program or read data. In this case, the data can be error-corrected data that has been corrected by an error-correcting code (ECC) engine. The data can be data processed by Data Bus Inversion (DBI) or Data Desensitization (DM), and may include Cyclic Redundancy Check (CRC) information. The data can be encrypted for security or privacy purposes.

[0168] Storage devices 7150 to 7150n and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to a read command received from the processor. Therefore, when reading data from NAND flash memory devices 7252 to 7252m, a read enable (RE) signal is input as a data output control signal, and data can be output to the DQ bus. A data strobe (DQS) can be generated using the RE signal. Command and address signals can be latched into the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0169] In one example embodiment, storage devices 7150 to 7150n and 7250 to 7250m can be referenced. Figures 1 to 19 The described storage device and the storage device retraining operation are implemented.

[0170] Controller 7251 controls the overall operation of storage device 7250. In one example embodiment, controller 7251 may include static random access memory (SRAM). Controller 7251 may write data to NAND flash memory device 7252 in response to a write command, or may read data from NAND flash memory device 7252 in response to a read command. For example, write and / or read commands may be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100n. DRAM 7253 may temporarily store (buffer) data to be written to or read from NAND flash memory device 7252. Furthermore, DRAM 7253 may store metadata. Metadata may be user data or data generated by controller 7251 for managing NAND flash memory device 7252.

[0171] According to the above example embodiments, for the storage device and the storage device retraining method, by including an interface chip that can use an unselected channel to determine whether retraining is needed and can send a retraining request to the controller based on the determined result, the storage device can automatically respond to timing changes caused by frequency, voltage or temperature.

[0172] Furthermore, for the storage device and the retraining method of the storage device in the example embodiment, retraining can be performed without time / region restrictions when the interface chip sends a retraining request to the controller.

[0173] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, comprising: Non-volatile memory package; and The controller is connected to the non-volatile memory package via a channel and is configured to control the non-volatile memory package. The non-volatile memory package includes an interface chip, a first non-volatile memory device, and a second non-volatile memory device. The interface chip includes a retraining check circuit. The first non-volatile memory device is connected to the interface chip via a first internal channel, and the second non-volatile memory device is connected to the interface chip via a second internal channel. The channels are connected to the first and second internal channels via the interface chip. The interface chip is configured to: select one of a first internal channel and a second internal channel in response to an operation request received from the controller, thereby designating the first internal channel as the selected internal channel and the second internal channel as an unselected internal channel, connecting the first internal channel to the channel, and activating a retraining check circuit in response to the operation request or a control signal received from the controller, and chip selection information indicating that the second internal channel is designated as an unselected internal channel. The retraining check circuit is configured to: determine whether retraining of the second non-volatile memory device is required via an unselected internal channel while a read or write operation is performed through the selected internal channel, and send a retraining request to the controller if retraining of the second non-volatile memory device is required. The process of determining whether retraining is required includes: sending expected data to a second non-volatile memory device through an unselected internal channel, receiving corresponding sampled data from the second non-volatile memory device through an unselected internal channel, and determining whether retraining is required by comparing the expected data with the sampled data.

2. The storage device according to claim 1, wherein, When it is determined that retraining is required, the retraining check circuit outputs a retraining request to the controller via at least one dedicated pin.

3. The storage device according to claim 1, wherein, The control signals include at least one of a read enable signal and a data strobe signal.

4. The storage device according to claim 1, wherein, The operation request is a read request, and The interface chip includes an activation signal generator, which is configured to receive chip selection information and generate an activation signal in response to reading an enable signal to activate the retraining check circuit.

5. The storage device according to claim 1, wherein, The interface chip also includes a chip enable signal decoder, which is configured to receive at least one chip enable signal from the controller and output chip selection information.

6. The storage device according to claim 1, wherein, The operation request is a read request, and The interface chip includes a counter configured to: receive chip selection information, count read enable signals to generate a count value for activating the retraining check circuit, and generate an activation signal by comparing the count value with a reference value.

7. The storage device according to claim 6, wherein, The interface chip also includes a reference value storage device, which is configured to store reference values.

8. The storage device according to claim 1, wherein, When it is determined that retraining is required, the retraining check circuit uses a status read operation to output a retraining request to the controller.

9. The storage device according to claim 8, wherein, The interface chip also includes logic circuitry configured to compare the output value of the retraining check circuitry with the state read result value corresponding to the state read command.

10. A storage device, comprising: A non-volatile memory package includes an interface chip, a first non-volatile memory device, and a second non-volatile memory device. The interface chip includes retraining check circuitry. The first non-volatile memory device is connected to the interface chip via a first internal channel, and the second non-volatile memory device is connected to the interface chip via a second internal channel. The interface chip is configured to: select one of a first internal channel and a second internal channel in response to an operation request received from the controller, thereby designating the first internal channel as the selected internal channel and the second internal channel as an unselected internal channel; and activate a retraining check circuit in response to the operation request or a control signal received from the controller, and chip selection information indicating that the second internal channel is designated as an unselected internal channel. The retraining check circuit is configured to: determine whether retraining of a second non-volatile memory device connected to an unselected internal channel is required while a read or write operation is performed using the selected internal channel, and, if it is determined that retraining of the second non-volatile memory device is required, provide a retraining request to the controller; and The controller is connected to an interface chip via a channel, wherein the channel is connected to a first internal channel and a second internal channel via the interface chip, and the controller is configured to: in response to a retraining request, send a retraining command to a non-volatile memory package, and The process of determining whether retraining is required includes: sending expected data to a second non-volatile memory device through an unselected internal channel, receiving corresponding sampled data from the second non-volatile memory device through an unselected internal channel, and determining whether retraining is required by comparing the expected data with the sampled data.

11. The storage device according to claim 10, wherein, The controller is also configured to send a state read command to the interface chip using one of the DQ signal and the write enable signal, and to receive a retraining request corresponding to the state read command using one of the DQ signal and the DQS signal provided by the interface chip.

12. The storage device according to claim 10 or claim 11, wherein, The controller periodically receives retraining requests from the retraining check circuit via a dedicated pin.

13. The storage device according to claim 10, wherein, An operation request includes either a write request or a read request.

14. A method for retraining a storage device, the method comprising: In response to an operation request received from the controller, one of a first internal channel and a second internal channel is selected via an interface chip included in a non-volatile memory package, thereby designating the first internal channel as the selected internal channel and the second internal channel as the unselected internal channel; In response to the operation request or a control signal received from the controller, and chip selection information indicating that the second internal channel is designated as an unselected internal channel, the retraining check circuit included in the interface chip is activated. While read or write operations are performed through the selected internal channel, a retraining check circuit determines whether retraining of the non-volatile memory device connected to the unselected internal channel is required. and When it is determined that retraining of a non-volatile memory device connected to an unselected internal channel is required, a retraining request is sent from the retraining check circuit to the controller, and The step of determining whether retraining is needed includes: sending expected data to a non-volatile memory device through an unselected internal channel, receiving corresponding sampled data from the non-volatile memory device through an unselected internal channel, and determining whether retraining is needed by comparing the expected data with the sampled data.

15. The retraining method according to claim 14, further comprising: The operation request is sent to the corresponding non-volatile memory device using the selected internal channel.

16. The retraining method according to claim 14, wherein, The operation request includes one of a write request and a read request, and the control signal includes a read enable signal.

17. The retraining method according to any one of claims 14 to 16, wherein, The steps to send a retraining request to the controller include: Logical calculations are performed on the state read value corresponding to the state read command and the retraining request corresponding to the determined result; and The logically calculated value is sent to the controller.

18. The retraining method according to any one of claims 14 to 16, wherein, The steps to send a retraining request to the controller include: A retraining request is sent via a dedicated pin.

Images