Data processing method and apparatus, and related product

Abstract

This disclosure relates to a data processing method and apparatus, as well as related products. The product includes a control module, which comprises: an instruction cache unit, an instruction processing unit, and a storage queue unit. The instruction cache unit stores computation instructions associated with the artificial neural network operation. The instruction processing unit parses the computation instructions to obtain multiple computation instructions. The storage queue unit stores an instruction queue, which includes multiple computation instructions or calculation instructions to be executed in the order of their sequence. Through the above method, this disclosure can improve the computational efficiency of related products when performing neural network model operations.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method and apparatus, as well as related products. Background Technology

[0002] With the development of artificial intelligence technology, it has achieved good results in fields such as image recognition. In the process of image recognition, it may be necessary to process a large amount of vector data (such as interpolation, expansion, transformation, etc.). However, the processing in related technologies is relatively complex and has a large data overhead. Summary of the Invention

[0003] Therefore, it is necessary to provide a data processing method, apparatus, and related products to address the aforementioned technical problems.

[0004] According to one aspect of this disclosure, a data processing method is provided, comprising:

[0005] When the decoded processing instruction is a vector extension instruction, determine the source data address, destination data address, and extension parameters of the data corresponding to the processing instruction;

[0006] Based on the expansion parameters, the first vector data of the source data address is expanded to obtain the expanded second vector data;

[0007] The second vector data is stored in the destination data address.

[0008] The source data address and the destination data address include consecutive data addresses.

[0009] According to another aspect of this disclosure, a data processing apparatus is provided, comprising:

[0010] The address determination module is used to determine the source data address, destination data address, and extended parameters of the data corresponding to the decoded processing instruction when the decoded processing instruction is a vector extension instruction.

[0011] The data expansion module is used to expand the first vector data of the source data address according to the expansion parameters to obtain the expanded second vector data;

[0012] The data storage module is used to store the second vector data to the destination data address.

[0013] The source data address and the destination data address include consecutive data addresses.

[0014] According to another aspect of this disclosure, an artificial intelligence chip is provided, the chip including the data processing device described above.

[0015] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned artificial intelligence chip.

[0016] According to another aspect of this disclosure, a board is provided, the board comprising: a storage device, an interface device, a control device, and the aforementioned artificial intelligence chip;

[0017] The artificial intelligence chip is connected to the storage device, the control device, and the interface device, respectively; the storage device is used to store data.

[0018] The interface device is used to realize data transmission between the artificial intelligence chip and external devices;

[0019] The controller is used to monitor the state of the artificial intelligence chip.

[0020] According to embodiments of this disclosure, vector expansion and storage can be achieved through the expansion parameters in the vector expansion instruction to obtain expanded vector data, thereby simplifying the processing and reducing data overhead.

[0021] By deducing the technical features in the claim, beneficial effects can be achieved to address the technical problems in the background art. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0023] Figure 1 A schematic diagram of a processor for a data processing method according to an embodiment of the present disclosure is shown.

[0024] Figure 2 A flowchart illustrating a data processing method according to an embodiment of the present disclosure is shown.

[0025] Figure 3 A block diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0026] Figure 4 A structural block diagram of a board according to an embodiment of the present disclosure is shown. Detailed Implementation

[0027] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0028] It should be understood that the terms “comprising” and “including” used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0029] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0030] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0031] The data processing method according to embodiments of this disclosure can be applied to a processor, which can be a general-purpose processor, such as a CPU (Central Processing Unit), or an artificial intelligence processor (IPU) for performing artificial intelligence operations. Artificial intelligence operations can include machine learning operations, neuromorphic operations, etc. Machine learning operations include neural network operations, k-means operations, support vector machine operations, etc. The artificial intelligence processor can, for example, include one or a combination of GPU (Graphics Processing Unit), NPU (Neural-Network Processing Unit), DSP (Digital Signal Processing Unit), and Field-Programmable Gate Array (FPGA) chips. This disclosure does not limit the specific type of processor.

[0032] In one possible implementation, the processor mentioned in this disclosure may include multiple processing units, each of which can independently run various assigned tasks, such as convolution operations, pooling tasks, or fully connected tasks. This disclosure does not limit the processing units or the tasks they run.

[0033] Figure 1 A schematic diagram of a processor for a data processing method according to an embodiment of the present disclosure is shown. Figure 1 As shown, the processor 100 includes multiple processing units 101 and storage units 102. The processing units 101 are used to execute instruction sequences, and the storage units 102 are used to store data, and may include random access memory (RAM) and a register file. The multiple processing units 101 in the processor 100 may share some storage space, such as sharing some RAM storage space and register file, or they may each have their own storage space.

[0034] Figure 2 A flowchart illustrating a data processing method according to an embodiment of this disclosure is shown. Figure 2 As shown, the method includes:

[0035] In step S11: when the decoded processing instruction is a vector extension instruction, the source data address, destination data address, and extension parameters of the data corresponding to the processing instruction are determined;

[0036] In step S12: the first vector data of the source data address is extended according to the extension parameters to obtain the extended second vector data;

[0037] In step S13, the second vector data is stored at the destination data address.

[0038] The source data address and the destination data address include consecutive data addresses.

[0039] According to embodiments of this disclosure, vector expansion and storage can be achieved through the expansion parameters in the vector expansion instruction to obtain expanded vector data, thereby simplifying the processing and reducing data overhead.

[0040] In one possible implementation, the method further includes: decoding the received processing instruction to obtain a decoded processing instruction. The decoded processing instruction includes an opcode, which is used to indicate vector expansion processing.

[0041] For example, when a processor receives a processing instruction, it can decode the received instruction to obtain a decoded processing instruction. This decoded processing instruction includes an opcode and an operation field. The opcode indicates the processing type of the instruction, and the operation field indicates the data to be processed and its parameters. If the opcode of the decoded processing instruction indicates vector extension processing, then the instruction is a vector extension instruction.

[0042] In one possible implementation, if the decoded processing instruction is a vector extension instruction, then in step S11, the source data address, destination data address, and extension parameters of the data corresponding to the processing instruction can be determined. The data corresponding to the processing instruction is the first vector data indicated by the operation field of the processing instruction, which includes multiple data points. The source data address represents the current data storage address of the multiple data points in the data storage space, and is a consecutive data address; the destination data address represents the data storage address of the multiple data points used to store the extended second vector data, and is also a consecutive data address. The data storage space where the source data address is located and the data storage space where the destination data address is located can be the same or different, and this disclosure does not impose any restrictions on this.

[0043] In one possible implementation, after determining the source data address and the extension parameters, the processor can read multiple data points of the first vector data from the source data address in step S12, and extend the multiple data points read according to the extension parameters to obtain multiple data points of the extended second vector data, thereby realizing vector extension.

[0044] In one possible implementation, multiple data points of the expanded second vector data can be sequentially stored in the destination data address to obtain the second vector data, thereby completing the vector expansion process.

[0045] In this way, when vector data needs to be expanded in applications such as image recognition, the original vector can be expanded into a new vector through vector expansion instructions and stored in a contiguous address space, thereby simplifying the processing and reducing data overhead.

[0046] In one possible implementation, step S11 may include: determining the source data address of the plurality of data points based on the source data base address and data size of the plurality of data points of the first vector data in the operation domain of the processing instruction.

[0047] For example, a vector expansion instruction may have an operation field that indicates parameters for the vector data to be expanded. The operation field may include, for example, the source data base address, the destination data base address, the single-point data size, the single-point data number, and expansion parameters.

[0048] Wherein, the source data base address can represent the base address of multiple data points of the first vector data in the current data storage space; the destination data base address can represent the base address of multiple data points of the expanded second vector data in the data storage space; the size of a single data point can represent the data size of each data point of the first and second vector data (e.g., 4 bits or 8 bits); the number of a single data point can represent the number N of data points of the first vector data (N is an integer greater than 1); the expansion parameter can indicate the expansion method of the N data points of the first vector data. This disclosure does not limit the specific number and type of parameters in the operation domain of the vector expansion instruction.

[0049] In one possible implementation, the operation domain of the vector extension instruction may include the source data base address and the single-point data size. Since the source data addresses are consecutive data addresses, the source data address of each data point can be determined directly based on its data size and its index. The source data address of the nth data point can be represented as:

[0050] Single Point Src Addr[n]= Source Data Base Address +n*Single PointData Size (1)

[0051] In formula (1), Single Point Src Addr[n] represents the source data address of the nth data point. When the source data base address is, for example, Addr1[0, 3], the size of a single data point is 4 bits, and n is 3, the source data address of the 3rd data point can be determined as Addr1[12, 15].

[0052] In this way, the source data address of each data point can be determined separately, so that each data point of the first vector data can be read from the source data address.

[0053] In one possible implementation, the first vector data includes N data points, where N is an integer greater than 1. Correspondingly, the extended parameters include N extended parameter bits corresponding to the N data points. Step S12 may include:

[0054] For the nth data point of the first vector data and the nth extended parameter bit corresponding to the nth data point, determine the k of the nth data position of the second vector data. n There are n data points, 1 ≤ n ≤ N, and k n ≥0;

[0055] The second vector data is determined based on the data points at N data positions of the second vector data.

[0056] For example, the extended parameters may include N extended parameter bits, each representing the number of times k of the N data points of the first vector data are copied. n For example, when N=5, the extended parameters can be represented as [1,2,0,3,1], which means that the 5 data points are copied 1 time, 2 times, 0 times, 3 times, and 1 time respectively.

[0057] In one possible implementation, for the nth data point (1≤n≤N) of the first vector data, the nth extended parameter bit corresponding to the nth data point is k. n (k n If k ≥ 0), then the nth data position of the second vector data can be determined to have k n The nth data point of the first vector data. In this way, by expanding the N data points of the first vector data, the N data points of the second vector data can be determined. For example, if the first vector data is [A,B,C,D,E], the expansion parameters can be [1,2,0,3,1], and after expansion, the second vector data obtained is [A,B,B,D,D,D,E].

[0058] It should be understood that extended parameters may also include other extended content (such as magnifying or reducing the value of each data point by a certain factor), and extended parameters may also include other representation methods. Those skilled in the art can set them according to the actual situation, and this disclosure does not limit them.

[0059] In this way, the expanded second vector data can be obtained.

[0060] In one possible implementation, step S13 may include: storing each data point of the second vector data sequentially according to the destination data base address and data size of the destination data address.

[0061] For example, after obtaining the expanded second vector data, the second vector data can be stored in a preset destination data address. The operation field of the vector expansion instruction can include the destination database address, and the destination data address of each data point of the second vector data can be determined based on the destination database address and the data size of a single data point.

[0062] Single Point Dest Addr[m]=Destination Data Base Address+m*SinglePoint Data Size (2)

[0063] In formula (2), Single Point Src Addr[m] represents the destination data address of the m-th data point of the second vector data (the second vector data includes M data points, 1≤m≤M, where M is an integer greater than 1). When the destination data base address is, for example, Addr2[14,17], the size of a single data point is 4 bits, and m is 3, the source data address of the 3rd data point can be determined as Addr2[26,29].

[0064] In this way, each data point of the second vector data can be stored sequentially into the destination data address, thus completing the entire process of vector expansion.

[0065] According to the data processing method of this disclosure, vectors can be extended by vector extension instructions. In application scenarios such as image recognition, when vector data needs to be extended, the original vector can be extended into a new vector and stored in a contiguous address space, thereby simplifying the processing and reducing data overhead.

[0066] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0067] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0068] Figure 3 A block diagram of a data processing apparatus according to an embodiment of the present disclosure is shown. Figure 3 As shown, the device includes:

[0069] Address determination module 31 is used to determine the source data address, destination data address and extended parameters of the data corresponding to the processing instruction when the decoded processing instruction is a vector extension instruction;

[0070] Data expansion module 32 is used to expand the first vector data of the source data address according to the expansion parameters to obtain the expanded second vector data;

[0071] Data storage module 33 is used to store the second vector data to the destination data address.

[0072] The source data address and the destination data address include consecutive data addresses.

[0073] In one possible implementation, the address determination module includes:

[0074] The source address determination submodule is used to determine the source data address of the multiple data points based on the source data base address and data size of multiple data points of the first vector data in the operation domain of the processing instruction.

[0075] In one possible implementation, the first vector data includes N data points, and the extended parameters include N extended parameter bits corresponding to the N data points, where N is an integer greater than 1.

[0076] The data expansion module includes:

[0077] The data point determination submodule is used to determine the k of the nth data position of the second vector data based on the nth data point of the first vector data and the nth extended parameter bit corresponding to the nth data point. n There are n data points, 1 ≤ n ≤ N, and k n ≥0;

[0078] The data determination submodule is used to determine the second vector data based on the data points at N data positions of the second vector data.

[0079] In one possible implementation, the data storage module includes:

[0080] The storage submodule is used to sequentially store each data point of the second vector data according to the destination data base address and data size of the destination data address.

[0081] In one possible implementation, the device further includes:

[0082] The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions.

[0083] The decoded processing instructions include an opcode, which is used to indicate vector expansion processing.

[0084] It should be understood that the above-described device embodiments are merely illustrative, and the device disclosed herein can be implemented in other ways. For example, the division of units / modules described in the above embodiments is only a logical functional division, and other division methods may be used in actual implementation. For example, multiple units, modules, or components may be combined, integrated into another system, or some features may be ignored or not executed.

[0085] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this disclosure can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0086] If the integrated unit / module is implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the artificial intelligence processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0087] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0088] In one possible implementation, an artificial intelligence chip is also disclosed, which includes the aforementioned data processing device.

[0089] In one possible implementation, an electronic device is also disclosed, which includes the aforementioned artificial intelligence chip.

[0090] In one possible implementation, a board is also disclosed, which includes a storage device, an interface device, a controller, and the aforementioned artificial intelligence chip; wherein the artificial intelligence chip is connected to the storage device, the controller, and the interface device respectively; the storage device is used to store data; the interface device is used to realize data transmission between the artificial intelligence chip and external devices; and the controller is used to monitor the status of the artificial intelligence chip.

[0091] Figure 4 A structural block diagram of a board according to an embodiment of the present disclosure is shown. (See attached diagram.) Figure 4 In addition to the chip 389, the aforementioned board may also include other supporting components, including but not limited to: storage device 390, interface device 391, and controller 392.

[0092] The storage device 390 is connected to the artificial intelligence chip via a bus and is used to store data. The storage device may include multiple sets of storage units 393. Each set of storage units is connected to the artificial intelligence chip via a bus. It can be understood that each set of storage units may be DDR SDRAM (Double Data Rate SDRAM).

[0093] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include four groups of storage cells. Each group of storage cells may include multiple DDR4 chips. In one embodiment, the AI ​​chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 chips are used in each group of storage cells, the theoretical data transmission bandwidth can reach 25600MB / s.

[0094] In one embodiment, each group of memory cells includes multiple Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs) arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling the DDR is provided in the chip for controlling the data transfer and data storage of each memory cell.

[0095] The interface device is electrically connected to the artificial intelligence chip. The interface device is used to realize data transmission between the artificial intelligence chip and external devices (e.g., servers or computers). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the chip via a standard PCIe interface, realizing data transfer. Preferably, when using a PCIe 3.0 x 16 interface, the theoretical bandwidth can reach 16000 MB / s. In another embodiment, the interface device can also be other interfaces; this disclosure does not limit the specific form of the other interfaces mentioned above, as long as the interface unit can realize the switching function. Furthermore, the calculation results of the artificial intelligence chip are still transmitted back to the external device (e.g., the server) by the interface device.

[0096] The controller is electrically connected to the artificial intelligence chip. The controller monitors the state of the artificial intelligence chip. Specifically, the artificial intelligence chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller (MCU). The artificial intelligence chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, capable of driving multiple loads. Therefore, the artificial intelligence chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the artificial intelligence chip.

[0097] In one possible implementation, an electronic device is disclosed that includes the aforementioned artificial intelligence chip. The electronic device includes data processing devices, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, dashcams, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound scanners, and / or electrocardiographs.

[0098] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0099] The foregoing can be better understood in accordance with the following terms:

[0100] Clause A1. A data processing method, comprising:

[0101] When the decoded processing instruction is a vector extension instruction, determine the source data address, destination data address, and extension parameters of the data corresponding to the processing instruction;

[0102] Based on the expansion parameters, the first vector data of the source data address is expanded to obtain the expanded second vector data;

[0103] The second vector data is stored in the destination data address.

[0104] The source data address and the destination data address include consecutive data addresses.

[0105] A2. According to the method described in A1, when the decoded processing instruction is a vector extension instruction, the source data address, destination data address, and extension parameters of the data corresponding to the processing instruction are determined, including:

[0106] The source data addresses of the multiple data points are determined based on the source data base addresses and data dimensions of the multiple data points of the first vector data in the operation domain of the processing instruction.

[0107] A3. According to the method described in A1 or A2, the first vector data includes N data points, and the extended parameters include N extended parameter bits corresponding to the N data points, where N is an integer greater than 1.

[0108] The step of expanding the first vector data of the source data address according to the expansion parameters to obtain the expanded second vector data includes:

[0109] Based on the nth data point of the first vector data and the nth extended parameter bit corresponding to the nth data point, determine the k of the nth data position of the second vector data. n There are n data points, 1 ≤ n ≤ N, and k n ≥0;

[0110] The second vector data is determined based on the data points at N data positions of the second vector data.

[0111] A4. Storing the second vector data at the destination data address according to any one of A1-A3, including:

[0112] Based on the destination data base address and data size of the destination data address, the data points of the second vector data are stored sequentially.

[0113] A5. The method according to any one of A1-A4, the method further comprising:

[0114] The received processing instructions are decoded to obtain the decoded processing instructions.

[0115] The decoded processing instructions include an opcode, which is used to indicate vector expansion processing.

[0116] A6. A data processing apparatus, comprising:

[0117] The address determination module is used to determine the source data address, destination data address, and extended parameters of the data corresponding to the decoded processing instruction when the decoded processing instruction is a vector extension instruction.

[0118] The data expansion module is used to expand the first vector data of the source data address according to the expansion parameters to obtain the expanded second vector data;

[0119] The data storage module is used to store the second vector data to the destination data address.

[0120] The source data address and the destination data address include consecutive data addresses.

[0121] A7. According to the apparatus described in A6, the address determination module includes:

[0122] The source address determination submodule is used to determine the source data address of the multiple data points based on the source data base address and data size of multiple data points of the first vector data in the operation domain of the processing instruction.

[0123] A8. According to the apparatus described in A6 or A7, the first vector data includes N data points, the extended parameters include N extended parameter bits corresponding to the N data points, where N is an integer greater than 1, and the data extension module includes:

[0124] The data point determination submodule is used to determine the k of the nth data position of the second vector data based on the nth data point of the first vector data and the nth extended parameter bit corresponding to the nth data point. n There are n data points, 1 ≤ n ≤ N, and k n ≥0;

[0125] The data determination submodule is used to determine the second vector data based on the data points at N data positions of the second vector data.

[0126] A9. The apparatus according to any one of A6-A8, the data storage module comprising:

[0127] The storage submodule is used to sequentially store each data point of the second vector data according to the destination data base address and data size of the destination data address.

[0128] A10. The apparatus according to any one of A6-A9, the apparatus further comprising:

[0129] The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions.

[0130] The decoded processing instructions include an opcode, which is used to indicate vector expansion processing.

[0131] A11. An artificial intelligence chip, the chip comprising a data processing device as described in any one of A6-A10.

[0132] A12. An electronic device comprising an artificial intelligence chip as described in A11.

[0133] A13. A board, the board comprising: a storage device, an interface device, and a control device, as well as an artificial intelligence chip as described in A11;

[0134] The artificial intelligence chip is connected to the storage device, the control device, and the interface device, respectively.

[0135] The storage device is used to store data;

[0136] The interface device is used to realize data transmission between the artificial intelligence chip and external devices;

[0137] The controller is used to monitor the state of the artificial intelligence chip.

[0138] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A data processing method, characterized by, include: When the decoded processing instruction is a vector extension instruction, the source data address, destination data address, and extension parameters of the data corresponding to the processing instruction are determined, and the vector extension instruction contains the extension parameters. Based on the expansion parameters, the first vector data of the source data address is expanded to obtain the expanded second vector data; The second vector data is stored in the destination data address. The source data address and the destination data address include consecutive data addresses; The first vector data includes N data points, and the extended parameters include N extended parameter bits corresponding to the N data points, where N is an integer greater than 1. The step of expanding the first vector data of the source data address according to the expansion parameters to obtain the expanded second vector data includes: According to the n th data point of the first vector data and the n th extended parameter bit corresponding to the n th data point, the k n th data point of the n th data position of the second vector data is determined, 1≤n≤N, k n ≥0; The second vector data is determined based on the data points at N data positions of the second vector data.

2. The method of claim 1, wherein, When the decoded processing instruction is a vector extension instruction, the source data address, destination data address, and extension parameters of the data corresponding to the processing instruction are determined, including: The source data addresses of the multiple data points are determined based on the source data base addresses and data dimensions of the multiple data points of the first vector data in the operation domain of the processing instruction.

3. The method of claim 1 or 2, wherein, Storing the second vector data at the destination data address includes: Based on the destination data base address and data size of the destination data address, the data points of the second vector data are stored sequentially.

4. The method of claim 1 or 2, wherein, The method further includes: The received processing instructions are decoded to obtain the decoded processing instructions. The decoded processing instructions include an opcode, which is used to indicate vector expansion processing.

5. A data processing apparatus, characterized by, include: The address determination module is used to determine the source data address, destination data address and extension parameters of the data corresponding to the decoded processing instruction when the decoded processing instruction is a vector extension instruction. The vector extension instruction includes extension parameters. The data expansion module is used to expand the first vector data of the source data address according to the expansion parameters to obtain the expanded second vector data; The data storage module is used to store the second vector data to the destination data address. The source data address and the destination data address include consecutive data addresses; The first vector data includes N data points, and the extended parameters include N extended parameter bits corresponding to the N data points, where N is an integer greater than 1. The data expansion module includes: The data point determination sub-module is configured to determine the k n data points of the nth data position of the second vector data according to the nth data point of the first vector data and the nth extended parameter bit corresponding to the nth data point, 1≤n≤N, and k n ≥0. The data determination submodule is used to determine the second vector data based on the data points at N data positions of the second vector data.

6. The apparatus of claim 5, wherein, The address determination module includes: The source address determination submodule is used to determine the source data address of the multiple data points based on the source data base address and data size of multiple data points of the first vector data in the operation domain of the processing instruction.

7. The apparatus of claim 5 or 6, wherein, The data storage module includes: The storage submodule is used to sequentially store each data point of the second vector data according to the destination data base address and data size of the destination data address.

8. The apparatus of claim 5 or 6, wherein, The device further includes: The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions. The decoded processing instructions include an opcode, which is used to indicate vector expansion processing.

9. An artificial intelligence chip, characterized by, The chip includes a data processing device as described in any one of claims 5-8.

10. An electronic device, comprising: The electronic device includes the artificial intelligence chip as described in claim 9.

11. A board card, characterized by The board includes: storage devices, interface devices, and control devices, as well as the artificial intelligence chip as described in claim 9; The artificial intelligence chip is connected to the storage device, the control device, and the interface device, respectively. The storage device is used to store data; The interface device is used to realize data transmission between the artificial intelligence chip and external devices; The controller is used to monitor the state of the artificial intelligence chip.

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