Data processing apparatus and method

Abstract

The present disclosure relates to adaptive load coalescing. Apparatuses and methods for processing load requests are disclosed. In response to a load request specifying data items to be fetched from memory, a series of data items is fetched that includes the data items identified by the load request. The load request is buffered prior to the load request being executed. A coalescing circuit determines whether an address adjacency condition is true for the load request and a set of one or more other load requests buffered in a pending load buffer circuit. The address adjacency condition is true when all data items identified by the set of one or more other load requests are included within the series of data items. The set of one or more other load requests is suppressed when the address adjacency condition is true. A coalescing prediction circuit generates a coalescing prediction for each load request based on previous processing of the load request by the coalescing circuit.

Description

Technical Field

[0001] This technology relates to data processing. More specifically, this technology relates to the processing of load requests in a data processing apparatus. Background Technology

[0002] During a loading operation, the data processing device can be provided with the ability to combine certain loads that have been identified as having an appropriate degree of spatial proximity, so that they can be served simultaneously. More specifically, it can be identified that the spatial proximity between two load requests is sufficiently close that only one memory access is required, which will return the data requested by each of the spatially adjacent load requests. Summary of the Invention

[0003] At least some examples provide an apparatus comprising: a load processing circuit that, in response to a load request for a specified data item, retrieves from memory a series of data items including data items identified by the load request; a pending load buffer circuit that buffers a load request before it is executed by the load processing circuit to retrieve the data items specified by the load request from memory; a merging circuit that determines whether an address proximity condition is true for the load request and a set of one or more other load requests buffered in the pending load buffer circuit, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the series of data items, wherein the merging circuit suppresses processing of the set of one or more other load requests by the load processing circuit in response to the address proximity condition being true; and a merge prediction circuit that generates a merge prediction for the load request based on previous processing of the load request by the merging circuit.

[0004] At least some examples provide a data processing method comprising: buffering a load request to retrieve a data item specified by the load request from memory before the load request is executed, wherein executing the load request for the specified data item includes retrieving from memory a series of data items including data items identified by the load request; determining whether an address proximity condition is true for the load request and a buffered set of one or more other load requests, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the series of data items; suppressing the execution of the set of one or more other load requests when the address proximity condition is true; and generating a merge prediction for the load request based on previous processing of the load request.

[0005] At least some examples provide an apparatus comprising: means for buffering a load request to retrieve data items specified by the load request from memory before the load request is executed, wherein executing the load request for the specified data items includes retrieving from memory a series of data items including data items identified by the load request; means for determining whether an address proximity condition is true for the load request and a set of one or more other buffered load requests, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the series of data items; means for suppressing the execution of the set of one or more other load requests when the address proximity condition is true; and means for generating a merge prediction for the load request based on previous processing of the load request. Attached Figure Description

[0006] The present technology will be further described by way of example only, with reference to embodiments of the technology shown in the accompanying drawings, which will be read in conjunction with the following description, in which: Figure 1 The schematic illustration shows an apparatus according to some example embodiments, including a load processing circuit with the ability to merge some pending loads; Figure 2A The schematic illustration shows an apparatus according to some example embodiments, including a load processing circuit with the ability to merge some pending loads; Figure 2B The schematic illustration shows the interaction between the pending load buffer and the merging circuitry according to some example embodiments; Figure 3 The schematic illustration shows an apparatus according to some example embodiments, including a load processing circuit with the ability to merge some pending loads; Figure 4A The schematic illustration shows a merging prediction circuit according to some example embodiments; Figure 4B The schematic illustration shows a merging prediction circuit according to some example embodiments; Figure 5A The schematic illustrations show hash generation circuits and Bloom filter circuits in some example embodiments; Figure 5B The schematic illustration shows an apparatus according to some example embodiments; and Figure 6 This is a flowchart illustrating a sequence of steps taken according to some example embodiments. Detailed Implementation

[0007] In one example, an apparatus includes: a load processing circuit that, in response to a load request for a specified data item, retrieves from memory a series of data items including data items identified by the load request; a pending load buffer circuit that buffers the load request before it is executed by the load processing circuit to retrieve the data item specified by the load request from memory; a merging circuit that determines whether an address proximity condition is true for the load request and a set of one or more other load requests buffered in the pending load buffer circuit, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the series of data items, wherein the merging circuit suppresses processing of the set of one or more other load requests by the load processing circuit in response to the address proximity condition being true; and a merge prediction circuit that generates a merge prediction for the load request based on the merging circuit's previous processing of the load request.

[0008] Merging load requests is based on identifying that load requests are spatially sufficiently close (in terms of the memory locations they reference) to be served by a "merged" memory access. This spatial proximity, which may be referred to herein as the "address proximity condition," is true for the relevant load request. The opportunity to merge load requests in this way arises in systems where load processing circuitry responds to a load request specifying a data item to be fetched from memory, typically retrieving more than just the data item itself as part of a triggered memory access. This is due to the efficiency gained by constraining memory accesses to a specific data size, such as aligning them with the cache line size in the system (although this technique is not limited to this particular choice and applies equally to other memory sizes). In general, while using merging circuitry to determine whether pending load requests can be merged incurs a certain cost, there are cases where the increased latency incurred by the merging circuitry can be offset by an improvement in memory access bandwidth, which can be substantial enough to achieve an overall performance improvement; for example, a significant portion of the load instructions can be merged. Nevertheless, the inventors of this technology have recognized that when only a relatively small number of load instructions can be successfully merged, the increased latency due to the additional merging process may outweigh the benefits. Therefore, this technology proposes providing a merge prediction circuit, arranged to generate a prediction, based on the merging circuit's prior processing of load requests, whether a given load request will be merged with other load requests. This merge prediction can then be utilized by the device in various ways, for example, to modify its behavior regarding a particular load request.

[0009] In some embodiments, the merging circuitry suppresses processing of load requests in response to a merging prediction that the load request will not be merged with other load requests. Thus, as a possible response to a generated prediction that the load request will not be merged with other load requests, the merging circuitry can avoid processing this load request and therefore save processing effort when it is expected that the load request will not be merged.

[0010] Information regarding the merging circuit's previous processing of load requests can be provided in various ways, but in some embodiments, the apparatus also includes a feedback path from the merging circuit to the merging prediction circuit, wherein the merging circuit, in response to the validity of the address proximity condition, notifies the merging prediction circuit via the feedback path of the merging result depending on the validity of the address proximity condition of the load request. Therefore, based on the merging circuit's determination of the address proximity condition of the load request, the merging circuit can notify the merging prediction circuit of the merging result. Depending on the configuration, this can be a positive or negative configuration; that is, the merging circuit can be arranged to specifically indicate to the merging prediction circuit load requests that have not yet been merged, or the merging circuit can notify the merging prediction circuit of those load requests that have been merged. The merging prediction circuit can then appropriately collect this information, and it can make future predictions based on this information.

[0011] The merge prediction circuit can be configured in various ways, but in some embodiments, the merge prediction circuit includes a merge history store to hold content that depends on the previous processing of the load request by the merge circuit, and the merge prediction circuit is arranged to generate a merge prediction for the load request based on the content of the merge history store.

[0012] The content held by the merge history storage can take various forms, but in some embodiments, it includes a probabilistic data structure. In some embodiments, this content may explicitly correspond to previous merge history results, but in other embodiments, it may be simplified probabilistically. Probabilistic history storage reduces the required storage capacity.

[0013] In some example embodiments, merging historical storage includes a Bloom filter.

[0014] In some embodiments, the apparatus further includes a hash generation unit for generating the content of a probabilistic data structure, wherein the hash generation unit includes a hash sequencer to generate the content of the probabilistic data structure in multiple hashing stages. Arranging hash sequences to generate the content of the probabilistic data structure in multiple hashing stages simplifies hardware implementation.

[0015] In cases where the probabilistic data structure (e.g., a Bloom filter) depends on an evolving data structure that asymmetrically captures the merge history—that is, the Bloom filter can be arranged to provide information about whether a particular load is necessarily merged or whether it might (but is uncertain) not be merged—the evolving nature of the data structure means that the false positive rate (e.g., a merged load being marked as not merged) generally increases over time. Therefore, in some embodiments, the device includes reset circuitry to reset the contents of the merge history storage in response to at least one of the following: the elapsed time period; the receipt of a scenario switching instruction; and / or the reaching of a predetermined fullness in the merge history storage.

[0016] As described above, the apparatus can be arranged in various ways to utilize the merge prediction generated by the merge prediction circuit. However, in some embodiments, the apparatus also includes a bypass path leading to the load processing circuit and bypassing the merge circuit, wherein the merge prediction circuit, in response to a non-mergeable merge prediction, provides a load request to the load processing circuit via the bypass path. Thus, the provision of the bypass path allows load requests identified as non-mergeable to proceed directly to the load processing circuit without being processed by the merge circuit.

[0017] In some embodiments, the apparatus further includes: a second load processing circuit that, in response to a load request for a specified data item, retrieves from memory a series of data items including the data item identified by the load request; and a load processing selection circuit that, in response to a merge prediction generated by a merge prediction circuit, directs the load request via a pending load buffer circuit to the load processing circuit, or to the second load processing circuit, in accordance with the merge prediction. Thus, according to this embodiment, the load processing circuit of the apparatus is "doubled" (by providing a second load processing circuit), and the load processing selection circuit can then use the merge prediction to either provide the load request to the load processing circuit via the pending load buffer circuit (and thus to be potentially merged via the merging circuit), or directly to the second load processing circuit (so that merging is not even attempted).

[0018] In some such embodiments, the apparatus further includes: a first load request dispatch queue for feeding to a pending load buffer circuit; and a second load request dispatch queue for feeding to a second load processing circuit, wherein the load processing selection circuit, in response to a merge prediction generated by the merge prediction circuit, directs a load request to either the first load request dispatch queue or the second load request dispatch queue, in accordance with the merge prediction. This arrangement thereby achieves a deeper level of decoupling of the paths to the (first) load processing circuit and the second load processing circuit, achieved by providing dedicated dispatch queues before each of them, namely a "merged" dispatch queue for the (first) load processing circuit path and a "non-merged" dispatch queue leading to the second load processing circuit.

[0019] The generated merge predictions can also be stored in various locations within the device, and in some embodiments, where the load request originates from a load instruction, the device also includes an instruction cache store to store entries for frequently used instructions, wherein the instruction cache store is arranged to store merge predictions in association with the load instruction. This allows for efficient utilization of the merge predictions when the load instruction is encountered again, with reduced latency.

[0020] Instruction cache storage can be, for example, a micro-operation cache.

[0021] In some embodiments, the apparatus further includes data dependency determination circuitry to determine data dependencies between instructions, wherein merge prediction circuitry is arranged to generate merge predictions in accordance with at least one data dependency determined by the data dependency determination circuitry. It has been found that, in certain circumstances, information relating to data dependencies between instructions is useful for determining the likelihood of merging. Generally, some load instructions directly (or to a very low degree indirectly) provide input values ​​to other nearby load instructions, and merging tends not to occur for loads accessing pointers. Therefore, the information generated by the data dependency determination circuitry can provide a basis for classifying instructions as merged or non-merged based on their dependencies and / or what dependent instructions might depend on them.

[0022] Data compliance determination circuitry may include, for example, register renaming circuitry.

[0023] In some embodiments, the merge prediction circuitry is configured to generate a merge prediction for a load request by default. Since this requires sending a load command at least once via the merge hardware to determine the probability of merging with other loads in flight, this corresponds to the device's default behavior being to merge.

[0024] In one example here, a data processing method includes: buffering a load request to retrieve a data item specified by the load request from memory before the load request is executed, wherein executing the load request for the specified data item includes retrieving a series of data items from memory that include data items identified by the load request; determining whether an address proximity condition is true for the load request and a buffered set of one or more other load requests, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the series of data items; suppressing the execution of the set of one or more other load requests when the address proximity condition is true; and generating a merge prediction for the load request based on previous processing of the load request.

[0025] In one example here, an apparatus includes: means for buffering a load request to retrieve data items specified by the load request from memory before the load request is executed, wherein executing the load request for the specified data items includes retrieving from memory a series of data items including data items identified by the load request; means for determining whether an address proximity condition is true for the load request and a set of one or more other buffered load requests, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the series of data items; means for suppressing the execution of the set of one or more other load requests when the address proximity condition is true; and means for generating a merge prediction for the load request based on previous processing of the load request.

[0026] Some specific embodiments will now be described with reference to the accompanying drawings.

[0027] Figure 1A schematic illustration shows an apparatus 10 arranged to receive load requests (e.g., generated by data processing circuitry in response to load instructions identified in executing program code) and generate memory accesses to serve these load requests. Apparatus 10 includes a load unit 12 that generates memory accesses in response to received load requests. Apparatus 10 also includes a pending load buffer 14 in which received load requests are held before being processed by the load unit 12. Apparatus 10 further includes a merger (merging circuitry) 16 that receives contents from the pending load buffer 14 and, where possible, merges one or more load requests such that they are processed by the load unit 12 as a single item, specifically generating only a single memory access request. The merger 16 is arranged to determine whether two (or more) load requests can be merged based on an address proximity condition. The address proximity condition is defined based on the arrangement of the load unit 12, i.e., in response to a given (individual) load request, the load unit generates a memory access that causes a series of data items to be retrieved from memory. For example, in some embodiments, this series of data items may correspond to the cache line size in a broader data processing system in which the device 10 forms part. That is, data is retrieved from memory in blocks of cache line size. Thus, when a second (or more) load request involves data items that will in any case be retrieved from memory by another (first) pending request, an opportunity arises to merge pending load requests due to the fact that the first load request will cause the retrieval of a series of data items, which includes one or more data items specified by the second (or more) load request. In the example of cache line-size data retrieval, the second (or more) load request involves data items within the same cache line as the first load request. Note that the labels “first” and “second” load requests are used here only to distinguish load requests and do not impose the necessary ordering on them during processing by the merger 16.

[0028] The apparatus 10 also includes a merge predictor arranged to receive an indication of an incoming load request (e.g., at least a portion of a load instruction address) and to generate a merge prediction based on information associated with the load request, based on previous encounters with that load request. The apparatus 10 also includes a path selection circuit 20 arranged to pass the incoming load request to the pending load buffer 14 or directly to the load unit 12. This path selection is based on the output of the merge predictor circuit. Therefore, based on how the apparatus 10 previously processed a given load request, the path selection circuit 20 selects the route the load request will take as it passes through the apparatus. Specifically, when a load request is not expected to be merged, it can be passed directly to the load unit 12, thus avoiding the processing associated with the path via the pending load buffer 14 and the merger 16.

[0029] Figure 2A The schematic illustrations depict apparatus 50 in some example embodiments. In a manner familiar to those skilled in the art, apparatus 50 is arranged in a pipelined manner to process instructions, and thus through a series of stages, namely, an acquisition stage 52, a decoding stage 54, a micro-operation buffer 56, a renaming stage 58, and an instruction queue 60. Those skilled in the art will also understand that many other components and stages are possible, but... Figure 2AThe choices shown are merely representative for the purpose of understanding this technique. According to the illustrated arrangement, fetch stage 52 causes instructions from a sequence of instructions defined in the program code to be retrieved from memory, and these instructions are passed to decode stage 54 for decoding. The decoded instructions can be stored in micro-operation cache 56 and then processed by renaming stage 58 (where device 50 is an out-of-order data processing device). Instructions queued in instruction queue 60 may then be passed to several destinations depending on their type, but the focus of this disclosure is on processing load instructions that generate load requests, and these instructions are passed from instruction queue 60 to register read stage 62 and then to address generation stage 64. Thus, it can be seen that the arrangement of device 50 includes “early” address resolution (regarding operations on load unit 72), which is useful in the context of this technique (i.e., when seeking to merge some pending loads) because it provides the device with sufficient (simultaneous) visibility of pending loads in flight (while they are held in pending load buffer 68) so as to make timely decisions about which loads should be grouped together (merged). The indication of a load instruction (which will trigger a load request) is also passed from the decoding stage 52 to the merge predictor 66, which is configured to generate a merge prediction based on this indication of the load instruction (e.g., the load instruction address), i.e., whether this load instruction is expected to result in a load request that will be merged with at least one other common pending load request. This is done based on the previous processing of the load request by the merging circuit (i.e., the merger 70). This merge prediction is communicated to the address generation circuit 64, which selects a forward path for each load request based on the received merge prediction. These forward paths lead to the loading unit 72. The first path is via the pending load buffer 68 and the merger 70, and the second path leads directly from the address generation circuit 64 to the loading unit 72. Therefore, in general, when a load request processed by the address generation circuit 64 is expected to be merged, it is passed via the first path (via the pending load buffer 68 and the merger 70 to attempt to merge with other pending loads held in the pending load buffer 68). Alternatively, when a pending load is not expected to merge, it is passed directly to the load unit 72. Since it is necessary to send a pending load at least once via the merging hardware to determine its probability of merging with other pending loads in flight, the default behavior of device 50 is a merge attempt; that is, initially all pending loads are assumed to be merge loads and will be passed via the pending load buffer 68 and the merger 70. However, once a pending load reaches the merger 70 and its merging is determined to have failed, the merger 70 notifies the merge predictor 66 of this failure.The merge predictor 66 then establishes a record indicating those loads that failed to merge in the past, and based on this, when they are encountered again, the signal from the merge predictor 66 to the address generation circuit 64 can cause these non-mergeable load requests to bypass the merge circuit 70 and proceed directly to the load unit 72. By reducing the number of pending loads passing through the pending load buffer, this also simplifies the structure of the pending load buffer 68 and the search logic for comparing various permutations of pending loads.

[0030] Also note that the output of the merge predictor 66 is... Figure 2A The output of the merge predictor 66 is also shown as being passed to the decoding circuit 54. Thus, the decoding circuit can, on the one hand, annotate decoded load instructions with its merge prediction indications, and on the other hand, it can maintain a record of merge predictions for at least some frequently decoded load instructions, thereby enabling these to be decoded more quickly. The output of the merge predictor 66 can also be passed to any other pipeline stage ( Figure 2A The dotted lines in the diagram can be used to store information in association with certain load instructions (e.g., in a micro-operation cache) or to annotate decoded load instructions as they pass through the pipeline using indications of their merge predictions (e.g., for timing purposes, which in some cases may preferably be performed downstream of decoding stage 54). Various configurations of the merge predictor 66, particularly the way it stores information relating to how previous load requests were processed, are conceivable and will be referenced below. Figure 4A , 4B 5A and 5B will be discussed in more detail.

[0031] Pending loads arriving at load unit 72 subsequently trigger data retrieval. The apparatus includes an active load store 74, which holds a record of in-flight loads that have been initiated but not yet completed accesses to the memory system. Processing of load requests begins with load unit 72 passing the request to translation lookaside buffer (TLB) lookup and fault-checking circuitry 76 to perform the necessary lookup (for translation from virtual to physical addressing) and respond appropriately to any faults. Note that various cache levels (not shown) may be additionally provided; these caches may be virtually indexed or physically indexed, and access to the TLB may be modified accordingly. When the relevant series of data items is retrieved, for example after a data cache access, either as a result of a cache hit or through further levels of access to the memory system (not shown), the data read and multiplexing circuitry 78 processes the obtained data. The data item corresponding to the load request itself is extracted and passed to selector 86. The series of data items resulting from the memory access is passed via data buffer 80 to de-merge and format circuitry 82. The de-merging circuit 82 receives an indication of a merged load request from the merger 70, indicating which elements of the series of data items should be additionally extracted (to provide data items corresponding to one or more other load requests that were suppressed due to merging with the nominally processed load request). The de-merging and formatting circuit 82 then extracts the required multiple data items for the merged load request. The result is then passed via data buffer 84 to another input of selector 86. Selector 86 thus receives an input from data buffer 84 and an input from data read and multiplexing circuit 78. The selection between these two is controlled by an input provided by load unit 72 indicating whether this is a merged load. The resulting data is then stored in result buffer 88, which can also provide input to register read stage 62 as part of its processing to determine the address of the load request it received.

[0032] Figure 2B The schematic illustration depicts the interaction between a pending load buffer and merging circuitry according to some example embodiments. The pending load buffer 90 includes several entries, each capable of storing a pending load (i.e., information related to a load that has been indicated but not yet executed). Figure 2BIn the example, the pending load buffer 90 has eight entries, but in other embodiments, the pending load buffer may have more or fewer entries—the technique is not limited to any particular number of entries in the pending load buffer. Each entry is shown as including a main portion 91 and a merge instruction 92. The main portion 91 stores the aforementioned information related to each load (in particular, the address that the load will access), and the merge instruction 92 is used to mark loads that have been identified as being merged with other loads in the pending load buffer. Figure 2B In the example, the oldest pending load in the buffer provides one part of the address comparison, while the other part is provided by the address of each of the other (seven) entries in the buffer. Address comparison circuit 93 compares the address of the oldest pending load with the address of each of the other pending loads in the buffer. This comparison can examine only a portion of each address. For example, in the case where the load unit is configured to initiate a load from memory on a cache line basis, the upper portions of the addresses can be compared to determine whether two load addresses will be served by retrieving a single cache line covering both addresses. The result of the address comparison performed by address comparison circuit 93 is notified to merge control circuit 94. When there is no (sufficiently close) match between the address of the oldest pending load and other pending loads, merge control 94 passes the oldest pending load to the load unit, and it is removed from the pending load buffer (in practice, it may be simpler to allow the entry to be overwritten in the pending load buffer). Merge control 94 also notifies the merge predictor that this load merge failed. However, when at least one (sufficiently close) match is found between the address of the oldest pending load and other pending loads, the merge control 94 updates the merge indication 92 for the matching one or more other pending loads. These other pending loads are thus marked as having been merged with another load preceding them in the pipeline of the pending load buffer. When a pending load becomes the oldest, the merge indication 92 is received by the merge control circuitry 94, which can then notify the loading unit as a merged load (as described above). However, further address comparisons of the merged loads with the contents of the pending load buffer are performed, as one or more pending loads may have arrived during this period and could also be merged.

[0033] Figure 3 The schematic illustrations depict apparatus 100 in some example embodiments. Figure 2A Compared to the schematic diagrams in the text, Figure 3 The example device 100 does not show the pipeline stage preceding instruction queue 102 (but this is merely for clarity and brevity in the discussion). Load instructions in instruction queue 102 are instructed (e.g., by instruction address) to merge predictor 104, which generates merge predictions based on that instruction. Figure 2A As in the example, a merge predictor can achieve this in various ways, and it can store its information in various ways, which will be referenced below. Figure 4A , 4B 5A and 5B are discussed in more detail. The generated merge prediction is notified to path selector 106, which then causes the load request to follow one of two paths through device 100. Based on the first path, i.e., the path caused by the merge prediction, the pending load request is passed to the coalescing issue queue (CIQ) 108. Alternatively, the non-coalescing prediction causes path selector 106 to pass the load request to the non-coalescing issue queue (NCIQ) 110. Load requests from CIQ 108 or NCIQ 110 utilize register read stage 112. Load requests passed via CIQ 108 are then passed outside register read stage 112 to address generation stage 114. They then enter pending load buffer 116, where several pending load requests are held simultaneously. Merger circuitry 118 refers to the contents of pending load buffer 116 when determining whether a given load request can be merged. When it fails, this fact is communicated to merge predictor 104, which establishes a record of those load requests that previously failed to merge, in order to generate its merge prediction. Pending load requests that have been merged with another load request and were not suppressed by merger 118 are passed to load unit 120, and the device maintains a record of active loads in its active load storage 122. (This is related to the above...) Figure 2A As in the described example embodiment, loading unit 120 then passes the pending load to TLB lookup and fault checking circuitry 124. Data read and multiplexing circuitry 126 extracts the data item corresponding to the load request itself and passes it to selector 134. A series of data items generated by memory access is passed to de-merge and format circuitry 130 via data buffer 128. De-merge and format circuitry 130 also receives input from merger 118 indicating the nature of the merge to be performed (i.e., which data items should be extracted), so that it can then de-merge the required data items from the retrieved series of data items (e.g., cache lines). These de-merge data items are then passed to selector 134 via data buffer 132.

[0034] Pending load requests predicted as non-mergeable are passed directly from NCIQ 110 to load unit 140 via register read stage 112. Since these load requests are predicted as non-mergeable, early address generation is unnecessary, and therefore address generation stage 142 is placed after load unit 140, allowing the memory accesses required to service these load requests to be initiated earlier, thus avoiding the latency associated with early address generation of merged paths. Load unit 140 also maintains a record of its active loads in active load memory 144. The result of address generation 142 is passed to TLB lookup and fault checking circuitry 124, and then to data read and multiplexing circuitry 126. The result of non-mergeable requests is passed directly from data read and multiplexing circuitry 126 to selector 134. Under the control of load unit 140, the selector then passes one of its inputs to result buffer 136, the contents of which can be utilized by register read stage 112 in its address resolution function.

[0035] Figure 4A The configuration of a merge predictor 150 according to some example embodiments is illustrated schematically in more detail. The merge predictor 150 is arranged to receive an indication of a load instruction, which, in the illustrated embodiment, includes a subset of addresses (bits [17:2]). This information is received by a comparison circuit 152, which receives another input from a merge history store 154. The comparison circuit 152 compares the load instruction address information with the contents of the merge history store 154 (i.e., the comparison circuit 152 has visibility of all historical entries in the merge history store 154 and compares them with the incoming load instruction address), and generates a prediction (merged or not merged) for this load instruction based on this. Previous merge results result in updates to the contents of the merge history store 154. These can, in principle, be explicit records of the merge results of previously encountered load instructions, or they can be limited to a specific result, such as a non-merged result. However, in other embodiments, it is also possible to maintain a record of merge results in the merge history store. Generally speaking, the merge history can be an explicit record of all merge results, a record of non-merge results, a record of merge results, or a probabilistic representation of any of these.

[0036] Figure 4B The schematic diagram illustrates more components of the merge predictor 160, which in fact can be... Figure 4A The merge predictor 150 is the same as the merge predictor, but... Figure 4B Different functions are highlighted. Specifically, the merge predictor 160, in addition to the merge history storage 162a-d, is also shown to include update control 164. The update control can receive information from one or more possible inputs, and... Figure 4BThe diagram shows the scenario switching signal, timer, and merge result (including information related to the load instruction address). Based on this, update control 164 modifies the contents of merge history stores 162a-d. Generally, the merge result leads to an update of the merge history store, which has already been described above (i.e., this can be an explicit record of all merge results, a record of non-merge results, a record of merge results, or a probabilistic representation of any of these). Update control thus maintains the contents of merge history stores 162a-d. There are various ways to reset the contents of the merge history store. One example is the elapsed of a predetermined time period (indicated by a timer), because given that the merge history store inevitably has a limited capacity, it is possible that the "fullness" of merge history stores 162a-d slowly leads to functional degradation over time. To mitigate this, update control 164 can reset the contents after a certain time period has elapsed. Alternatively or additionally, when a broader data processing system undergoes a scenario change, it may be appropriate to reset the contents of the merge history store, and thus update control 164 can trigger this reset upon receiving a scenario change indication. Update control 164 also directly monitors the merge history stores 162a-d, and can reset their contents when a certain "fullness" is reached. The merge history store... Figure 4B The merge history storage is shown as comprising four parts: 162a, 162b, 162c, and 162d. These different parts of the merge history storage are used to store different sets of merge history data, which, for example, can be used to store merge history information related to different process contexts. Update control 164 can instruct the merge history storage to switch between these different history sets when a process context changes.

[0037] Figure 5AThe schematic illustration provides further details of the operation of a merge predictor according to some example embodiments. In such embodiments, a hashing unit 170 is provided, which is arranged to generate a hash of the instruction address information it receives. The hashing unit 170 receives load instruction address information from two sources: an indication of an incoming load instruction in the instruction queue, and an indication related to the merge result from the merging unit. The hashing unit 170 utilizes a hash key store and a sequencer circuit 172 to generate its hash value. The provision of the sequencer 172 allows the hashing unit to generate hash values ​​in multiple hashing stages, thereby reducing the overall complexity of the hardware required to support the hashing functionality. This type of non-cryptographic hash can be generated quickly, for example, using an efficient hardware configuration employing XOR and / or shift operations. The output of the hashing unit 170 is passed to a path selector 174, which determines the forward path of the hash information based on whether a check is performed on the merge predictor store (i.e., generating a merge prediction) or whether the contents of the store are modified using the merge result. Figure 5A In the example, this storage is Bloom filter storage 174. Therefore, the content of Bloom filter storage 174 is updated based on the hash generated from the merge result. The Bloom filter shown thus determines whether a particular load request can be merged, or whether there is a possibility that it might not be merged. Subsequently, when the load instruction address (or a portion thereof) is received by cache unit 70, this information is passed to comparison circuit 176, which compares the instruction address information with the content of Bloom filter storage 144 and generates a merge prediction based on this comparison.

[0038] Figure 5B The schematic illustration shows components of a data processing apparatus 180 that include a sequence of pipeline stages in the manner described in some of the embodiments above. These components are shown as an acquisition stage 182, a decoding stage 184, a micro-operation buffer stage 186, a renaming stage 188, and an instruction queue 190. As in the examples of the embodiments described above, the load instruction decoded by the decoding stage 184 is also notified to the merge predictor circuit 192 so that it generates a merge prediction. This merge prediction is passed to the instruction queue 190, thereby allowing the forward path taken by the load request through the rest of the apparatus (not shown, but according to any of the embodiments described above). Reference Figure 5BIt is important to note that the merge predictor also receives input from the renaming stage 188. More generally, the merge predictor 192 can be provided with input from any data compliance determination circuit (the renaming stage 188 being one example). This is because it has been found that the data compliance of load instructions includes useful information that can be used to determine whether a particular load request will be merged. Specifically, it has been found that loads of access pointers tend not to be merged when some load instructions directly (or with a very low degree of indirection) provide input values ​​to other co-pending load instructions. Therefore, this data compliance information can be taken into account in the determinations made by the merge predictor when generating its merge prediction. Figure 5B An example is also illustrated where a merge predictor is arranged to provide (dashed arrows in the figure) merge predictions for certain load instructions to either or both of the decoding stage 184 and the micro-operation buffer 186 (see reference above). Figure 2A (As described). In this arrangement, when the renaming stage detects a load-load dependency chain (which, as mentioned above, has been found to significantly reduce the likelihood of merging), not only will the renaming stage 188 notify the merge predictor 192 to update itself to indicate that the first load should not be merged, but the renaming stage 188 may also decide to overturn a prediction if the merge predictor 192 has already provided a prediction earlier in the pipeline (e.g., in the decoding stage or in the micro-operations buffer). More specifically, the renaming stage 188 may be arranged to determine whether the merge predictor 192 has an actual prediction for this load, or whether the merge predictor 192 has assumed a default "mergeable" prediction. Thus, the merge predictor may, for example, use a single bit of the merge prediction it provides to indicate either the "actual prediction" or the "default prediction" for this load. In the latter case, the renaming stage may overturn the prediction for the first load if it detects a load-load dependency chain.

[0039] Figure 6This is a flowchart illustrating a sequence of steps taken according to a method based on some embodiments. The process can be considered to begin at step 200, where the next load request is received. Then, at step 202, it is determined whether a non-merge prediction has been previously stored for this load request (i.e., for this load instruction). If so, the process proceeds directly to step 212, where the load request is executed alone (i.e., no attempt is made to merge it with other load requests). However, if it is found in step 202 that no non-merge prediction has been stored for this load request, the process proceeds to step 204. Here, the load request is added to the pending load buffer. Then, at step 206, it is determined whether the load request can be merged with the contents of other pending load buffers. If not, the process proceeds via step 207, where it is checked whether the pending load buffer has sufficient content to allow a meaningful determination of "non-merge". This is done with reference to a threshold for the occupancy of the pending load buffer. Below this threshold, it is defined that a "non-merge" determination should not be made because the buffer does not hold sufficient other loads to compare with the current load request. Therefore, when the current occupancy rate is not higher than the threshold, the process proceeds to step 212, and the load is processed separately. The process then returns to step 200. However, if the current occupancy rate is higher than the threshold, the process proceeds via step 208, where a non-merging prediction is stored for this load request, and then it is processed separately in step 212. Returning to considerations of step 206, however, if it is determined in step 206 that the load request can be merged with other pending load buffer contents, other “overlapping” load requests are suppressed in step 210. This may include the other pending load buffer contents mentioned above, or it may include the load request itself, depending on the configuration adopted and, for example, the order in which the load requests travel through the pending load buffers. For example, it might be preferable that the oldest load request in the sequential pending load buffers is acted upon (to reduce latency), while those merged with it after it are suppressed, but this is not necessary.

[0040] In summary, apparatus and methods for processing load requests are disclosed. In response to a load request specifying data items to be retrieved from memory, a series of data items, including those identified by the load request, are retrieved. The load request is buffered before execution. A merging circuit determines whether an address proximity condition is true for the load request and a set of one or more other load requests buffered in a pending load buffer circuit. The address proximity condition is true when all data items identified by the set of one or more other load requests are included in the series of data items. When the address proximity condition is true, the set of one or more other load requests is suppressed. A merging prediction circuit generates a merging prediction for each load request based on the merging circuit's previous processing of the load requests.

[0041] In this application, the term "configured as" is used to mean that the elements of the device are configured to perform defined operations. In this context, "configuration" refers to the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform that function. "Configured as" does not mean that the elements of the device need to be changed in any way in order to provide the defined operations.

[0042] While illustrative embodiments have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to these specific embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, features of the dependent claims may be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. A data processing apparatus, comprising: A loading processing circuit, in response to a loading request for a specified data item, retrieves from memory a series of data items including the data item identified by the loading request; A pending load buffer circuit buffers the load request before it is executed by the load processing circuit in order to retrieve the data item specified by the load request from memory. The merging circuit determines whether an address proximity condition is true for the set of the load request and one or more other load requests buffered in the pending load buffer circuit, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the set of data items. The merging circuit, in response to the address proximity condition being true, suppresses the processing circuit's processing of the set of one or more other load requests; A merge prediction circuit generates a merge prediction for the load request based on the previous processing of the load request by the merging circuit. A second loading processing circuit, in response to a loading request specifying the data item, retrieves from the memory the series of data items including the data item identified by the loading request; and The load processing selection circuit, in response to a merge prediction generated by the merge prediction circuit, and in accordance with the merge prediction, directs the load request via the pending load buffer circuit to the load processing circuit, or to the second load processing circuit.

2. The apparatus claimed in claim 1, wherein the merging circuit suppresses the processing of the loading request by the merging circuit in response to a non-merging merging prediction.

3. The apparatus as claimed in claim 1 or claim 2, further comprising a feedback path from the merging circuit to the merging prediction circuit, wherein, In response to the validity of the address proximity condition, the merging circuit informs the merging prediction circuit via the feedback path of the merging result, which depends on the validity of the address proximity condition in relation to the load request.

4. The apparatus claimed in claim 1, wherein the merge prediction circuit includes a merge history store to hold content depending on the previous processing of the load request by the merge circuit, and the merge prediction circuit is arranged to generate a merge prediction for the load request based on the content of the merge history store.

5. The apparatus claimed in claim 4, wherein the content held by the merged history storage includes a probabilistic data structure.

6. The apparatus claimed in claim 5, wherein the merged history storage includes a Bloom filter.

7. The apparatus claimed in claim 5 or claim 6 further comprises a hash generation unit for generating the contents of the probabilistic data structure, wherein the hash generation unit includes a hash sequencer for generating the contents of the probabilistic data structure in a plurality of hashing stages.

8. The apparatus claimed in any one of claims 4-6, further comprising a reset circuit to reset the contents of the merged history storage in response to at least one of the following: After the scheduled time period; Received a scenario switching instruction; and / or The predetermined fullness of the merged historical storage is achieved.

9. The apparatus claimed in claim 1 or claim 2, further comprising a bypass path leading to the load processing circuit and bypassing the merging circuit, wherein the merging prediction circuit, in response to a non-merging merging prediction, provides the load request to the load processing circuit via the bypass path.

10. The apparatus as claimed in claim 1 or claim 2, further comprising: The first load request is sent to the queue to be fed to the pending load buffer circuit; as well as The second load request queue is sent to the second load processing circuit. The load processing selection circuit, in response to a merge prediction generated by the merge prediction circuit, directs the load request to either the first load request dispatch queue or the second load request dispatch queue, in accordance with the merge prediction.

11. The apparatus claimed in claim 1 or claim 2, wherein the load request originates from a load instruction, and the apparatus further includes an instruction cache storage for storing entries of frequently used instructions, wherein the instruction cache storage is arranged to store the merge prediction in association with the load instruction.

12. The apparatus claimed in claim 11, wherein the instruction cache storage is a micro-operation cache.

13. The apparatus claimed in claim 1 or claim 2, further comprising a data compliance determination circuit for determining data compliance between instructions, wherein the merge prediction circuit is arranged to generate the merge prediction in accordance with at least one data compliance determined by the data compliance determination circuit.

14. The apparatus claimed in claim 13, wherein the data compliance determination circuitry includes register renaming circuitry.

15. The apparatus claimed in claim 1 or claim 2, wherein the merge prediction circuit is arranged to generate a merge prediction for the load request by default.

16. A data processing method, comprising: A load request is buffered before it is executed to retrieve the data item specified by the load request from memory, wherein executing the load request for the specified data item includes retrieving from the memory a series of data items including the data item identified by the load request; Determine whether an address proximity condition is true for the set of the load request and one or more other load requests in the buffer, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the set of data items; When the address proximity condition is true, the execution of the set of one or more other load requests is suppressed; A merged prediction is generated for the load request based on the previous processing of the load request; In response to the load request, the series of data items, including the data item identified by the load request, are retrieved from the memory; and In response to the merge prediction, and in accordance with the merge prediction, the load request is directed to either the first load processing circuit or the second load processing circuit via the pending load buffer circuit.

17. A data processing apparatus, comprising: A means for buffering a load request to retrieve data items specified by the load request from memory before the load request is executed, wherein executing the load request for the specified data items includes retrieving from memory a series of data items including data items identified by the load request; A means for determining whether an address proximity condition is true for the set of the load request and one or more other load requests in the buffer, wherein the address proximity condition is true when all data items identified by the set of one or more other load requests are included in the set of data items; A means for suppressing the execution of the set of one or more other load requests when the address proximity condition is true; A means for generating a merged prediction for a load request based on previous processing of the load request; Means for retrieving, in response to the load request, the series of data items including the data item identified by the load request from the memory; and A means for responding to, and complying with, the merge prediction, directing the load request via a pending load buffer circuit to a first load processing circuit or to a second load processing circuit.

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