Data processing method and apparatus, and related product
Patent Information
- Application Number
- CN202010383257.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-05-08
- Publication Date
- 2026-09-22
- Estimated Expiration
- 2040-05-08
AI Technical Summary
在图像识别过程中，可能需要对大量离散的数据点进行处理(例如进行差值运算等)，然而，相关技术中对离散数据点的处理过程较为复杂，数据开销较大
[0012]根据本公开的实施例，能够通过数据搬运指令将离散数据搬运到连续的数据地址，得到向量数据，以便进行向量运算等处理，从而简化处理过程，减小数据开销。
Smart Images
Figure CN113626081B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method and apparatus, as well as related products. Background Technology
[0002] With the development of artificial intelligence technology, it has achieved good results in fields such as image recognition. In the process of image recognition, it may be necessary to process a large number of discrete data points (such as performing interpolation operations). However, the processing of discrete data points in related technologies is relatively complex and has a large data overhead. Summary of the Invention
[0003] Therefore, it is necessary to provide a data processing method, apparatus, and related products to address the aforementioned technical problems.
[0004] According to one aspect of this disclosure, a data processing method is provided, comprising: when the decoded processing instruction is a data transfer instruction, determining a source data address and a destination data address for the data corresponding to the processing instruction; storing data read from the source data address into the destination data address to obtain vector data, wherein the source data address includes a plurality of discrete data addresses, and the destination data address includes a plurality of consecutive data addresses.
[0005] According to another aspect of this disclosure, a data processing apparatus is provided, comprising: an address determination module, configured to determine a source data address and a destination data address of data corresponding to a data transfer instruction when the decoded processing instruction is a data transfer instruction; and a data storage module, configured to store data read from the source data address into the destination data address to obtain vector data, wherein the source data address includes a plurality of discrete data addresses, and the destination data address includes a plurality of consecutive data addresses.
[0006] According to another aspect of this disclosure, an artificial intelligence chip is provided, the chip including the data processing device described above.
[0007] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned artificial intelligence chip.
[0008] According to another aspect of this disclosure, a board is provided, the board comprising: a storage device, an interface device, a control device, and the aforementioned artificial intelligence chip;
[0009] The artificial intelligence chip is connected to the storage device, the control device, and the interface device, respectively; the storage device is used to store data.
[0010] The interface device is used to realize data transmission between the artificial intelligence chip and external devices;
[0011] The controller is used to monitor the state of the artificial intelligence chip.
[0012] According to embodiments of this disclosure, discrete data can be moved to consecutive data addresses via data transfer instructions to obtain vector data, which can then be used for vector operations and other processing, thereby simplifying the processing and reducing data overhead.
[0013] By deducing the technical features in the claim, beneficial effects can be achieved to address the technical problems in the background art. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0014] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0015] Figure 1 A schematic diagram of a processor for a data processing method according to an embodiment of the present disclosure is shown.
[0016] Figure 2 A flowchart illustrating a data processing method according to an embodiment of the present disclosure is shown.
[0017] Figure 3 A block diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.
[0018] Figure 4 A structural block diagram of a board according to an embodiment of the present disclosure is shown. Detailed Implementation
[0019] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0020] It should be understood that the terms “comprising” and “including” used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0021] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.
[0022] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."
[0023] The data processing method according to embodiments of this disclosure can be applied to a processor, which can be a general-purpose processor, such as a CPU (Central Processing Unit), or an artificial intelligence processor (IPU) for performing artificial intelligence operations. Artificial intelligence operations can include machine learning operations, neuromorphic operations, etc. Machine learning operations include neural network operations, k-means operations, support vector machine operations, etc. The artificial intelligence processor can, for example, include one or a combination of GPU (Graphics Processing Unit), NPU (Neural-Network Processing Unit), DSP (Digital Signal Processing Unit), and Field-Programmable Gate Array (FPGA) chips. This disclosure does not limit the specific type of processor.
[0024] In one possible implementation, the processor mentioned in this disclosure may include multiple processing units, each of which can independently run various assigned tasks, such as convolution operations, pooling tasks, or fully connected tasks. This disclosure does not limit the processing units or the tasks they run.
[0025] Figure 1 A schematic diagram of a processor for a data processing method according to an embodiment of the present disclosure is shown. Figure 1As shown, the processor 100 includes multiple processing units 101 and storage units 102. The processing units 101 are used to execute instruction sequences, and the storage units 102 are used to store data, and may include random access memory (RAM) and a register file. The multiple processing units 101 in the processor 100 may share some storage space, such as sharing some RAM storage space and register file, or they may each have their own storage space.
[0026] Figure 2 A flowchart illustrating a data processing method according to an embodiment of this disclosure is shown. Figure 2 As shown, the method includes:
[0027] In step S11: when the decoded processing instruction is a data transfer instruction, the source data address and destination data address of the data corresponding to the processing instruction are determined;
[0028] In step S12: the data read from the source data address is stored at the destination data address to obtain vector data.
[0029] The source data address includes multiple discrete data addresses, and the destination data address includes consecutive data addresses.
[0030] According to embodiments of this disclosure, discrete data can be moved to consecutive data addresses via data transfer instructions to obtain vector data, which can then be used for vector operations and other processing, thereby simplifying the processing and reducing data overhead.
[0031] In one possible implementation, the method further includes: decoding the received processing instruction to obtain a decoded processing instruction. The decoded processing instruction includes an opcode, which is used to instruct data transfer processing.
[0032] For example, when a processor receives a processing instruction, it can decode the received instruction to obtain a decoded processing instruction. This decoded processing instruction includes an opcode and an operation field. The opcode indicates the processing type of the instruction, and the operation field indicates the data to be processed and its parameters. If the opcode of the decoded processing instruction indicates data transfer processing, then this instruction is a data transfer instruction (Gather Load).
[0033] In one possible implementation, if the decoded processing instruction is a data transfer instruction, the source data address and destination data address corresponding to the processing instruction can be determined in step S11. The data corresponding to the processing instruction refers to the discrete multiple data points indicated by the operation field of the processing instruction. The source data address represents the current data storage address of the multiple data points in the data storage space, and is a discrete set of multiple data addresses; the destination data address represents the data address of the data storage space to which the multiple data points will be transferred, and is a continuous set of data addresses. The data storage space where the source data address is located and the data storage space where the destination data address is located can be the same or different, and this disclosure does not impose any restrictions on this.
[0034] In one possible implementation, after determining the source data address and the destination data address, the processor can read multiple discrete data from the source data address in step S12 and store the read data into the destination data address to obtain vector data of a preset length, thereby completing the data transfer process.
[0035] In one possible implementation, after the data transfer is completed, the vector data can be further processed through data operation instructions, such as arithmetic operations between two or more vector data, or difference operations between two vector data.
[0036] In this way, in applications such as image recognition where a large number of discrete pairs of data points need to be processed, discrete data can be moved to a continuous address space and aggregated into vector data before vector operations are performed. This transforms the operation of discrete data points into vector operations, simplifying the processing and reducing data overhead.
[0037] In one possible implementation, step S11 may include: determining the source data address of the plurality of data based on the source data base address and data offset address of the plurality of data in the operation field of the processing instruction.
[0038] For example, a data transfer instruction may have an operation field that indicates the data parameters of the data to be transferred. The operation field may include the source data base address, the destination data base address, the size of a single data point, the number of single data points, the offset vector base address of a single data point, and the offset size, etc.
[0039] Wherein, the source data base address can represent the base address of multiple discrete data points currently in the data storage space; the destination data base address can represent the base address of multiple data points to be moved to the data storage space; the size of a single data point can represent the data size of each discrete data point (e.g., 4 bits or 8 bits); the number of single data points can represent the number of discrete data points N (N is an integer greater than 1); the data offset base address of a single data point can represent the base address offset of each discrete data point relative to the source data base address; the offset size can represent the width of the offset address corresponding to each discrete data point, for example, equal to the size of a single data point. This disclosure does not limit the specific number and type of parameters in the operation field of the data moving instruction.
[0040] In one possible implementation, the data offset address of each data point can be determined based on the data offset base address and offset size of a single data point in the operation domain. For example, for the nth data point (1≤n≤N), if the data offset base address of this data point is 24 and the offset size is 4, then the data offset address[n] of this data point is [24,27]. In this way, the source data address of the nth data point can be determined based on the source data base address and the data offset address.
[0041] Single Point Src Addr[n] = Source Data Base Address + Offset Address[n] (1)
[0042] In formula (1), Single Point Src Addr[n] represents the source data address of the nth data point. When the source data base address is, for example, Addr1
[15] and the data offset address of the nth data point is [24,27], the source data address of the nth data point can be determined as Addr1[39,42].
[0043] In this way, the source data address of each piece of data can be determined separately, so that each piece of data can be read from the source data address.
[0044] In one possible implementation, step S11 may include: determining the destination data address of the plurality of data based on the destination data base address and data size of the plurality of data in the operation domain of the processing instruction.
[0045] As mentioned earlier, the operation field of a data transfer instruction may include the destination database address and the single-point data size. Since the destination data address is a contiguous set of data addresses, the destination data address of each data point can be determined directly based on its size and sequence number. The destination data address of the nth data point can be represented as:
[0046] Single Point Dest Addr[n]=Destination Data Base Address+n*SinglePoint Data Size(2)
[0047] In formula (2), Single Point Dest Addr[n] represents the destination data address of the nth data point. When the destination data base address is, for example, Addr2[0, 3], the size of a single data point is 4 bits, and n is 3, the destination data address of the 3rd data point can be determined as Addr2[12, 15].
[0048] In this way, the destination data address of each piece of data can be determined separately, so that each piece of data read from the source data address can be moved to its respective destination data address.
[0049] In one possible implementation, step S12 may include: reading each piece of data from the source data address of each piece of data in the plurality of data; storing each piece of data sequentially into the destination data address to obtain the vector data.
[0050] For example, after determining the source and destination data addresses of each data point in the operation domain, each data point can be read from its source address and stored sequentially in its destination address. For instance, when n is 3, data is read from the source address Addr1[39,42] of the 3rd data point and stored in the destination address Addr2[9,12], thus completing the data transfer for that data point. In this way, by sequentially transferring each data point, N consecutive data points are obtained stored in the destination address, realizing the process of aggregating discrete data points into vector data.
[0051] This method enables data transfer, providing a data foundation for subsequent processing.
[0052] According to the data processing method of this disclosure, discrete data can be moved into a continuous address space through data transfer instructions and aggregated into vector data. This allows for the conversion of discrete data point operations into vector operations in application scenarios such as image recognition, which require operations on a large number of discrete pairs of data points. This simplifies the processing and reduces data overhead.
[0053] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.
[0054] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0055] Figure 3 A block diagram of a data processing apparatus according to an embodiment of the present disclosure is shown. Figure 3 As shown, the device includes:
[0056] Address determination module 31 is used to determine the source data address and destination data address of the data corresponding to the data when the decoded processing instruction is a data transfer instruction;
[0057] Data storage module 32 is used to store the data read from the source data address to the destination data address to obtain vector data.
[0058] The source data address includes multiple discrete data addresses, and the destination data address includes consecutive data addresses.
[0059] In one possible implementation, the address determination module includes:
[0060] The source address determination submodule is used to determine the source data address of the multiple data based on the source data base address and data offset address of the multiple data in the operation field of the processing instruction.
[0061] In one possible implementation, the address determination module includes:
[0062] The destination address determination submodule is used to determine the destination data address of the multiple data based on the destination data base address and data size of the multiple data in the operation field of the processing instruction.
[0063] In one possible implementation, the data storage module includes:
[0064] The reading submodule is used to read each piece of data from the source data address of each piece of data in the plurality of data;
[0065] The storage submodule is used to sequentially store each piece of data into the destination data address to obtain the vector data.
[0066] In one possible implementation, the device further includes:
[0067] The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions.
[0068] The decoded processing instructions include an opcode, which is used to instruct data transfer processing.
[0069] It should be understood that the above-described device embodiments are merely illustrative, and the device disclosed herein can be implemented in other ways. For example, the division of units / modules described in the above embodiments is only a logical functional division, and other division methods may be used in actual implementation. For example, multiple units, modules, or components may be combined, integrated into another system, or some features may be ignored or not executed.
[0070] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this disclosure can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.
[0071] If the integrated unit / module is implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the artificial intelligence processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), etc.
[0072] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.
[0073] In one possible implementation, an artificial intelligence chip is also disclosed, which includes the aforementioned data processing device.
[0074] In one possible implementation, an electronic device is also disclosed, which includes the aforementioned artificial intelligence chip.
[0075] In one possible implementation, a board is also disclosed, which includes a storage device, an interface device, a controller, and the aforementioned artificial intelligence chip; wherein the artificial intelligence chip is connected to the storage device, the controller, and the interface device respectively; the storage device is used to store data; the interface device is used to realize data transmission between the artificial intelligence chip and external devices; and the controller is used to monitor the status of the artificial intelligence chip.
[0076] Figure 4 A structural block diagram of a board according to an embodiment of the present disclosure is shown. (See attached diagram.) Figure 4 In addition to the chip 389, the aforementioned board may also include other supporting components, including but not limited to: storage device 390, interface device 391, and controller 392.
[0077] The storage device 390 is connected to the artificial intelligence chip via a bus and is used to store data. The storage device may include multiple sets of storage units 393. Each set of storage units is connected to the artificial intelligence chip via a bus. It can be understood that each set of storage units may be DDR SDRAM (Double Data Rate SDRAM).
[0078] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include four groups of storage cells. Each group of storage cells may include multiple DDR4 chips. In one embodiment, the AI chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 chips are used in each group of storage cells, the theoretical data transmission bandwidth can reach 25600MB / s.
[0079] In one embodiment, each group of memory cells includes multiple Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs) arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling the DDR is provided in the chip for controlling the data transfer and data storage of each memory cell.
[0080] The interface device is electrically connected to the artificial intelligence chip. The interface device is used to realize data transmission between the artificial intelligence chip and external devices (e.g., servers or computers). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the chip via a standard PCIe interface, realizing data transfer. Preferably, when using a PCIe 3.0 x 16 interface, the theoretical bandwidth can reach 16000 MB / s. In another embodiment, the interface device can also be other interfaces; this disclosure does not limit the specific form of the other interfaces mentioned above, as long as the interface unit can realize the switching function. Furthermore, the calculation results of the artificial intelligence chip are still transmitted back to the external device (e.g., the server) by the interface device.
[0081] The controller is electrically connected to the artificial intelligence chip. The controller monitors the state of the artificial intelligence chip. Specifically, the artificial intelligence chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller (MCU). The artificial intelligence chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, capable of driving multiple loads. Therefore, the artificial intelligence chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the artificial intelligence chip.
[0082] In one possible implementation, an electronic device is disclosed that includes the aforementioned artificial intelligence chip. The electronic device includes data processing devices, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, dashcams, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound scanners, and / or electrocardiographs.
[0083] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.
[0084] The foregoing can be better understood in accordance with the following terms:
[0085] Clause A1. A data processing method, comprising:
[0086] When the decoded processing instruction is a data transfer instruction, determine the source data address and destination data address of the data corresponding to the processing instruction;
[0087] The data read from the source data address is stored at the destination data address to obtain vector data.
[0088] The source data address includes multiple discrete data addresses, and the destination data address includes consecutive data addresses.
[0089] A2. According to the method described in A1, when the decoded processing instruction is a data transfer instruction, determining the source data address and destination data address of the data corresponding to the processing instruction includes:
[0090] Based on the source data base address and data offset address of multiple data in the operation field of the processing instruction, the source data address of the multiple data is determined respectively.
[0091] A3. According to the method described in A1 or A2, when the decoded processing instruction is a data transfer instruction, determine the source data address and destination data address of the data corresponding to the processing instruction, including:
[0092] The destination data address of the multiple data is determined based on the destination data base address and data size of the multiple data in the operation field of the processing instruction.
[0093] A4. According to any one of A1-A3, the data read from the source data address is stored in the destination data address to obtain vector data, including:
[0094] Read each piece of data from its source data address;
[0095] Each piece of data is stored sequentially into the destination data address to obtain the vector data.
[0096] A5. The method according to any one of A1-A4, the method further comprising:
[0097] The received processing instructions are decoded to obtain the decoded processing instructions.
[0098] The decoded processing instructions include an opcode, which is used to instruct data transfer processing.
[0099] A6. A data processing apparatus, comprising:
[0100] The address determination module is used to determine the source data address and destination data address of the data corresponding to the data when the decoded processing instruction is a data transfer instruction;
[0101] The data storage module is used to store the data read from the source data address to the destination data address to obtain vector data.
[0102] The source data address includes multiple discrete data addresses, and the destination data address includes consecutive data addresses.
[0103] A7. According to the apparatus described in A6, the address determination module includes:
[0104] The source address determination submodule is used to determine the source data address of the multiple data based on the source data base address and data offset address of the multiple data in the operation field of the processing instruction.
[0105] A8. According to the apparatus described in A6 or A7, the address determination module includes:
[0106] The destination address determination submodule is used to determine the destination data address of the multiple data based on the destination data base address and data size of the multiple data in the operation field of the processing instruction.
[0107] A9. The apparatus according to any one of A6-A8, the data storage module comprising:
[0108] The reading submodule is used to read each piece of data from the source data address of each piece of data in the plurality of data;
[0109] The storage submodule is used to sequentially store each piece of data into the destination data address to obtain the vector data.
[0110] A10. The apparatus according to any one of A6-A9, the apparatus further comprising:
[0111] The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions.
[0112] The decoded processing instructions include an opcode, which is used to instruct data transfer processing.
[0113] A11. An artificial intelligence chip, the chip comprising a data processing device as described in any one of A6-A10.
[0114] A12. An electronic device comprising an artificial intelligence chip as described in A11.
[0115] A13. A board card, the board card comprising: a storage device, an interface device, and a control device, as well as an artificial intelligence chip as described in A11;
[0116] The artificial intelligence chip is connected to the storage device, the control device, and the interface device, respectively.
[0117] The storage device is used to store data;
[0118] The interface device is used to realize data transmission between the artificial intelligence chip and external devices;
[0119] The controller is used to monitor the state of the artificial intelligence chip.
[0120] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.
Claims
1. A data processing method, characterized in that, include: Based on the source data base address and data offset address of multiple data in the operation field of the processing instruction, the source data address of the multiple data is determined respectively; based on the destination data base address and data size of the multiple data in the operation field of the processing instruction, the destination data address of the multiple data is determined. The data read from the source data address is stored at the destination data address to obtain vector data. The source data address includes multiple discrete data addresses, and the destination data address includes consecutive data addresses. The operation field of the processing instruction includes the source data base address for determining the source data address, the data offset address of each data point, and the offset size. The offset size represents the width of the offset address corresponding to the data to be transferred, and the width of the offset address represents the size of a single data point.
2. The method according to claim 1, characterized in that, The data read from the source data address is stored at the destination data address to obtain vector data, including: Read each piece of data from its source data address; Each piece of data is stored sequentially into the destination data address to obtain the vector data.
3. The method according to any one of claims 1 or 2, characterized in that, The method further includes: The received processing instructions are decoded to obtain the decoded processing instructions. The decoded processing instructions include an opcode, which is used to instruct data transfer processing.
4. A data processing apparatus, characterized in that, include: The address determination module is used to determine the source data address of the multiple data based on the source data base address and data offset address of the multiple data in the operation field of the processing instruction, and to determine the destination data address of the multiple data based on the destination data base address and data size of the multiple data in the operation field of the processing instruction. The data storage module is used to store the data read from the source data address to the destination data address to obtain vector data. The source data address includes multiple discrete data addresses, and the destination data address includes consecutive data addresses. The operation field of the processing instruction includes the source data base address for determining the source data address, the data offset address of each data point, and the offset size. The offset size represents the width of the offset address corresponding to the data to be transferred, and the width of the offset address represents the size of a single data point.
5. The apparatus according to claim 4, characterized in that, The data storage module includes: The reading submodule is used to read each piece of data from the source data address of each piece of data in the plurality of data; The storage submodule is used to sequentially store each piece of data into the destination data address to obtain the vector data.
6. The apparatus according to any one of claims 4 or 5, characterized in that, The device further includes: The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions. The decoded processing instructions include an opcode, which is used to instruct data transfer processing.
7. An artificial intelligence chip, characterized in that, The chip includes a data processing device as described in any one of claims 4-6.
8. An electronic device, characterized in that, The electronic device includes the artificial intelligence chip as described in claim 7.
9. A circuit board, characterized in that, The board includes: storage devices, interface devices, and control devices, as well as the artificial intelligence chip as described in claim 7; The artificial intelligence chip is connected to the storage device, the control device, and the interface device, respectively. The storage device is used to store data; The interface device is used to realize data transmission between the artificial intelligence chip and external devices; The controller is used to monitor the state of the artificial intelligence chip.
Citation Information
Patent Citations
Matrix transposition automatic control circuit system and matrix transposition method
CN101706760A