Compensating for semiconductor material loss during semiconductor structure formation

Abstract

In a first aspect, the invention relates to a method for forming a semiconductor structure (10), comprising: (a) providing a structure comprising (i) a substrate (20), (ii) a layer stack (30) on the substrate (20), and (iii) a trench (40) through the layer stack (30), the layer stack (30) comprising at least one semiconductor layer (31) of a semiconductor material and at least one sacrificial layer (32) under the semiconductor layer (31); (b) forming a recess (70) in the layer stack (30) by etching a portion of the sacrificial layer (32) exposed by the trench (40), the etching preferentially etching the sacrificial layer (32) relative to the semiconductor layer (31); and (c) epitaxially growing a liner (80) of the semiconductor material on a surface of the semiconductor layer (31) exposed by the trench (40).

Description

Technical Field

[0001] This invention relates to the formation of semiconductor structures, and more particularly to offsetting semiconductor material loss during such formation. Background Technology

[0002] To successfully implement fin-type FET architectures in advanced complementary metal-oxide-semiconductor (CMOS) devices, particularly for 5nm and beyond technology nodes, the Gate-all-around (GAA) field-effect transistor (FET) architecture has been proposed. This GAA FET can typically be based on one or more nanowires or nanosheets. The design can be relatively simple (e.g., for nanowire FETs or nanosheet FETs), but can also involve more complex designs (e.g., fork-chip FETs or complementary FETs (CFETs)). Ryckaert et al. proposed an evolutionary path for scaling sub-5nm CMOS technologies from nanosheets to fork-chips to CFETs (RYCKAERT, J. et al., Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller, presented at the IEEE International Electron Devices Meeting (IEDM) 2019, IEEE 2019, pp. 29.4.1-29.4.4).

[0003] Vertically stacked gate-all-around Sinanowire FETs have been demonstrated, for example, by Mertens et al. (MERTENS, H. et al., 2017 IEEE International Electron Devices Meeting (IEDM), "Vertically stacked gate-all-around Sinanowire transistors: Key process optimizations and ring oscillator demonstration", IEEE, 2017, pp. 37.4.1-37.4.4).

[0004] Barraud et al. also described stacked GAA Si nanowires and nanosheet FETs (Barraud et al., Performance and design considerations for gate-all-around stacked-nanowires FETs, IEEE, 2017, pp. 29.2.1-29.2.4).

[0005] However, further improvements are still needed before these GAA FETs become commercially relevant. Summary of the Invention

[0006] The objective of this invention is to provide a good method for forming semiconductor structures. Another objective of this invention is to provide good uses and semiconductor structures associated with this method. This objective is achieved through the method, semiconductor structure, and uses according to the invention.

[0007] An advantage of embodiments of the present invention is that semiconductor material loss (e.g., distal thinning of the semiconductor layer) can be compensated when a recess is formed in the sacrificial layer relative to the semiconductor layer. Another advantage of embodiments of the present invention is that distal thinning of the semiconductor layer can be (partially) reduced or further increased.

[0008] An advantage of embodiments of the present invention is that it can reduce the access resistance to the semiconductor layer.

[0009] An advantage of the embodiments of the present invention is that these embodiments are applicable to a variety of semiconductor structures, including GAA FETs, such as nanowires, nanosheets, forked wafers, or complementary CFETs.

[0010] The advantage of the embodiments of the present invention is that these embodiments can be implemented in a relatively simple and economical manner.

[0011] In a first aspect, the present invention relates to a method for forming a semiconductor structure, comprising: (a) providing a structure including (i) a substrate, (ii) a layer stack on the substrate, and (iii) a trench through the layer stack, the layer stack including at least one semiconductor layer of semiconductor material and at least one sacrificial layer below the semiconductor layer; (b) forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench, the etching such that the sacrificial layer is preferentially etched relative to the semiconductor layer; and (c) epitaxially growing a liner of semiconductor material on a surface of the semiconductor layer exposed by the trench.

[0012] If step b can be performed completely selectively relative to the semiconductor layer in the method without step c, then an inner spacer can be formed in the recess (see step d) and an ideal structure can be obtained, such as... Figure 1The diagram is schematically depicted in the image; the latter shows a semiconductor structure (10) comprising a stack (30) of alternating sacrificial layers (32) and semiconductor layers (31) on a substrate (20), a source / drain structure (41) extending through the stack (30), a dummy gate region (50) on the stack (30) comprising a dummy gate oxide (51) and a dummy gate (52), a gate spacer (60) sideways to the dummy gate region (50), and an inner spacer (71) adjacent to the sacrificial layer (32). However, it is observed within this invention that in reality, it is generally obtained as shown in the image. Figure 2 The schematically depicted structure (10) includes inner spacers (71) that partially extend into semiconductor layers (31) and a decreasing distal thickness (d) in each semiconductor layer (31). This is consistent with the work of Barraud et al. above (e.g., in which...). Figure 2 (3) is clearly visible) and the same is true for Mertens et al. (slightly less obvious in, for example, Figure 17(c), but confirmed); even though the issue is not discussed in these disclosures. This thinning of the far end of the semiconductor layer thus results in a reduction in the contact area between each semiconductor layer (31) and the source / drain structure (41), thereby increasing the parasitic resistance and thus increasing the access resistance to the semiconductor layer (31).

[0013] This observation regarding the thinning of the distal ends of semiconductor layers can now be traced back to the fact that such complete selectivity is generally unattainable and therefore inevitably results in some semiconductor material loss. Without theoretical constraints, this undesirable loss can have various causes, such as one or more of the following: (i) limited etch selectivity between the bulk semiconductor material (e.g., Si) and the bulk sacrificial material (e.g., SiGe); (ii) mixing of the (bulk) semiconductor and sacrificial material at the semiconductor / sacrificial layer interface; and (iii) oxidation (e.g., native oxide formation) on the surface of the semiconductor layer. However, regardless of whether it is due to the lack of such material selectivity and / or due to some interface or surface effect, etching results in some semiconductor material loss, thereby extending the recess (70) portion into the semiconductor layer (31) and thus thinning the distal thickness (d) of each semiconductor layer (31). This in Figure 3 This is also clearly visible in the transmission electron microscope (TEM) images, and in Figure 4 Further schematic depictions are provided below. As shown above, after the inner spacer (71) (see step d) and the source / drain structure (41) (see step e) are formed, the contact area between each semiconductor layer (31) and the source / drain structure (41) is then reduced (see step e). Figure 2 This leads to increased parasitic resistance and consequently increased access resistance to the semiconductor layer (31).

[0014] To address the aforementioned problems, the present invention envisions forming a semiconductor material liner (80) on the semiconductor layer (31) (and optionally on the sacrificial material) (step c), such as Figure 5 This is schematically depicted. Therefore, the semiconductor material loss in step b can be (at least partially) compensated and the distal thickness (d) of the semiconductor layer (31) can be (at least partially) restored. This can also be achieved... Figure 6 As seen in the text, Figure 6 TEM images of a semiconductor structure (10) with and without a semiconductor material liner (80) are shown (left image) and (right image). Although the liner (80) is not specifically distinguished from the semiconductor layer (31) (and the sacrificial layer (32)) in this case, it is clear that the semiconductor material loss in the semiconductor structure (10) in the left image is significantly reduced in the right image. More specifically, as... Figure 6 As shown, the height difference between the distal edge and the edge of the middle attachment of the semiconductor layer (31) is measured to be about 1.1 nanometers for the left semiconductor structure (10) and less than 0.5 nanometers for the right semiconductor structure (10); that is, the reduction in distal thickness (d) is measured to be about 2.2 nanometers and less than 1 nanometer, respectively.

[0015] In a second aspect, the present invention relates to a semiconductor structure comprising: (i) a substrate; (ii) a layer stack on the substrate, the layer stack comprising at least one semiconductor layer of semiconductor material and at least one auxiliary layer below the semiconductor layer; (iii) a trench through the layer stack; (iv) a recess relative to the semiconductor layer, the recess abutting the auxiliary layer; and (v) a liner of semiconductor material liner relative to the trench on the semiconductor layer and optionally the auxiliary layer.

[0016] In a third aspect, the present invention relates to the use of a liner of semiconductor material in a semiconductor structure as defined in any embodiment of the second aspect, the use of which is for reducing access resistance to the semiconductor layer.

[0017] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be suitably combined with features of the independent claims and other dependent claims, and not merely as expressly set forth in the claims.

[0018] Although devices in the field are constantly being improved, changed, and developed, it is believed that the concepts of this invention represent a sufficiently novel and original advancement, including deviations from prior practice, thereby providing devices with this property that are more efficient, stable, and reliable.

[0019] The above and other features, characteristics, and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of the invention by way of example. This description is given for illustrative purposes only and does not limit the scope of the invention. The accompanying drawings are referenced below. Attached Figure Description

[0020] Figure 1 An idealized semiconductor structure is schematically depicted, which can be as follows: Figure 1 It is obtained as schematically depicted in the illustration. However, it is observed in reality, as shown in the present invention, that it is obtained as... Figure 2 A schematic depiction of the structure.

[0021] Figure 2 schematically depicted Figure 1 A more realistic version of the semiconductor structure, which shows the result of undesirable semiconductor material loss.

[0022] Figure 3 Transmission electron microscopy (TEM) images are shown, illustrating the problem of undesirable semiconductor material loss.

[0023] Figure 4 The problem of undesirable semiconductor material loss is further illustrated schematically.

[0024] Figure 5 A liner for compensating for undesirable semiconductor material loss according to an embodiment of the invention is schematically depicted.

[0025] Figure 6 Transmission electron microscopy (TEM) images are shown, illustrating the difference between using (left) and not using (right) a liner according to an embodiment of the invention.

[0026] Figures 7 to 13 The semiconductor structures at different stages of the illustrative process flow according to exemplary embodiments of the present invention are schematically depicted.

[0027] In different accompanying drawings, the same reference numerals refer to the same or similar elements. Detailed Implementation

[0028] The invention will be described with reference to specific embodiments and particular drawings, but the invention is not limited thereto but is defined only by the claims. The described drawings are illustrative only and are not restrictive. In the drawings, some elements may be enlarged and not drawn to scale for illustrative purposes. Scale and relative scale do not correspond to an actual reduction in the implementation of the invention.

[0029] Furthermore, the terms first, second, and third, etc., in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a temporal, spatial, arrangement, or any other chronological order. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can be operated in a different order than that described or explained herein.

[0030] Furthermore, the terms top, bottom, above, below, etc., used in the specification and claims are for descriptive purposes and not necessarily for describing relative positions. It should be understood that these terms, as used so, can be interchanged with their antonyms where appropriate, and the embodiments of the invention described herein can operate in orientations other than those described or illustrated herein.

[0031] It should be noted that the term "comprising" as used in the claims should not be construed as limiting itself to the devices listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the stated features, integers, steps, or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the term "comprising" covers the case where only the stated feature is present, as well as the case where these features are present along with one or more other features. Therefore, the scope of the statement "an apparatus comprising devices A and B" should not be construed as limited to an apparatus consisting only of components A and B. This means that for the present invention, the only relevant components of the apparatus are A and B.

[0032] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrase "in one embodiment" or "in an embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, as will be obvious to those skilled in the art from this disclosure, particular features, structures, or characteristics can be combined in any suitable manner.

[0033] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of simplifying the disclosure and aiding in the understanding of one or more inventive aspects. However, this method of disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, inventive aspects exist in fewer features than all the features of a single foregoing disclosed embodiment. Therefore, the claims appended following the detailed description are thus explicitly incorporated into this detailed description, wherein each claim itself represents a separate embodiment of the invention.

[0034] Furthermore, while some embodiments described herein include features that are included in other embodiments but not others, it will be understood by those skilled in the art that combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments. For example, any embodiment of the claimed embodiments in the appended claims can be used in any combination.

[0035] Numerous specific details are set forth in the description provided herein. However, it should be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0036] Reference will be made to transistors. These are devices having a first main terminal (e.g., source or collector), a second main terminal (e.g., drain or emitter), and a control terminal (e.g., gate or base) for controlling the charge flow between the first and second main terminals.

[0037] The following items are provided separately to facilitate understanding of the invention.

[0038] As used herein, unless otherwise specified, 'source / drain structure' is understood to mean 'source structure and / or drain structure'. In various embodiments, the source structure and drain structure may be comparable (e.g., indistinguishable), and their naming may depend on the relative voltage difference applied between them in the final semiconductor structure.

[0039] As used herein, unless otherwise specified, when it is said that a first entity (e.g., a first layer or material) is selectively removed (e.g., etched) relative to a second entity (e.g., a second layer or material), it means that the first entity is removed faster than the second entity. Preferably, the removal (e.g., etching) process will remove the first entity at least twice as fast as the second entity, more preferably at least five times faster, and even more preferably at least ten times faster. In some preferred embodiments, the removal process may substantially not remove the second entity.

[0040] As used herein, unless otherwise specified, a 'dummy' entity (e.g., a dummy gate region) is a non-functional entity that is typically used as a placeholder that will be replaced by a functional entity at a later stage of semiconductor processing. For example, a dummy gate region may be replaced by a functional gate region during a metal gate replacement process. A 'dummy' entity may alternatively be referred to as a 'sacrificial' entity.

[0041] In a first aspect, the present invention relates to a method for forming a semiconductor structure, comprising: (a) providing a structure including (i) a substrate, (ii) a layer stack on the substrate, and (iii) a trench through the layer stack, the layer stack including at least one semiconductor layer of semiconductor material and at least one sacrificial layer below the semiconductor layer; (b) forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench, the etching such that the sacrificial layer is preferentially etched relative to the semiconductor layer; and (c) epitaxially growing a liner of semiconductor material on a surface of the semiconductor layer exposed by the trench.

[0042] In various embodiments, the semiconductor structure may include or may be a gate-all-around (GAA) field-effect transistor (FET), such as a nanowire, nanosheet, forksheet, or complementary field-effect transistor. In various embodiments, the method can thus be used to form a gate-all-around field-effect transistor, preferably a nanowire, nanosheet, forksheet, or complementary field-effect transistor. Forksheet FETs have been described, for example, by Weckx et al. (Novel forksheet device architecture as ultimate logic scaling device towards 2nm, presented at the IEEE International Electron Devices Meeting (IEDM) 2019, IEEE, 2019, pp. 36.5.1-36.5.4), which is incorporated herein by reference.

[0043] In various embodiments, the substrate may be a semiconductor structure, such as a IV cluster substrate (e.g., Si, Ge, or SiGe), a III-V cluster substrate, or a semiconductor-on-insulator substrate.

[0044] At least one semiconductor layer is a semiconductor material layer; that is, it may include or be composed of a semiconductor material. In some embodiments, the bulk semiconductor layer may substantially include (e.g., be composed of) a semiconductor material, while the surface or interface includes (e.g., be composed of) a derivative of the semiconductor material (e.g., a natural oxide or a hybrid material). In various embodiments, the semiconductor material may be a cluster IV material (e.g., Si, Ge, or SiGe) or a cluster III-V material (e.g., AlxGa1-xAs, GaN, InAs, or GaxIn1-xP). In various embodiments, the semiconductor layer may be a nanowire or a nanosheet, preferably a nanosheet.

[0045] At least one sacrificial layer is typically a sacrificial material layer; that is, it may include or be composed of a sacrificial material. In various embodiments, the sacrificial layer may also be a semiconductor material (in this case, it may be alternatively referred to as 'sacrificial semiconductor material'). In various embodiments, the sacrificial layer may be a nanowire or nanosheet, preferably a nanosheet. The designations 'semiconductor layer / material' and 'sacrificial layer / material' thus refer to their function in the method. More specifically, the semiconductor layer is typically maintained in the method (e.g., to play a functional role in the final semiconductor structure), while the sacrificial layer is expected to be sacrificed during the process of the method. Thus, the semiconductor layer / material may also be referred to as 'functional semiconductor layer / material' (e.g., the opposite of 'sacrificial semiconductor layer / material'). Nevertheless, the sacrificial material and the semiconductor material may (although not necessarily) be selected from the same list of materials; for example, in one embodiment, SiGe may be the sacrificial material, while in other embodiments, SiGe may be the semiconductor material.

[0046] In various embodiments, the layer stack may include a plurality of semiconductor layers alternating with sacrificial layers. In a preferred embodiment, at least the bottom layer of the layer stack may be one of the sacrificial layers. In various embodiments, the top layer of the layer stack may be one of the semiconductor layers or one of the sacrificial layers.

[0047] In various embodiments, the semiconductor structure may further include: (vi) a dummy gate region above (e.g., directly above) the layer stack. In various embodiments, the dummy gate region may include a dummy gate oxide (e.g., SiO2) and a dummy gate (e.g., polysilicon). In various embodiments, the semiconductor structure may further include: (vii) a gate spacer (e.g., SiCON or SiBCN) sideways to the dummy gate region.

[0048] Note that although the sacrificial layer is preferentially etched relative to the semiconductor layer in step b, the achievable etch selectivity is generally inevitably limited (i.e., complete selectivity cannot be achieved), making some semiconductor material loss generally unavoidable (see above). Therefore, a portion of the semiconductor layer will still be etched in step b.

[0049] Given this limited etch selectivity, step c then allows for (at least partially) reduction of semiconductor material loss by epitaxially growing a semiconductor material liner on the trench-exposed surface of the semiconductor layer. In some embodiments, the liner can be epitaxially grown selectively on the surface of the semiconductor layer relative to the surface of the sacrificial layer. In other embodiments, step c may further include growing the liner on the trench-exposed surface of the sacrificial layer (i.e., the liner can be epitaxially grown on both the semiconductor layer surface and the sacrificial layer surface). Having a liner also on the surface of the sacrificial layer can have undesirable effects, as the liner portion will generally remain in the final semiconductor structure and can increase parasitic capacitance therein (e.g., by reducing the effectiveness of internal spacers; see below). Thus, where possible, it is preferable to selectively grow the liner only on the surface of the semiconductor layer. However, for certain combinations of semiconductor and sacrificial layers (e.g., Si and SiGe), this growth selectivity can be challenging or even impossible to achieve. However, although it may be desirable to then take into account the effect of the liner on, for example, parasitic capacitance in the final semiconductor structure, growing the liner on both the semiconductor layer surface and the sacrificial layer surface still produces beneficial results. For example, this could include striking a balance between good access resistance and good parasitic capacitance through appropriate selection of the liner thickness; that is, thick enough to adequately increase access resistance (e.g., through a larger contact area with the source / drain structure), but also thin enough to drastically increase parasitic capacitance.

[0050] In various embodiments, the liner grown in step c may have a thickness of 3 nanometers or less, preferably 2.5 nanometers or less, more preferably 2 nanometers or less, even more preferably 1.5 nanometers or less, such as 1.2 nanometers or less. In various embodiments, the liner grown in step c may have a thickness of at least 0.5 nanometers, even more preferably at least 1 nanometer. The thickness of the liner may be advantageously selected to at least partially compensate for the semiconductor material loss in step b, but other factors such as its effect on parasitic capacitance (see above) may also be taken into account. For this purpose, the liner thickness ( Figure 5 In this context, t2) can be equal to (i.e., fully compensating for the thinning of the far-end thickness of the semiconductor layer) the semiconductor material loss. Figure 4 The value of t1 in the equation can be either smaller (i.e., partially compensated) or larger (i.e., overcompensated).

[0051] In various embodiments, the method may include an additional step d following step c: (d) filling the recess with a dielectric material, thereby forming an inner spacer (which may be alternatively referred to as an 'internal spacer'). The inner spacer is generally advantageously used to reduce parasitic capacitance in the final semiconductor structure (e.g., between the gate region and the source / drain structure; see below).

[0052] In various embodiments, the method may include an additional step e following step d: (e) forming a source / drain structure (e.g., SiGe:B or Si:P) in the trench. In various embodiments, forming the source / drain structure in the trench may include epitaxially growing the source / drain structure in the construction. The source / drain structure (e.g., source / drain contacts) is generally advantageously used to contact the source / drain regions of the semiconductor layer of the final semiconductor structure.

[0053] In various embodiments, the method may include an additional step f: (f) removing the sacrificial layer. In various embodiments, step f may be performed after step d, preferably after step e. In various embodiments, the removal of the sacrificial layer may be performed preferentially (e.g., selectively) relative to the semiconductor layer and liner, preferably preferentially relative to the semiconductor layer, liner, and inner spacer. For example, the removal of the sacrificial layer may be performed preferentially relative to the semiconductor layer, liner, inner spacer, and source / drain structure. Typically, an opening is obtained in which the sacrificial layer is removed. Nevertheless, as before, complete selectivity in removing the sacrificial layer relative to the semiconductor layer and liner is generally not achievable, such that some semiconductor material (of the semiconductor layer and / or liner) will generally still be removed during step f. For example, in the case where the liner is in contact with the sacrificial layer, a liner thickness of up to about 1 nanometer may be lost during step f. For these liner regions, the thickness of the liner after step f may be 2 nanometers or less, preferably 1.5 nanometers or less, more preferably 1.2 nanometers or less, even more preferably 1 nanometer or less, most preferably 0.8 nanometers or less (e.g., completely removed). Removing the liner (partially) where it contacts the sacrificial layer can be advantageous, since these liner portions are often the ones that have the most negative impact on parasitic capacitance and contribute less to improving access resistance.

[0054] In various embodiments, step f may further include (e.g., removing the dummy gate region before or simultaneously with the removal of the sacrificial layer). Step f may also be referred to as a semiconductor layer release step (e.g., nanowire or nanosheet release).

[0055] In various embodiments, the method may include an additional step g following step f: (g) forming a gate region (e.g., a functional gate region) at the location where the sacrificial layer has been removed in step f. Step g may thus include forming the gate region in an opening obtained after step f. In various embodiments, forming the gate region may include forming a gate dielectric (e.g., a high-k dielectric, such as HfO2), a work function metal (e.g., TiN, TiAl, or TaN), and a gate metal (e.g., W, Co, or Ru). In various embodiments, the gate region may be a full-ring gate region. Alternative metal gate (RMG) processes may be used, for example, to perform steps f and g.

[0056] In each embodiment, any feature of any embodiment of the first aspect may be described independently as correspondingly to any embodiment of any other aspect.

[0057] In a second aspect, the present invention relates to a semiconductor structure comprising: (i) a substrate; (ii) a layer stack on the substrate, the layer stack comprising at least one semiconductor layer of semiconductor material and at least one auxiliary layer below the semiconductor layer; (iii) a trench through the layer stack; (iv) a recess relative to the semiconductor layer, the recess abutting the auxiliary layer; and (v) a liner of semiconductor material liner relative to the trench on the semiconductor layer and optionally the auxiliary layer.

[0058] The second aspect of the embodiment thus corresponds to obtaining a semiconductor structure after any of the steps in step cg.

[0059] In various embodiments, the semiconductor structure may further include: (vi) a dummy gate region above (e.g., directly above) the layer stack. In various embodiments, the dummy gate region may include a dummy gate oxide (e.g., SiO2) and a dummy gate (e.g., polysilicon). In various embodiments, the semiconductor structure may further include: (vii) a gate spacer (e.g., SiCON or SiBCN) sideways to the dummy gate region.

[0060] In various embodiments, the auxiliary layer may include a sacrificial layer, an opening, or a gate region.

[0061] In various embodiments, the recess may include an inner spacer.

[0062] In various embodiments, the trench may include a source / drain structure.

[0063] In each embodiment, any feature of any embodiment of the second aspect may be described independently as correspondingly to any embodiment of any other aspect.

[0064] In a third aspect, the present invention relates to the use of a liner of semiconductor material in a semiconductor structure as defined in any embodiment of the second aspect, the use of which is for reducing access resistance to the semiconductor layer.

[0065] In each embodiment, any feature of any embodiment of the third aspect may be described independently as correspondingly to any embodiment of any other aspect.

[0066] The invention will now be described in detail through several embodiments thereof. It will be apparent that other embodiments of the invention can be configured based on the knowledge of those skilled in the art without departing from the true technical teachings of the invention, which is limited only by the terms of the appended claims.

[0067] As an example of an embodiment of the present invention, an illustrative process flow for forming an all-ring gate field-effect transistor (e.g., nanowire, nanosheet, forked plate, or complementary field-effect transistor) is described in... Figures 7 to 13 It is described in the text and further described below.

[0068] Now refer to Figure 7 A semiconductor structure (10) is provided, comprising a stack (30) of alternating sacrificial layers (32) (e.g., SiGe, such as SiGe nanowires or nanosheets) and semiconductor layers (31) (e.g., Si, such as Si nanowires or nanosheets) on a substrate (20) (e.g., a silicon wafer). The semiconductor structure (10) further includes one or more trenches (40) extending down through the stack (30) to the substrate (20); one or more dummy gate regions (50) (e.g., silicon dioxide dummy gate oxide (51) and polysilicon dummy gate (52)) above the stack (30); and gate spacers (e.g., SiCON or SiBCN) sideways to the dummy gate regions (50).

[0069] Now refer to Figure 8 One or more recesses (70) are formed in the layer stack (30) by etching the portion of the sacrificial layer (32) exposed by the trench (40). The sacrificial layer (32) is etched preferentially relative to the semiconductor layer (31), but this selectivity is inevitably imperfect (see above) so that some semiconductor material loss (and possibly substrate (20) material loss) will also necessarily occur (see above). Figure 3 , Figure 4 and Figure 6 ).

[0070] Now refer to Figure 9 To compensate for semiconductor material losses, a liner (80) of semiconductor material (e.g., Si) is epitaxially grown on the surface of the semiconductor layer (31) and optionally the sacrificial layer (32) and / or the substrate (20) exposed by the trench (40). For example, the liner (80) may liner the entire bottom of the trench (40) and extend upward to the gate spacer (60). Depending on the desired results, the liner (80) may have a semiconductor material loss less than, equal to, or greater than the semiconductor material loss. Figure 4 The thickness of t1 in ( Figure 5 In t2); that is, the thinning of the distal thickness (d) can be partially or completely (see t2); Figure 5 ( ) or overcompensation. For example, in the case where the liner (80) is placed on both the semiconductor layer (31) and the sacrificial layer (32), a thicker liner (80) will generally result in a lower access resistance to the semiconductor layer (31), but will also result in a higher parasitic capacitance. The balance between these two can thus be sought by selecting an appropriate thickness (t2) of the liner (80).

[0071] Now refer to Figure 10 The dielectric material is used to fill the recess (70), thereby forming an inner spacer (71).

[0072] Now refer to Figure 11 Fill the trench (40) (e.g., by epitaxial growth of SiGe:B or Si:P) to form the source / drain structure (41).

[0073] Now refer to Figure 12 The semiconductor layer (31) is released by removing the dummy gate region (50) and the sacrificial layer (32).

[0074] Now refer to Figure 13 A functional alternative gate region is formed in the opening (90) where the sacrificial layer (32) and dummy gate region (50) have been previously removed. The functional alternative gate region includes a gate dielectric (e.g., HfO2), a work function metal stack (e.g., TiN, TiAl, or TaN), and a metal gate filler (e.g., W, Co, or Ru).

[0075] It is understood that although preferred embodiments, specific structures and configurations, and materials have been discussed herein with respect to the device according to the invention, various changes or modifications in form and detail may be made without departing from the scope and technical teachings of the invention. For example, any molecular formulas given above represent only steps that may be used. Functions can be added or removed from the block diagrams, and operations can be interchanged between function blocks. Steps can be added or removed from the methods within the scope of the invention.

Claims

1. A method for forming a semiconductor structure, comprising: a. Provide a structure, said structure comprising: i. Substrate; ii. A layer stack on the substrate, wherein the layer stack comprises at least one semiconductor layer of semiconductor material and at least one sacrificial layer beneath the semiconductor layer, and wherein the semiconductor material is an IV or III–V cluster material; and iii. Through trenches formed by the stacked layers; b. Forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench, wherein the etching includes preferential etching of the sacrificial layer relative to the semiconductor layer; c. Epitaxially growing a semiconductor material liner of the semiconductor material, the semiconductor material liner completely covering the entire surface of the semiconductor layer exposed by the trench and the entire surface of the sacrificial layer exposed by the trench; and d. The recess is filled with a dielectric material to form an inner spacer.

2. The method of claim 1, wherein the semiconductor material liner grown in step c has a thickness of 3 nanometers or less.

3. The method of claim 2, wherein the semiconductor material liner grown in step c has a thickness of 2.5 nanometers or less.

4. The method of claim 3, wherein the semiconductor material liner grown in step c has a thickness of 2 nanometers or less.

5. The method of claim 4, wherein the semiconductor material liner grown in step c has a thickness of 1.5 nanometers or less.

6. The method of claim 1, wherein the layer stack comprises a plurality of semiconductor layers alternating with the sacrificial layers.

7. The method of claim 1, wherein the method includes an additional step e following step d: e. Form a source / drain structure in the trench.

8. The method of claim 7, wherein the method comprises the following additional step f: f. Remove the sacrifice layer.

9. The method of claim 8, wherein the method includes an additional step g following step f: g. A gate region is formed where the sacrificial layer has been removed in step f.

10. The method of any of the preceding claims, wherein the method is used to form an all-ring gate field-effect transistor, the all-ring gate field-effect transistor being a nanowire, nanosheet, fork, or complementary field-effect transistor.

11. A semiconductor structure formed using the method of claim 1, comprising: i. Substrate; ii. A layer stack on the substrate, the layer stack comprising at least one semiconductor layer of semiconductor material and at least one auxiliary layer under the semiconductor layer, the auxiliary layer being a functional alternative gate region formed in an opening of a previously removed sacrificial layer and a dummy gate region, wherein the semiconductor material is an IV or III–V cluster material; iii. A source / drain structure formed by filling trenches that run through the stack of said layers; iv. An inner spacer formed by filling the recess adjacent to the auxiliary layer with a dielectric material; as well as v. A semiconductor material liner of the semiconductor material, the semiconductor material liner completely covering the entire surface of the semiconductor layer exposed by the trench.

12. The semiconductor structure of claim 11, wherein the trench comprises a source / drain structure.

13. The semiconductor structure of claim 11 or 12, wherein the semiconductor material liner is used to reduce the access resistance to the semiconductor layer.

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