Thin Film Transistors and Display Panels

Abstract

This application provides a thin-film transistor and a display panel. By making the first size of the first transmission section electrically connected to the heavily doped source portion and the second size of the second transmission section electrically connected to the heavily doped drain portion different, wherein the first size is the size of the first transmission section in the direction from the first transmission section to the heavily doped source portion, and the second size is the size of the second transmission section in the direction from the second transmission section to the heavily doped drain portion, the electric field strength experienced by the carriers transmitted in the transmission section corresponding to the larger of the first size or the second size is small when the thin-film transistor is turned on, thereby reducing the bombardment effect of carriers on the source or drain, improving the damage of bias stress to the source or drain, and improving the stability of the thin-film transistor.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a thin-film transistor and a display panel. Background Technology

[0002] Currently, dual-channel thin-film transistors are prone to failure when subjected to continuous bias stress, which is detrimental to the stability of their operation.

[0003] Therefore, it is necessary to propose a technical solution to address the problem of failure caused by continuous bias stress in dual-channel thin-film transistors. Summary of the Invention

[0004] The purpose of this application is to provide a thin-film transistor and a display panel to solve the problem of failure of thin-film transistors with dual channels due to continuous bias stress.

[0005] To achieve the above objectives, the technical solution is as follows:

[0006] A thin-film transistor, comprising:

[0007] The gate pattern includes a first gate and a second gate that are spaced apart and electrically connected to each other; and

[0008] Active patterns, including:

[0009] The source is heavily doped;

[0010] A first transmission section is electrically connected to the heavily doped source section and at least partially overlaps with the first gate. In the direction from the first transmission section to the heavily doped source section, the first transmission section has a first size.

[0011] Drain heavily doped region; and

[0012] The second transmission section is electrically connected to the heavily doped drain section and at least partially overlaps with the second gate. In the direction from the second transmission section to the heavily doped drain section, the second transmission section has a second size.

[0013] The first transmission section and the second transmission section are both located between the heavily doped source section and the heavily doped drain section, and the first transmission section and the second transmission section are spaced apart. The first size and the second size are different.

[0014] A thin-film transistor, the thin-film transistor comprising:

[0015] The gate pattern includes a first gate and a second gate that are spaced apart and electrically connected to each other; and

[0016] Active patterns, including:

[0017] The source is heavily doped;

[0018] A first transmission section is electrically connected to the heavily doped source section and at least partially overlaps with the first gate. In the direction from the first transmission section to the heavily doped source section, the first transmission section has a first size.

[0019] Drain heavily doped region; and

[0020] The second transmission section is electrically connected to the heavily doped drain section and at least partially overlaps with the second gate. In the direction from the second transmission section to the heavily doped drain section, the second transmission section has a second size.

[0021] The first transmission section and the second transmission section are both located between the heavily doped source section and the heavily doped drain section, and the first transmission section and the second transmission section are spaced apart.

[0022] When the thin-film transistor is turned on, the electric field strength applied to the charge carriers transported in the first transmission section is different from the electric field strength applied to the charge carriers transported in the second transmission section.

[0023] A display panel comprising the aforementioned thin-film transistor.

[0024] Beneficial Effects: This application provides a thin-film transistor and a display panel. By making the first size of the first transmission section electrically connected to the heavily doped source portion and the second size of the second transmission section electrically connected to the heavily doped drain portion different, wherein the first size is the size of the first transmission section in the direction from the first transmission section to the heavily doped source portion, and the second size is the size of the second transmission section in the direction from the second transmission section to the heavily doped drain portion, the electric field strength experienced by the carriers transmitted in the transmission section corresponding to the larger of the first and second sizes is small when the thin-film transistor is turned on, thereby reducing the bombardment effect of carriers on the source or drain, improving the damage of bias stress to the source or drain, and improving the stability of the thin-film transistor. Attached Figure Description

[0025] Figure 1 This is a cross-sectional schematic diagram of a thin-film transistor according to an embodiment of this application;

[0026] Figure 2 for Figure 1 A planar schematic diagram of a thin-film transistor is shown.

[0027] Figure 3 This is a cross-sectional schematic diagram of a thin-film transistor according to another embodiment of this application;

[0028] Figure 4 for Figure 3 A planar schematic diagram of a thin-film transistor is shown.

[0029] Figure 5 This is a schematic diagram of the display panel according to an embodiment of this application;

[0030] Figure 6 for Figure 5 The diagram shows the architecture of the gate drive circuit of the display panel.

[0031] Figure 7 for Figure 6 The circuit diagram of the gate drive circuit shown is shown. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] Please see Figure 1 and Figure 2 , Figure 1 This is a cross-sectional schematic diagram of a thin-film transistor according to an embodiment of this application. Figure 2 for Figure 1 The diagram shows a planar schematic of a thin-film transistor. This thin-film transistor is an N-type transistor. The thin-film transistor 100 includes an active pattern 10, a gate insulating layer 20, a gate pattern 30, an interlayer insulating layer 40, and source / drain electrode leads 50. It is understood that this thin-film transistor could also be a P-type thin-film transistor.

[0034] In this embodiment, the active pattern 10 is strip-shaped and linear. The active pattern 10 is fabricated using low-temperature polycrystalline silicon. In other embodiments, the active pattern 10 can also be fabricated using a metal oxide semiconductor material, such as indium gallium zinc oxide.

[0035] In this embodiment, the active pattern 10 includes a heavily doped source region 101, a first transport region 102, a heavily doped drain region 103, a second transport region 104, and an intermediate connection region 105. The first transport region 102 is adjacent to and electrically connected to the heavily doped source region 101, and the second transport region 104 is adjacent to and electrically connected to the heavily doped drain region 103. Both the first transport region 102 and the second transport region 104 are located between the heavily doped source region 101 and the heavily doped drain region 103, and are spaced apart. The second transport region 104 and the first transport region 102 are respectively connected to opposite sides of the intermediate connection region 105. Both the first transport region 102 and the second transport region 104 are used to transport charge carriers. The intermediate connection region 105 is also used to transport charge carriers.

[0036] In this embodiment, the first transmission section 102 includes a first channel 1021 and at least one first lightly doped section 1022. The first channel 1021 has not undergone ion implantation treatment. The first lightly doped section 1022 and the source heavily doped section 101 are both obtained by ion implantation treatment of semiconductors. The ion implantation dose of the first lightly doped section 1022 is less than the ion implantation dose of the source heavily doped section 101. The second transmission section 104 includes a second channel 1041 and at least one second lightly doped section 1042. The second channel 1041 has not undergone ion implantation treatment. The second lightly doped section 1042 and the drain heavily doped section 103 are both obtained by ion implantation of semiconductors. The ion implantation dose of the second lightly doped section 1042 is the same as the ion implantation dose of the first lightly doped section 1022. The ion implantation dose of the source heavily doped section 101 is the same as the ion implantation dose of the drain heavily doped section 103. For example, the ion implantation dose of the source heavily doped region 101 and the ion implantation dose of the drain heavily doped region 103 are both 10 per cubic centimeter. 14 The ion implantation dose of the second lightly doped part 1042 is 10 ions per cubic centimeter, the same as that of the first lightly doped part 1022. 13 One ion.

[0037] Specifically, the first transport section 102 includes two first lightly doped sections 1022 and a first channel 1021. The two first lightly doped sections 1022 are connected to opposite sides of the first channel 1021. One first lightly doped section 1022 is connected between the source heavily doped section 101 and the first channel 1021, and the other first lightly doped section 1022 is connected to the side of the first channel 1021 away from the source heavily doped section 101. The two first lightly doped sections 1022 are identical. The second transport section 104 includes two second lightly doped sections 1042 and a second channel 1041. The two second lightly doped sections 1042 are connected to opposite sides of the second channel 1041. One second lightly doped section 1042 is connected between the drain heavily doped section 103 and the second channel 1041, and the other second lightly doped section 1042 is connected to the side of the second channel 1041 away from the drain heavily doped section 103. The two second lightly doped sections 1042 are identical. It is understood that the first transmission section 102 may also include only one first lightly doped section 1022 and the first lightly doped section 1022 is disposed between the first channel 1021 and the source heavily doped section 101, and the second transmission section 104 may also include only one second lightly doped section 1042 and the second lightly doped section 1042 is disposed between the second channel 1041 and the drain heavily doped section 103.

[0038] In this embodiment, the first transmission section 102 has a first size D1 in the direction pointing from the first transmission section 102 to the heavily doped source section 101; the second transmission section 104 has a second size D2 in the direction pointing from the second transmission section 104 to the heavily doped drain section 103. The first size D1 and the second size D2 are different, so that the electric field strength applied to the carriers transmitted by the first transmission section 102 when the thin film transistor is turned on is different from the electric field strength applied to the carriers transmitted by the second transmission section 104. The transmission section corresponding to the larger of the first size D1 and the second size D2 has a smaller electric field strength on the carriers transmitted when the thin film transistor is turned on, which reduces the bombardment effect of the carriers on the source or drain, improves the damage of the bias stress to the source or drain, and improves the stability of the thin film transistor.

[0039] Specifically, the first dimension D1 is smaller than the second dimension D2, so that the electric field strength applied to the charge carriers during the transmission of charge carriers in the second transmission section 104 is small, and the bombardment effect of the charge carriers on the drain is small. This helps to solve the problem of high bias stress on the drain of the thin-film transistor when the N-type low-temperature polycrystalline silicon thin-film transistor is used in the gate drive circuit. It can be understood that the first dimension D1 can also be larger than the second dimension D2 to reduce the bombardment effect of the charge carriers on the source.

[0040] In this embodiment, the first channel 1021 is the portion of the first transmission section 102 that overlaps with the first gate 301 in the thickness direction of the thin-film transistor. In the direction from the first transmission section 102 to the heavily doped source section 101, the first channel 1021 has a third dimension D3, and the two first lightly doped sections 1022 have a fifth dimension 2×D5. The second channel 1041 is the portion of the second transmission section 104 that overlaps with the second gate 302 in the thickness direction of the thin-film transistor. In the direction from the second transmission section 104 to the heavily doped drain section 103, the second channel 1041 has a fourth dimension D4, and the two second lightly doped sections 1042 have a sixth dimension 2×D6. The fifth dimension 2×D5 is equal to the sixth dimension 2×D6, and the third dimension D3 is smaller than the fourth dimension D4, so that the first dimension D1 of the first transmission section 102 is smaller than the second dimension D2 of the second transmission section 104. Specifically, the third dimension D3 is greater than 0 micrometers and less than or equal to 200 micrometers, and the fourth dimension D4 is greater than 0 micrometers and less than or equal to 400 micrometers. For example, the third dimension D3 is 80 micrometers, 100 micrometers, 120 micrometers, or 180 micrometers; the fourth dimension D4 is 100 micrometers, 140 micrometers, 180 micrometers, 200 micrometers, 250 micrometers, 300 micrometers, or 400 micrometers. D5 and D6 are greater than 0 micrometers and less than or equal to 25 micrometers, for example, 10 micrometers, 15 micrometers, 20 micrometers, or 25 micrometers.

[0041] In this embodiment, the gate insulating layer 20 covers the active pattern 10. The gate insulating layer 20 is made of at least one of silicon nitride or silicon oxide. The thickness of the gate insulating layer 20 is 1000 angstroms to 2000 angstroms.

[0042] In this embodiment, the gate pattern 30 is interdigitated and disposed on the gate insulating layer 20. The gate pattern 30 includes a first gate 301, a second gate 302, a connecting segment 303, a first extension segment 304, and a second extension segment 305. The two ends of the connecting segment 303 are respectively connected to the first gate 301 and the second gate 302. The first gate 301 and the second gate 302 are located on the same side of the connecting segment 303. The first extension segment 304 connects to the side of the first gate 301 away from the connecting segment 303, and the second extension segment 305 connects to the side of the second gate 302 away from the connecting segment 303. The first gate 301 is the portion of the gate pattern 30 that overlaps with the active pattern 10 and is close to the heavily doped source portion 101. The second gate 302 is the portion of the gate pattern 30 that overlaps with the active pattern 10 and is close to the heavily doped drain portion 103. The first gate 301 has a dimension equal to the third dimension D3 of the first channel 1021 in the direction from the first transmission section 102 to the heavily doped source section 101, and the second gate 302 has a dimension equal to the fourth dimension D4 of the second channel 1041 in the direction from the second transmission section 104 to the heavily doped drain section 103. The material used to fabricate the gate pattern 30 is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.

[0043] In this embodiment, the interlayer insulating layer 40 covers the gate pattern 30 and the gate insulating layer 20. The thickness of the interlayer insulating layer 40 is 5000-6000 angstroms, and the material used to prepare the interlayer insulating layer 40 is selected from at least one of silicon nitride or silicon oxide.

[0044] In this embodiment, the source / drain electrode leads 50 include a source lead 501 and a drain lead 502. The source lead 501 is connected to the heavily doped source portion 101 through a first via 100a penetrating the interlayer insulating layer 40 and the gate insulating layer 20. The drain lead 502 is connected to the heavily doped drain portion 103 through a second via 100b penetrating the interlayer insulating layer 40 and the gate insulating layer 20. The material used to fabricate the source / drain electrode leads 50 is selected from at least one of molybdenum, aluminum, titanium, copper, and silver. The source lead 501 and the heavily doped source portion 101 form the source, and the drain lead 502 and the heavily doped drain portion 103 form the drain.

[0045] In this embodiment, the thin-film transistor reduces the electric field applied to the charge carriers during the transport of charge carriers by making the fourth dimension D4 of the second transport section near the heavily doped drain section larger than the third dimension D3 of the first transport section near the heavily doped source section. This reduces the bombardment of charge carriers on the drain and prevents the thin-film transistor from failing.

[0046] It should be noted that the technical solution in this embodiment can also be applied to P-type thin-film transistors, which may not have lightly doped portions.

[0047] Please see Figure 3 and Figure 4 , Figure 3 This is a cross-sectional schematic diagram of a thin-film transistor according to another embodiment of this application. Figure 4 for Figure 3 The diagram shows a planar schematic of a thin-film transistor. Figure 3 The thin-film transistor shown is Figure 1 The thin-film transistors shown are basically similar, except that the third dimension D3 is equal to the fourth dimension D4, the fifth dimension 2×D5 is smaller than the sixth dimension 2×D6, and D5 is smaller than D6, so that the first dimension D1 of the first transmission section 102 is smaller than the second dimension D2 of the second transmission section 104. D5 is greater than 0 micrometers and less than or equal to 20 micrometers, and D6 is greater than 0 micrometers and less than or equal to 30 micrometers. For example, D5 is 15 micrometers and D6 is 25 micrometers.

[0048] It should be noted that, Figure 1 and Figure 3 The schemes shown can also be combined. For example, while adjusting the third dimension D3 and the fourth dimension D4 to be different, the fifth dimension 2×D5 and the sixth dimension 2×D6 can also be different, so that the first dimension D1 of the first transmission unit 102 is different from the second dimension D2 of the second transmission unit 104.

[0049] Please see Figures 5-7 , Figure 5 This is a schematic diagram of the display panel according to an embodiment of this application. Figure 6 for Figure 5 The diagram shows the architecture of the gate drive circuit for the display panel. Figure 7 for Figure 6 The circuit diagram of the gate drive circuit shown is shown.

[0050] In this embodiment, the display panel 200 is a liquid crystal display panel, which is used in automotive applications. The display panel 200 can also be an organic light-emitting diode (OLED) display panel. The display panel 200 has a display area 200a and a peripheral area 200b. The display panel 200 includes scan lines 202, data lines 203, and multiple gate driving units 60. Multiple scan lines 202 and multiple data lines 203 are disposed in the display area 200a of the display panel 200, and multiple gate driving units 60 are disposed in the peripheral area 200b of the display panel 200 and located on opposite sides of the display area 200a. Each scan line 202 is connected to two opposite gate driving units 60. The gate driving unit 60 includes the aforementioned thin-film transistors to meet the requirements of automotive displays for the stability of the gate driving circuit due to complex operating environments and long operating times.

[0051] In this embodiment, the nth gate drive unit 60 includes an input module 601, a pull-up module 602, a pull-down module 603, a pull-down control module 604, a feedback module 605, and a functional module 606.

[0052] In this embodiment, the input module 601 is used to receive the forward scan signal U2D, the reverse scan signal D2U, the (n-2)th level scan signal G(n-2), and the (n+2)th level scan signal G(n+2), and adjust the potential of the first node Q in response to the (n-2)th level scan signal G(n-2) and the (n+2)th level scan signal G(n+2). Specifically, the input module 601 includes a first thin-film transistor NT1 and a second thin-film transistor NT2. The gate of the first thin-film transistor NT1 receives the (n-2)th level scan signal G(n-2), the first electrode of the first thin-film transistor NT1 receives the forward scan signal U2D, and the second electrode of the first thin-film transistor NT1 is connected to the first node Q. The gate of the second thin-film transistor NT2 receives the (n+2)th level scan signal G(n+2), the first electrode of the second thin-film transistor NT2 receives the reverse scan signal D2U, and the second electrode of the second thin-film transistor NT2 is connected to the first node Q.

[0053] In this embodiment, the pull-up module 602 is used to pull up the nth-level scan signal G(n) according to the voltage of the first node Q. Specifically, the pull-up module 602 includes a seventh thin-film transistor NT7 and a ninth thin-film transistor NT9. The gate of the seventh thin-film transistor NT7 receives a constant voltage high-level signal VGH, the first terminal of the seventh thin-film transistor NT7 is connected to the first node Q, the second terminal of the seventh thin-film transistor NT7 is connected to the gate of the ninth thin-film transistor NT9, the first terminal of the ninth thin-film transistor NT9 receives a first clock signal CK(n), and the second terminal of the ninth thin-film transistor NT9 outputs the pulled-up nth-level scan signal G(n).

[0054] In this embodiment, the pull-down module 603 is used to pull down the nth level scan signal G(n) according to the voltage of the second node P. Specifically, the pull-down module 603 includes a tenth thin-film transistor NT10, the gate of which is connected to the second node P, the first terminal of which receives a constant voltage low-level signal VGL, and the second terminal of which is connected to the second terminal of the ninth thin-film transistor NT9, so as to output the pulled-down nth level scan signal G(n).

[0055] In this embodiment, the pull-down control module 604 is used to receive a forward scan signal U2D, a reverse scan signal D2U, a second clock signal CK(n+1), and a third clock signal CK(n-1) to adjust the potential of the second node P. Specifically, the pull-down control module 604 includes a third thin-film transistor NT3, a fourth thin-film transistor NT4, and an eighth thin-film transistor NT8. The gate of the third thin-film transistor NT3 receives the forward scan signal U2D, the first terminal of the third thin-film transistor NT3 receives the second clock signal CK(n+1), and the second terminal of the third thin-film transistor NT3 is connected to the gate of the eighth thin-film transistor NT8. The gate of the fourth thin-film transistor NT4 receives the reverse scan signal D2U, the first terminal of the fourth thin-film transistor NT4 receives the third clock signal CK(n-1), and the second terminal of the fourth thin-film transistor NT4 is connected to the gate of the eighth thin-film transistor NT8. The first terminal of the eighth thin-film transistor NT8 is connected to a constant high voltage level VGH, and the second terminal of the eighth thin-film transistor NT8 is connected to the second node P.

[0056] In this embodiment, the feedback module 605 is connected to the first node Q and the second node P. The feedback module 605 is used to adjust the potential of the second node P according to the potential of the first node Q and to adjust the potential of the first node Q according to the potential of the second node P. Specifically, the feedback module 605 includes a sixth thin-film transistor NT6 and a fifth thin-film transistor NT5. The gate of the fifth thin-film transistor NT5 is connected to the second node P, the first terminal of the fifth thin-film transistor NT5 receives a constant voltage low-level signal VGL, and the second terminal of the fifth thin-film transistor NT5 is connected to the first node Q. The gate of the sixth thin-film transistor NT6 is connected to the first node Q, the first terminal of the sixth thin-film transistor NT6 receives a constant voltage low-level signal VGL, and the second terminal of the sixth thin-film transistor NT6 is connected to the second node P.

[0057] In this embodiment, functional module 606 is used to pull up the nth-level scan signal G(n) when the display panel experiences an abnormal power failure, and also to pull down the nth-level scan signal G(n) when the display panel is touched. Functional module 606 includes an eleventh thin-film transistor NT11, a twelfth thin-film transistor NT12, and a thirteenth thin-film transistor NT13. The gate of the twelfth thin-film transistor NT12 receives a first global control signal GAS1, the first terminal of the twelfth thin-film transistor NT12 receives a constant voltage low-level signal VGL, and the second terminal of the twelfth thin-film transistor NT12 is connected to the second node P. The gate of the eleventh thin-film transistor NT11 receives the first global control signal GAS1, the first terminal of the eleventh thin-film transistor NT11 is connected to its gate, and the second terminal of the eleventh thin-film transistor NT11 is connected to the second terminal of the ninth thin-film transistor NT9. The gate of the thirteenth thin-film transistor NT13 is connected to a second global control signal GAS2, the first terminal of the thirteenth thin-film transistor NT13 receives a constant voltage low-level signal, and the second terminal of the thirteenth thin-film transistor NT13 is connected to the second terminal of the ninth thin-film transistor NT9. When the display panel is displaying normally, the first global control signal GAS1 is a constant low-level signal; when the display panel is abnormally powered off, the first global control signal GAS1 is a constant high-level signal, causing the nth-level gate drive unit to output a pulled-up nth-level scan signal G(n). When the display panel is in touch-driven mode, the second global control signal GAS2 is a constant high-level signal, causing the nth-level gate drive unit to output a pulled-down nth-level scan signal G(n).

[0058] In this embodiment, the first thin-film transistor NT1 to the thirteenth thin-film transistor NT13 in the gate drive circuit are all N-type low-temperature polysilicon thin-film transistors. The first thin-film transistor NT1 to the thirteenth thin-film transistor NT13 can all be the aforementioned thin-film transistors with a first channel 1021 and a second channel 1041, to improve the problem of high bias stress on the channel near the drain when a dual-channel low-temperature polysilicon thin-film transistor is applied to the gate drive circuit, thereby improving the stability of the gate drive circuit. In particular, the fifth thin-film transistor NT5, due to continuous bias stress, is even more beneficial to improving the stability of the gate drive circuit as it is the aforementioned thin-film transistor.

[0059] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate driving circuit, characterized in that, The system includes a pull-up module, a pull-down module, and a feedback module. The pull-up module is used to pull up the nth level scan signal based on the voltage of the first node. The pull-down module is used to pull down the nth level scan signal based on the voltage of the second node. The feedback module includes a fifth thin-film transistor (TFT). The gate of the fifth TFT is connected to the second node. The first electrode of the fifth TFT is used to receive a constant low-level voltage signal. The second electrode of the fifth TFT is connected to the first node. The fifth TFT includes: The gate pattern includes a first gate and a second gate that are spaced apart and electrically connected to each other; and Active patterns, including: Source of extremely heavy doped region; A first transmission section is electrically connected to the heavily doped source section and at least partially overlaps with the first gate. In the direction from the first transmission section to the heavily doped source section, the first transmission section has a first size. The first transmission section includes a first channel, which is the portion of the first transmission section that overlaps with the first gate. In the direction from the first transmission section to the heavily doped source section, the first channel and the first gate have a third size. Drain heavily doped region; and The second transport section is electrically connected to the heavily doped drain section and at least partially overlaps with the second gate. In the direction from the second transport section to the heavily doped drain section, the second transport section has a second dimension. The second transport section includes a second channel, which is the portion of the second transport section that overlaps with the second gate. In the direction from the second transport section to the heavily doped drain section, the second channel and the second gate have a fourth dimension, and the third dimension is smaller than the fourth dimension. The first transmission section and the second transmission section are both located between the heavily doped source section and the heavily doped drain section, and the first transmission section and the second transmission section are spaced apart, with the first size being smaller than the second size.

2. The gate driving circuit according to claim 1, characterized in that, The first transport section includes at least one first lightly doped section, and in the direction from the first transport section to the source heavily doped section, at least one first lightly doped section has a fifth dimension; The second transport section includes at least one second lightly doped section, and in the direction of the second transport section pointing toward the heavily doped drain section, at least one second lightly doped section has a sixth dimension; The fifth dimension is smaller than the sixth dimension.

3. The gate driving circuit according to claim 2, characterized in that, The first transmission section includes two first lightly doped sections and a first channel, with the two first lightly doped sections respectively connected to opposite sides of the first channel; The second transport section includes two second lightly doped sections and a second channel, wherein the two second lightly doped sections are respectively connected to opposite sides of the second channel; The active pattern also includes an intermediate connecting portion, wherein the first transmission portion and the second transmission portion are respectively connected to opposite sides of the intermediate connecting portion.

4. The gate driving circuit according to claim 1, characterized in that, The active pattern is linear.

5. The gate driving circuit according to claim 1, characterized in that, The gate pattern further includes a connecting segment, the two ends of which are respectively connected to the first gate and the second gate, and the first gate and the second gate are located on the same side of the connecting segment.

6. A display panel, characterized in that, The display panel includes the gate driving circuit as described in any one of claims 1-5.

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