Semiconductor module

Abstract

A semiconductor module is disclosed. In an embodiment, the semiconductor module includes a low-side switch and a high-side switch. The low-side switch and the high-side switch are arranged laterally adjacent to each other and coupled in series between a ground package pad and a VIN package pad of the semiconductor module, forming a half-bridge configuration with an output node. The semiconductor module further includes a first capacitor pad coupled to a ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low-side switch, and the second capacitor pad is arranged vertically above the high-side switch.

Description

Background Technology

[0001] A semiconductor package may include one or more semiconductor devices within a housing. The package may include a substrate or lead frame, comprising external contacts for mounting the package on a redistribution board such as a printed circuit board, and internal electrical connections from the semiconductor devices to the substrate or lead frame. The housing may be formed of a plastic molding compound covering the semiconductor devices and the internal electrical connections.

[0002] US 2013 / 0221442 A1 discloses a package with an embedded power stage comprising two field-effect transistors arranged in a stacked manner and having a half-bridge configuration. The field-effect transistors are embedded in a dielectric substrate formed of multiple dielectric layers, which are stacked with one or more foil layers to facilitate the formation of electrical interconnects for the package. The power stage can be used as a component, for example, in a DC / DC converter.

[0003] The desired outcome is to further improve the efficiency and reliability of semiconductor packages that provide power stages. Summary of the Invention

[0004] According to the present invention, a semiconductor module including a low-side switch and a high-side switch is provided. The low-side switch and the high-side switch are arranged laterally adjacent to each other and coupled in series between a ground package pad and a VIN package pad of the semiconductor module, forming a half-bridge configuration with an output node. The semiconductor module further includes a first capacitor pad coupled to a ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low-side switch, and the second capacitor pad is arranged vertically above the high-side switch.

[0005] In some embodiments, the low-side switch includes a first side and a second side opposite to the first side, a source pad on the first side and a drain pad on the second side, wherein the source pad of the low-side switch is connected to a first conductive layer, and a first capacitor pad is arranged vertically above the drain pad of the low-side switch.

[0006] In some embodiments, the high-side switch includes a first side and a second side opposite to the first side, a source pad on the first side and a drain pad on the second side, wherein the drain pad of the high-side switch is connected to a second conductive layer substantially coplanar with the first conductive layer. A second capacitor pad is arranged vertically above the source pad of the high-side switch.

[0007] In some embodiments, the output node is formed by a third conductive layer extending between the drain pad of the low-side switch and the source pad of the high-side switch.

[0008] In some embodiments, the third conductive layer includes a first opening in which a first capacitor pad is disposed and a second opening in which a second capacitor pad is disposed. This embodiment can be used in semiconductor modules fabricated using a stack-up type process, such as embedded chip modules, wherein the third conductive layer is deposited and constructed layer by layer.

[0009] In some embodiments, the third conductive layer includes an opening in which a first capacitor pad and a second capacitor pad are disposed. This embodiment can be used in an embedded chip module or in a semiconductor module in which the third conductive layer is provided by a contact jig pre-fabricated and attached to a drain pad of a low-side switch and a source pad of a high-side switch. Capacitors may also be disposed in the opening and coupled to the first and second capacitor pads.

[0010] In some embodiments, the third conductive layer is spaced apart from the drain pad of the low-side switch and the source pad of the high-side switch by an electrically insulating layer, and the first capacitor pad is electrically insulated from the drain pad of the low-side switch by an electrically insulating layer.

[0011] In some embodiments, the semiconductor module further includes a first vertical conductive connection that electrically couples the first capacitor pad to the ground plane of the semiconductor module.

[0012] In some embodiments, the first vertical conductive connection includes a conductive via extending through the body of the low-side switch and electrically insulated from the body of the low-side switch.

[0013] In some embodiments, the first vertical conductive connection includes a conductive via extending on the side of the low-side switch and electrically insulated from the body of the low-side switch.

[0014] In some embodiments, the semiconductor module further includes a second vertical conductive connection that electrically couples the second capacitor pad to the VIN potential.

[0015] In some embodiments, the second vertical conductive connection is provided by a conductive via extending through the body of the high-side switch and electrically insulated from the body of the high-side switch, or by a conductive via extending on the side of the body of the high-side switch and electrically insulated from the body of the high-side switch.

[0016] In some embodiments, the second vertical conductive connection is provided by the body of the high-side switch, and a second capacitor pad is disposed on the first side of the high-side switch. The second capacitor pad is electrically coupled to the drain pad of the high-side switch through the body of the high-side switch. The body of the high-side switch may be formed of a highly doped semiconductor material and is conductive.

[0017] In some embodiments, grounding package pads and VIN package pads are arranged on a first side of the semiconductor module, the grounding package contact pads are coupled to a ground layer and a first conductive layer, and the VIN package contact pads are coupled to a second conductive layer.

[0018] In some embodiments, the first conductive layer provides a ground plane. In some embodiments, the first conductive layer provides a grounding encapsulation pad.

[0019] In some embodiments, the second conductive layer is coupled to the VIN package pad. In some embodiments, the second conductive layer provides the VIN package pad.

[0020] In some embodiments, the semiconductor module further includes a control chip.

[0021] In some embodiments, the semiconductor module further includes at least one further half-bridge configuration, the at least one further half-bridge configuration including a low-side switch and a high-side switch.

[0022] In some embodiments, the semiconductor module further includes a capacitor extending between and electrically connected to the first and second capacitor pads. The capacitor is electrically coupled between a ground package pad and a VIN package pad.

[0023] In some embodiments, the first capacitor pad and the second capacitor pad are exposed from the upper electrically insulating layer forming the outer surface of the semiconductor module. In these embodiments, the capacitors can be mounted on the module and are freely accessible.

[0024] In some embodiments, the first capacitor pad and the second capacitor pad are located in an upper electrically insulating layer forming the outer surface of the semiconductor module. In these embodiments, the capacitor may be embedded within the module, for example, embedded in the upper electrically insulating layer.

[0025] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0026] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings, and exemplary embodiments are described in detail below.

[0027] Figure 1 The diagram shows a power stage circuit including two transistor devices and a decoupling capacitor.

[0028] Figure 2The figure shows a schematic cross-sectional view of a semiconductor module according to an embodiment.

[0029] Figure 3 includes Figure 3A and Figure 3B The illustration shows a top view and a cross-sectional view of a semiconductor module according to an embodiment.

[0030] Figure 4 includes Figures 4A to 4E , its in Figures 4A to 4D The diagram shows a top view of a semiconductor module, and... Figure 4E The diagram shows the lower side switch along... Figure 4D A cross-sectional view of line AA.

[0031] Figure 5 includes Figures 5A to 5D ,exist Figure 5A The figure shows a top view of a semiconductor module according to an embodiment and... Figure 5B The figure shows its cross-sectional view. Figure 5C The figure shows a cross-sectional view of a semiconductor module according to an embodiment, and... Figure 5D The figure shows a cross-sectional view of a semiconductor module according to an embodiment.

[0032] Figure 6 includes Figure 6A and Figure 6B The illustration shows a top view and a cross-sectional view of a semiconductor module according to an embodiment.

[0033] Figure 7 includes Figure 7A and Figure 7B The illustration shows a top view and a cross-sectional view of a semiconductor module according to an embodiment. Detailed Implementation

[0034] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and which illustrate specific embodiments in which the invention may be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “front end,” “end,” etc., are used to indicate orientation with reference to the described figures(s). Because components of the embodiments may be positioned in many different orientations, these directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention should not be taken in a limiting sense, and the scope of the invention is defined by the appended claims.

[0035] Many exemplary embodiments will now be explained. In this context, the same structural features in the various figures are identified by the same or similar reference numerals. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or extension generally parallel to the lateral extension of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0036] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly on" or "directly extending onto" another element, no intermediate elements are present.

[0037] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0038] Figure 1 The diagram illustrates a power stage circuit 10, which includes a low-side switch 11 and a high-side switch 12. These switches are electrically coupled in series between a ground (GND) terminal 13 and a VIN terminal 14 and have a half-bridge configuration with an output (VSW) node 15. Each of the low-side switch 11 and the high-side switch 12 can be formed by a transistor device, such as a field-effect transistor (FET). The source of the transistor forming the low-side switch 11 is electrically coupled to the ground terminal 13, and the drain of the transistor forming the low-side switch 11 is electrically coupled to the output node 15. The source of the transistor forming the high-side switch 12 is electrically coupled to the output node 15, and the drain of the transistor forming the high-side switch 12 is electrically coupled to the VIN terminal 14. The gate of each of the low-side switch 11 and the high-side switch 12 is electrically coupled to a terminal of a gate driver circuit 16. Circuit 10 further includes a capacitor 17, which is coupled between ground terminal 13 and VIN terminal 14 and serves as a decoupling capacitor.

[0039] One parameter of very fast switching power stage circuits is parasitic stray loop inductance. Parasitic stray loop inductance directly affects the amplitude of drain-source voltage spikes during transistor switching. These spikes can potentially exceed the transistor's voltage ratings and have a significant impact on the safe operation of the power stage. Therefore, these spikes are undesirable. When the high-side switch 12 is turned off, the energy in the loop inductance charges the drain-source voltage VDS at the high-side switch 12, and for higher currents, the high-side switch 12 will enter avalanche, leading to carrier stress in the device. Additionally, the energy stored in the loop inductance will be lost, which negatively impacts efficiency when the power stage operates at high currents and frequencies.

[0040] The power loop involves two transistors and is closed by a capacitor 17, which acts as a VIN-to-ground decoupling capacitor and provides a high-bandwidth power supply during fast switching events. The power loop in... Figure 1 The value is indicated by the dashed line 18. The inductance of the power loop depends on the loop area; the smaller the area, the shorter the power current path and the smaller the inductance. According to the invention, the power loop inductance is reduced by improving the package design—including the position of capacitor 17 relative to the low-side switch 11 and the high-side switch 12.

[0041] According to the present invention, a semiconductor module is provided in which a low-side switch 11 and a high-side switch 12 are arranged laterally adjacent to each other and form a half-bridge circuit. A decoupling capacitor 17 may be mounted on pads arranged vertically above the low-side switch 11 and the high-side switch 12. Thus, the semiconductor module provides a power stage with a small size, a shorter power current path, and lower loop inductance. In some embodiments, the semiconductor module further includes capacitors mounted on the pads. Figure 2 Figure 7 illustrates an embodiment of a semiconductor module with such an arrangement. The loop inductance of the power stage provided by these semiconductor modules is reduced to less than 0.2 nH or less than 0.15 nH.

[0042] Figure 2 The illustrated semiconductor module 20 according to an embodiment includes a low-side switch 21 and a high-side switch 22 arranged laterally adjacent to each other and coupled in series via a connector 23. The low-side switch 21 and the high-side switch 22 are coupled between a ground package pad 24 and a VIN package pad 25 to form a half-bridge configuration with an output node 26. The semiconductor module 20 further includes a first capacitor pad 27 coupled to a ground potential and a second capacitor pad 28 coupled to a VIN potential. The first capacitor pad 27 is arranged vertically above the low-side switch 21, and the second capacitor pad 28 is arranged vertically above the high-side switch 22.

[0043] In some embodiments, the grounding package pad 24 is coupled to a potential greater than 0 but less than VIN and can be designated as a low-voltage package pad.

[0044] As used herein, the term "vertically above" encompasses an arrangement in which the first capacitor pad 27 partially overlaps the low-side switch 21 vertically, i.e., partially overlaps it in the z-direction in Cartesian coordinates, and completely overlaps it vertically. Similarly, the term includes an arrangement in which the second capacitor pad 28 partially overlaps the high-side switch 22 vertically, and completely overlaps it vertically.

[0045] The low-side switch 21 can be provided by a transistor device, such as a field-effect transistor, e.g., a MOSFET. The high-side switch 22 can also be provided by a transistor device, such as a field-effect transistor, e.g., a MOSFET. The low-side switch 21 and the high-side switch 22 can be formed in two separate semiconductor dies, as shown in the figures. However, in other embodiments not shown, the low-side switch 21 and the high-side switch 22 can be formed in a common semiconductor die and are laterally adjacent to each other in the common semiconductor die.

[0046] The first capacitor pad 27 can be coupled to the ground pad 24 to couple the first capacitor pad 27 to the ground potential. The second capacitor pad 28 can be electrically coupled to the VIN package pad 25 to electrically couple the second capacitor pad 28 to the VIN potential. The connector 23 for series coupling of the low-side switch 21 and the high-side switch 22 can be electrically coupled to the output node 26 of the package.

[0047] In some embodiments, the transistor device providing the low-side switch 21 and the transistor device providing the high-side switch 22 are vertical transistor devices, each including a vertical drift path. In some embodiments, the low-side switch 21 includes a source pad 29 on a first side 30 of the low-side switch 21 and a drain pad 31 on a second side 32 opposite to the first side 30. The source pad 29 of the low-side switch 21 is mounted on and electrically connected to a first conductive layer 33, and can be considered to be facing downwards such that the drain pad 31 faces upwards. In this embodiment, a first capacitor pad 27 is arranged vertically above the drain pad 31 of the low-side switch 21. The first conductive layer 33 may be formed from a portion of a lead frame—for example, a die pad that may also provide a ground package pad 24 for the semiconductor module 20.

[0048] The high-side switch 22 includes a source pad 34 on a first side 35 and a drain pad 36 on a second side 37 opposite to the first side 35. The drain pad 36 is mounted on and electrically connected to the second conductive layer 38. Therefore, the drain pad 36 of the high-side switch 22 faces downward and the source pad 34 faces upward. A second capacitor pad 28 is arranged vertically above the source pad 34 of the high-side switch 22. The second conductive layer 38 is substantially coplanar with the first conductive layer 33 on which the low-side switch 21 is mounted, so that the low-side switch 21 and the high-side switch 22 are arranged laterally adjacent to each other within the module 20.

[0049] Connector 23 may be formed of a third conductive layer 23 extending between the drain pad 31 of the low-side switch 21 and the source pad 34 of the high-side switch 22. Connector 23 is electrically coupled to the output node 26 of the semiconductor module 20. The third conductive layer 23 may be formed of metal foil or a deposited metal layer. In other embodiments, connector 23 may be formed of a pre-fabricated fixture.

[0050] In some embodiments, the third conductive layer 23 includes a first opening 39 in which a first capacitor pad 27 is disposed and a second opening 40 in which a second capacitor pad 28 is disposed. The first capacitor pad 27 and the second capacitor pad 28 are spaced apart from and electrically insulated from the surrounding third conductive layer 23. The first capacitor pad 27 and the second capacitor pad 28 may be substantially coplanar with the third conductive layer 23. Arranging the capacitor pads 27, 28 in the openings 39, 40 of the third conductive layer 23 allows the third conductive layer 23 to have a large area and low resistance, while allowing the capacitor pads 27, 28 to be arranged near the low-side switch 21 and the high-side switch 22, thereby shortening the power current path and reducing the loop inductance.

[0051] exist Figure 2 In the embodiment illustrated, the third conductive layer 23 is spaced apart from the drain pad 31 of the low-side switch 21 and the source pad 34 of the high-side switch 22 by an electrical insulating layer 41. The first capacitor pad 27 is electrically insulated from the drain pad 31 by the intermediate electrical insulating layer 41. The second capacitor pad 28 is electrically insulated from the source pad 34 (the second capacitor pad 28 is located above the source pad 34) by a portion of the intermediate electrical insulating layer 41.

[0052] By directly arranging the pads 27, 28 for the decoupling capacitors above at least a portion of the low-side switch 21 and the high-side switch 22, a compact arrangement is provided where the capacitors are arranged laterally adjacent to the high-side switch 22 and the low-side switch 21, or where the capacitors are located outside the module 20. Additionally, the distance between the low-side switch 21, the high-side switch 22, and the capacitor pads 27, 28 is reduced, which allows for a reduction in the distance between the switches 21, 22 and the capacitor pads 27, 28, and a reduction in the inductance of the power loop.

[0053] In some embodiments, the first capacitor pad 27 is electrically coupled to the ground plane of the semiconductor module by means of a vertical conductive connection. The ground plane may be a conductive layer on which the source pad 29 of the low-side switch 21 is mounted, or it may be a layer separate from the layer on which the source pad 29 of the low-side switch 21 is mounted. Figures 3 to 7 illustrate semiconductor modules according to various embodiments, the semiconductor module including a vertical conductive connection between the first capacitor pad 27 of the semiconductor module and the ground plane.

[0054] Figure 3A The figure shows a top view of the semiconductor module 50 according to an embodiment and Figure 3B The illustration shows a cross-sectional view of a semiconductor module 50 according to an embodiment. Figure 2 Similar to the embodiment illustrated in the figure, semiconductor module 50 includes a low-side switch 21 and a high-side switch 22, which are arranged laterally adjacent to each other and electrically coupled in series through conductive layer 23. The low-side switch 21 is provided by a vertical transistor device and has a source pad 29 on a first side 30, which is mounted on and electrically connected to a first conductive layer 33 coupled to a ground package pad 24. A drain pad 31 is arranged on the opposite second side 32, facing upwards, and electrically connected to conductive layer 23. The high-side switch 22 is also provided by a vertical transistor device and has a drain pad 36 arranged on a second side 37, which is arranged on and electrically connected to a second conductive layer 38 coupled to a VIN package pad 25. A source pad 34 is arranged on the first surface 35, facing upwards, and electrically coupled to a third conductive layer 23.

[0055] As in Figure 3AAs can be more easily seen in the top view, the third conductive layer 23 includes a first opening 39 in which a first capacitor pad 27 is arranged and a second opening 40 in which a second capacitor pad 28 is arranged. The first capacitor pad 27 is spaced apart from the sidewall defining the opening 39, thereby electrically insulating the first capacitor pad 27 from the third conductive layer 23. The first opening 39 and thus the first capacitor pad 27 are arranged vertically above the second side 32 of the low-side switch 21. The second capacitor pad 28 is spaced apart from the sidewall defining the second opening 40, thereby electrically insulating the first capacitor pad 28 from the third conductive layer 23. The second opening 40 and the second capacitor pad 28 are arranged vertically above the first side 35 of the high-side switch 22.

[0056] An electrical insulating layer 41 is disposed on the second side 32 of the low-side switch and extends across the gap between the low-side switch 21 and the high-side switch 22 and extends above the first side of the high-side switch 22. Specifically, the electrical insulating layer 41 separates the third conductive layer 23 vertically above the upper surfaces of the low-side switch 21 and the high-side switch 22, and also spaces the capacitor pads 27, 28 from the drain pads 31 and the source pads 34 on the upper surfaces of the first low-side switch 21 and the high-side switch 22, and electrically insulates the first capacitor pad 27 and the second capacitor pad 28 from the drain pads 31 and the source pads 34 on the upper surfaces of the first low-side switch 21 and the high-side switch 22.

[0057] The third conductive layer 23 is electrically coupled to the drain pad 31 through a plurality of conductive vias 51 extending through the electrically insulating layer 41. The source pad 34 of the high-side switch 22 is electrically coupled to the third conductive layer 23 through a plurality of conductive vias 52 extending through the electrically insulating layer 41. The sides of the low-side switch 21 and the high-side switch 22 are embedded in a further dielectric layer 63 on which the electrically insulating layer 41 is disposed.

[0058] In the embodiment illustrated in FIG3, the first capacitor pad 27 is electrically coupled to the first conductive layer 33 and the ground package pad 24 via a vertical conductive connection 53 extending vertically in the z-direction between the first capacitor pad 27 and the first conductive layer 33. A portion of the vertical conductive connection 53 is located in the body of the low-side switch 21 and extends through the body of the low-side switch 21. The vertical conductive connection 53 is formed by a conductive via 55 extending between the second side 32 and the first side 30 of the low-side switch 21. The conductive via 55 is electrically insulated from the material of the low-side switch 21 by an electrically insulating portion 54 formed in the sidewall of the via in the low-side switch 21 by a pad. The conductive via 55 arranged in the low-side switch 21 extends into a conductive via 56 extending through an electrically insulating layer 41 located on the second side 32 of the low-side switch 21. Therefore, the vertical conductive connection 53 is formed by a stack of conductive vias 55 and 56.

[0059] In the embodiment illustrated in FIG3, the grounding package pad 24 is located vertically below the low-side switch 21 and the first conductive layer 33, and is spaced apart from the first conductive layer 33 by a further insulating layer 58.

[0060] The first conductive layer 33 is electrically connected to the ground package pad 24 by a plurality of conductive vias 57 extending through a further insulating layer 58 and between the ground package pad 24 and the first conductive layer 33.

[0061] In the embodiment illustrated in FIG3, the second capacitor pad 28 is electrically coupled to the VIN package pad 25 via a vertical conductive connection 59 extending between the second capacitor pad 28 and the second conductive layer 38. The second vertical conductive connection 59 includes a conductive via 60 located in the body of the high-side switch 22 and extending from the first side 35 through the body of the high-side switch 22 to the second side 37, and is electrically insulated from the body of the high-side switch 22 by an electrically insulating portion 61 of the sidewall of a via or through-hole arranged in the material of the high-side switch 22. A conductive via 62 is also located between the first surface 35 of the high-side switch 22 and the second capacitor pad 28 extending through the electrically insulating layer 41 and located above the conductive via 60, and connected to the conductive via 60. The VIN package pad 33 is vertically located below the high-side switch 22. The second conductive layer 38 is electrically connected to the VIN package pad 33 via a plurality of conductive vias 64 extending through the second electrically insulating layer 58.

[0062] Semiconductor module 50 may be formed by a stack of substantially flat electrically insulating layers 58, 63, 41 and conductive layers 24, 25, 26; 33, 38; 23, wherein a low-side switch 21 and a high-side switch 22 are embedded in a layer 63 of electrically insulating material. Semiconductor module 50 may be considered to have a stacked or embedded structure. Each conductive layer is connected in the vertical direction through conductive vias. In some embodiments, one or more of the electrically insulating layers and adjacent conductive layers may be formed by a pre-formed intermediate arrangement (e.g., a circuit board type arrangement).

[0063] The power circuit 18 of the power stage is indicated by a dashed line in Figure 3. The stacked arrangement of capacitor pads 27 and 28 above the low-side switch 21 and the high-side switch 22, respectively, allows for a smaller distance between the capacitors extending between the half-bridge configuration and the capacitor pads 27 and 28, resulting in a reduction in the effective loop area. Additionally, current flows along the surfaces of vias 55 and 60, reducing the vertical loop and decreasing the inductance of the power circuit 18 to, for example, less than 0.2 nH.

[0064] In the embodiment illustrated in FIG3, capacitor pads 27, 28 have lateral regions and positions such that their regions in the xy-plane completely overlap with the lower-side switch 21 and the higher-side switch 22 located below them in the vertical or z-direction, as can be seen through the positions of the sides 65, 66 of the lower-side switch 21 and the higher-side switch 22. In other embodiments, capacitor pads 27, 28 may partially overlap the lower-side switch 21 and the higher-side switch 22 in the vertical direction, respectively. For example, a portion of the first capacitor pad 27 extends over and across one or more sides of the lower-side switch 21, such that a portion of it is laterally positioned adjacent to one or more sides of the lower-side switch 21 and vertically positioned above the electrical insulation layer 63.

[0065] Figures 4A to 4C The illustrations include three top views of the semiconductor module 70 arranged as shown in Figure 3. Figure 4A The figure shows a top view of the third conductive layer 23. Figure 4B The diagram shows that the third conductive layer 23 has been removed, and a top view of the low-side switch 21 and the high-side switch 22 can be seen. The positions of the first capacitor pad 27 above the low-side switch 21 and the second capacitor pad 28 above the high-side switch 22 are also shown. Figure 4C The illustration shows a top view of the bottom conductive layer that provides VIN package pad 38, ground package pad 24 and conductive via 64.

[0066] As in Figure 4B As most readily apparent, the low-side switch 21 is positioned toward the first lateral side of the package module 70 and extends across most of the width of the semiconductor module 70. Each of the low-side switch 21 and the high-side switch 22 has a substantially rectangular shape, and in this embodiment, the low-side switch 21 has a larger area than the high-side switch 22. In other embodiments, the low-side switch 21 and the high-side switch 22 may have substantially the same area. The high-side switch 22 is arranged such that its long side is substantially perpendicular to the long side of the low-side switch 21.

[0067] The semiconductor module 70 also includes a control chip 71, which may include gate driver circuitry for driving the gates of the low-side switch 21 and the high-side switch 22. The control chip 71 is arranged laterally adjacent to the low-side switch 21 and the high-side switch 22.

[0068] The first capacitor pad 27 is vertically positioned above the low-side switch 21. In this embodiment, the entire area of ​​the first capacitor pad 27 vertically overlaps the top side of the low-side switch 21. Similarly, the second capacitor pad 28 is located above the upper surface of the high-side switch 22, and its area completely overlaps the upper surface of the high-side switch 22. The capacitor pads 27 and 28 are positioned toward the mutually facing and substantially aligned sides 65 and 66 of the low-side switch 21 and the high-side switch 22, respectively, such that a capacitor can be mounted on the capacitor pads 27 and 28, which extend across the gap between the sides 65 and 66 of the low-side switch 21 and the high-side switch 22 and are substantially perpendicular to the sides 65 and 66.

[0069] Semiconductor module 70 includes an output node 26, which is laterally positioned adjacent to the low-side switch 21 and extends substantially across the width of the module 70, surrounding the low-side switch 21. A third conductive layer 23, providing a series connection between the drain pad 31 of the low-side switch 21 and the source pad 34 of the high-side switch 22, extends laterally such that it lies over the entire area of ​​the low-side switch 21, the entire area of ​​the high-side switch 22, and the entire area of ​​the output node 26. The area of ​​the conductive layer 23 is increased by including a sloped surface between the portions located above the low-side switch 21 and the high-side switch 22, such that a portion of the third conductive layer 23 lies over the area of ​​the module 70 disposed between the high-side switch 22, the low-side switch 21, and the control chip 71. Since the contact pads 27 and 28 for the capacitor are located within the openings 39 and 40 of the third conductive layer 23 above the low-side switch 21 and the high-side switch 22, respectively, instead of being positioned laterally adjacent to the third conductive layer 23 and laterally adjacent to the low-side switch 21 and the high-side switch 22 (e.g., between the control chip 71 and the sides of the high-side switch 22 and the low-side switch 21), this increase in the area of ​​the conductive layer 23 is made possible.

[0070] The third conductive layer 23 can extend in a single plane above the top sides 32, 35 of the high-side switch 22 and the low-side switch 21, and above the top surface of the output node 26. The conductive layer 23 can be electrically coupled to the source pad 34 of the high-side switch 22 and the drain pad 31 of the low-side switch 21 through multiple conductive vias 52, 51, and can be electrically coupled to the upper surface of the output node 26 through multiple conductive vias 72.

[0071] exist Figure 4C In the top view, the position of gate pad 73 on the top side 35 of the high-side switch 22 can be seen. Gate pad 73 is electrically connected to the control chip 71 via conductive connection 74. The low-side switch 21 has a source-down arrangement such that gate pad 75 is located on the lower surface adjacent to source pad 29.

[0072] Figure 4D The illustration shows a top view of the semiconductor module 70 according to an embodiment, and Figure 4E It is along the low-side switch 21 Figure 4D A cross-sectional view of line AA. Semiconductor module 70 has a cross-sectional view with... Figures 4A to 4C A similar layout is shown, but the arrangement of the gate pad 75 of the low-side switch 21 differs. Figure 4D and Figure 4E In the embodiment illustrated in the figure, the low-side switch 21 has a source-down arrangement and includes a through-silicon via 76, such that the gate pad 75 is arranged on the upper surface 32 adjacent to the drain pad 31 of the low-side switch 21.

[0073] Figure 5A The figure shows a top view of a semiconductor module 80 providing a power stage according to an embodiment. Figure 5B The figure shows a side view of semiconductor module 80. The power stage includes two switches in a half-bridge configuration and pads for decoupling capacitors. The arrangement of semiconductor module 80 differs from that of semiconductor module 50 shown in Figure 3 in that it is used for vertical conductive connections 59 to electrically couple the second capacitor pad 28 to the second conductive layer 38 and the VIN potential.

[0074] In semiconductor module 80, high-side switch 22 includes conductive pads 81 on its first surface 35, positioned adjacent to source pads 34 and to an active region schematically indicated by frame 82 of the transistor device. For MOSFET devices, the active region 82 typically includes an active trench of the transistor device. In this embodiment, the body 83 of high-side switch 22 (i.e., the semiconductor material providing the die for the vertical transistor device and high-side switch 22) is at VIN potential. In the region outside active region 82, body 83 is formed of highly doped semiconductor (typically highly doped silicon). Body 83 is coupled to a second conductive layer 38 by means of drain pads 36 on the opposite side 37 of high-side switch 22. Pads 81 located on the opposite upper side 35 of high-side switch 22 are also coupled to the second conductive layer 38 and VIN potential by means of the body of high-side switch 22.

[0075] Figure 5C The diagram illustrates the arrangement of the connection between pad 81 and body 83. Figure 5A and Figure 5B The illustration shows a cross-sectional view of a different semiconductor module 80 in an embodiment. The uppermost portion of the active region 82 has a certain doping level, which, due to processing, is similar to the uppermost portion of the non-active region of the body 83—it is in Figure 5CThe doping level is indicated by reference numeral 85. This top region 85 has a higher resistance and contributes more to the total resistance of the connection between the pad 81 and the drain pad 36 located on the opposite side of the high-side switch 22. This resistance can be reduced by including a deposit 86 formed by a region of the body 83 that includes a higher doping level. The deposit 86 is positioned adjacent to the active region 82 and extends from the upper side 35 through the lower doped region 85 to at least reach the highly doped region of the body 83. In some embodiments, the deposit extends to the opposite lower side 37 of the high-side switch 22.

[0076] The second capacitor pad 28, located above the high-side switch 22, is situated above the pad 81 on the first surface 35 of the high-side switch 22. The second capacitor pad 28 is electrically coupled to the VIN potential and the second conductive layer 38 via a conductive via 84 and the material of the body 83 of the high-side switch 22. The conductive via 84 extends from the second capacitor pad 28 through the electrically insulating layer 41 to the pad 81 on the upper surface 35 of the high-side switch. The material of the body 83 of the high-side switch 22 is electrically coupled to the drain pad 36 on the opposite side 37 of the high-side switch 22, which is then electrically connected to the second conductive layer 38 and the VIN package pad 25.

[0077] The first capacitor pad 27 is electrically coupled to the first conductive layer 24 and ground potential via a vertical conductive connection 53, which extends through the body of the low-side switch 21 and includes a conductive via 55 electrically insulated from the body of the low-side switch 21 and the conductive via 56, as illustrated in the semiconductor module 50 in FIG3.

[0078] In other embodiments, the electrical insulating layer 41 and the conductive via 84 are omitted, and the capacitor pad 28 is directly disposed on the upper surface 35 of the high-side switch 22.

[0079] Figure 5D The figure shows a cross-sectional view of a semiconductor module 80 in which capacitor pads 27 and 28 can be directly disposed on the upper surface 35 of the high-side switch 22 and the upper surface 32 of the low-side switch 21, respectively. A third conductive layer 23 is provided by a contact jig 87 having openings 88 for the first capacitor pads 27 and 28. The openings 88 have lateral dimensions and shapes such that the outer peripheral areas of both the first and second capacitor pads 27 and 28, as well as the low-side and high-side switches 21 and 22, are exposed at the bottom of the openings 88. The jig 87 is disposed on the upper surface 35 of the high-side switch 22 and the upper surface 32 of the low-side switch 21, such that each of the first and second capacitor pads 27 and 28 is disposed at the bottom of the opening 88. Figure 5DA capacitor (not shown) can be mounted in the hole 88 and extends between the first capacitor pad 27 and the second capacitor pad 28, bridging the gap between adjacent sides of the low-side switch 21 and the high-side switch 22. This arrangement can be useful for modules with packages such as PQFN packages—which are fabricated without using a stacking process to embed the low-side switch 21 and the high-side switch 22.

[0080] Figure 6A The figure shows a top view of a semiconductor module 90 providing a power stage according to an embodiment. Figure 6B The illustration shows a side view of a semiconductor module 90. The power stage includes two switches in a half-bridge configuration and pads for decoupling capacitors. Semiconductor module 90 differs from semiconductor module 50 illustrated in FIG. 3 in the arrangement of the first vertical conductive connection 53 between the first capacitor pad 27 and the first conductive layer 24 regarding the low-side switch 21. In semiconductor module 90, a portion of the vertical conductive connection 53 takes the form of a conductive layer 91 located on the side 65 of the low-side switch 21 instead of in conductive vias surrounded on all sides by the material of the low-side switch 21. The conductive layer 91 on the side 65 can be electrically insulated from the low-side switch 21 by an electrically insulating layer 92 located on the side 65 of the low-side switch 21. The first vertical conductive connection 53 also includes a conductive via 56 extending through an electrically insulating layer 41 located on the top surface 32 of the low-side switch 21. This arrangement of layers on the side can be more easily manufactured compared to forming conductive vias that are the thickness of the semiconductor die providing the switch.

[0081] In semiconductor module 90, the second vertical conductive connection 59, which electrically connects the second capacitor pad 28 to the second conductive layer 38, also includes a layered portion 93 located on the side 66 of the high-side switch 22, rather than in a conductive via surrounded on all sides by the material of the high-side switch 22. The conductive layer 93 may be electrically insulated from the body of the high-side switch 22 by an insulating layer 94 located on the side 66. In embodiments where the body of the high-side switch 22 is at the VIN potential, the conductive layer 93 may also be located directly on the side 66. The second vertical conductive connection 59 also includes a conductive via 62 extending through the electrically insulating layer 41 and thus contacting both the second capacitor pad 28 and the second conductive layer 38.

[0082] For both the low-side switch 21 and the high-side switch 22, the arrangement of the first vertical conductive connection 53 and the second vertical conductive connection 59 within the semiconductor module can be the same or different. For example, one of the vertical conductive connections 53, 59 of the semiconductor module 90 can be provided by means of a conductive via as used in the embodiment illustrated in FIG. 3, and the other of the vertical conductive connections 53, 59 has a portion extending on the side of the respective switch 21, 22, as illustrated, for example, in FIG. 6.

[0083] In the semiconductor module 90 illustrated in FIG6, the first capacitor pad 27 and the second capacitor pad 28 may partially overlap with the low-side switch 21 and the high-side switch 22, and may extend on the outer peripheral edges of the low-side switch 21 and the high-side switch 22 provided by the sides 65 and 66, respectively.

[0084] In some embodiments, one or both of the capacitor pads 27, 28 may be vertically positioned above but not overlapping the respective switches. In this embodiment, the capacitor pads are arranged laterally between the opposing sides 65, 66 of the lower-side switch 21 and the higher-side switch 22. This embodiment can be used to save lateral space, such as space in the y-direction, compared to an arrangement where the capacitor pads 27, 28 are arranged laterally adjacent to sides of the switches that are not opposing each other. This embodiment can be used if the capacitor size is suitable for matching within the available space between the opposing sides 65, 66 of the switches 21, 22.

[0085] In some embodiments, such as in reference Figure 2 In the embodiments described in Figure 6, the semiconductor module is provided in a form in which capacitor pads 27, 28 are accessible from the outside of the module, so that capacitors of desired ratings can be mounted on and electrically coupled to capacitor pads 27, 28. For example, capacitors can be soldered to capacitor pads 27, 28. In embodiments in which the semiconductor module includes a molding compound providing the outer surface of the module, capacitor pads 27, 28 can be exposed from the molding compound. In embodiments in which the module includes an upper electrical insulating layer (e.g., a stacked or so-called embedded chip type module), the first capacitor pad 27 and the second capacitor pad 28 can be exposed from the electrical insulating material of the upper layer and are accessible from the outside of the module 90 from the top surface 96 of the module 90. Package pads 24, 25, 26 are arranged on opposite sides 95 of the module 90. These embodiments can be useful for applications in which the capacitance value depends on the purpose and operation of the circuit, so that capacitors with suitable capacitance can be selected for the specific application and circuit in which the module is used.

[0086] In some embodiments, the semiconductor module further includes capacitors mounted on and electrically connected to capacitor pads 27, 28. These embodiments can be useful for standardized circuits in which the appropriate value of the capacitance is known in advance.

[0087] In some embodiments, a semiconductor module may include more than one half-bridge configuration, each half-bridge configuration including a low-side switch and a high-side switch. For example, a semiconductor module may include three half-bridge configurations to provide a three-phase inverter circuit. Each half-bridge configuration within the module may have the same configuration to simplify manufacturing. However, the configuration of each switch and half-bridge may differ depending on the requirements of the specific circuit.

[0088] In some embodiments, the semiconductor module is provided with embedded capacitors. In these embodiments, the capacitor pads 27, 28 are located within the electrical insulation layer of the module and are not freely accessible from the outside of the module.

[0089] Figure 7A The top view of module 100 is shown. Figure 7B The diagram shows a side view of module 100. In addition to providing a power stage including two switches with a half-bridge configuration and pads for decoupling capacitors, module 100 also includes an embedded decoupling capacitor 101. The capacitor 101 is mounted on a first capacitor pad 27 vertically above the low-side switch 21 and a second capacitor pad 28 vertically above the high-side switch 22, and is electrically coupled between the first capacitor pad 27 and the second capacitor pad 28.

[0090] The first capacitor pad 27 is coupled to the ground package pad 24 via a first vertical conductive connection 53 and the second capacitor pad 28 is electrically coupled via a second vertical conductive connection 59. The first vertical conductive connection 53 includes a conductive via 55 extending through the body of the low-side switch 21 to the ground package pad 24, and the second vertical conductive connection 59 includes a conductive via extending through the body of the high-side switch 22 to the VIN package pad 25.

[0091] Capacitor 101 is embedded within insulating layer 102, which is situated above and covers the third conductive layer 23, the top sides 32 and 35 of low-side switch 21 and high-side switch 22, and capacitor 101. Package contact pads 24 and 25 are located on opposite surfaces 103 of semiconductor module 100.

[0092] In this embodiment, the first conductive layer and grounding package pad 24 are provided by a first die pad of the leadframe on which the low-side switch 21 is mounted, and in particular the source pad 29 of the low-side switch 21. Similarly, the second conductive layer 38 and VIN package pad 25 are provided by a second die pad of the leadframe on which the high-side switch 22 is mounted, and in particular the drain pad 36 of the high-side switch 22. The third conductive layer 23 is electrically coupled to a further portion of the leadframe through one or more conductive vias, which is located in the module 100 in Figure 7B In a plane that cannot be seen in a cross-sectional view.

[0093] An arrangement (such as a leadframe) in which a single conductive portion provides a first conductive layer 33 and a grounding package pad 24, and a single conductive portion provides a second conductive layer 38 and a VIN package pad 25, can also be used in accordance with reference. Figure 2 In the modules of the embodiment described in Figure 6.

[0094] For ease of description, spatial relative terms such as "below," "below," "lower part," "above," and "upper part" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, areas, sections, etc., and are not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0095] As used herein, the terms “having,” “comprising,” “including,” and “including” are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “an,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is to be understood that, unless otherwise specifically indicated, features of the various embodiments described herein can be combined with each other.

[0096] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A semiconductor module, comprising: Low-side switch; High-side switch; The low-side and high-side switches are arranged laterally adjacent to each other and coupled in series between the ground package pad and the VIN package pad of the semiconductor module to form a half-bridge configuration with an output node. The first capacitor pad coupled to ground potential; The second capacitor pad coupled to the VIN potential; The first capacitor pad is arranged vertically above the low-side switch, and the second capacitor pad is arranged vertically above the high-side switch. The low-side switch includes a first side and a second side opposite to the first side, a source pad on the first side and a drain pad on the second side, wherein the source pad of the low-side switch is connected to a first conductive layer and a first capacitor pad is arranged vertically above the drain pad of the low-side switch. The high-side switch includes a first side and a second side opposite to the first side, a source pad on the first side and a drain pad on the second side, wherein the drain pad of the high-side switch is connected to a second conductive layer substantially coplanar with the first conductive layer, and wherein a second capacitor pad is arranged vertically above the source pad of the high-side switch. The output node is formed by a third conductive layer extending between the drain pad of the low-side switch and the source pad of the high-side switch. The third conductive layer includes a first opening in which a first capacitor pad is disposed and a second opening in which a second capacitor pad is disposed, or the third conductive layer includes an opening in which a first capacitor pad and a second capacitor pad are disposed.

2. The semiconductor module of claim 1, wherein the third conductive layer is spaced apart from the drain pad of the low-side switch and the source pad of the high-side switch by an electrically insulating layer, and the first capacitor pad is electrically insulated from the drain pad of the low-side switch by an electrically insulating layer.

3. The semiconductor module according to claim 1 or 2, further comprising a first vertical conductive connection, the first vertical conductive connection electrically coupling the first capacitor pad to the ground plane of the semiconductor module.

4. The semiconductor module according to claim 3, wherein the first vertical conductive connection comprises: A conductive via extending through the body of the low-side switch and electrically insulated from the body of the low-side switch, or A conductive via extending on the side of the low-side switch and electrically insulated from the body of the low-side switch.

5. The semiconductor module according to claim 1, further comprising a second vertical conductive connection, the second vertical conductive connection electrically coupling the second capacitor pad to the VIN potential.

6. The semiconductor module of claim 5, wherein the second vertical conductive connection is provided by a conductive via extending through the body of the high-side switch and electrically insulated from the body of the high-side switch, or by a conductive via extending on the side of the body of the high-side switch and electrically insulated from the body of the high-side switch.

7. The semiconductor module of claim 5, wherein the second vertical conductive connection is provided by the body of the high-side switch, and the second capacitor pad is disposed on the first side of the high-side switch and electrically coupled to the drain pad of the high-side switch.

8. The semiconductor module of claim 3, wherein the ground package pad and the VIN package pad are disposed on a first side of the semiconductor module, the ground package contact pad is coupled to a ground layer and a first conductive layer, and the VIN package contact pad is coupled to a second conductive layer.

9. The semiconductor module according to claim 1, further comprising a control chip.

10. The semiconductor module of claim 1, further comprising at least one further half-bridge configuration, the at least one further half-bridge configuration comprising a low-side switch and a high-side switch.

11. The semiconductor module of claim 1, further comprising a capacitor extending between the first capacitor pad and the second capacitor pad and electrically connected to the first capacitor pad and the second capacitor pad.

12. The semiconductor module according to claim 1, wherein The first capacitor pad and the second capacitor pad are exposed from the upper electrically insulating layer forming the outer surface of the semiconductor module, or The first capacitor pad and the second capacitor pad are located in the upper electrical insulating layer that forms the outer surface of the semiconductor module.

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