Display device and method for manufacturing a display device

Abstract

A display device and a manufacturing method of a display device are provided. The display device includes a substrate, a buffer layer disposed on the substrate and including a first buffer film and a second buffer film sequentially stacked in a thickness direction, a semiconductor pattern disposed on the buffer layer, a gate insulating film disposed on the semiconductor pattern, and a gate electrode disposed on the gate insulating film, wherein the first buffer film and the second buffer film include the same substance as each other, and a density of the first buffer film is greater than a density of the second buffer film.

Description

Technical Field

[0001] This invention relates to a display device and a method for manufacturing the display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are used in a variety of electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEPs), and organic light-emitting displays (OLEDs). In these flat panel displays, because organic light-emitting displays include self-emissive light-emitting elements for each pixel of the display panel, images can be displayed even without a backlight unit that provides light to the display panel.

[0003] An organic light-emitting display device may include a plurality of pixels, and each of the plurality of pixels may include: a light-emitting element; a driving transistor that adjusts the amount of driving current supplied from a power line to the light-emitting element according to the voltage of its gate electrode; and a switching transistor for supplying a data voltage of a data line to the gate electrode of the driving transistor in response to a scan signal of a scan line. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a display device and a method for manufacturing the display device that can block or minimize hydrogen (H) flowing into the semiconductor layer from the bottom of the semiconductor layer.

[0005] The technical problems of this invention are not limited to those mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art through the following description.

[0006] A display device according to an embodiment for solving the above-mentioned technical problems includes: a substrate; a buffer layer disposed on the substrate, including a first buffer film and a second buffer film stacked sequentially along the thickness direction; a semiconductor pattern disposed on the buffer layer; a gate insulating film disposed on the semiconductor pattern; and a gate electrode disposed on the gate insulating film, wherein the first buffer film and the second buffer film comprise the same material as each other, and the density of the first buffer film is greater than the density of the second buffer film.

[0007] The density of the second buffer membrane can be 2.5 g / cm³. 3 the following.

[0008] The second buffer membrane can be arranged below the first buffer membrane.

[0009] The thickness of the second buffer film can be more than three times the thickness of the first buffer film.

[0010] The [NH] / [Si-H] value of the first buffer membrane can be greater than the [NH] / [Si-H] value of the second buffer membrane, where [NH] represents the number of bonds between nitrogen and hydrogen per unit volume, and [Si-H] represents the number of bonds between silicon and hydrogen per unit volume.

[0011] The [NH] / [Si-H] value of the first buffer membrane can be more than five times the [NH] / [Si-H] value of the second buffer membrane.

[0012] The [NH] / [Si-H] value of the second buffer membrane can be in the range of 1.3 to 3.0.

[0013] The first buffer film and the second buffer film may include silicon nitride.

[0014] The buffer layer may further include a third buffer film, comprising silicon oxide, wherein the third buffer film is disposed on the upper part of the first buffer film and the second buffer film.

[0015] The semiconductor pattern can be arranged on the third buffer film.

[0016] The display device may further include: a fourth buffer film disposed between the first buffer film and the second buffer film, and the density of the fourth buffer film gradually changes along the thickness direction, wherein the density of the fourth buffer film gradually decreases from the first buffer film side toward the second buffer film side.

[0017] The [NH] / [Si-H] values ​​of the first buffer membrane and the second buffer membrane can be measured using a Fourier transform infrared spectrometer (FT-IR spectrometer).

[0018] The semiconductor pattern may include oxide semiconductors.

[0019] A display device according to an embodiment for solving the above-mentioned technical problems includes: a substrate; a first buffer film disposed on the substrate; a semiconductor pattern disposed on the first buffer film; a gate insulating film disposed on the semiconductor pattern; and a gate electrode disposed on the gate insulating film, wherein the value of [NH] / [Si-H] of the first buffer film is in the range of 1.3 to 3.0.

[0020] It may also include: a second buffer membrane disposed on the first buffer membrane, wherein the first buffer membrane and the second buffer membrane comprise the same material as each other, and the density of the first buffer membrane is less than the density of the second buffer membrane.

[0021] The [NH] / [Si-H] value of the first buffer membrane can be smaller than the [NH] / [Si-H] value of the second buffer membrane.

[0022] The density of the first buffer membrane can be 2.5 g / cm³. 3 the following.

[0023] A method for manufacturing a display device according to an embodiment for solving the above-mentioned technical problems includes the following steps: forming a first buffer film on a substrate; forming a second buffer film on the first buffer film, the second buffer film comprising the same material as the first buffer film and having a density less than that of the first buffer film; and dehydrogenating the first buffer film and the second buffer film by heat treatment.

[0024] After the step of dehydrogenating the first buffer film and the second buffer film, the following steps may be included: forming a semiconductor pattern on the second buffer film; and forming a gate electrode on the gate insulating film.

[0025] The [NH] / [Si-H] value of the first buffer membrane that has undergone the above dehydrogenation can be greater than the [NH] / [Si-H] value of the second buffer membrane that has undergone the above dehydrogenation, wherein the [NH] / [Si-H] value of the second buffer membrane is in the range of 1.3 to 3.0.

[0026] A display device and a method for manufacturing the display device are provided in which the transistors including the semiconductor layer can operate more smoothly by blocking or minimizing the flow of hydrogen gas (H2) from the lower part of the semiconductor layer into the semiconductor layer.

[0027] The effects of the embodiments are not limited to those illustrated above, and more diverse effects are included in this specification. Attached Figure Description

[0028] Figure 1 This is a plan view of a display device according to one embodiment.

[0029] Figure 2 This is a block diagram schematically illustrating a display device according to one embodiment.

[0030] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to one embodiment.

[0031] Figure 4This is a cross-sectional view of the display panel of a display device according to one embodiment (main embodiment).

[0032] Figure 5 It is magnification Figure 4 Enlarged view of region A (main embodiment).

[0033] Figure 6 This is a graph illustrating the threshold voltage of a transistor with or without a second buffer membrane according to one embodiment.

[0034] Figures 7 to 14 This is a cross-sectional view (manufacturing method) of each process step in a method for manufacturing a display device according to an embodiment.

[0035] Figure 15 This is an enlarged view of a portion of the cross-section of a display device according to another embodiment (another embodiment 1 - change in the stacking order of the buffer layer).

[0036] Figure 16 This is a graph illustrating the threshold voltage of a transistor with or without a second buffer film according to another embodiment (another embodiment 1 - effect).

[0037] Figure 17 This is an enlarged view of a portion of the cross-section of a display device according to yet another embodiment (another embodiment 2 - omitting the first buffer film with a higher density).

[0038] Figure 18 This is a graph illustrating the threshold voltage of a transistor with or without a second buffer membrane according to yet another embodiment (Another embodiment 2 - Effect).

[0039] Figure 19 This is an enlarged view of a portion of a cross-section of a display device according to yet another embodiment (another embodiment 3 - including a plurality of second buffer films).

[0040] Figure 20 It is an enlarged view of a portion of the cross-section of a display device according to yet another embodiment (another embodiment 4 - including a fourth buffer film with gradually changing film density).

[0041] Figure 21 This is an enlarged view of a portion of the cross-section of a display device according to yet another embodiment (another embodiment 5 - including a fourth buffer film, omitting the first buffer film).

[0042] Figure 22 This is a cross-sectional view of a display device according to yet another embodiment (another embodiment - a second buffer film arranged only in a portion of the area).

[0043] Explanation of reference numerals in the attached figures

[0044] 1: Display device 130: Semiconductor layer

[0045] 10: Display panel 140: Second conductive layer

[0046] 101: Base substrate; 150: Third conductive layer

[0047] 110: First conductive layer; 160: Fourth conductive layer

[0048] 120: Buffer layer; 121: First buffer membrane

[0049] 122: Second buffer membrane 123: Third buffer membrane Detailed Implementation

[0050] References and Appendix Figure 1 The advantages and features of the invention, as well as the methods for achieving them, will become clear from the detailed embodiments described below. However, the invention can be implemented in many different forms and is not limited to the embodiments disclosed below. These embodiments are provided only to complete the disclosure of the invention and to fully inform those skilled in the art of the invention of its scope. The invention is defined only by the scope of the claims.

[0051] The reference to elements or layers being "on" other elements or layers includes situations where they are immediately above or adjacent to other elements, or where other layers or elements are sandwiched in between. Throughout the specification, the same reference numerals refer to the same constituent elements.

[0052] Although terms such as "first" and "second" are used to describe various constituent elements, these constituent elements are clearly not limited to these terms. These terms are only used to distinguish one constituent element from another. Therefore, the "first constituent element" mentioned below can obviously also be a "second constituent element" within the technical concept of this invention.

[0053] The specific embodiments will now be described with reference to the accompanying drawings.

[0054] Figure 1 This is a plan view of a display device according to one embodiment. Figure 2 This is a block diagram schematically illustrating a display device according to one embodiment.

[0055] As a device for displaying video or still images, the display device 1 can be used not only as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, smartwatch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-portable mobile PCs (UMPCs), but also as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things products.

[0056] According to one embodiment, the display device 1 can be configured as a substantially rectangular shape on a plane. The display device 1 can be a rectangle with vertical corners on the plane. However, it is not limited to this; the display device 1 can be a rectangular shape with rounded corners on the plane.

[0057] In the figure, the first direction DR1 represents the horizontal direction of the display device 1 in the plan view, and the second direction DR2 represents the vertical direction of the display device 1 in the plan view. Furthermore, the third direction DR3 represents the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 intersect each other perpendicularly, and the third direction DR3 intersects both the first direction DR1 and the second direction DR2 perpendicularly in the direction intersecting the plane containing both directions. However, the directions mentioned in the embodiments should be understood as relative directions, and the embodiments are not limited to the mentioned directions.

[0058] Unless otherwise defined, in this specification, "upper part", "upper surface" and "upper side" as referred to with respect to a third party DR3 mean the display surface side with respect to display device 1, and "lower part", "lower surface" and "lower side" mean the opposite side of the display surface with respect to display device 1.

[0059] According to one embodiment, the display device 1 may include a display panel 10, a timing control unit 21, a data driving unit 22, and a scanning driving unit 30.

[0060] Display panel 10 may be an organic light-emitting display panel. In the following embodiments, an organic light-emitting display panel is used as an example to illustrate the use of an organic light-emitting display panel as display panel 10, but it is not limited to this. Other types of display panels, such as liquid crystal displays (LCDs), quantum dot organic light-emitting display panels (QD-OLEDs), quantum dot liquid crystal displays (QD-LCDs), quantum nano light-emitting display panels (nano NEDs), and micro LEDs, may also be used.

[0061] The display panel 10 may include a display area DA of the display screen and a non-display area NDA. In a plan view, the display panel 10 can be divided into the display area DA and the non-display area NDA. The non-display area NDA may be arranged to surround the display area DA. The non-display area NDA may form a border.

[0062] The display area DA can be a rectangle with perpendicular corners or a rectangle with rounded corners on a plane. However, the planar shape of the display area DA is not limited to a rectangle; it can be circular, elliptical, or other shapes.

[0063] The display area DA may include multiple pixels PX. The pixels PX may be arranged in a matrix shape. Each pixel PX may include a light-emitting layer and a circuit layer that controls the amount of light emitted by the light-emitting layer. The circuit layer may include wiring, electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed with an encapsulation film. The specific structure of the pixel PX will be described later.

[0064] In the display area DA, not only can pixels PX be arranged, but also multiple scan lines SL1 to SLk (k being an integer of 2 or higher), multiple data lines DL1 to DLj (j being an integer of 2 or higher), and multiple power lines (not shown) connected to the pixels PX can be arranged. Scan lines SL can extend along a first direction DR1 and are arranged along a second direction DR2. Data lines DL can extend along the second direction DR2 and are arranged along the first direction DR1.

[0065] The display panel 10 includes a plurality of pixels PX arranged in a matrix at the intersections of multiple scan lines SL1 to SLk (k being an integer of 2 or more) and multiple data lines DL1 to DLj (j being an integer of 2 or more). Each pixel PX can be connected to at least one of the scan lines SL and one of the data lines DL.

[0066] The timing control unit 21 receives digital video data DATA and timing signals from the host system. The timing control unit 21 generates a control signal CS for controlling the operating timing of the data drive unit 22 and the scan drive unit 30. The control signal CS may include a source control signal CONT2 for controlling the operating timing of the data drive unit 22 and a scan control signal CONT1 for controlling the operating timing of the scan drive unit 30.

[0067] The scan drive unit 30 generates scan signals S1 to Sk (k is an integer greater than or equal to 2) based on the scan control signal CONT1 and supplies them to the scan lines SL1 to SLk of the display panel 10.

[0068] The data driver unit 22 converts digital video data DATA into analog data voltage according to the source control signal CONT2 and supplies it to the data lines DL1 to DLj of the display panel 10.

[0069] The power supply circuit (not shown) can generate the voltage required to drive the display panel 10 from the main power applied by the system board and supply it to the display panel 10.

[0070] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to one embodiment.

[0071] Reference Figure 3 A pixel PX may include a first transistor TR1, a second transistor TR2, a light-emitting element OLED, and a capacitor Cst. Although Figure 3 The illustration shows a 2-transistor-1-capacitor (2T1C) structure where each pixel PX has two transistors TR1 and TR2 and one capacitor Cst, but it is not limited to this. Each pixel PX can include multiple transistors and multiple capacitors. For example, each pixel PX can also use other modified pixel PX structures such as 3T1C, 6T1C, and 7T1C.

[0072] Each of the first transistor TR1 and the second transistor TR2 may include a first source / drain electrode, a second source / drain electrode, and a gate electrode. One of the first source / drain electrode and the second source / drain electrode may be a source electrode, and the other may be a drain electrode.

[0073] Each of the first transistor TR1 and the second transistor TR2 can be formed using a thin-film transistor. Furthermore, although in Figure 3 The text describes the case where each of the first transistor TR1 and the second transistor TR2 is formed using an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), but it is not limited to this. The first transistor TR1 and the second transistor TR2 can also be formed using a P-type MOSFET. In this case, the positions of the source and drain electrodes of each of the first transistor TR1 and the second transistor TR2 can be changed. The following example illustrates the case where the first transistor TR1 and the second transistor TR2 are N-type MOSFETs.

[0074] The first transistor TR1 can be a driving transistor. Specifically, the gate electrode of the first transistor TR1 is connected to the second source / drain electrode of the second transistor TR2 and the second electrode (or, the first electrode) of the capacitor Cst. The first source / drain electrode of the first transistor TR1 is connected to the first power supply line ELVDL. The second source / drain electrode of the first transistor TR1 is connected to the anode electrode of the light-emitting element OLED. The first transistor TR1 receives a data signal Dj (j is an integer greater than or equal to 1) according to the switching operation of the second transistor TR2 and supplies driving current to the light-emitting element OLED.

[0075] The second transistor TR2 can be a switching transistor. Specifically, the gate electrode of the second transistor TR2 is connected to the scan line SL. The first source / drain electrode of the second transistor TR2 is connected to the data line DL. The second source / drain electrode of the second transistor TR2 is connected to the gate electrode of the first transistor TR1 and the second electrode of the capacitor Cst. The second transistor TR2 performs a switching operation to transmit the data signal Dj (j is an integer greater than or equal to 1) to the gate electrode of the first transistor TR1 when it is turned on according to the scan signal Sk (k is an integer greater than or equal to 1).

[0076] The first electrode (or second electrode) of capacitor Cst can be connected to the first power line ELVDL and the first source / drain electrode of the first transistor TR1, and the second electrode of capacitor Cst is connected to the gate electrode of the first transistor TR1 and the second source / drain electrode of the second transistor TR2. Capacitor Cst can serve to keep the data voltage applied to the gate electrode of the first transistor TR1 constant.

[0077] The OLED light-emitting element can emit light according to the driving current of the first transistor TR1. The OLED can be an organic light-emitting diode (OLED) comprising an anode electrode (or, a first electrode), an organic light-emitting layer, and a cathode electrode (or, a second electrode). However, it is not limited to this. The anode electrode of the OLED can be connected to the second source / drain electrode of the first transistor TR1, and the cathode electrode can be connected to a second power line ELVSL that is subjected to a second power supply voltage ELVSS lower than the first power supply voltage ELVDD.

[0078] The cross-sectional structure of the aforementioned pixel PX will be described in detail below.

[0079] Figure 4 This is a cross-sectional view of the display panel of a display device according to one embodiment. Figure 4 The illustration shows an example of a second transistor TR2 and a capacitor Cst for a pixel PX.

[0080] Reference Figure 4 According to one embodiment, the second transistor TR2 includes a conductive layer constituting an electrode, a semiconductor pattern forming a channel, and an insulating layer. The capacitor Cst includes a conductive layer constituting an electrode and an insulating layer disposed between the conductive layers. The plurality of conductive layers may include a first conductive layer 110, a second conductive layer 140, a third conductive layer 150, a fourth conductive layer 160, and an anode electrode ANO. The plurality of insulating layers may include a buffer layer (or, a lower insulating layer) 120, a gate insulating film GI, a first interlayer insulating film ILD1, a second interlayer insulating film ILD2, and a via layer VIA.

[0081] The various layers of the display panel 10 can be arranged on the base substrate 101 in the following order: barrier layer 102, first conductive layer 110, buffer layer 120, semiconductor layer 130, gate insulating film GI, second conductive layer 140, first interlayer insulating film ILD1, third conductive layer 150, second interlayer insulating film ILD2, fourth conductive layer 160, via layer VIA, anode electrode ANO, pixel definition film PDL, etc. While each of the above layers can be constructed using a single film, it can also be constructed using a stack of films comprising multiple films. Other layers can also be arranged between the various layers.

[0082] The base substrate 101 supports the various layers disposed thereon. The base substrate 101 can be made of an insulating material such as a polymer resin. The polymer material can be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The base substrate 101 may also include a metallic material.

[0083] The base substrate 101 can be a flexible substrate capable of bending, folding, rolling, etc. The material constituting the flexible substrate can be, for example, polyimide (PI), but is not limited to this.

[0084] When the organic light-emitting display device is a back-emitting or double-sided emitting type, a transparent substrate can be used. When the organic light-emitting display device is a front-emitting type, not only transparent substrates, but also translucent or opaque substrates can be used.

[0085] A barrier layer 102 may be disposed on a base substrate 101. The barrier layer 102 can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and perform surface planarization. The barrier layer 102 may include silicon nitride, silicon oxide, or silicon oxide nitride, etc. Depending on the type of base substrate 101 or the process conditions, the barrier layer 102 may also be omitted.

[0086] The first conductive layer 110 is disposed on the barrier layer 102. However, it is not limited thereto; if the barrier layer 102 is omitted, the first conductive layer 110 may also be disposed on the base substrate 101. The first conductive layer 110 may include a lower light-blocking pattern 111.

[0087] The lower light-blocking pattern 111 can be disposed on the lower part of the semiconductor pattern 131. The lower light-blocking pattern 111 can overlap at least with the channel region 131c of the semiconductor pattern 131 in the thickness direction (third direction DR3). At least a portion of the lower light-blocking pattern 111 can completely overlap with the channel region 131c of the semiconductor pattern 131, and in the thickness direction (third direction DR3) it does not overlap with or only partially overlaps with the first source / drain region 131a and the second source / drain region 131b of the semiconductor pattern 131 of the first transistor TR1, but is not limited thereto.

[0088] Although not shown, the lower light-blocking pattern 111 can be electrically connected to the gate electrode 141 through a contact hole (not shown) that passes through the first interlayer insulating film ILD1, the gate insulating film GI, and the buffer layer 120, or it can be electrically connected to the first source / drain electrode or the second source / drain electrode through a contact hole (not shown) that passes through the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, the gate insulating film GI, and the buffer layer 120.

[0089] The first conductive layer 110 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single-layer film or a multilayer film.

[0090] A buffer layer 120 is disposed on the first conductive layer 110. The buffer layer 120 can cover the first conductive layer 110 in the display area DA and the non-display area NDA, and is disposed on the entire surface of the barrier layer 102 exposed by the first conductive layer 110. The buffer layer 120 can function as an interlayer insulating film that insulates the first conductive layer 110 from the semiconductor layer 130. Furthermore, the buffer layer 120 can block moisture, external air, and impurities from penetrating from below, thereby protecting the upper thin-film transistors and light-emitting layer.

[0091] For a more detailed explanation of buffer layer 120, please refer to further... Figure 5 . Figure 5 It is magnification Figure 4 The diagram of region A. Figure 5 The diagram illustrates the stacked structure of the buffer layer 120.

[0092] Reference Figure 4 and Figure 5 The buffer layer 120 may include a first buffer membrane 121, a second buffer membrane 122 and a third buffer membrane 123.

[0093] The first buffer film 121 may cover the first conductive layer 110 and is disposed on the barrier layer 102. The second buffer film 122 may be disposed on the first buffer film 121, and the third buffer film 123 may be disposed on the second buffer film 122. That is, among the first buffer film 121, the second buffer film 122, and the third buffer film 123, the first buffer film 121 may be disposed at the bottom, the third buffer film 123 may be disposed at the top, and the second buffer film 122 may be disposed between the first buffer film 121 and the third buffer film 123.

[0094] The first buffer film 121 and the second buffer film 122 may contain the same material as each other, while the third buffer film 123 may contain a material different from the first buffer film 121 and the second buffer film 122. For example, the first buffer film 121 and the second buffer film 122 may contain silicon nitride (SiN). x The third buffer film 123 may include silicon oxide (SiO2). x However, it is not limited to this.

[0095] The thickness of the first buffer film 121 and the thickness of the second buffer film 122 can be the same as each other. The sum of the thickness of the first buffer film 121 and the thickness of the second buffer film 122 can be 80nm, and the thickness of the first buffer film 121 and the thickness of the second buffer film 122 are 40nm respectively, but are not limited to this.

[0096] In the buffer layer 120, silicon nitride (SiN) can be included. xAt least a portion of the membrane is provided with a second buffer membrane 122, which has a relatively low density. In other words, the first buffer membrane 121 and the second buffer membrane 122 may comprise the same material but have different densities. The density of the first buffer membrane 121 may be greater than the density of the second buffer membrane 122. The density of the first buffer membrane 121 may be at least 1.5 times or at least 4 times the density of the second buffer membrane 122. The density of the second buffer membrane 122 may be 2.3 g / cm³. 3 Below or 3.0g / cm 3 The following, but not limited to, describes the density of the first buffer membrane 121 and the second buffer membrane 122, which can be calculated by measuring the weight per unit volume.

[0097] The first buffer membrane 121 and the second buffer membrane 122 may contain the same materials but have different compositional ratios. In other words, the nitrogen (N) content of the first buffer membrane 121 may be higher than that of the second buffer membrane 122, and the silicon (Si) content of the first buffer membrane 121 may be lower than that of the second buffer membrane 122. The nitrogen (N) content of the first buffer membrane 121 may be in the range of 51.0 at% to 52.5 at%, or 51.8 at%, but is not limited thereto. The nitrogen (N) content of the second buffer membrane 122 may be in the range of 50.0 at% to 50.9 at%, or 50.6 at%. The silicon (Si) content of the first buffer membrane 121 may be in the range of 46.0 at% to 47.5 at%, or 46.7 at%. The silicon (Si) content of the second buffer membrane 122 may be in the range of 47.6 at% to 49.0 at%, or 48.4 at%. The composition ratio of the first buffer film 121 and the second buffer film 122 (or the content of nitrogen (N) and silicon (Si) etc.) can be analyzed by X-ray photoelectron spectroscopy (XPS), but the method for analyzing the above composition ratio is not limited to this.

[0098] In the first buffer film 121 and the second buffer film 122, the ratios of bonds between nitrogen (N) and hydrogen (H) and bonds between silicon (Si) and hydrogen (H) can be different. Specifically, the bond between nitrogen (N) and hydrogen (H) can be referred to as the first bond, and the bond between silicon (Si) and hydrogen (H) can be referred to as the second bond. The ratio of the first bond to the second bond in the relatively dense first buffer film 121 can be different from the ratio of the first bond to the second bond in the relatively less dense second buffer film 122.

[0099] The ratio of the first bond to the second bond in the first buffer film 121 can be greater than the ratio of the first bond to the second bond in the second buffer film 122. That is, in the case of silicon nitride (SiN) xIn the first buffer membrane 121 and the second buffer membrane 122, the greater the density of the first buffer membrane 121 and the second buffer membrane 122, the greater the number of first bonds and the fewer the number of second bonds can be within the first buffer membrane 121 and the second buffer membrane 122. In the second buffer membrane 122, the ratio of first bonds to second bonds can be in the range of 1.3 to 3.0 or in the range of 0.7 to 4.0.

[0100] In other words, the [NH] / [Si-H] value of the first buffer membrane 121 can be different from the [NH] / [Si-H] value of the second buffer membrane 122. Furthermore, the [NH] / [Si-H] value of the first buffer membrane 121 can be greater than the [NH] / [Si-H] value of the second buffer membrane 122. The [NH] / [Si-H] value of the first buffer membrane 121 can be more than five times, or more than ten times, the [NH] / [Si-H] value of the second buffer membrane 122, but is not limited to this. The [NH] / [Si-H] value of the first buffer membrane 121 can be 16.79, or in the range of 16 to 17 or 13 to 20. The [NH] / [Si-H] value of the second buffer membrane 122 can be 2.81, or in the range of 1.3 to 3.0 or 0.7 to 4.0.

[0101] [NH] represents the number of nitrogen (N) to hydrogen (H) bonds (first bonds) per unit volume in each of the first buffer membrane 121 or the second buffer membrane 122, and [Si-H] represents the number of silicon (Si) to hydrogen (H) bonds (second bonds) per unit volume in each of the first buffer membrane 121 or the second buffer membrane 122. The value of [NH] / [Si-H] is the ratio of the number of nitrogen (N) to hydrogen (H) bonds ([NH]) per unit volume in each of the first buffer membrane 121 or the second buffer membrane 122 to the number of silicon (Si) to hydrogen (H) bonds ([Si-H]). The above values ​​and / or the above ratios can be analyzed by a Fourier transform infrared spectrometer (FT-IR spectrometer), but are not limited thereto.

[0102] With the inclusion of silicon nitride (SiN) x The density of the buffer films 121 and 122 increases, allowing the silicon (Si) within the buffer films 121 and 122 to be surrounded by more nitrogen (N). The silicon (Si) can bond to nitrogen (N) but not to hydrogen (H), and the nitrogen (N) can bond to both silicon (Si) and hydrogen (H). Therefore, silicon nitride (SiN) is included. x The greater the density of the buffer films 121 and 122, the fewer the number of bonds (second bonds) between silicon (Si) and hydrogen (H) inside, and the more bonds (first bonds) between nitrogen (N) and hydrogen (H).

[0103] As will be explained later, the process of forming the buffer layer 120 may include a heat treatment process through which hydrogen (H2) from the buffer layer 120 can be released. In this case, the amount of hydrogen (H2) released from the second buffer film 122 can be greater than the amount of hydrogen (H2) released from the first buffer film 121. The hydrogen (H) atoms in the relatively less dense second buffer film 122 can move more freely than those in the relatively more dense first buffer film 121, and are more likely to bond with other surrounding hydrogen (H) atoms. That is, the lower the density of the buffer film, the easier it is for hydrogen (H) inside the buffer film to move to the interface of the buffer film and to bond with other surrounding hydrogen (H) atoms, thus making it easier for hydrogen (H) to be released as gas from the less dense buffer film. Therefore, the amount of hydrogen (H2) released from the relatively less dense second buffer film 122 can be greater than that from the relatively more dense first buffer film 121.

[0104] Due to the presence of silicon nitride (SiN) x A portion of the buffer films 121 and 122 are provided with a second buffer film 122 of lower density. Therefore, the amount of hydrogen (H2) released from the buffer layer 120 can be increased by a heat treatment process, and the amount of hydrogen (H2) remaining in the buffer layer 120 can be reduced after the heat treatment process. Accordingly, the amount of hydrogen (H2) flowing into the semiconductor pattern 131 disposed on the buffer layer 120 can be reduced.

[0105] As a result, by arranging the second buffer film 122 with a lower density, the inflow of hydrogen gas (H2) into the channel region 131c of the semiconductor pattern 131 can be suppressed or prevented. Accordingly, the threshold voltage (Vth) of the second transistor TR2 can be shifted in the positive direction overall, thereby ensuring the threshold voltage margin. Furthermore, the shift of the threshold voltage Vth of the second transistor TR2 in the negative direction can be suppressed, and short circuits in the channel region 131c can be suppressed or prevented. That is, poor switching characteristics of the second transistor TR2 can be suppressed or prevented.

[0106] To provide a detailed explanation of the above content, please refer to... Figure 6 .

[0107] Figure 6 This is a graph illustrating the threshold voltage of a transistor according to an embodiment, based on the presence or absence of a second buffer film. X represents the case including the first buffer film 121 but not the second buffer film 122, and Y represents the case including both the first buffer film 121 and the second buffer film 122.

[0108] Further reference Figure 6 In the case (X) where the first buffer film 121 with a relatively high density is included but the second buffer film 122 with a relatively low density is excluded, the threshold voltage Vth of the transistor is -0.54V, indicating a shift in the negative direction. Conversely, in the case (Y) where the first buffer film 121 with a relatively high density and the second buffer film 122 with a relatively low density are included, the threshold voltage Vth of the transistor is +0.09V, indicating a shift in the positive direction.

[0109] As a result, when the buffer layer 120 includes a first buffer film 121 and a second buffer film 122, the switching characteristics of the transistor can be improved, or the degradation of the switching characteristics can be suppressed or prevented.

[0110] Furthermore, with the development of silicon nitride (SiN) x The release of hydrogen (H2) from buffer membranes 121 and 122 increases, including from silicon oxide (SiO2). x The buffer film 123 can be formed to include more hydrogen (H). Therefore, the uniformity of the buffer film 123 can be improved, and the element distribution of the second transistor TR2 can be enhanced. Furthermore, with the addition of silicon nitride (SiN)... x The increased hydrogen (H2) release from the buffer films 121 and 122 can raise the process temperature for forming the gate insulating film GI and the interlayer insulating films ILD1 and ILD2, thereby improving the reliability of transistors including oxide semiconductors and enabling short channels for the transistors.

[0111] With the inclusion of silicon nitride (SiN) x The increased release of hydrogen (H2) from the buffer films 121 and 122 may eliminate the need for an additional oxide semiconductor layer (not shown) between the gate insulating film GI and the gate electrode 141. This oxide semiconductor layer (not shown) can release hydrogen (H) flowing into the channel region 131c. Consequently, the number of masks required for the process can be reduced, process efficiency improved, and process costs lowered.

[0112] Refer again Figure 4 The semiconductor layer 130 can be disposed on the buffer layer 120. The semiconductor layer 130 may include a semiconductor pattern 131. The semiconductor pattern 131 may be the active layer of the second transistor TR2.

[0113] The semiconductor pattern 131 may overlap with the lower light-blocking pattern 111 in at least a portion of its area. At least a portion of the side surfaces of the semiconductor pattern 131 may protrude outward relative to the side surfaces of the lower light-blocking pattern 111, but are not limited thereto.

[0114] The semiconductor pattern 131 may include: a channel region 131c, which overlaps with the gate electrode 141 in the thickness direction; a first source / drain region 131a and a second source / drain region 131b, located on one side and the other side of the channel region 131c, respectively. The first source / drain region 131a and the second source / drain region 131b are conductive regions, which can have higher conductivity and lower resistance compared to the channel region 131c.

[0115] Semiconductor layer 130 may include an oxide semiconductor. The oxide semiconductor may, for example, include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB) x C y ), quaternary compounds (AB) x C y D z In one embodiment, the semiconductor layer 130 may include indium tin zinc oxide (IGZO).

[0116] A gate insulating film GI can be disposed on the semiconductor layer 130. The gate insulating film GI can cover the semiconductor layer 130 and is disposed on the entire surface of the buffer layer 120 exposed by the semiconductor layer 130. The gate insulating film GI can cover not only the upper surface of the semiconductor layer 130, but also the sides of the semiconductor layer 130. The gate insulating film GI can function as a gate insulating film that insulates the semiconductor layer 130 from the second conductive layer 140.

[0117] Gate insulating film (GI) can include silicon compounds, metal oxides, etc. For example, gate insulating film (GI) can include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials can be used alone or in combination with each other.

[0118] A second conductive layer 140 is disposed on the gate insulating film GI. The second conductive layer 140 may include a gate electrode 141. The gate electrode 141 may be connected to the scan line SL (see reference SL). Figure 3 Electrical connection. Gate electrode 141 can function as the gate electrode of the second transistor TR2.

[0119] The second conductive layer 140 may further include a second electrode C2 of the capacitor Cst. The gate electrode 141 and the second electrode C2 of the capacitor Cst may be integrally formed. That is, the second electrode C2 of the capacitor Cst may be formed by the gate electrode 141 itself, or by a portion extending from the gate electrode 141. For example, a portion of the pattern of the integral second conductive layer 140 may overlap with the semiconductor pattern 131 and function as the gate electrode 141 at the corresponding location, while another portion may not overlap with the semiconductor pattern 131 and function as the second electrode C2 of the capacitor Cst that overlaps with the first electrode 151 of the upper capacitor.

[0120] The second conductive layer 140 may be made of a low-resistance material. The second conductive layer 140 may include, but is not limited to, one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0121] The first interlayer insulating film ILD1 is disposed on the second conductive layer 140. The first interlayer insulating film ILD1 can be disposed substantially covering the entire surface of the base substrate 101. The first interlayer insulating film ILD1 can not only cover the upper surface of the second conductive layer 140, but also cover the sides of the second conductive layer 140.

[0122] The first interlayer insulating film (ILD1) may include silicon compounds, metal oxides, etc. For example, the first interlayer insulating film (ILD1) may include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials may be used alone or in combination with each other.

[0123] A third conductive layer 150 is disposed on the first interlayer insulating film ILD1. The third conductive layer 150 may include a first electrode 151 of a capacitor Cst. The first electrodes 151 of the capacitor Cst may face each other in a region overlapping with the second electrode C2 of the lower capacitor Cst to form the capacitor Cst. The first interlayer insulating film ILD1 disposed between the first electrode 151 and the second electrode C2 of the capacitor Cst in the overlapping region may act as a dielectric of the capacitor Cst.

[0124] The third conductive layer 150 may include, but is not limited to, one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0125] A second interlayer insulating film (ILD2) is disposed on the third conductive layer 150. The second interlayer insulating film (ILD2) can be disposed substantially covering the entire surface of the base substrate 101. The second interlayer insulating film (ILD2) can cover not only the upper surface of the third conductive layer 150, but also the sides of the third conductive layer 150.

[0126] The second interlayer insulating film (ILD2) can include silicon compounds, metal oxides, etc. For example, the second interlayer insulating film (ILD2) can include silicon oxides, silicon nitrides, silicon nitrides, aluminum oxides, tantalum oxides, hafnium oxides, zirconium oxides, titanium oxides, etc. These materials can be used alone or in combination with each other.

[0127] A fourth conductive layer 160 is disposed on the second interlayer insulating film ILD2. The fourth conductive layer 160 may include a first source / drain electrode 161a and a second source / drain electrode 161b.

[0128] The first source / drain electrode 161a can be connected to the data line DL (see reference). Figure 3 It is composed of itself, or related to the data cable DL (refer to...). Figure 3 Electrical connection. That is, the first source / drain electrode 161a in a portion of the pattern of the fourth conductive layer 160 can be connected to the data line DL (refer to...). Figure 3 The pattern is integrally formed. The portion of the pattern overlapping with the semiconductor pattern 131 functions as the first source / drain electrode 161a of the second transistor TR2, and the portion not overlapping with the semiconductor pattern 131 functions as the data line DL (see reference). Figure 3 () function.

[0129] In the portion overlapping with the semiconductor pattern 131, the first source / drain electrode 161a can be electrically connected to the lower semiconductor pattern 131 through a contact hole CNT1 that exposes a portion of the semiconductor pattern 131 by penetrating the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the gate insulating film GI.

[0130] The second source / drain electrode 161b can be connected to the first transistor TR1 (see reference). Figure 3 The gate electrode of the transistor is electrically connected. However, it is not limited to this; the second source / drain electrode 161b can also be connected to the gate electrode of the first transistor TR1 (see reference 1). Figure 3The gate electrode is integrally formed.

[0131] In the portion overlapping with the semiconductor pattern 131, the second source / drain electrode 161b can be electrically connected to the lower semiconductor pattern 131 through a contact hole CNT2 that exposes a portion of the semiconductor pattern 131 by penetrating the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the gate insulating film GI.

[0132] The fourth conductive layer 160 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 160 may be a single-layer film or a multilayer film. For example, the fourth conductive layer 160 may be formed as a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0133] The passivation layer PVX can be disposed on the fourth conductive layer 160. The passivation layer PVX serves to cover and protect the fourth conductive layer 160. The passivation layer PVX can be disposed approximately over the entire surface of the base substrate 101. The passivation layer PVX can cover not only the upper surface of the fourth conductive layer 160, but also the sides of the fourth conductive layer 160.

[0134] The passivation layer PVX may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide. Although not illustrated, the passivation layer PVX may be formed in the display area DA, but not in at least a portion of the non-display area NDA.

[0135] The via layer (VIA) can be disposed on the passivation layer (PVX). The via layer (VIA) can be disposed on top of the passivation layer (PVX) and completely cover the upper surface of the passivation layer (PVX). When the via layer (VIA) is made of an organic film, its upper surface can be flat even if there is a step difference at the bottom.

[0136] The via-layer VIA can include inorganic insulating materials or organic insulating materials such as polyacrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). The via-layer VIA may also include photosensitive materials, but is not limited to these.

[0137] The anode electrode ANO is disposed on the via layer VIA. The anode electrode ANO can be disposed separately on each pixel. Although not shown, the anode electrode ANO can penetrate the via layer VIA and, through the first transistor TR1 (see reference...) Figure 3 A portion of the exposed contact hole (not shown) of the second source / drain region of the transistor is electrically connected to the first transistor TR1 (see reference). Figure 3 The second source / drain region (not shown). The anode electrode ANO can be arranged in the display area DA, but not in the non-display area NDA.

[0138] The anode electrode (ANO) can have a multilayer structure containing layers of materials with high work functions, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In₂O₃), and layers of reflective materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof, but is not limited to these. Layers with high work functions can be arranged on top of the reflective material layer and close to the light-emitting layer (EL). The anode electrode (ANO) can have multilayer structures such as ITO / Mg, ITO / MgF₂, ITO / Ag, and ITO / Ag / ITO, but is not limited to these.

[0139] A pixel-defining film (PDL) can be disposed on the anode electrode (ANO). The PDL may include openings that partially expose the anode electrode (ANO). The PDL can be constructed using organic or inorganic insulating materials. For example, the PDL may include at least one of polyimide-based resins, acrylic resins, silicone compounds, and polyacrylic resins.

[0140] A light-emitting layer EL, a cathode electrode CAT, and a thin-film encapsulation layer 170 can also be arranged on the exposed anode electrode ANO of the pixel definition film PDL.

[0141] The light-emitting layer (EL) may include an organic material layer. The organic material layer of the light-emitting layer may include an organic light-emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0142] The cathode electrode (CAT) can be disposed on the light-emitting layer (EL). The cathode electrode (CAT) can be a common electrode disposed on the entire surface without distinguishing between pixels (PX). The anode electrode (ANO), the light-emitting layer (EL), and the cathode electrode (CAT) can each constitute an organic light-emitting element (OLED).

[0143] The cathode electrode CAT may comprise a layer of material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, or compounds or mixtures thereof (e.g., mixtures of Ag and Mg). The cathode electrode CAT may also comprise a transparent metal oxide layer disposed on the material layer with the low work function.

[0144] A thin-film encapsulation layer 170 is disposed on the cathode electrode CAT. The thin-film encapsulation layer 170 may include a first inorganic film 171, a first organic film 172, and a second inorganic film 173. Although not shown, the first inorganic film 171 and the second inorganic film 173 may be in contact with each other at their ends. The first organic film 172 may be sealed by the first inorganic film 171 and the second inorganic film 173.

[0145] The first inorganic membrane 171 and the second inorganic membrane 173 may respectively include silicon nitride, silicon oxide, or silicon nitride. The first organic membrane 172 may include organic insulating material.

[0146] Hereinafter, a method for manufacturing a display device 1 according to an embodiment will be described.

[0147] Figures 7 to 14 This is a cross-sectional view of each process step in a method for manufacturing a display device according to an embodiment.

[0148] Reference Figure 7First, a barrier layer 102 is formed on the entire surface of the base substrate 101, and a patterned first conductive layer 110 is formed on the barrier layer 102.

[0149] The patterned first conductive layer 110 can be formed using a masking process. For example, it can be formed by patterning using a photolithography process after depositing a material layer for the first conductive layer on the entire surface of the barrier layer 102. Figure 7 The first conductive layer 110 shown includes a lower light-blocking pattern 111.

[0150] Next, refer to Figure 8 and Figure 9 A buffer layer 120 is formed on a barrier layer 102 on which a patterned first conductive layer 110 is arranged, and a dehydrogenation process is performed.

[0151] A buffer layer 120 is formed on the entire surface of the barrier layer 102 on which the first conductive layer 110 is disposed. That is, a first buffer film 121, a second buffer film 122 and a third buffer film 123 are sequentially stacked on the entire surface of the barrier layer 102 on which the first conductive layer 110 is disposed.

[0152] After the first buffer film 121 is stacked, the amounts of ammonia (NH3), nitrogen (N2) and silane (SiH4) are adjusted to regulate the ratio between the first bond of nitrogen (N) and hydrogen (H) and the second bond of silicon (Si) and hydrogen (H), thereby forming a second buffer film 122 with a density lower than that of the first buffer film 121.

[0153] After the buffer layer 120 is stacked, dehydrogenation of the buffer layer 120 can be performed. The dehydrogenation process may include heat treatment processes such as heat treatment at high temperatures. The heat treatment process may include annealing processes, but is not limited to them. Through this dehydrogenation, the hydrogen (H2) content in the buffer layer 120 can be reduced.

[0154] In other words, hydrogen (H) atoms bonded to silicon (Si) or nitrogen (N) within the second buffer film 122 and the third buffer film 123 are broken by a heat treatment process and bonded to surrounding hydrogen (H) atoms, thereby being released to the outside of the second buffer film 122 and the third buffer film 123 in the form of hydrogen gas (H2).

[0155] In this case, a larger amount of hydrogen (H2) gas can be released from the relatively less dense second buffer membrane 122. The amount of hydrogen released from the second buffer membrane 122 can be below 4000. This amount of hydrogen released can be measured by thermogravimetric analysis.

[0156] However, it is not limited to this. For example, within the third buffer membrane 123 and near the interface between the second buffer membrane 122 and the third buffer membrane 123, hydrogen (H) atoms can move toward the second buffer membrane 122 and can also meet and bond with other hydrogen (H) atoms in the relatively less dense second buffer membrane 122.

[0157] As a result, by arranging the relatively less dense second buffer film 122 on the third buffer film 123, the dehydrogenation process of the buffer layer 120 can proceed more smoothly, and the hydrogen (H2) content within the buffer layer 120 generated by the dehydrogenation process can be significantly reduced. Accordingly, the amount of hydrogen permeating into the upper semiconductor pattern 131 (see reference) can be reduced. Figure 4 The channel region 131c (refer to) Figure 4 The amount of hydrogen (H) atoms and / or hydrogen gas (H2) in ).

[0158] Next, refer to Figure 10 A patterned semiconductor layer 130 is formed on the buffer layer 120.

[0159] The patterned semiconductor layer 130 can be formed using a masking process. For example, after depositing a material layer for the semiconductor layer onto the entire surface of the buffer layer 120, it can be patterned using a photolithography process to form a pattern. Figure 10 The semiconductor layer 130 shown includes a first semiconductor pattern 131.

[0160] Next, refer to Figure 11 A gate insulating film GI is deposited on the entire surface of a buffer layer 120 on which a semiconductor layer 130 is disposed, and a second conductive layer 140 is formed on the gate insulating film GI.

[0161] A gate insulating film GI is deposited on the entire surface of a buffer layer 120 on which a semiconductor layer 130 is disposed, and a patterned second conductive layer 140 is formed on the gate insulating film GI. The patterned second conductive layer 140 can be formed by a mask process. For example, it can be formed by photolithography after the material for the second conductive layer is deposited on the entire surface of the gate insulating film GI. Figure 11 The second conductive layer 140 shown includes a gate electrode 141.

[0162] Next, refer to Figure 12 A first interlayer insulating film ILD1 is deposited on the entire surface of the gate insulating film GI on which the second conductive layer 140 is disposed, and a third conductive layer 150 is formed on the first interlayer insulating film ILD1.

[0163] A first interlayer insulating film ILD1 is deposited on the entire surface of the gate insulating film GI on which the second conductive layer 140 is disposed, and a patterned third conductive layer 150 is formed on the first interlayer insulating film ILD1. The patterned third conductive layer 150 can be formed by a mask process. For example, it can be formed by photolithography after depositing the material for the third conductive layer on the entire surface of the first interlayer insulating film ILD1. Figure 12 The third conductive layer 150 shown includes the first electrode 151 of the capacitor Cst.

[0164] Next, refer to Figure 13 A second interlayer insulating film ILD2 is deposited on the entire surface of the first interlayer insulating film ILD1 on which the third conductive layer 150 is disposed, and a fourth conductive layer 160 is formed on the second interlayer insulating film ILD2.

[0165] First, after depositing a second interlayer insulating film ILD2 on the entire surface of the first interlayer insulating film ILD1, on which the third conductive layer 150 is disposed, contact holes CNT1 and CNT2 are formed to expose the first semiconductor pattern 131. Contact holes CNT1 and CNT2 can be formed using a mask process. A photoresist pattern is formed on the second interlayer insulating film ILD2 to expose a portion of the first semiconductor pattern 131, and this pattern is used as an etching mask to etch the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the gate insulating film GI, thereby forming contact holes CNT1 and CNT2 that expose a portion of the first semiconductor pattern 131.

[0166] Subsequently, a patterned fourth conductive layer 160 is formed on the second interlayer insulating film ILD2. The patterned fourth conductive layer 160 can be formed by a mask process. For example, a material layer for the fourth conductive layer is deposited on the entire surface of the second interlayer insulating film ILD2. During the deposition process, the material layer for the fourth conductive layer can be deposited into the interior of the contact holes CNT1 and CNT2. The first source / drain electrode 161a and the second source / drain electrode 161b can be physically and / or electrically connected to the first semiconductor pattern 131, respectively.

[0167] Next, a photoresist layer is coated on the material layer used for the fourth conductive layer. After forming a photoresist pattern through exposure and development, it is used as an etching mask to pattern the material layer used for the fourth conductive layer, thereby completing the process as follows: Figure 13 The fourth conductive layer 160 shown includes a first source / drain electrode 161a and a second source / drain electrode 161b.

[0168] Next, refer to Figure 14A via layer VIA is formed on the fourth conductive layer 160, and an anode electrode ANO is formed on the via layer VIA. Subsequently, a patterned pixel definition film PDL is formed on the via layer VIA.

[0169] First, a via layer VIA is formed by coating a material layer for the via layer onto a second interlayer insulating film ILD2 covering and on which the fourth conductive layer 160 is disposed. Then, although not shown, a via contact hole (not shown) penetrating the via layer VIA can be formed by etching the via layer VIA. The via contact hole (not shown) can expose the first transistor TR1 (see reference). Figure 3 The second source / drain electrode (not shown).

[0170] After forming the via layer VIA, the anode electrode ANO is formed. The anode electrode ANO can be formed using a mask process. For example, a material layer for the anode electrode is deposited on the entire surface of the via layer VIA. During the deposition process, the material layer for the anode electrode can be deposited inside the via contact hole (not shown). Therefore, the anode electrode ANO can be connected to the first transistor TR1 (see reference). Figure 3 The second source / drain electrode (not shown).

[0171] A photoresist layer is coated onto the anode electrode material layer. After forming a photoresist pattern through exposure and development, this pattern is used as an etching mask to etch the anode electrode material layer. Subsequently, the photoresist pattern is removed by a stripping or etching process, thus completing the process. Figure 14 The patterned anode electrode ANO is shown.

[0172] After the anode electrode ANO is completed, a pixel definition film PDL is formed that covers the anode electrode ANO and is patterned on the via layer VIA.

[0173] Pixel-Defining Films (PDLs) can, for example, comprise organic materials containing photosensitive substances. In this case, patterned PDLs can be formed by exposure and development after coating an organic material layer for pixel definition. Accordingly, it is possible to form... Figure 14 The patterned pixel definition film (PDL) shown is illustrated.

[0174] The pixel definition film (PDL) can be formed along the boundary of the pixel (PX) and partially overlap with the anode electrode (ANO). The PDL can also be formed to overlap with a via contact hole (not shown). Even if the anode electrode (ANO) only partially fills the internal space of the via contact hole (not shown), the PDL can completely fill the internal space of the via contact hole (not shown).

[0175] The luminescent layer EL on top of the pixel definition film PDL (refer to) Figure 4 ), cathode electrode CAT (refer to) Figure 4 ) and thin film encapsulation layer 170 (refer to) Figure 4 The manufacturing method of the above structure is well known, therefore the description of the manufacturing method of the above structure is omitted in this specification.

[0176] The following describes another embodiment. In the following embodiments, repeated descriptions of the same configurations as those described above will be omitted or simplified, and the description will focus primarily on the differences.

[0177] Figure 15 This is an enlarged view of a portion of a cross-section of a display device according to another embodiment.

[0178] Reference Figure 15 ,and Figure 4 The difference in the embodiments is that the stacking order of the first buffer film 121_1 and the second buffer film 122_1 of the display device 1_1 according to this embodiment has been changed.

[0179] Specifically, the buffer layer 120_1 according to this embodiment may include a first buffer film 121_1, a second buffer film 122_1, and a third buffer film 123, with the first buffer film 121_1 disposed between the second buffer film 122_1 and the third buffer film 123. That is, the second buffer film 122_1 may be disposed below the first buffer film 121_1, and the third buffer film 123 may be disposed above the first buffer film 121_1.

[0180] The thickness TH2 of the second buffer membrane 122_1 can be greater than the thickness TH1 of the first buffer membrane 121_1. The thickness TH2 of the second buffer membrane 122_1 can be more than three times the thickness TH1 of the first buffer membrane 121_1, but is not limited to this.

[0181] In this case, hydrogen (H2) inflow into the channel region 131c of the semiconductor pattern 131 can also be suppressed or prevented by arranging a second buffer film 122_1 with a lower density. Therefore, short circuits in the channel region 131c can be suppressed or prevented, and poor switching characteristics of the second transistor TR2 can be suppressed or prevented.

[0182] To illustrate the above content, please refer to... Figure 16 .

[0183] Figure 16 This is a graph illustrating the threshold voltage of a transistor according to another embodiment, based on the presence or absence of a second buffer film. X indicates the case including the first buffer film 121_1 but not the second buffer film 122_1, and Z indicates the case including both the first buffer film 121_1 and the second buffer film 122_1 according to another embodiment.

[0184] Further reference Figure 16 It can be seen that, in the case of a first buffer film 121_1 with a relatively high density and a second buffer film 122_1 with a relatively low density, and the first buffer film 121_1 being arranged on top of the second buffer film 122_1 (Z), the threshold voltage Vth of the transistor is +0.34V, and it can be seen that it has also shifted in the positive direction.

[0185] Figure 17 This is an enlarged view of a portion of a cross-section of a display device according to yet another embodiment.

[0186] Reference Figure 17 According to the display device 1_2 of this embodiment and Figure 4 The difference between the embodiments is that the first buffer membrane 121 is not included (see reference). Figure 4 ).

[0187] Specifically, the buffer layer 120_2 according to this embodiment may include a second buffer film 122_2 and a third buffer film 123, but does not include the first buffer film 121 (see reference). Figure 4 The thickness of the second buffer film 122_2 can be 80 nm, or in the range of 70 nm to 90 nm, but is not limited to this.

[0188] In this case, hydrogen (H2) inflow into the channel region 131c of the semiconductor pattern 131 can also be suppressed or prevented by arranging a second buffer film 122_2 with a lower density. Therefore, short circuits in the channel region 131c can be suppressed or prevented, and poor switching characteristics of the second transistor TR2 can be suppressed or prevented.

[0189] To illustrate the above content, please refer to... Figure 18 .

[0190] Figure 18 This is a graph illustrating the threshold voltage of a transistor with or without a second buffer film according to yet another embodiment. X indicates the case including the first buffer film 121_1 but not including the second buffer film 122_2, and W indicates the case of the second buffer film 122_2 according to yet another embodiment.

[0191] Further reference Figure 18 It can be seen that, in the case of only including the relatively low-density second buffer film 122_2 without including the relatively high-density first buffer film 121_1 (W), the threshold voltage Vth of the transistor is +0.44V, which also indicates that it has shifted in the positive direction.

[0192] Figure 19 This is an enlarged view of a portion of a cross-section of a display device according to yet another embodiment.

[0193] Reference Figure 19 According to the display device 1_3 of this embodiment and Figure 4 The difference between the embodiments is that multiple second buffer membranes 122a_3, 122b_3 are included.

[0194] Specifically, the buffer layer 120_3 according to this embodiment may include a plurality of second buffer films 122a_3, 122b_3, a first buffer film 121, and a third buffer film 123. The first buffer film 121 may be arranged among the plurality of second buffer films 122a_3, 122b_3, but is not limited thereto. The plurality of second buffer films 122a_3, 122b_3 may be substantially identical to each other, and are consistent with the above-described... Figure 4 The second buffer membrane 122 (refer to) Figure 4 They are essentially the same.

[0195] In this case, hydrogen (H2) inflow into the channel region 131c of the semiconductor pattern 131 can also be suppressed or prevented by arranging a second buffer film 122a_3, 122b_3 with a lower density. Therefore, short circuits in the channel region 131c can be suppressed or prevented, and poor switching characteristics of the second transistor TR2 can be suppressed or prevented.

[0196] In this embodiment, two second buffer films 122a_3 and 122b_3 are illustrated, but the number is not limited to this. Furthermore, although the illustrated buffer layer 120_3 includes multiple second buffer films 122a_3 and 122b_3, it is not limited to this and may also include multiple second buffer films 122a_3 and 122b_3 and / or multiple first buffer films 121.

[0197] Figure 20 This is an enlarged view of a portion of a cross-section of a display device according to yet another embodiment.

[0198] Reference Figure 20 According to the display device 1_4 of this embodiment and Figure 4 The difference between the embodiments is that a fourth buffer membrane 124_4 with gradually varying membrane density is also included.

[0199] Specifically, the buffer layer 120_4 in this embodiment includes not only the first buffer film 121, the second buffer film 122, and the third buffer film 123, but may also include a fourth buffer film 124_4. The fourth buffer film 124_4 may include regions with different film densities. For example, the film density of the fourth buffer film 124_4 may gradually decrease from the bottom to the top, but it is not limited to this. That is, the film density of the fourth buffer film 124_4 may gradually decrease from the first buffer film 121 side towards the second buffer film 122 side. The film density of the fourth buffer film 124_4 may be substantially the same as the film density of the second buffer film 122 in the portion contacting the second buffer film 122, and substantially the same as the film density of the first buffer film 121 in the portion contacting the first buffer film 121.

[0200] In this case, hydrogen (H2) inflow into the channel region 131c of the semiconductor pattern 131 can also be suppressed or prevented by arranging a second buffer film 122 with a lower density. Therefore, short circuits in the channel region 131c can be suppressed or prevented, and poor switching characteristics of the second transistor TR2 can be suppressed or prevented.

[0201] In this embodiment, the case where the membrane density of the fourth buffer membrane 124_4 gradually decreases towards the top is described, but it is not limited to this and can also gradually increase towards the top.

[0202] Figure 21 This is an enlarged view of a portion of a cross-section of a display device according to yet another embodiment.

[0203] Reference Figure 21 According to the display device 1_5 of this embodiment and Figure 4 The difference between the embodiments is that the first buffer membrane 121 is not included (see reference). Figure 20 ).

[0204] Specifically, the buffer layer 120_5 in this embodiment may include a second buffer film 122, a third buffer film 123, and a fourth buffer film 124_5, but does not include the first buffer film 121. In this case, the fourth buffer film 124_5 may be disposed on the lower light-blocking pattern 111, and the second buffer film 122 and the third buffer film 123 may be disposed on the fourth buffer film 124_5.

[0205] In this case, hydrogen (H2) inflow into the channel region 131c of the semiconductor pattern 131 can also be suppressed or prevented by arranging a second buffer film 122 with a lower density. Therefore, short circuits in the channel region 131c can be suppressed or prevented, and poor switching characteristics of the second transistor TR2 can be suppressed or prevented.

[0206] Although the buffer layer 120_5 according to this embodiment is described as not including the first buffer film 121 (see reference) Figure 20 The situation may include, but is not limited to, the first buffer membrane 121 (see reference 121). Figure 20 At least one of the first and second buffer membranes 122.

[0207] Figure 22 This is a cross-sectional view of a display device according to yet another embodiment.

[0208] Reference Figure 22 According to this embodiment, the display device 1_6 and Figure 4 The difference between the embodiments is that the second buffer film 122_6 of the buffer layer 120_6 is only arranged in a portion of the area.

[0209] Specifically, the buffer layer 120_6 according to this embodiment may include a first buffer film 121, a second buffer film 122_6, and a third buffer film 123. The difference is that the first buffer film 121 and the third buffer film 123 are disposed throughout the entire area of ​​the barrier layer 102, while the second buffer film 122_6 is disposed only in a portion of the area. The second buffer film 122_6 may overlap at least with the channel region 131c of the semiconductor pattern 131.

[0210] For example, the second buffer film 122_6 can be formed as a pattern with substantially the same shape as the semiconductor pattern 131 on the plane, but is not limited thereto. The entire area of ​​the semiconductor pattern 131 and the lower light-blocking pattern 111 can overlap with the second buffer film 122_6.

[0211] In this case, hydrogen (H2) inflow into the channel region 131c of the semiconductor pattern 131 can also be suppressed or prevented by arranging a second buffer film 122_6 with a lower density. Therefore, short circuits in the channel region 131c can be suppressed or prevented, and poor switching characteristics of the second transistor TR2 can be suppressed or prevented. Furthermore, by arranging the second buffer film 122_6 only in a portion of the region, the material used to form the second buffer film 122_6 can be minimized, thereby reducing process costs.

[0212] While embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that other specific forms can be implemented without altering the technical concept or essential features of the invention. Therefore, the embodiments described above should be understood as exemplary in all respects, and not as limiting.

Claims

1. A display device, comprising: substrate; A buffer layer is disposed on the substrate and includes a first buffer film and a second buffer film stacked sequentially along the thickness direction. Semiconductor patterns are arranged on the buffer layer; A gate insulating film is disposed on the semiconductor pattern; as well as The gate electrode is disposed on the gate insulating film. The first buffer film and the second buffer film both comprise silicon nitride, and the density of the first buffer film is greater than the density of the second buffer film. The buffer layer also includes a third buffer film containing silicon oxide. The third buffer membrane is disposed on the upper part of the first buffer membrane and the second buffer membrane. The semiconductor pattern is arranged on the third buffer film.

2. The display device according to claim 1, wherein, The second buffer membrane is disposed below the first buffer membrane.

3. The display device according to claim 2, wherein, The thickness of the second buffer film is more than three times the thickness of the first buffer film.

4. The display device according to claim 1, wherein, The [NH] / [Si-H] ratio of the first buffer membrane is greater than that of the second buffer membrane. [NH] represents the number of nitrogen-hydrogen bonds per unit volume. [Si-H] represents the number of bonds between silicon and hydrogen per unit volume.

5. The display device according to claim 4, wherein, The [NH] / [Si-H] value of the second buffer membrane is in the range of 1.3 to 3.

0.

6. The display device according to claim 1, wherein, The semiconductor pattern includes oxide semiconductors.

7. The display device according to claim 6, wherein, The third buffer film is in contact with the semiconductor pattern.

8. The display device according to claim 1, wherein, The first buffer film, the second buffer film, and the third buffer film are stacked sequentially.

9. The display device according to claim 1, wherein, Also includes: A fourth buffer film is disposed between the first and second buffer films, and its density gradually changes along the thickness direction. The density of the fourth buffer membrane gradually decreases from the first buffer membrane side toward the second buffer membrane side.

10. A method for manufacturing a display device, comprising the following steps: A first buffer film is formed on the substrate; A second buffer film is formed on the first buffer film, the second buffer film comprising the same material as the first buffer film but having a lower density than the first buffer film; and The first and second buffer membranes are dehydrogenated by heat treatment.

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