Negative voltage protection for bus interface devices

Abstract

Negative voltage protection for a bus interface device is disclosed. A bus interface bus is described. On the bus, a first logic state is conveyed by a higher voltage level and a second logic state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logic state, and a protection device between the power transistor and the bus. The protection device, when turned on, couples the power transistor to the bus and, when turned off, limits negative voltage excursions at the power transistor. A control circuit of the interface is configured to turn on the protection device when the bus voltage is above the lower voltage level and to turn off the protection device when the bus voltage is at or below the lower voltage level.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 023,387, filed May 12, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to negative voltage protection for MOSFET-based bus interfaces such as Local Area Network (LIN) bus interfaces and Clock Extended Peripheral Interface (CXPI) bus interfaces. Specifically, it relates to an interface for the bus, a transceiver and a battery management semiconductor die including the interface, and a method for interfacing with the bus. Background Technology

[0004] LIN (Local Area Network) is a serial network protocol used for communication between components in a vehicle. The LIN bus is a single-wire, bidirectional bus used for in-vehicle networking. A transceiver or similar device provides the interface between the microcontroller and the physical LIN bus. The microcontroller's logic values ​​are driven onto the LIN bus via the 'TxD' input of the LIN interface, where transmitted data on the TxD input is converted into LIN bus signals. The LIN interface also has an 'RxD' output, which reads information from the LIN bus back to the microcontroller.

[0005] According to LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, two logic states are allowed on the LIN bus: dominant and recessive. In the dominant state, the voltage on the LIN bus is set to ground or near ground. In the recessive state, the voltage on the LIN bus is set to the supply voltage. The interface generates a dominant level on its LIN bus interface pins by setting the TxD input of the LIN interface to logic low. The RxD output of the LIN interface reads back the signal on the LIN bus and indicates the dominant LIN bus signal to the microcontroller using a logic low signal. In response to the microcontroller setting the TxD pin of the interface device to logic high, the interface sets its LIN bus interface pins to recessive levels. Simultaneously, a logic high level on the RxD output of the interface indicates the recessive level on the LIN bus.

[0006] Bipolar transistors (BJTs) are widely used in LIN interfaces to drive the LIN bus. Due to their higher cost, BJTs have been gradually replaced by less expensive MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices—typically high-voltage PMOS devices. High-voltage PMOS devices need protection from negative voltages on the LIN bus, which can range from -40V to +45V. High-voltage diodes have been used to protect high-voltage PMOS-based drivers from these negative voltages. However, high-voltage PMOS devices are susceptible to the conduction of parasitic PNP devices. The LIN specification requires a slope time for the voltage on the LIN bus, necessitating slew rate control. The conduction of parasitic PNP devices present in high-voltage PMOS-based LIN drivers hinders slew rate control and increases substrate noise in the LIN driver die.

[0007] Therefore, improved negative voltage protection is needed for MOSFET-based LIN bus interfaces. Summary of the Invention

[0008] According to an implementation of an interface for a bus, on which a first logic state is conveyed by a higher voltage level and a second logic state is conveyed by a lower voltage level, the interface includes: an output stage including: a power transistor configured to drive a lower voltage level onto the bus to convey the second logic state; and a protection device between the power transistor and the bus, the protection device being configured to: couple the power transistor to the bus when the protection device is turned on and limit a negative voltage offset at the power transistor when the protection device is turned off; and a control circuit configured to: turn on the protection device when the bus voltage is higher than the lower voltage level and turn off the protection device when the bus voltage is at or below the lower voltage level.

[0009] According to an embodiment of a battery management semiconductor die, the battery management semiconductor die includes: logic configured to measure one or more parameters associated with charging and / or discharging a battery; and an interface configured to transmit the measurement results for the battery via a bus, on which a first logic state is communicated by a higher voltage level and a second logic state is communicated by a lower voltage level, wherein the interface includes: an output stage including: a power transistor configured to drive a lower voltage level onto the bus to communicate the second logic state; and a protection device between the power transistor and the bus, the protection device being configured to: couple the power transistor to the bus when the protection device is turned on and limit a negative voltage offset at the power transistor when the protection device is turned off; and a control circuit configured to: turn on the protection device when the bus voltage is higher than the lower voltage level and turn off the protection device when the bus voltage is at or below the lower voltage level.

[0010] According to an implementation of a method for interfacing with a bus, on which a first logic state is communicated by a higher voltage level and a second logic state is communicated by a lower voltage level, the method includes: driving a lower voltage level onto the bus via an output stage having a power transistor and a protection device to communicate the second logic state, wherein the protection device is configured to: couple a power transistor to the bus when the protection device is turned on and limit a negative voltage offset at the power transistor when the protection device is turned off; and control the voltage at the gate terminal of the protection device such that the protection device is turned on when the bus voltage is higher than the lower voltage level and turned off when the bus voltage is at or below the lower voltage level.

[0011] Other features and advantages will be recognized by those skilled in the art upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0012] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals refer to corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail in the following description.

[0013] Figure 1 A block diagram illustrating an implementation of a Local Area Network (LIN) transceiver is shown.

[0014] Figure 2 A more detailed schematic diagram of the LIN transceiver interface is shown.

[0015] Figure 3 It shows the relationship with Figure 2 The various waveforms associated with the operation of the LIN interface are shown.

[0016] Figure 4 , Figure 6 , Figure 8 and Figure 10 Schematic diagrams of different implementations of the control circuitry included in the LIN interface are shown.

[0017] Figure 5 , Figure 7 , Figure 9 and Figure 11 They respectively showed the same as Figure 4 , Figure 6 , Figure 8 and Figure 10 The waveforms associated with the operation of the control circuit shown are illustrated.

[0018] Figure 12 A circuit diagram of an embodiment of a charge pump including a control circuit is shown.

[0019] Figure 13 It shows the relationship with Figure 12 The various waveforms associated with the operation of the charge pump are shown.

[0020] Figures 14 to 17 A schematic diagram of an additional implementation of the control circuit is shown.

[0021] Figure 18 A schematic diagram of an implementation of a protection device included in a LIN interface is shown.

[0022] Figure 19 A partial cross-section of a semiconductor substrate is shown, in which p-channel transistor devices protecting the device share a common body region.

[0023] Figure 20 A block diagram illustrating an implementation of a battery management semiconductor die (chip) including a LIN interface is shown. Detailed Implementation

[0024] The embodiments described herein provide negative voltage protection for MOSFET-based bus interfaces such as Local Area Network (LIN) bus interfaces and Clock Extended Peripheral Interface (CXPI) bus interfaces. The output (driver) stage of the MOSFET-based bus interface may include, for example, PMOS power transistor devices for driving the voltage level of the bus according to the logic state to be conveyed on the bus. For example, in the cases of LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, the voltage level driven onto the bus indicates a dominant or recessive state. The protection device couples the power transistors of the output stage to the bus when the protection device is on and limits the negative voltage offset at the power transistors when the protection device is off. The negative voltage protection scheme described herein includes control circuitry for controlling the on / off state of the protection device in a manner that limits the negative voltage offset at the power transistors while also preventing the conduction of parasitic devices within the protection device.

[0025] Exemplary embodiments of the improved negative voltage protection scheme are described below with reference to the accompanying drawings. The embodiments are described in the context of a LIN bus. However, the improved negative voltage protection scheme described herein can also be applied to other automotive communication protocols that enable multiplexing between electronic control units (ECUs) in applications such as automotive body control systems (including steering switches, AC, and dashboard systems). For example, the interfaces, buses, and transceiver elements described in the following embodiments may be compatible with the CXPI protocol rather than the LIN protocol.

[0026] Figure 1 An embodiment of a LIN transceiver 100 is illustrated. The LIN transceiver 100 includes an interface 102 for a LIN bus, on which a first logic state is communicated by a higher voltage level and a second logic state is communicated by a lower voltage level. In one embodiment, the interface 102 is compatible with LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, where the first logic state corresponds to a recessive state defined in LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, and the second logic state corresponds to a dominant state defined in LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A.

[0027] Regardless of the specific type of LIN bus, the LIN interface 102 includes an output stage 104 having a power transistor T1 for driving the LIN bus and a protection device 'PD' 106 between the power transistor T1 and the LIN bus. The power transistor T1 drives a higher voltage level onto the LIN bus to convey a first logic state and a lower voltage level onto the LIN bus to convey a second logic state.

[0028] The protection device 106 couples the power transistor T1 to the LIN bus when the protection device 106 is turned on and limits the negative voltage offset at the power transistor T1 when the protection device 106 is turned off. The LIN interface 102 also includes a control circuit 108, which is used to: turn on the protection device 106 when the LIN bus voltage is higher than a lower voltage level and turn off the protection device 106 when the LIN bus voltage is at or below a lower voltage level.

[0029] Figure 1 The LIN transceiver 100 shown also includes a LIN bus pin 'Bus', which is coupled to the output stage 104 of the LIN interface 102. The LIN bus pin 'Bus' is used to couple the LIN transceiver 100 to the LIN bus. The transmit data input pin 'TxD' of the LIN transceiver 100 is used to receive a transmit data stream 'TX_data' from a controller 110, such as a microcontroller. The transmit data input circuitry 112 of the LIN transceiver 100 converts the received transmit data stream into a LIN bus signal 'Lbus', which is provided to the driver circuitry 114 of the LIN interface 102. In the cases of LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, an integrated pull-down device R... TD Ensure that the received transmitted data stream is logic low in a dominant state. LIN transceiver 100 also has a ground pin 'GND' and a power input pin 'Vs' for providing the power supply voltage vsup (e.g., battery voltage). Internal termination and pull-up current source 110 can couple the power input pin Vs to the LIN bus pin Bus.

[0030] The receiving circuit 116 of the LIN transceiver reads back the LIN bus signal from the LIN bus and indicates the logic state of the LIN bus based on the voltage level of the LIN bus signal. The receiving circuit 116 uses a pull-up circuit R... X1 R X2 Coupled to the power input pin Vs. The receive data output pin 'RxD' of the LIN transceiver 100 transmits the logic state of the LIN bus as indicated by the receiving circuit 116 to the controller 110 via the driver device T2, which transmits the received data stream 'RX_data' to the controller 110.

[0031] The LIN transceiver 100 may also have an enable input pin 'EN' for receiving an enable signal. An integrated pull-down device R may be coupled to the enable input pin EN. ENCircuit 118 is used to set LIN transceiver 100 to normal operating mode when a signal received at enable input pin EN is valid (e.g., logic high). In normal operating mode, data from controller 112 is transmitted to the LIN bus via TxD pin, and receiver 116 detects the data flow on the LIN bus and forwards the detected data to RxD output pin.

[0032] The LIN transceiver 100 may also have a wake-up input pin 'WK' that relates to the state of the LIN bus. This wake-up input pin can be used to put the LIN transceiver 100 into a standby mode, in which communication on the LIN bus is not allowed. The LIN transceiver 100 may include: a comparator circuit 120 for monitoring the state of the wake-up input pin WK and the LIN bus to determine when to put the LIN transceiver 100 into a standby mode; and a pull-up device T3 for pulling the transmit data input pin TxD to the power input pin Vs to indicate a first logic state (e.g., a recessive state as defined in LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A).

[0033] The LIN transceiver 100 may also have an inhibit output pin 'INH' as a power-related output. The inhibit output pin INH can be used to control an external voltage regulator or an external bus terminating resistor when the LIN transceiver 100 is used in master mode. The inhibit output pin INH is coupled to the power input Vs via power device T4. The LIN transceiver 100 may also include circuitry 122 for putting the LIN transceiver 100 into slave mode. A resistor R can be connected, for example, via a switching device T5, between the LIN bus pin Bus and the power input pin Vs or the inhibit output pin INH. slave A reverse diode D1 is used to put the LIN transceiver 100 into master mode. However, other additional circuitry may also be included in the LIN transceiver 100.

[0034] Figure 2 The LIN interface 102 is shown in more detail. According to this embodiment, the power input pin Vs of the LIN transceiver 100 is connected to the LIN bus pin Bus via, for example, a pair of series-connected reverse diodes Da, Db and resistors Ra, Rb. The control circuit 108 of the LIN interface 102 shuts off the protection device 106 when the LIN bus voltage 'Vlin' is below the maximum permissible value for the lower voltage level and above 0V, and turns on the protection device 106 when it is above this voltage condition. In one embodiment, for example, as specified in LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, the maximum permissible value for the lower voltage level is as follows: Figure 3 The value shown is 1.2V.

[0035] exist Figure 2 In the diagram, protection device 106 is shown as a p-channel transistor device PM1, which has a drain terminal 'D' coupled to the LIN bus pin Bus and a source terminal 'S' coupled to the power transistor T1 driving the LIN bus. For the p-channel device, the source and drain regions are p-doped, and the body region is n-doped. The body region 'BG' is at a substrate potential 'Vsub', which can be at the same potential as the ground reference terminal 'Vssl'. When the p-channel transistor protection device PM1 is turned on by the control circuit 108, a driver current 'Idrv' flows from the drain D of PM1 to the source S, and a voltage Vdi appears at the drain terminal D of the power transistor T1.

[0036] When the LIN bus signal Lbus, provided by the data input circuit 114 of the LIN transceiver 100, transitions from logic high to logic low, the LIN bus voltage Vlin transitions from a first logic state to a second logic state at a controlled transition rate. Similarly, when the LIN bus signal Lbus transitions from logic low to logic high, the LIN bus voltage Vlin transitions from the second logic state to the first logic state at a controlled transition rate. Figure 2 The dashed slant line in the Vlin waveform at the upper right indicates the high-to-low slew rate and the low-to-high slew rate. The control circuit 108 of the LIN interface 102 ensures that the protection device 106 does not adversely affect the slew rate control by avoiding parasitic conduction within the p-channel transistor device PM1.

[0037] Therefore, and for Figure 2 In the embodiment of the p-channel transistor protection device PM1 shown, the control circuit 108 drives the gate terminal 'G' of the p-channel transistor device PM1 towards 0V, thereby causing the LIN bus to transition from a first logic state to a second logic state, wherein for Figure 2 In the embodiment shown, the voltage 'Vg1' at the gate terminal G of the p-channel transistor device PM1 determines the lower voltage level for the LIN bus. For LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, this means that the control circuit 108 shuts off the p-channel transistor protection device PM1 when the LIN bus voltage is 0V or close to 0V. For example, as Figure 3 As shown, the control circuit 108 can turn off the p-channel transistor protection device PM1 between 0V and the maximum voltage 'VMax' that allows the LIN bus to be in a dominant state. By controlling the protection device 106 in this way, parasitic conduction in the p-channel transistor protection device PM1 is avoided, and the negative voltage offset at the power transistor T1 is also limited.

[0038] Figure 4 The control circuit 108 of the LIN interface 102 is shown in more detail. According to this embodiment, the control circuit 108 includes a first p-channel transistor device PM2 and a second p-channel transistor device PM3 connected in series. The first p-channel transistor device PM2 and the second p-channel transistor device PM3 are coupled in parallel with a power transistor T1. The source terminal S and body region BG of the p-channel transistor device PM2 are coupled to a protection device 106. The drain terminal D and gate terminal G of the p-channel transistor device PM2 are coupled to the source terminal S of the p-channel transistor device PM3. The body region BG of the p-channel transistor device PM3 is coupled to the protection device 106. The gate terminal G of the p-channel transistor device PM3 is coupled to the drain terminal D of the p-channel transistor device PM3 and is also coupled to the gate terminal G of the protection device 106. The control circuit 108 also includes a resistor R1 connected in series between the drain terminal D of the p-channel transistor device PM3 and the ground reference terminal Vssl. Under LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, resistor R1 can be in the megaohm range.

[0039] according to Figure 4 In this implementation, the voltage level of the second logic state is determined by the threshold voltage 'Vthp1' of the p-channel transistor protection device PM1. Under LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, this means that, depending on the amount of variation in Vthp1, the maximum level VMax of 1.2V required by the LIN specification for the dominant state may not be met. This is in Figure 5 It is shown in the middle, Figure 5 The difference between the LIN bus voltage Vlin and the gate voltage Vg1 of the p-channel transistor protection device PM1 is shown. This difference corresponds to the gate-source voltage 'Vgs1' of the p-channel transistor protection device PM1, which is given by the following formula:

[0040] Vgs1=Vthp2+Vthp3>Vthp1 (1)

[0041] Where Vthp2 is the threshold voltage of p-channel transistor device PM2, and Vthp3 is the threshold voltage of p-channel transistor device PM3.

[0042] Figure 6 Another embodiment of the control circuit 108 of the LIN interface 102 is shown. Figure 6 The implementation methods shown are the same as Figure 4The implementation shown is similar. However, the difference is that the control circuit 108 also includes a first n-channel transistor device NM1 connected in series between the p-channel transistor device PM3 and the ground reference terminal Vssl. For the n-channel device, the source and drain are n-doped and the body is p-doped. Figure 6 In this configuration, the source terminal S and body region BG of the n-channel transistor NM1 are coupled to the ground reference terminal Vssl. The drain terminal D of the n-channel transistor NM1 is coupled to the drain terminal D of the p-channel transistor PM3, for example, through a resistor R1. The gate terminal G of the n-channel transistor NM1 is coupled to the drain terminal D of the n-channel transistor NM1. When the LIN bus voltage Vlin drops below the threshold voltage 'Vthn1' of the n-channel transistor NM1, the n-channel transistor NM1 is turned off. When the LIN bus voltage Vlin drops below the threshold voltage Vthp1 of the p-channel transistor protection device PM1 minus the forward voltage 'Vfn1' of the body diode BD1 of the n-channel transistor NM1, the control circuit 108 shuts down the protection device 106.

[0043] like Figure 7 As shown, when the LIN bus voltage Vlin drops below the threshold voltage Vthn1 of the n-channel transistor NM1, the n-channel transistor NM1 is turned off. When this condition occurs, both the p-channel transistors PM2 and PM3 are also turned off. Correspondingly, the gate voltage Vg1 of the p-channel transistor protection device PM1 can be reduced to -Vfn1 by the gate capacitance of PM1. In LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, this means that the voltage level used for the dominant state is maintained below the maximum value of 1.2V, with sufficient margin.

[0044] Figure 8 Another embodiment of the control circuit 108 of the LIN interface 102 is shown. Figure 8 The implementation methods shown are the same as Figure 6 The implementation shown is similar. However, unlike the previous one, the control circuit 108 also includes a charge pump 200 coupled in parallel with the n-channel transistor device NM1. The charge pump 200 is a current source that provides a current 'Icp' that maintains a negative voltage at the gate terminal G of the protection device 106 when the LIN bus is in the second logic state, such as... Figure 9 As shown. In the cases of LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2 and 2.2A, the charge pump 200 is activated in the dominant state to maintain a negative voltage -Vg1 at the gate terminal G of the p-channel transistor protection device PM1 according to the DC specification of the LIN specification.

[0045] Figure 10 Another embodiment of the control circuit 108 of the LIN interface 102 is shown. Figure 8 The implementation methods shown are the same as Figure 6 The implementation shown is similar. However, the difference is that the control circuit 108 further includes a second n-channel transistor device NM2 connected in series between the n-channel transistor device NM1 and the ground reference terminal Vssl. The source terminal S of the n-channel transistor device NM1 is coupled to the drain terminal D of the n-channel transistor device NM2. The drain terminal D and gate terminal G of the n-channel transistor device NM1 are coupled to the drain terminal D of the p-channel transistor device PM3. Both the source terminal S and the body region BG of the second n-channel transistor device NM2, as well as the body region BG of the n-channel transistor device NM1, are coupled to the ground reference terminal Vssl. When the LIN bus is in a first logic state, the n-channel transistor device NM2 is configured to be turned off. In one implementation, the gate terminal G of the n-channel transistor device NM2 is controlled by the logic state of the LIN bus such that when the LIN bus is in the first logic state, the n-channel transistor device NM2 is turned off.

[0046] For example, the LIN bus signal Lbus provided by the data input circuit 114 of the LIN transceiver 100 can be inverted 300. The inverted signal drives the gate terminal G of the n-channel transistor device NM2. Accordingly, when the LIN bus is in the first logic state, the n-channel transistor device NM2 is turned off. In the cases of LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A, this means that the n-channel transistor device NM2 is turned off in the recessive state. LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A require a maximum current consumption of 20μA when the output stage 104 and driver 114 are turned off. Turning off the n-channel transistor device NM2 when the LIN bus is in the recessive state reduces the current consumption I at the LIN bus pin Bus. BUS_PAS_rec And thus helps to satisfy LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2 and 2.2A.

[0047] The inverted Lbus signal also forms the charge pump enable signal en_cp for the charge pump 200, which is coupled in parallel with the series-connected n-channel transistor devices NM1 and NM2. (As previously combined...) Figure 8 As explained, when the LIN bus is in the second logic state, the charge pump 200 maintains a negative voltage at the gate terminal G of the protection device 106. Figure 9In the LIN bus, when the LIN bus signal Lbus is logic high, indicating a first logic state (e.g., a recessive state in LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A), the charge pump enable signal en_cp is logic low, thus disabling charge pump 200. When the LIN bus signal Lbus is logic low, indicating a second logic state (e.g., a dominant state in LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2, and 2.2A), the charge pump enable signal en_cp is logic high, thus enabling charge pump 200.

[0048] Figure 12 An embodiment of the charge pump 200 is shown. According to this embodiment, the charge pump 200 has a p-channel transistor device PMcp1 coupled to a power supply voltage Vddd and an n-channel transistor device NMcp1 coupled to the p-channel transistor device PMcp1 via a resistor Rcp1. Two additional n-channel transistor devices NMcp2 and NMcp3 are coupled to node 'vcp' via a capacitor Ccp1. A charge pump enable signal en_cp and a buffered signal at node vcp are input to a logic AND gate 400. The inverted output of the logic AND gate 400 is coupled to the drain of a fourth n-channel transistor device NMcp4 via a resistor Rcp2. The gate of the n-channel transistor device NMcp4 is coupled to the non-inverted output of the logic AND gate 400. The inverted output of the logic AND gate 400 is inverted again to form a trigger signal 'vtrig', which is coupled to the gates of the p-channel transistor device PMcp1 and the n-channel transistor device NMcp1. The inverted version of the trigger signal vtrig drives the gate of the n-channel transistor device NMcp2 and is inverted again to drive the gate of the n-channel transistor device NMcp3. The source of the n-channel transistor device NMcp3 forms a charging node 'cp', which is as follows: Figure 8 and Figure 10 The drain terminal of the n-channel transistor device NM1 is shown.

[0049] Figure 13 Various current (I) and voltage (V) waveforms at different nodes of the charge pump 200 are shown. Figure 13 As shown in the second waveform at the top, the trigger signal vtrig controls the charging / discharging state of the charge pump 200 based on the on / off states of transistor devices PMcp1, NMcp1, NMcp2, and NMcp3.

[0050] Figure 14 Another embodiment of the control circuit 108 of the LIN interface 102 is shown. Figure 14 The implementation methods shown are the same as Figure 4The implementation shown is similar. However, the difference is that the control circuit 108 includes a current source 500 connected in series between the drain terminal D of the p-channel transistor device PM3 and the ground reference terminal Vssl instead of a resistor R1.

[0051] Figure 15 Another embodiment of the control circuit 108 of the LIN interface 102 is shown. Figure 15 The implementation methods shown are the same as Figure 6 The implementation shown is similar. However, the difference is that the control circuit 108 includes an additional n-channel transistor device NM3 and a current source 600 coupled to the drain terminal D of the n-channel transistor device NM3. Both the source terminal S and the body region BG of the n-channel transistor device NM3 are coupled to the ground reference terminal Vssl. The gate terminals G of the n-channel transistor device NM3 are both coupled to the drain terminal D of the n-channel transistor device NM3 and to the gate terminal G of the n-channel transistor device NM1.

[0052] Figure 16 Another embodiment of the control circuit 108 of the LIN interface 102 is shown. Figure 16 The implementation methods shown are the same as Figure 15 The implementation shown is similar. However, the difference is that the control circuit 108 also includes a charge pump 200 coupled in parallel with the n-channel transistor device NM1. (As in conjunction with...) Figure 8 and Figure 10 As explained, when the LIN bus is in the second logic state, the charge pump 200 maintains the negative voltage at the gate terminal G of the protection device 106.

[0053] Figure 17 Another embodiment of the control circuit 108 of the LIN interface 102 is shown. Figure 17 The implementation methods shown are the same as Figure 16 The implementation shown is similar. However, the difference is that the control circuit 108 also includes an additional n-channel transistor device NM2 connected in series between the n-channel transistor device NM1 and the p-channel transistor device PM3. When the LIN bus is in the first logic state, the n-channel transistor device NM2 is turned off.

[0054] Figure 18Another embodiment of the protection device 106 for the LIN interface 102 is shown. According to this embodiment, the protection device 106 includes a p-channel transistor device PM1 monolithically integrated with another p-channel transistor device PM4, such that p-channel transistor devices PM1 and PM4 share a common body region. The source terminal S of p-channel transistor device PM1 is coupled to a power transistor T1. The drain terminal D of p-channel transistor device PM1 and the drain terminal of p-channel transistor device PM4 are coupled to the LIN bus pin Bus. The source terminal S of p-channel transistor device PM4 is coupled to the common body region. The gate terminal G of p-channel transistor device PM1 and the gate terminal of p-channel transistor device PM4 are coupled to a control circuit 108, and both the gate terminal G of p-channel transistor device PM1 and the gate terminal of p-channel transistor device PM4 have the same gate voltage Vg1.

[0055] Figure 19 A partial cross-section of a semiconductor substrate 700 is shown, in which p-channel transistor devices PM1 and PM4 of the protection device 106 share a common body region 702. The semiconductor substrate 700 is p-type doped, the common body region 702 is n-type doped, and the source and drain regions 704 of the p-channel transistor devices PM1 and PM4 are p-type doped. According to this embodiment, even if the body region BG / 702 of the p-channel transistor device PM4 floats, Figure 19 The parasitic PNP device shown will also not be activated. In this case, the voltage level for the second logic state (e.g., the dominant state in LIN specifications 1.2, 1.3, 2.0, 2.1, 2.2 and 2.2A) is increased by controlling the gate terminal G of p-channel transistor device PM1 and the gate terminal G of p-channel transistor device PM4.

[0056] Figure 20An embodiment of a battery management semiconductor die 800 (chip) including the LIN interface 102 described herein is illustrated. The battery management semiconductor die 800 also includes logic 802, such as analog and / or digital circuitry, for measuring one or more parameters associated with charging and / or discharging a battery 804 that supplies power to one or more electrical loads 806. For example, the measurement logic 802 may include one or more current sensors, voltage sensors, temperature sensors, etc. The LIN interface 102 transmits the measurement results of the battery 804 to an electronic control unit (ECU) 808 (e.g., a microcontroller) via a LIN bus 810, on which a first logic state is communicated by a higher voltage level and a second logic state by a lower voltage level. As previously explained herein, the LIN interface 102 includes an output stage 104 having a power transistor T1 for driving a lower voltage level onto the LIN bus 810 to communicate the second logic state. Figure 20 (not shown in the image) and protection device 106 between power transistor T1 and LIN bus 810. Figure 20 (Not shown in the image). Protection device 106 couples power transistor T1 to the LIN bus 810 when protection device 106 is turned on and limits the negative voltage offset at power transistor T2 when protection device 106 is turned off. LIN interface 102 also includes control circuitry 108. Figure 20 (Not shown in the image) The control circuit 108 turns on the protection device 106 when the LIN bus voltage is higher than the lower voltage level, and turns off the protection device 106 when the LIN bus voltage is at or below the lower voltage level.

[0057] As explained earlier in this document, the improved negative voltage protection scheme can be applied to automotive communication protocols other than LIN. For example, the interface, bus, and transceiver elements described in the previous embodiments can be compatible with the CXPI protocol but not with the LIN protocol.

[0058] Although this disclosure is not so limited, the following numbered examples illustrate one or more aspects of this disclosure.

[0059] Example 1. An interface for a bus, on which a first logic state is conveyed by a higher voltage level and a second logic state is conveyed by a lower voltage level, the interface comprising: an output stage including: a power transistor configured to drive the lower voltage level onto the bus to convey the second logic state; and a protection device between the power transistor and the bus, the protection device being configured to: couple the power transistor to the bus when the protection device is turned on and limit a negative voltage offset at the power transistor when the protection device is turned off; and control circuitry configured to: turn on the protection device when the bus voltage is higher than the lower voltage level and turn off the protection device when the bus voltage is at or below the lower voltage level.

[0060] Example 2. According to the interface described in Example 1, wherein the control circuit is configured to shut down the protection device when the bus voltage is lower than the maximum permissible value for the lower voltage level and higher than 0V.

[0061] Example 3. An interface according to Example 1 or 2, wherein the control circuit is configured to drive the gate terminal of the protection device toward 0V to cause the bus to transition from the first logic state to the second logic state, and wherein the voltage at the gate terminal of the protection device determines the lower voltage level for the bus.

[0062] Example 4. An interface according to any one of Examples 1 to 3, wherein the control circuit includes a first p-channel transistor device and a second p-channel transistor device connected in series, the first p-channel transistor device and the second p-channel transistor device being coupled in parallel with the power transistor.

[0063] Example 5. The interface according to Example 4, wherein: the source terminal and body region of the first p-channel transistor device are coupled to the protection device; the drain terminal and gate terminal of the first p-channel transistor device are coupled to the source terminal of the second p-channel transistor device; the body region of the second p-channel transistor device is coupled to the protection device; and the gate terminal of the second p-channel transistor device is coupled to the drain terminal of the second p-channel transistor device and coupled to the gate terminal of the protection device.

[0064] Example 6. The interface according to Example 4 or 5, wherein: the control circuit further includes a first n-channel transistor device series coupled between the second p-channel transistor device and ground; the first n-channel transistor device is configured to turn off when the bus voltage drops below a threshold voltage of the first n-channel transistor device; and the control circuit is configured to turn off the protection device when the bus voltage drops below a threshold voltage of the protection device minus the forward voltage of the body diode of the first n-channel transistor device.

[0065] Example 7. The interface according to Example 6, wherein: the source terminal and body region of the first n-channel transistor device are coupled to ground; the drain terminal of the first n-channel transistor device is coupled to the drain terminal of the second p-channel transistor device; and the gate terminal of the first n-channel transistor device is coupled to the drain terminal of the first n-channel transistor device.

[0066] Example 8. An interface according to Example 6 or 7, wherein: the control circuitry further includes a charge pump coupled in parallel with the first n-channel transistor device; and the charge pump is configured to maintain a negative voltage at the gate terminal of the protection device when the bus is in the second logic state.

[0067] Example 9. An interface according to any one of Examples 6 to 8, wherein: the control circuitry further includes a second n-channel transistor device connected in series between the first n-channel transistor device and ground; the second n-channel transistor device is configured to be turned off when the bus is in the first logic state.

[0068] Example 10. An interface according to Example 9, wherein: the source terminal of the first n-channel transistor device is coupled to the drain terminal of the second n-channel transistor device; the drain terminal and gate terminal of the first n-channel transistor device are coupled to the drain terminal of the second p-channel transistor device; both the source terminal and the body region of the second n-channel transistor device and the body region of the first n-channel transistor device are coupled to ground; and the gate terminal of the second n-channel transistor device is controlled by the logic state of the bus such that the second n-channel transistor device is turned off when the bus is in the first logic state.

[0069] Example 11. An interface according to Example 9 or 10, wherein: the control circuit further includes a charge pump coupled in parallel to the first n-channel transistor device and the second n-channel transistor device connected in series; and the charge pump is configured to maintain a negative voltage at the gate terminal of the protection device when the bus is in the second logic state.

[0070] Example 12. An interface according to any one of Examples 6 to 11, wherein the control circuitry further includes a resistor connected in series between the drain terminal of the second p-channel transistor device and the drain terminal of the first n-channel transistor device.

[0071] Example 13. An interface according to any one of Examples 6 to 12, wherein the control circuitry further includes a second n-channel transistor device and a current source coupled to the drain terminal of the second n-channel transistor device.

[0072] Example 14. The interface according to Example 13, wherein: both the source terminal and the body region of the second n-channel transistor device are coupled to ground; and the gate terminal of the second n-channel transistor device is coupled to both the drain terminal of the second n-channel transistor device and the gate terminal of the first n-channel transistor device.

[0073] Example 15. An interface according to Example 13 or 14, wherein: the control circuitry further includes a charge pump coupled in parallel with the first n-channel transistor device; and the charge pump is configured to maintain a negative voltage at the gate terminal of the protection device when the bus is in the second logic state.

[0074] Example 16. The interface according to Example 15, wherein: the control circuit further includes a third n-channel transistor device series coupled between the first n-channel transistor device and the second p-channel transistor device; and the third n-channel transistor device is configured to: turn off when the bus is in the first logic state.

[0075] Example 17. An interface according to any one of Examples 4 to 16, wherein the control circuitry further includes a current source connected in series between the drain terminal of the second p-channel transistor device and ground.

[0076] Example 18. An interface according to any one of Examples 1 to 17, wherein: the protection device includes a p-channel transistor device having a drain terminal coupled to the bus and a source terminal coupled to the power transistor; the control circuitry is configured to: drive the gate terminal of the p-channel transistor device toward 0V to cause the bus to transition from a first logic state to a second logic state; and wherein the voltage at the gate terminal of the p-channel transistor device determines the lower voltage level for the bus.

[0077] Example 19. An interface according to any one of Examples 1 to 18, wherein: the protection device includes a first p-channel transistor device monolithically integrated with a second p-channel transistor device, such that the first p-channel transistor device and the second p-channel transistor device share a common body region; the source terminal of the first p-channel transistor device is coupled to the power transistor; the drain terminal of the first p-channel transistor device and the drain terminal of the second p-channel transistor device are coupled to the bus; the source terminal of the second p-channel transistor device is coupled to the common body region; and the gate terminal of the first p-channel transistor device and the gate terminal of the second p-channel transistor device are coupled to the control circuit.

[0078] Example 20. An interface according to any one of Examples 1 to 19, wherein the bus is a Local Area Network (LIN) bus.

[0079] Example 21. An interface according to any one of Examples 1 to 19, wherein the bus is a Clock Extended Peripheral Interface (CXPI) bus.

[0080] Example 22. A transceiver comprising an interface according to any one of Examples 1 to 21, the transceiver further comprising: a first pin coupled to an output stage and configured to be coupled to a bus; a second pin configured to receive a transmission data stream from a controller; a transmission circuit configured to convert the received transmission data stream into a bus signal provided to the interface; a receiving circuit configured to read back the bus signal from the bus and indicate a logic state of the bus based on a voltage level of the bus signal; and a third pin configured to transmit the logic state of the bus indicated by the receiving circuit to the controller.

[0081] Example 23. A battery management semiconductor die, comprising: logic configured to measure one or more parameters associated with charging and / or discharging a battery; and an interface configured to transmit the measurement results for the battery via a bus, on which a first logic state is communicated by a higher voltage level and a second logic state is communicated by a lower voltage level, wherein the interface includes: an output stage including: a power transistor configured to drive the lower voltage level onto the bus to communicate the second logic state; and a protection device between the power transistor and the bus, the protection device being configured to: couple the power transistor to the bus when the protection device is turned on and limit a negative voltage offset at the power transistor when the protection device is turned off; and control circuitry configured to: turn on the protection device when the bus voltage is higher than the lower voltage level and turn off the protection device when the bus voltage is at or below the lower voltage level.

[0082] Example 24. A method of interfacing with a bus, on which a first logic state is communicated by a higher voltage level and a second logic state is communicated by a lower voltage level, the method comprising: driving the lower voltage level onto the bus via an output stage having a power transistor and a protection device to communicate the second logic state, wherein the protection device is configured to: couple the power transistor to the bus when the protection device is turned on and limit a negative voltage offset at the power transistor when the protection device is turned off; and control the voltage at the gate terminal of the protection device such that the protection device is turned on when the bus voltage is higher than the lower voltage level and the protection device is turned off when the bus voltage is at or below the lower voltage level.

[0083] Terms such as "first," "second," etc., are used to describe various elements, areas, parts, etc., and the terms are not intended to be restrictive. Throughout the specification, similar terms refer to similar elements.

[0084] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles “an,” “a,” and “the” are intended to include both plural and singular forms.

[0085] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0086] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations can be used instead of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. An interface for a bus, on which a first logic state is communicated by a higher voltage level and a second logic state is communicated by a lower voltage level, the interface comprising: An output stage, comprising: a power transistor configured to drive the lower voltage level onto the bus to convey the second logic state; and a protection device between the power transistor and the bus, the protection device being configured to: couple the power transistor to the bus when the protection device is turned on and limit negative voltage offset at the power transistor when the protection device is turned off; and A control circuit configured to: turn on the protection device when the bus voltage is higher than the lower voltage level and turn off the protection device when the bus voltage is at or below the lower voltage level.

2. The interface according to claim 1, wherein, The control circuit is configured to shut down the protection device when the bus voltage is below the maximum permissible value for the lower voltage level and above 0V.

3. The interface according to claim 1, wherein, The control circuit is configured to drive the gate terminal of the protection device toward 0V to cause the bus to transition from the first logic state to the second logic state, wherein the voltage at the gate terminal of the protection device determines the lower voltage level for the bus.

4. The interface according to claim 1, wherein, The control circuit includes a first p-channel transistor device and a second p-channel transistor device connected in series, and the first p-channel transistor device and the second p-channel transistor device are coupled in parallel with the power transistor.

5. The interface according to claim 4, wherein: The source terminal and body region of the first p-channel transistor device are coupled to the protection device; The drain terminal and gate terminal of the first p-channel transistor device are coupled to the source terminal of the second p-channel transistor device; The body region of the second p-channel transistor device is coupled to the protection device; as well as The gate terminal of the second p-channel transistor device is coupled to the drain terminal of the second p-channel transistor device and is coupled to the gate terminal of the protection device.

6. The interface according to claim 4, wherein: The control circuit also includes a first n-channel transistor device that is connected in series between the second p-channel transistor device and ground. The first n-channel transistor device is configured to turn off when the bus voltage drops below a threshold voltage of the first n-channel transistor device; and The control circuit is configured to shut down the protection device when the bus voltage drops below the threshold voltage of the protection device minus the forward voltage of the body diode of the first n-channel transistor device.

7. The interface according to claim 6, wherein: The source terminal and body region of the first n-channel transistor device are coupled to ground; The drain terminal of the first n-channel transistor device is coupled to the drain terminal of the second p-channel transistor device; as well as The gate terminal of the first n-channel transistor device is coupled to the drain terminal of the first n-channel transistor device.

8. The interface according to claim 6, wherein: The control circuit further includes a charge pump coupled in parallel with the first n-channel transistor device; and The charge pump is configured to maintain a negative voltage at the gate terminal of the protection device when the bus is in the second logic state.

9. The interface according to claim 6, wherein: The control circuit also includes a second n-channel transistor device that is connected in series between the first n-channel transistor device and ground. The second n-channel transistor device is configured to turn off when the bus is in the first logic state.

10. The interface according to claim 9, wherein: The source terminal of the first n-channel transistor device is coupled to the drain terminal of the second n-channel transistor device; The drain terminal and gate terminal of the first n-channel transistor device are coupled to the drain terminal of the second p-channel transistor device; Both the source terminal and the body region of the second n-channel transistor device, and the body region of the first n-channel transistor device, are coupled to ground; and The gate terminal of the second n-channel transistor device is controlled by the logic state of the bus, such that the second n-channel transistor device is turned off when the bus is in the first logic state.

11. The interface according to claim 9, wherein: The control circuit further includes a charge pump coupled in parallel to the first n-channel transistor device and the second n-channel transistor device connected in series; and The charge pump is configured to maintain a negative voltage at the gate terminal of the protection device when the bus is in the second logic state.

12. The interface according to claim 6, wherein, The control circuit also includes a resistor connected in series between the drain terminal of the second p-channel transistor device and the drain terminal of the first n-channel transistor device.

13. The interface according to claim 6, wherein, The control circuit also includes a second n-channel transistor device and a current source coupled to the drain terminal of the second n-channel transistor device.

14. The interface according to claim 13, wherein: Both the source terminal and the body region of the second n-channel transistor device are coupled to ground; and The gate terminal of the second n-channel transistor device is coupled to both the drain terminal of the second n-channel transistor device and the gate terminal of the first n-channel transistor device.

15. The interface according to claim 13, wherein: The control circuit further includes a charge pump coupled in parallel with the first n-channel transistor device; and The charge pump is configured to maintain a negative voltage at the gate terminal of the protection device when the bus is in the second logic state.

16. The interface according to claim 15, wherein: The control circuit further includes a third n-channel transistor device connected in series between the first n-channel transistor device and the second p-channel transistor device; and The third n-channel transistor device is configured to be turned off when the bus is in the first logic state.

17. The interface according to claim 4, wherein, The control circuit also includes a current source connected in series between the drain terminal of the second p-channel transistor device and ground.

18. The interface according to claim 1, wherein: The protection device includes a p-channel transistor device having a drain terminal coupled to the bus and a source terminal coupled to the power transistor; The control circuit is configured to drive the gate terminal of the p-channel transistor device toward 0V, so that the bus transitions from the first logic state to the second logic state. as well as The voltage at the gate terminal of the p-channel transistor device determines the lower voltage level used for the bus.

19. The interface according to claim 1, wherein: The protection device includes a first p-channel transistor device monolithically integrated with the second p-channel transistor device, such that the first p-channel transistor device and the second p-channel transistor device share a common body area. The source terminal of the first p-channel transistor device is coupled to the power transistor; The drain terminals of the first p-channel transistor device and the second p-channel transistor device are coupled to the bus; The source terminal of the second p-channel transistor device is coupled to the common body region; as well as The gate terminal of the first p-channel transistor device and the gate terminal of the second p-channel transistor device are coupled to the control circuit.

20. The interface according to claim 1, wherein, The bus is a Local Area Network (LIN) bus.

21. The interface according to claim 1, wherein, The bus in question is the Clock Extended Peripheral Interface (CXPI) bus.

22. A transceiver comprising the interface according to claim 1, the transceiver further comprising: The first pin is coupled to the output stage and configured to be coupled to the bus; The second pin is configured to receive a transmission data stream from the controller; A transmission circuit configured to convert a received transmission data stream into a bus signal provided to the interface; A receiving circuit configured to read back the bus signal from the bus and indicate the logic state of the bus based on the voltage level of the bus signal; as well as A third pin is configured to transmit the logic state of the bus, as indicated by the receiving circuitry, to the controller.

23. A battery management semiconductor die, comprising: Logic, which is configured to measure one or more parameters associated with charging and / or discharging the battery; as well as An interface configured to transmit measurement results for the battery via a bus, on which a first logic state is communicated by a higher voltage level and a second logic state by a lower voltage level. The interface includes: An output stage, comprising: a power transistor configured to drive the lower voltage level onto the bus to convey the second logic state; and a protection device between the power transistor and the bus, the protection device being configured to: couple the power transistor to the bus when the protection device is turned on and limit negative voltage offset at the power transistor when the protection device is turned off; and A control circuit configured to: turn on the protection device when the bus voltage is higher than the lower voltage level and turn off the protection device when the bus voltage is at or below the lower voltage level.

24. A method of interfacing with a bus, on which a first logic state is communicated by a higher voltage level and a second logic state is communicated by a lower voltage level, the method comprising: The lower voltage level is driven onto the bus via an output stage having a power transistor and a protection device to convey the second logic state, wherein the protection device is configured to: couple the power transistor to the bus when the protection device is turned on and limit the negative voltage offset at the power transistor when the protection device is turned off; and The voltage at the gate terminal of the protection device is controlled such that the protection device is turned on when the bus voltage is higher than the lower voltage level and turned off when the bus voltage is at or below the lower voltage level.

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