Locking circuit for contention kernel in hardware accelerator

Abstract

An example hardware accelerator in a computing system includes a bus interface coupled to a peripheral bus of the computing system, a lock circuit coupled to the bus interface, and a plurality of core circuits coupled to the lock circuit and the bus interface; wherein the plurality of core circuits provide lock requests to the lock circuit, the lock requests being for data stored in a system memory of the computing system; wherein the lock circuit is configured to process the lock requests from the plurality of core circuits and to issue atomic transactions over the bus interface on the peripheral bus based on the lock requests.

Description

Technical Field

[0001] The examples disclosed herein generally relate to hardware acceleration in computing systems, and more specifically to locking circuitry for competing kernels in hardware accelerators. Background Technology

[0002] Hardware acceleration involves using hardware to perform functions more efficiently than software running on a general-purpose CPU. Hardware accelerators are specialized hardware designed to accelerate specific applications. Example applications include neural networks, video encoding, decoding, transcoding, and network data processing. Software running on the computing system interacts with the hardware accelerator through various drivers and libraries. One type of hardware accelerator includes a programmable device and associated circuitry. For example, a programmable device can be a Field-Programmable Gate Array (FPGA) or a System-on-Chip (SoC), which includes FPGA programmable logic and other subsystems such as a processing system, a Data Processing Engine (DPE) array, a Network on-Chip (NOC), etc.

[0003] In multiprocessing systems, thread synchronization can be achieved using mutexes to avoid race conditions. The use of mutexes is common in software environments, where mutual exclusion of shared data is implemented via atomic operations. Protocols such as the Peripheral Component Interface Express (PCIe) and Cache Coherent Interconnect for Accelerators (CCIX) also provide support for atomic operations, allowing hardware acceleration kernels to acquire locks and compete with software threads. For systems with multiple acceleration kernels operating in parallel, lock requests from acceleration kernels to the host computer system can lead to unnecessary peripheral bus utilization and increased contention on the host computer. A more efficient technique is needed to handle access to shared data by multiple acceleration kernels in a hardware-accelerated system. Summary of the Invention

[0004] A technique for providing locking circuitry for competing cores in a hardware accelerator is described. In one example, a hardware accelerator in a computing system includes: a bus interface coupled to a peripheral bus of the computing system; locking circuitry coupled to the bus interface; and multiple core circuits coupled to the locking circuitry and the bus interface; wherein the multiple core circuits provide lock requests to the locking circuitry, the lock requests being for data stored in the system memory of the computing system; and wherein the locking circuitry is configured to process lock requests from the multiple core circuits and issue atomic transactions on the peripheral bus via the bus interface based on the lock requests.

[0005] In another example, a computing system includes: system memory; a processor coupled to the system memory; a peripheral bus coupled to the system memory; and a hardware accelerator coupled to the peripheral bus. The hardware accelerator includes a bus interface coupled to the peripheral bus; a locking circuit coupled to the bus interface; and multiple core circuits coupled to the locking circuit and the bus interface; wherein the multiple core circuits provide lock requests to the locking circuit, the lock requests being for data stored in the system memory of the computing system; wherein the locking circuit is configured to process the lock requests from the multiple core circuits and issue atomic transactions on the peripheral bus via the bus interface based on the lock requests.

[0006] In another example, a method for managing locking of data stored in memory among multiple cores executing in a hardware accelerator of a computing system includes: receiving a lock request from one of the multiple cores at a locking circuit in the hardware accelerator; determining whether the lock is held by another core; indicating a pending request to the core in response to the lock being held by another core; and issuing an atomic request for the lock from the locking circuit via the bus interface of the computing system to acquire the lock in response to the lock not being held by another core.

[0007] These and other aspects can be understood by referring to the following detailed description. Attached Figure Description

[0008] To gain a more detailed understanding of the features described above, a more specific description can be obtained by referring to the example implementations (briefly outlined above), some of which are shown in the accompanying drawings. However, it should be noted that the drawings only show typical example implementations and should not be considered as limiting their scope.

[0009] Figure 1A It is a block diagram depicting a hardware acceleration system based on the example.

[0010] Figure 1B It is a block diagram depicting the accelerated application based on the example.

[0011] Figure 1C It is a block diagram depicting the acceleration circuit according to the example.

[0012] Figure 2 It is a description Figure 1A A block diagram of the logical view of the computing system.

[0013] Figure 3 This is a block diagram depicting an example kernel-locked array.

[0014] Figure 4 This is a block diagram depicting another example of a kernel-locked array.

[0015] Figure 5This is a flowchart depicting the method for managing lock requests based on the example.

[0016] Figure 6 This is a flowchart depicting the method for managing lock release based on the example.

[0017] Figure 7A It is a block diagram depicting a multi-integrated circuit (IC) programmable device according to the example.

[0018] Figure 7B It is a block diagram depicting a programmable IC based on the example.

[0019] Figure 7C It is a block diagram depicting a system-on-chip (SoC) implementation of a programmable IC based on the example.

[0020] Figure 7D A field-programmable gate array (FPGA) implementation based on an example programmable IC is shown.

[0021] For ease of understanding, the same reference numerals are used where possible to denote common elements shared by the figures. It can be expected that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0022] The various features are described below with reference to the accompanying drawings. It should be noted that these drawings may be drawn to scale or not, and throughout the drawings, elements with similar structures or functions are indicated by the same reference numerals. It should be noted that these drawings are merely to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or a limitation on the scope of the claimed invention. Furthermore, the examples shown do not need to possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or explicitly described.

[0023] Techniques for providing locking circuitry for competing kernels in a hardware accelerator are described. These techniques provide an efficient method for handling atomic operations initiated by multiple hardware accelerator kernels. Locking circuitry provides central contention handling circuitry within an integrated circuit (IC) containing the hardware accelerator kernels. The locking circuitry is responsible for initiating atomic requests to the host computer system, which includes hardware accelerators with shared data structures, via the bus interface. This prevents kernel circuitry from directly issuing atomic requests via the bus interface. Therefore, these techniques reduce the frequency of atomic transactions on the bus interface, thereby reducing contention on the host. When locks can be granted to multiple kernels (based on use cases), these techniques also improve performance by allowing different accelerator kernels to execute in parallel. These and other aspects are described below with reference to the accompanying drawings.

[0024] Figure 1A This is a block diagram depicting a hardware acceleration system 100 according to an example. The hardware acceleration system 100 includes a host computing system 102. The host computing system 102 includes a hardware platform (“hardware 104”) and a software platform (“software 106”) executing on the hardware 104. The hardware 104 includes a processing system 110, system memory 116, storage devices (“storage unit 118”), and a hardware accelerator 122. The software 106 includes an operating system (OS) 144, an acceleration stack 146, a host application 150, and competing threads 139.

[0025] The processing system 110 includes a microprocessor 112, support circuitry 114, and a peripheral bus 115. The microprocessor 112 can be any type of general-purpose central processing unit (CPU), such as an x86-based processor, or a processor based on... The microprocessor 112 may include one or more cores and associated circuitry (e.g., cache memory, memory management unit (MMU), interrupt controller, etc.). The microprocessor 112 is configured to execute program code that performs one or more operations described herein and may be stored in system memory 116 and / or storage unit 118. Support circuitry 114 includes various devices that cooperate with the microprocessor 112 to manage data flow between the microprocessor 112, system memory 116, storage unit 118, hardware accelerator 122, or any other peripheral devices. For example, support circuitry 114 may include chipsets (e.g., northbridge, southbridge, platform host controller, etc.), voltage regulators, firmware (e.g., basic input / output system (BIOS)), etc. Support circuitry 114 manages data flow between the microprocessor 112 and peripheral bus 115, where various peripheral devices such as hardware accelerator 122 are connected. In some examples, the microprocessor 112 may be a system-in-package (SiP), system-on-a-chip (SOC), or similar device that incorporates all or most of the functions of a chipset (e.g., the northbridge, southbridge, etc.). The peripheral bus 115 may implement extended bus standards, such as PCIe (Peripheral Component Interconnect).

[0026] System memory 116 is a device that allows the storage and retrieval of information such as executable instructions and data. System memory 116 may include, for example, one or more random access memory (RAM) modules, such as double data rate (DDR) dynamic RAM (DRAM). Storage device 118 includes local storage devices (e.g., one or more hard disks, flash memory modules, solid-state drives, and optical disks) and / or storage interfaces that enable computing system 102 to communicate with one or more network data storage systems. Hardware 104 may include various other conventional devices and peripherals of the computing system, such as graphics cards, universal serial bus (USB) interfaces, etc.

[0027] In one example, hardware accelerator 122 includes programmable device 128 and RAM 126. Hardware accelerator 122 may optionally include non-volatile memory (NVM) 124. Programmable device 128 may be a field-programmable gate array (FPGA) or a system-on-a-chip (SoC) with FPGA programmable logic and other embedded subsystems. NVM 124 may include any type of non-volatile memory, such as flash memory. RAM 126 may include DDR DRAM, etc. RAM 126 may be organized into discrete RAM groups 127, as further described below. Programmable device 128 is coupled to NVM 124 and RAM 126. Programmable device 128 is also coupled to peripheral bus 115 of processing system 110.

[0028] OS 144 can be any commercial operating system known in the art, such as Microsoft Mac Etc. The acceleration stack 146 includes drivers and libraries that provide an application programming interface (API) to the hardware accelerator 122 for its command and control.

[0029] Figure 1B This is a block diagram depicting an acceleration application 180 according to an example. Acceleration application 180 includes a host application 150 and acceleration circuitry 130. Acceleration circuitry 130 is programmed in programmable logic (PL) 3 of programmable device 128 on hardware accelerator 122. Host application 150 includes software executing on microprocessor 112 that uses API calls to acceleration stack 146 to invoke acceleration circuitry 130 to perform some work. Host application 150 may include applications of neural network, video processing, network processing, or similar types that offload some functionality to hardware accelerator 122.

[0030] Figure 1CThis is a block diagram depicting an acceleration circuit 130 according to an example. Acceleration circuit 130 includes a bus interface 141, a core 138, and a locking circuit 140. Specifically, host application 150 calls the API of acceleration stack 146 to program the core circuit ((multiple) "cores 138") in PL3 of programmable device 128. The (multiple) cores 138 include computing units for processing data. Once the (multiple) cores 138 are programmed, host application 150 can access the (multiple) cores 138 via bus interface 141. Cores 138 can process data stored in system memory 116 and / or RAM 126. Specifically, core 138 accesses system memory 116 via bus interface 141 and RAM 126 via the memory interface of programmable device 128. Core 138 can compete with competing thread 139 for access to data in system memory 116. Because system memory 116 is shared between competing thread 139 and core 138, acceleration circuit 130 includes locking circuit 140. Kernel 138 is coupled to locking circuit 140 and uses locking circuit 140 to issue atomic transactions via bus interface 141 to acquire locks on data in system memory 116. Locking circuit 140 provides a single source of atomic transactions via bus interface 141, rather than having all individual kernels 138 issue atomic transactions via bus interface 141. The operation of locking circuit 140 is discussed further below.

[0031] In this example, processing system 110 is shown separate from hardware accelerator 122. In other examples discussed further below, processing system 110 and hardware accelerator 122 may be implemented within the same programmable device (e.g., a programmable device with an embedded processing system). In this case, processing system 110 may utilize an alternative interconnect with PL 3 to communicate with acceleration circuitry 130, examples of which are described below. Furthermore, in the examples discussed herein, acceleration circuitry 130 is implemented in programmable device 128. In other examples, programmable device 128 may be replaced with any integrated circuit (IC), including application-specific integrated circuit (ASIC), in which acceleration circuitry 130 includes a hardened circuitry system formed therein. Therefore, the locking circuitry 140 and mutual exclusion scheme discussed herein are applicable to acceleration circuitry in both programmable devices and ASICs.

[0032] Figure 2 This is a block diagram depicting a logical view of the computing system 102 according to the example. For example... Figure 2As shown, kernel 138 accesses data 202 in system memory 116 via bus interface 141 and peripheral bus 115. Contention thread 139 executes on microprocessor 112 and also accesses data 202 in system memory 116. Contention thread 139 uses lock array 204 to control access to data 202. Lock array 204 is indexed by identifiers of certain portions of data 202. Before accessing a portion of data 202, contention thread 139 uses the identifier of the data portion to check lock array 204 to see if the lock has been set by another thread. If not, contention thread 139 sets the lock and accesses the data mutually exclusive with other contention threads 139. Contention thread 139 uses atomic instructions of microprocessor 112 to set and check locks in lock array 204.

[0033] Locking circuit 140 maintains kernel lock array 206. Locking circuit 140 is the central contention handling block for all kernels 138. Assume there are N kernels 138, where N is an integer greater than 1. Locking circuit 140 maintains kernel lock array 206 indexed by identifiers of data 202. In one example, the identifier is all or part of a hash value generated from the key of data 202. Each element in kernel lock array 206 is (2*N) bits wide, where the lower N bits indicate the lock status and the higher N bits indicate pending requests. All kernels 138 direct their lock requests to locking circuit 140, rather than directly on peripheral bus 115 via bus interface 141. Locking circuit 140 is the only circuit that requests locks via bus interface 141.

[0034] Figure 3 This is a block diagram depicting an example of a kernel locking array 206. In this example, the kernel locking array 206 includes an array index 302. The array index 302 can be any set of identifiers for data 202, such as all or part of a hash value derived from a key of the data (e.g., a memory address or some other key associated with data 202). Each entry in the kernel locking array 206 includes a pending request 304 and a lock state 306. The pending request 304 includes N bits, one bit per kernel (138 bits). The lock state 306 includes N bits, one bit per kernel (138 bits).

[0035] Figure 5 This is a flowchart depicting method 500 for managing lock requests, based on an example. (Reference) Figure 2 and 5The locking circuit 140 operates as follows. Upon receiving a lock request including a kernel ID and an index value from kernel 138 (step 502), the locking circuit 140 checks the kernel lock array 206 indexed by the index value to determine whether the lock is held by another kernel 138 (step 504). If the lock is not held (step 506), the locking circuit 140 issues an atomic request to the peripheral bus 115 via bus interface 141 to check the lock array 204 (step 508). If the requested data portion is not locked (510), the peripheral bus 115 returns the lock to the locking circuit 140. The locking circuit 140 then marks the lock status in the kernel lock array 206 as "1" at the bit position corresponding to the kernel ID (512). If the requested data portion cannot be locked (510), the locking circuit 140 may issue another atomic request after a certain waiting period. If the lock status is non-zero (step 506), indicating that another kernel 138 holds the lock, then the locking circuit 140 instead sets the kernel ID bit in the pending request field (step 514). Kernel 138 must then wait to access the requested data portion.

[0036] Figure 6 This is a flowchart depicting method 600 for managing lock release according to an example. (Reference) Figure 2 and 6 Upon receiving a lock release request including the kernel ID and index from kernel 138 (step 602), locking circuit 140 checks the pending request field of the lock index (604). If the pending request field is zero (step 606), locking circuit 140 releases the lock by sending an atomic transaction on the peripheral bus via bus interface 141 (step 608). If the pending request field is non-zero (step 606), locking circuit 140 instead grants the lock to another kernel 138 that previously requested the lock but did not receive the lock but now has a pending request set (step 610).

[0037] Locking circuit 140 prevents unnecessary atomic transactions on peripheral bus 115 and accelerates local processing of related contention. Core 138 waiting for lock grant does not need to send duplicate atomic transactions through peripheral bus 115.

[0038] If kernel 138 needs a lock to access data only (not modify it), locking circuitry 140 can grant locks to multiple kernels 138 simultaneously. The pending request field can be converted into a counter to track how many kernels are currently being locked. Figure 4This is a block diagram depicting an example of a kernel lock array 206 with a counter field 308 instead of a pending request field 304. The counter field 308 includes a value for each entry indicating the number of kernels for which a lock has been granted. Locking circuitry 140 decrements the counter field 308 based on lock release requests from kernel 138. When the counter field 308 reaches zero, locking circuitry 140 sends an atomic request via peripheral bus 115 to release the lock on the data. This scheme is useful in applications such as memory caching (memcached), where locking is primarily used to prevent host applications from modifying data as in SET operations when GET operations are offloaded to multiple kernels 138. This facilitates parallel processing that is not possible with software alone.

[0039] Based on application requirements, if a write operation (e.g., an increment of a field in a data structure) is needed when kernel 138 acquires the lock, this increment can be performed via an atomic store add operation, and multiple user kernels 138 can still operate in parallel to provide better overall performance. If use case analysis suggests that holding the lock for a period of time would cause starvation of competing threads 139, a threshold counter can be implemented in the locking circuit 140 so that once the first kernel 138 acquires the lock, the lock will not be held for more than a set number of kernels 138.

[0040] Figure 7A This is a block diagram depicting a programmable device 54 according to an example. Programmable device 54 can be used to implement programmable device 128 in hardware accelerator 122. Programmable device 54 includes multiple programmable integrated circuits (ICs) 1, such as programmable ICs 1A, 1B, 1C, and 1D. In one example, each programmable IC 1 is an IC die disposed on an inserter 51. Each programmable IC 1 includes a super logic region (SLR) 53 of programmable device 54, such as SLRs 53A, 53B, 53C, and 53D. Programmable ICs 1 are interconnected via conductors (referred to as super long lines (SLL) 52) on inserter 51.

[0041] Figure 7BThis is a block diagram depicting a programmable IC 1 according to an example. Programmable IC 1 can be used to implement one of programmable device 128 or programmable ICs 1A-1D in programmable device 54. Programmable IC 1 includes programmable logic 3 (also called a programmable structure), configuration logic 25, and configuration memory 26. Programmable IC 1 can be coupled to external circuitry, such as non-volatile memory 27, DRAM 28, and other circuitry 29. Programmable logic 3 includes logic cells 30, support circuitry 31, and programmable interconnects 32. Logic cells 30 include circuitry that can be configured to implement general logic functions with multiple inputs. Support circuitry 31 includes special-purpose circuitry, such as transceivers, input / output blocks, digital signal processors, memories, etc. Logic cells and support circuitry 31 can be interconnected using programmable interconnects 32. Information for programming logic cells 30, setting parameters of support circuitry 31, and programming programmable interconnects 32 is stored in configuration memory 26 by configuration logic 25. Configuration logic 25 can obtain configuration data from non-volatile memory 27 or any other source (e.g., DRAM 28 or from other circuitry 29). In some examples, programmable IC 1 includes a processing system 2. Processing system 2 may include microprocessors(s), memory, support circuitry, I / O circuitry, etc. In some examples, programmable IC 1 includes an on-chip network (NOC) 55 and a data processing engine (DPE) array 56. NOC 55 is configured to provide communication between subsystems of programmable IC 1, such as PS 2, PL 3, and DPE array 56. DPE array 56 may include a DPE array configured to perform data processing, such as a vector processor array.

[0042] Figure 7C This is a block diagram depicting a System-on-a-Chip (SoC) implementation of a programmable IC 1 according to an example. In this example, programmable IC 1 includes a processing system 2 and programmable logic 3. The processing system 2 includes various processing units, such as a Real-Time Processing Unit (RPU) 4, an Application Processing Unit (APU) 5, a Graphics Processing Unit (GPU) 6, a Configuration and Security Unit (CSU) 12, a Platform Management Unit (PMU) 122, etc. The processing system 2 also includes various supporting circuitry, such as an on-chip memory (OCM) 14, a transceiver 7, peripheral devices 8, an interconnect 16, a DMA circuit 9, a memory controller 10, peripheral devices 15, and multiplexed I / O (MIO) circuitry 13. The processing units and supporting circuitry are interconnected via interconnect 16. PL 3 is also coupled to interconnect 16. Transceiver 7 is coupled to external pin 24. PL 3 is coupled to external pin 23. Memory controller 10 is coupled to external pin 22. MIO 13 is coupled to external pin 20. PS 2 is typically coupled to external pin 21. The APU 5 may include a CPU 17, a memory 18, and support circuitry 19.

[0043] exist Figure 3 In example C, programmable IC 1 can be used in hardware accelerator 122 and can function as described above. Acceleration circuit 130 can be programmed in PL 3 and functions as described above. In another example, the functionality of the aforementioned hardware 104 can be implemented using PS 2 instead of through the hardware of the computing system. In this case, software 106 executes on PS2 and functions as described above.

[0044] Referring to PS 2, each of the processing units includes one or more central processing units (CPUs) and associated circuitry such as memory, interrupt controllers, direct memory access (DMA) controllers, memory management units (MMUs), floating-point units (FPUs), etc. Interconnects 16 include various switches, buses, communication links, etc., configured to interconnect the processing units and to interconnect other components in PS 2 to the processing units.

[0045] OCM 14 includes one or more RAM modules, which may be distributed throughout the PS 2. For example, OCM 14 may include Battery Backup RAM (BBRAM), Tightly Coupled Memory (TCM), etc. Memory controller 10 may include a DRAM interface for accessing external DRAM. Peripheral devices 8 and 15 may include one or more components that provide interfaces to the PS 2. For example, peripheral device 15 may include a graphics processing unit (GPU), a display interface (e.g., DisplayPort, High Definition Multimedia Interface (HDMI) port), a Universal Serial Bus (USB) port, an Ethernet port, a Universal Asynchronous Receiver / Transmitter (UART) port, a Serial Peripheral Interface (SPI) port, a General Purpose I / O (GPIO) port, a Serial Advanced Technology Attachment (SATA) port, a PCIe port, etc. Peripheral device 15 may be coupled to MIO 13. Peripheral device 8 may be coupled to transceiver 7. Transceiver 7 may include serializer / deserializer (SERDES) circuitry, a multi-gigabit transceiver (MGT), etc.

[0046] Figure 7D An implementation of a field-programmable gate array (FPGA) including a programmable IC 1 with PL 3 is shown. Figure 7DThe PL 3 shown can be used in any example of the programmable device described herein. The PL 3 includes a large number of different programmable blocks, including a transceiver 37, a configurable logic block (“CLB”) 33, a random access memory block (“BRAM”) 34, an input / output block (“IOB”) 36, configuration and clock logic (“CONFIG / CLOCKS”) 42, a digital signal processing block (“DSP”) 35, dedicated input / output blocks (“I / O”) 41 (e.g., configuration ports and clock ports), and other programmable logic 39, such as a digital clock manager, an analog-to-digital converter, system monitoring logic, etc. The PL 3 may also include a PCIe interface 40, an analog-to-digital converter (ADC) 38, etc.

[0047] In some PLs, each programmable block may include at least one programmable interconnect element (“INT”) 43, which has connections to input and output terminals 48 of programmable logic elements within the same block, such as... Figure 7D The top includes an example as shown. Each programmable interconnect element 43 may also include a connection to an interconnect segment 49 of adjacent programmable interconnect elements in the same block or other blocks(s). Each programmable interconnect element 43 may also include a connection to an interconnect segment 50 of a general routing resource between logic blocks (not shown). The general routing resource may include routing paths between logic blocks (not shown), including tracks for interconnect segments (e.g., interconnect segment 50) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segment of the general routing resource (e.g., interconnect segment 50) may span one or more logic blocks. The programmable interconnect element 43, together with the general routing resource, implements a programmable interconnect structure (“programmable interconnect”) for the illustrated PL.

[0048] In the example implementation, CLB 33 may include configurable logic elements (“CLE”) 44, which can be programmed to implement user logic plus a single programmable interconnect element (“INT”) 43. In addition to one or more programmable interconnect elements, BRAM 34 may also include BRAM logic elements (“BRL”) 45. Typically, the number of interconnect elements included in a block depends on the block height. In the example shown, the BRAM block has the same height as five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect elements, DSP block 35 may also include DSP logic elements (“DSPL”) 46. In addition to one instance of programmable interconnect element 43, IOB 36 may also include two instances, for example, input / output logic elements (“IOL”) 47. Those skilled in the art will appreciate that, for example, the actual I / O pads connected to I / O logic elements 47 are typically not limited to the area of ​​the input / output logic elements 47.

[0049] In the example shown, the horizontal region near the center of the die (such as...) Figure 3 (D) is used for configuration, clocking, and other control logic. The vertical column 51 extending from this horizontal area or column is used to distribute clock and configuration signals across the width of the PL.

[0050] use Figure 7D Some of the logic blocks (PLs) in the architecture shown include additional logic blocks that disrupt the regular columnar structure that makes up most of the PL. These additional logic blocks can be programmable blocks and / or dedicated logic.

[0051] Notice, Figure 7D This is intended to illustrate only an exemplary PL architecture. Examples include the number of logic blocks in a row, the relative width of the row, the number and order of rows, the types of logic blocks included in a row, the relative size of the logic blocks, and... Figure 7D The interconnect / logic implementations included at the top are merely exemplary. For example, in a real PL, more than one adjacent CLB line is typically included wherever a CLB appears to facilitate efficient implementation of user logic, but the number of adjacent CLB lines varies with the overall size of the PL.

[0052] This disclosure may also be represented in one or more of the following examples (but is not limited thereto):

[0053] Example 1: A hardware accelerator in a computing system includes: a bus interface coupled to a peripheral bus of the computing system; a locking circuit coupled to the bus interface; and a plurality of core circuits coupled to the locking circuit and the bus interface; wherein the plurality of core circuits provide locking requests to the locking circuit, the locking requests being for data stored in system memory of the computing system; wherein the locking circuit is configured to process the locking requests from the plurality of core circuits and issue atomic transactions on the peripheral bus via the bus interface based on the locking requests.

[0054] Example 2: According to the hardware accelerator of Example 1, the locking circuit is configured to maintain a kernel locking array, and the kernel locking array includes multiple elements, each element having a pending request field and a lock status field.

[0055] Example 3: According to the hardware accelerator of Example 2, the pending request field includes multiple entries corresponding to the plurality of kernel circuits, and the lock status field includes multiple entries corresponding to the plurality of kernel circuits.

[0056] Example 4: According to the hardware accelerator of Example 3, wherein the locking circuit is configured to check the lock status field of the corresponding element in the kernel locking array for each locking request in the locking request, and if available, set a lock in the lock status field of the corresponding element, and if the lock is not available, indicate a pending lock request in the pending request field.

[0057] Example 5: According to the hardware accelerator of Example 1, the locking circuit is configured to maintain a kernel locking array, and the kernel locking array includes multiple elements, each having a counter field and a lock status field.

[0058] Example 6: According to the hardware accelerator of Example 5, the counter field includes a value, and the lock state field includes multiple entries corresponding to the plurality of core circuits.

[0059] Example 7: According to the hardware accelerator of Example 6, wherein the locking circuit is configured to, for each locking request in the locking request, check the lock status field of the corresponding element in the kernel locking array, set a lock in the lock status field of the corresponding element, and increment the value in the counter field of the corresponding element.

[0060] Example 8: A computing system includes: system memory; a processor coupled to the system memory; a peripheral bus coupled to the system memory; a hardware accelerator coupled to the peripheral bus; a bus interface coupled to the peripheral bus; a locking circuit coupled to the bus interface; and a plurality of core circuits coupled to the locking circuit and the bus interface; wherein the plurality of core circuits provide a locking request to the locking circuit, the locking request being for data stored in the system memory of the computing system; wherein the locking circuit is configured to process the locking request from the plurality of core circuits and issue an atomic transaction on the peripheral bus via the bus interface based on the locking request.

[0061] Example 9: According to the computing system of Example 8, the locking circuit is configured to maintain a kernel locking array, and the kernel locking array includes multiple elements, each element having a pending request field and a lock status field.

[0062] Example 10: According to the computing system of Example 9, the pending request field includes multiple entries corresponding to the plurality of kernel circuits, and the lock status field includes multiple entries corresponding to the plurality of kernel circuits.

[0063] Example 11: According to the computing system of Example 10, the locking circuit is configured to check the lock status field of the corresponding element in the kernel locking array for each locking request in the locking request, and if available, set a lock in the lock status field of the corresponding element, and if the lock is unavailable, indicate a pending lock request in the pending request field.

[0064] Example 12: According to the computing system of Example 8, the locking circuit is configured to maintain a kernel locking array, and the kernel locking array includes multiple elements, each element having a counter field and a lock status field.

[0065] Example 13: The computing system according to Example 12, wherein the counter field includes a value, and wherein the lock state field includes a plurality of entries corresponding to the plurality of core circuits.

[0066] Example 14: According to the computing system of Example 13, wherein the locking circuit is configured to, for each locking request in the locking request, check the lock status field of the corresponding element in the kernel locking array, set a lock in the lock status field of the corresponding element, and increment the value in the counter field of the corresponding element.

[0067] Example 15: A method for managing locking of data stored in memory among a plurality of cores executing in a hardware accelerator of a computing system, the method comprising: receiving a lock request from one of the plurality of cores at a locking circuit in the hardware accelerator; determining whether the lock is held by another core among the plurality of cores; indicating a pending request for the core in response to the lock being held by the other core; and issuing an atomic request for the lock from the locking circuit through a bus interface of the computing system to acquire the lock in response to the lock not being held by the other core.

[0068] Example 16: The method according to Example 15 further includes: instructing the kernel to have the lock.

[0069] Example 17: The method according to Example 15 further includes: receiving a lock release request from the kernel at the locking circuit; determining whether another kernel among the plurality of kernels has a pending lock request; issuing another atomic request from the locking circuit through the bus interface of the computing system to release the lock in response to the absence of a pending lock request; and granting the lock to another kernel among the plurality of kernels by the locking circuit in response to the presence of a pending lock request.

[0070] Example 18: According to the method of Example 15, the locking circuit is configured to maintain a kernel locking array, and the kernel locking array includes multiple elements, each element having a pending request field and a lock status field.

[0071] Example 19: According to the method of Example 18, the pending request field includes a plurality of entries corresponding to the plurality of kernel circuits, and the lock status field includes a plurality of entries corresponding to the plurality of kernel circuits.

[0072] Example 20: According to the method of Example 15, the locking circuit is configured to maintain a kernel locking array, and the kernel locking array includes multiple elements, each element having a counter field and a lock status field.

[0073] Although the above is for a specific example, other and additional examples can be designed without departing from its basic scope, and its scope is determined by the following examples.

[0074] Although the above examples are specific, other and additional examples may be devised without departing from their basic scope, the scope of which is determined by the appended claims.

Claims

1. A hardware accelerator in a computing system, comprising: A bus interface, coupled to the peripheral bus of the computing system; A locking circuit is coupled to the bus interface; as well as Multiple core circuits are coupled to the locking circuit and the bus interface; The plurality of kernel circuits provide lock requests to the locking circuit, the lock requests being for data stored in the system memory of the computing system; The locking circuitry is configured to process the lock requests from the plurality of core circuits and, in response to a lock not being held by another core, to issue an atomic transaction on the peripheral bus via the bus interface.

2. The hardware accelerator of claim 1, wherein the locking circuit is configured to maintain a kernel locking array, and wherein the kernel locking array comprises a plurality of elements, each element having a pending request field and a lock status field.

3. The hardware accelerator of claim 2, wherein the pending request field includes a plurality of entries corresponding to the plurality of kernel circuits, and wherein the lock status field includes a plurality of entries corresponding to the plurality of kernel circuits.

4. The hardware accelerator of claim 3, wherein the locking circuit is configured to, for each locking request in the locking request, check the lock status field of the corresponding element in the kernel locking array, and if available, set a lock in the lock status field of the corresponding element, and if a lock is unavailable, indicate a pending locking request in the pending request field.

5. The hardware accelerator of claim 1, wherein the locking circuit is configured to maintain a kernel locking array, and wherein the kernel locking array comprises a plurality of elements, each element having a counter field and a lock status field.

6. The hardware accelerator of claim 5, wherein the counter field includes a value, and wherein the lock state field includes a plurality of entries corresponding to the plurality of core circuits.

7. The hardware accelerator of claim 6, wherein the locking circuit is configured to, for each of the locking requests, check the lock status field of the corresponding element in the kernel locking array, set a lock in the lock status field of the corresponding element, and increment the value in the counter field of the corresponding element.

8. A computing system, comprising: System memory; The processor is coupled to the system memory; The peripheral bus is coupled to the system memory; as well as The hardware accelerator according to claim 1 is coupled to the peripheral bus.

9. The computing system of claim 8, wherein the locking circuit is configured to maintain a kernel locking array, and wherein the kernel locking array comprises a plurality of elements, each element having a pending request field and a lock status field.

10. A method for managing locking of data stored in memory among multiple cores executing in a hardware accelerator of a computing system, the method comprising: At the locking circuitry in the hardware accelerator, a locking request is received from one of the plurality of cores. Determine whether the lock is held by another kernel among the plurality of kernels; In response to the lock being held by another kernel, an pending request to that kernel is indicated; as well as In response to the lock not being held by another core, an atomic request for the lock is issued from the locking circuit through the bus interface of the computing system to acquire the lock.

11. The method of claim 10, further comprising: This indicates that the kernel has the lock.

12. The method of claim 10, further comprising: At the locking circuit, a lock release request is received from the kernel; Determine whether another kernel among the plurality of kernels has an pending lock request; In response to the absence of any pending lock requests, another atomic request is issued from the locking circuit via the bus interface of the computing system to release the lock; as well as In response to an pending lock request, the locking circuit grants the lock to another core among the plurality of cores.

13. The method of claim 10, wherein the locking circuit is configured to maintain a kernel locking array, and wherein the kernel locking array comprises a plurality of elements, each element having a pending request field and a lock status field.

14. The method of claim 13, wherein the pending request field includes a plurality of entries corresponding to the plurality of kernel circuits, and wherein the lock status field includes a plurality of entries corresponding to the plurality of kernel circuits.

15. The method of claim 10, wherein the locking circuit is configured to maintain a kernel locking array, and wherein the kernel locking array comprises a plurality of elements, each element having a counter field and a lock status field.

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