Semiconductor structure and method of forming the same

Abstract

The present application relates to a semiconductor structure and a method of forming the same. The semiconductor structure includes a first wiring layer and a second wiring layer located above the first wiring layer, the second wiring layer including a first conductive wiring and a first dielectric layer covering the first conductive wiring. The first conductive wiring extends into the first dielectric layer and a top surface of the first conductive wiring is located below a top surface of the first dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] The primary goal of substrate (e.g., fan-out substrate, FOSub) design is to reduce the number of fan-out layers and substrate layers. In some cases, such as due to the electrical requirements of serializers / deserializers (SerDes), a thicker RDL (Redirect Linear Distribution Layer) is needed in the fan-out redistribution layer (RDL) design. Specifically, a thicker metal layer is required in the RDL because a thin metal layer would cause signal loss. If the metal layer thickness is not increased, the width of the metal layer could be increased, but this would increase the number of RDL layers. On the other hand, current processes for forming fine-line structures use thin-film photoresist, and due to variations in photoresist and electroplating, the thickness of the fine lines can only be controlled at 2-3 micrometers. The RDL cannot meet the design requirements of a thickness of 6-7 micrometers. To increase the thickness of the RDL, the linewidth and spacing of the fine lines must be widened. In other words, if photoresist with the required thickness is used, the fine lines cannot be accommodated in the design. Summary of the Invention

[0003] To address the aforementioned problems in related technologies, this invention proposes a semiconductor structure and a method for forming the same.

[0004] According to one aspect of an embodiment of the present invention, a semiconductor structure is provided, comprising: a first circuit layer; and a second circuit layer located above the first circuit layer, the second circuit layer including a first conductive line and a first dielectric layer covering the first conductive line, wherein the first conductive line extends into the first dielectric layer and the top surface of the first conductive line is located below the top surface of the first dielectric layer.

[0005] In some embodiments, the aspect ratio of the first conductive line is greater than 1.

[0006] In some embodiments, the linewidth of the first conductive line is less than 5 micrometers, and the spacing between the first conductive lines is less than 5 micrometers.

[0007] In some embodiments, the width of at least a portion of the first conductive line within the first dielectric layer gradually decreases in the direction from the top surface of the first line layer to the first dielectric layer.

[0008] In some embodiments, the semiconductor structure further includes a serializer / deserializer located above and electrically connected to the second line layer.

[0009] In some embodiments, the second circuit layer further includes a second conductive line passing through the first dielectric layer.

[0010] In some embodiments, the second circuit layer further includes a second dielectric layer located below the first dielectric layer and additional first conductive lines embedded in the second dielectric layer, wherein the top surface of the additional first conductive lines is located below the top surface of the second dielectric layer.

[0011] In some embodiments, the second circuit layer further includes a connection via connected to the first conductive line, and the width of the connection via gradually increases in the direction from the first circuit layer to the top surface of the first dielectric layer.

[0012] According to another aspect of the present invention, a method for forming a semiconductor structure is also provided, comprising: providing a first dielectric layer on a carrier; forming a first line trench in the first dielectric layer, the bottom surface of the first line trench being higher than the bottom surface of the first dielectric layer; and filling the first line trench with a conductive material to form a first line located in the first dielectric layer.

[0013] In some embodiments, forming a first line trench includes: forming a first line trench and a second line trench in a first dielectric layer using a grayscale photomask, wherein the depth of the second line trench is greater than the depth of the first line trench.

[0014] In some embodiments, the second line trench passes through the first dielectric layer.

[0015] In some embodiments, the method of forming a semiconductor structure further includes: covering a second line trench when the first line trench is filled with a conductive material.

[0016] In some embodiments, the method of forming a semiconductor structure further includes: forming a serializer / deserializer located above the line layer and electrically connected to the line layer.

[0017] In some embodiments, the method of forming a semiconductor structure further includes: attaching a first dielectric layer to a substrate and removing a carrier; forming a connection via opening on the surface of the first dielectric layer opposite to the substrate to reach a first line; and filling the connection via opening with a conductive material to form a connection via.

[0018] In some embodiments, the linewidth of the first line is less than 5 micrometers, and the spacing between the first lines is less than 5 micrometers.

[0019] In some embodiments, the method of forming a semiconductor structure further includes: forming a serializer / deserializer located above the line layer and electrically connected to the line layer.

[0020] In some embodiments, the method of forming a semiconductor structure further includes: forming a second dielectric layer over a first dielectric layer; forming another first line trench in the second dielectric layer, wherein the bottom surface of the other first line trench is higher than the bottom surface of the second dielectric layer; and filling the second line trench with a conductive material to form another first line located in the second dielectric layer.

[0021] In some embodiments, the aspect ratio of the first line trench is greater than 1.

[0022] In some embodiments, the linewidth of the first line is less than 5 micrometers, and the spacing between the first lines is less than 5 micrometers.

[0023] In some embodiments, the width of the first line trench gradually increases in the direction from the carrier to the top surface of the first dielectric layer. Attached Figure Description

[0024] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0026] Figures 2A to 2G This is a schematic diagram of the various stages of a method for forming a semiconductor structure according to an embodiment of the present invention. Specific Implementation

[0027] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1As shown, the semiconductor structure may include a first circuit layer 110 and a second circuit layer 120 located above the first circuit layer 110. The second circuit layer 120 includes a first conductive line 125 and a first dielectric layer 121 covering the first conductive line 125. The first conductive line 125 extends into the first dielectric layer 121, and the top surface of the first conductive line 125 is located below the top surface of the first dielectric layer 121. Furthermore, there is a distance between the top surface of the first conductive line 125 and the top surface of the first dielectric layer 121. In some embodiments, the first circuit layer 110 may be a substrate. In some embodiments, the second circuit layer 120 may be a redistribution layer (RDL).

[0029] In some embodiments, a grayscale photomask can be used to create trenches in the first dielectric layer 121 to accommodate the first conductive line 125, and then the trenches can be filled with a metal material through a process such as electroplating. By utilizing the characteristic that the dielectric layer is not fully exposed by the grayscale photomask, the first conductive line 125 can be embedded in the first dielectric layer 121. In this way, the overall thickness of the second circuit layer 120 (e.g., RDL layer) can be increased by increasing the thickness of the first dielectric layer 121, thus forming a thin circuit with a thicker thickness and line width and spacing that meets the requirements of fine circuits without sacrificing electrical characteristics. This improves the process yield, which can reach greater than 99.5%. On the other hand, because of the design of embedding the first conductive line 125, the number of layers of the second circuit layer 120 can be reduced compared with the prior art, making the semiconductor structure of the present invention thinner.

[0030] In some embodiments, the aspect ratio of the first conductive line 125 is greater than 1. The linewidth of the first conductive line 125 is less than 5 micrometers, and the spacing between the first conductive lines 125 (i.e., line pitch) is less than 5 micrometers. In some embodiments, the linewidth of the first conductive line 125 is less than 2 micrometers, and the spacing between the first conductive lines 125 is less than 2 micrometers. That is, the linewidth and line pitch of the first conductive line 125 can meet the requirements for fine lines.

[0031] In some embodiments, the semiconductor structure may further include a serializer / deserializer (SerDes) (not shown), which is located above and electrically connected to the second line layer 120. This invention achieves the electrical design requirements of the SerDes through an embedded RDL, such as a thicker RDL.

[0032] Continue to refer to Figure 1As shown, in the direction from the top surface of the first circuit layer 110 to the first dielectric layer 121, the width of the portion of the first conductive line 125 within the first dielectric layer 121 gradually decreases. The second circuit layer 120 may further include a second conductive line 126 that passes through the first dielectric layer 121. Furthermore, the second circuit layer 120 may also include a via 129 connected to the first conductive line 125. The via 129 communicates with the top surface of the first dielectric layer 121. In the direction from the top surface of the first circuit layer 110 to the first dielectric layer 121, the width of the via 129 gradually increases. That is, the outline of the via 129 is opposite to the outline of the first conductive line 125.

[0033] The second circuit layer 120 may further include a second dielectric layer 122 located below the first dielectric layer 121 and another first conductive line 125 embedded in the second dielectric layer 122. Similar to the first conductive line 125, the top surface of the other first conductive line 125 is located below the top surface of the second dielectric layer 122, and there is a distance between the top surface of the other first conductive line 125 and the top surface of the second dielectric layer 122. In some embodiments, the distance between the embedded first conductive line 125 and the other first conductive line 125 in the next layer may be in the range of 2 micrometers to 3 micrometers.

[0034] In the illustrated embodiment, a third dielectric layer 123 and additional first conductive lines 125 and second conductive lines 126 located within the third dielectric layer 123 are further disposed below the second dielectric layer 122. The additional first conductive lines 125 and second conductive lines 126 in the third dielectric layer 123 may be similar to the additional first conductive lines 125 and second conductive lines 126 in the second dielectric layer 122, and will not be described again here. The second circuit layer 120 can be attached to the first circuit layer 110 via an adhesive layer 190.

[0035] An embodiment of the present invention also provides a method for forming a semiconductor structure. Figures 2A to 2G This is a schematic diagram of the various stages of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] First, such as Figure 2AAs shown, a carrier 201 is provided, and a first dielectric layer 121 is provided on the carrier 201. Then, a first circuit trench 221 is formed in the first dielectric layer 121 using a grayscale photomask. The first circuit trench 221 formed using the grayscale photomask does not penetrate the first dielectric layer 121, therefore the bottom surface of the first circuit trench 221 is higher than the bottom surface of the first dielectric layer 121. In this step, a second circuit trench 222 can also be formed simultaneously, the depth of the second circuit trench 222 being greater than the depth of the first circuit trench 221. The second circuit trench 222 can penetrate the first dielectric layer 121.

[0037] Then, as Figure 2B As shown, a mask 230 is used to cover the second line trench 222, and a conductive material is used to fill the first line trench 221 to form a first conductive line 125 (also referred to as the first line). Figure 2C As shown, the mask 230 is removed to expose the second wiring trench 222, and conductive material is filled into the second wiring trench 222 to form a second conductive line 126 (also referred to as a second line). After the first conductive line 125 and the second conductive line 126 are formed, pits are generated on the top surfaces of the first conductive line 125 and the second conductive line 126 due to insufficient line thickness above the first dielectric layer. In some embodiments, the depth of the pits can be in the range of 1 micrometer to 3 micrometers.

[0038] As described above, by using a grayscale photomask, the first dielectric layer 121 is not fully exposed, thus allowing the fabrication of a first conductive line 125 embedded within the first dielectric layer 121. This allows the thickness of the second circuit layer 120 (e.g., an RDL layer) to be increased by adjusting the thickness of the first dielectric layer 121, resulting in a thin circuit with sufficient linewidth and spacing to meet the requirements of fine lines without sacrificing electrical properties. Because of the embedded first conductive line 125 design, the number of layers in the second circuit layer 120 can be reduced compared to existing technologies, and the semiconductor structure of this invention can be made thinner.

[0039] like Figure 2D As shown, a second dielectric layer 122 is formed above the first dielectric layer 121. A second first line trench 221 is formed in the second dielectric layer 122 using a grayscale photomask. The bottom surface of the second first line trench 221 is higher than the bottom surface of the second dielectric layer 122, meaning the second first line trench 221 does not penetrate the second dielectric layer 122. Additionally, a second second line trench 222 is formed in the second dielectric layer 122, penetrating the second dielectric layer 122. Furthermore, conductive material is filled into the second first conductive line trench 125 and the second line trench 222 to form additional first conductive lines 125 and 126 located in the second dielectric layer 122.

[0040] like Figure 2EAs shown, a third dielectric layer 123 can be formed above the second dielectric layer 122. And with... Figure 2D Similarly, additional first conductive lines 125 and second conductive lines 126 are formed in the third dielectric layer 123. The first dielectric layer 121, the second dielectric layer 122, and the third dielectric layer 123, along with the first conductive lines 125 and the second conductive lines 126 therein, are collectively referred to as the second circuit layer 120. In other embodiments, the second circuit layer 120 may also comprise any suitable number of layers.

[0041] like Figure 2F As shown, for example, the second circuit layer 120 is attached to the first circuit layer 110 via the adhesive layer 190, and the carrier 201 is removed. Then, as... Figure 2G As shown, a connection via opening is formed on the surface of the first dielectric layer 121 opposite to the first circuit layer 110, leading to the first conductive line 125. The connection via opening is filled with conductive material to form a connection via 129. As described above, the outline of the connection via is opposite to that of the first conductive line 125.

[0042] Subsequently, UBM (Under-Bump Metal) 195 is formed on the connecting via and the second conductive line 126 passing through the first dielectric layer 121 to obtain Figure 1 The semiconductor structure shown. In some embodiments not shown, a SerDes may also be formed above the second circuit layer 120 and electrically connected to the circuits in the second circuit layer 120.

[0043] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, characterized by, include: First line layer; A second circuit layer is located above the first circuit layer. The second circuit layer includes a first conductive line and a first dielectric layer covering the first conductive line, wherein the first conductive line extends into the first dielectric layer and the top surface of the first conductive line is located below the top surface of the first dielectric layer. The second circuit layer further includes a second conductive line passing through the first dielectric layer. The depth of the second conductive line is greater than the depth of the first conductive line. In the direction from the bottom surface of the first dielectric layer to the top surface of the first dielectric layer, the width of the second conductive line gradually decreases from the bottom surface of the first dielectric layer until it passes through the top surface of the first dielectric layer to connect with the under-bump metal. The second conductive line has smooth sidewalls extending from the bottom surface of the first dielectric layer to the top surface of the first dielectric layer.

2. The semiconductor structure of claim 1, wherein, In the direction from the first line layer to the top surface of the first dielectric layer, the width of the first conductive line, at least in the portion within the first dielectric layer, gradually decreases.

3. The semiconductor structure of claim 1, wherein, Also includes: The serializer deserializer (SerDes) is located above the second line layer and is electrically connected to the second line layer.

4. The semiconductor structure according to claim 1, characterized in that, The second conductive line is interconnected with an adjacent first conductive line.

5. The semiconductor structure according to claim 1, characterized in that, The second circuit layer further includes a second dielectric layer located below the first dielectric layer and another first conductive line embedded in the second dielectric layer, wherein the top surface of the other first conductive line is located below the top surface of the second dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that, The second circuit layer further includes a connecting via, which is connected to the first conductive line, and the width of the connecting via gradually increases in the direction from the first circuit layer to the top surface of the first dielectric layer.

7. A method for forming a semiconductor structure, characterized in that, include: A first dielectric layer is provided on the carrier; A first line trench and a second line trench are formed in the first dielectric layer using a grayscale photomask. The depth of the second line trench is greater than the depth of the first line trench, and the bottom surface of the first line trench is higher than the bottom surface of the first dielectric layer. The first line trench is filled with conductive material to form a first line located in the first dielectric layer. A second line is formed within the second line trench, penetrating the first dielectric layer, and the depth of the second line is greater than the depth of the first line. In the direction from the top surface of the first dielectric layer to the bottom surface of the first dielectric layer, the width of the second line gradually decreases from the top surface of the first dielectric layer until it passes through the bottom surface of the first dielectric layer, and the second line has smooth sidewalls extending from the bottom surface of the first dielectric layer to the top surface of the first dielectric layer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The second line is interconnected with one of the first lines adjacent to it.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, Also includes: The first dielectric layer is attached to another circuit layer and the carrier is removed; A connection via is formed on the surface of the first dielectric layer opposite to the other circuit layer to reach the first circuit. The connection through-hole is filled with conductive material to form a connection through-hole.

10. The method for forming a semiconductor structure according to claim 7, characterized in that, Also includes: A second dielectric layer is formed above the first dielectric layer, and another first circuit trench is formed in the second dielectric layer, wherein the bottom surface of the other first circuit trench is higher than the bottom surface of the second dielectric layer. The additional first line trench is filled with conductive material to form an additional first line located in the second dielectric layer.

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