Storage device and method of manufacturing the same

Abstract

A memory device includes a magnetic track layer extending over a substrate, the magnetic track layer having a two-dimensional villous fold structure; a plurality of read units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers; and a plurality of bit lines extending over different ones of the plurality of read units, the plurality of read units being between the magnetic track layer and respective ones of the plurality of bit lines.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0057831, filed on May 14, 2020 with the Korean Intellectual Property Office and entitled "Memory Device and Method of Manufacturing the Same", is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to storage devices and methods of manufacturing the same, and more specifically, to storage devices including racetracks and methods of manufacturing the same. Background Technology

[0004] Due to the demands for miniaturization, multifunctionality, and high performance in electronic products, high-capacity storage devices are required. To provide high capacity, a domain wall shift register type storage device with a track is proposed, wherein the track comprises multiple domains that store information by moving between domains via domain walls. Summary of the Invention

[0005] According to an embodiment, a storage device is provided, the storage device comprising: a magnetic track layer extending on a substrate in a folded structure, wherein the magnetic track layer is two-dimensionally fluffy; a plurality of read cells including a plurality of fixing layers and a tunnel barrier layer disposed between the magnetic track layer and the plurality of fixing layers; and a plurality of bit lines extending on different read cells among the plurality of read cells, the plurality of read cells being located between the magnetic track layer and the plurality of bit lines.

[0006] According to an embodiment, a storage device is also provided, the storage device comprising: a substrate having a storage region and a connection region in a first horizontal direction of the storage region; a plurality of storage stacks, each of the plurality of storage stacks including a magnetic track layer stacked on the substrate, and each forming a step in the connection region, and extending and arranged in a folded structure above the storage region and the connection region, wherein the magnetic track layer is at least two fluffy, including a plurality of extended track layers extending two-dimensionally in one direction and at least two connecting track layers connecting two of the plurality of extended track layers; a plurality of read units, wherein... The plurality of read cells include a plurality of fixed layers and a tunnel barrier layer disposed between the magnetic track layer and the plurality of fixed layers; a plurality of bit lines extending over different read cells among the plurality of read cells, the plurality of read cells being located between the magnetic track layer and the plurality of bit lines; a plurality of connection contact plugs connected to a pad track layer that is part of one end of the magnetic track layer of the plurality of memory stacks in the connection region; and a common source line connected to the magnetic track layer of the plurality of memory stacks in the memory region opposite to the connection region in the first direction.

[0007] According to an embodiment, a storage device is also provided, the storage device comprising: a substrate including a storage region, a first connection region in a first horizontal direction of the storage region, and a second connection region in a second horizontal direction perpendicular to the first horizontal direction of the storage region; a plurality of storage stacks, each of the plurality of storage stacks including an etch stop layer stacked on the substrate while forming steps in the first connection region and the second connection region; and a magnetic track layer extending over the storage region and the first connection region in a folded structure along the upper surface of the etch stop layer, wherein the magnetic track layer is at least two-pile-like, including a plurality of extended track layers extending two-dimensionally in one direction and at least two connecting track layers connecting two of the plurality of extended track layers and having a plurality of magnetic domains; The system comprises multiple read cells, each including multiple fixed layers and a tunnel barrier layer disposed between the magnetic track layer and the multiple fixed layers; multiple bit lines extending on different read cells among the multiple read cells, the multiple read cells being located between the magnetic track layer and the multiple bit lines to form a magnetic tunnel junction (MTJ); multiple first connection contact plugs connected in a first connection region to a pad track layer that is part of one end of the magnetic track layer; a common source line connected to a second end of the magnetic track layer in the memory region opposite to the first connection region in the first horizontal direction; and multiple second connection contact plugs connected in the second connection region to partial bit line pad cells that are part of the bit lines.

[0008] According to an embodiment, a method of manufacturing a storage device is also provided, the method comprising: providing a substrate including a storage region and a connection region in a first horizontal direction of the storage region; forming a plurality of storage stacks having steps formed in the connection regions and stacked on the substrate; and forming a plurality of connection contact plugs connecting to the steps of the plurality of storage stacks. Each of the plurality of storage stacks includes: an etch stop layer located on the substrate; a magnetic track layer extending over the storage region and the connection region in a folded structure along an upper surface of the etch stop layer, wherein the magnetic track layer is at least two-folded to include a plurality of extended track layers extending two-dimensionally in one direction and at least two connection track layers connecting two of the plurality of extended track layers; a plurality of read cells including a plurality of fixing layers and a tunnel barrier layer disposed between the magnetic track layer and the plurality of fixing layers; and a plurality of bit lines extending on different read cells among the plurality of read cells, the plurality of read cells being located between the magnetic track layer and the plurality of bit lines. Forming the plurality of connection contact plugs includes: forming a plurality of connection contact holes in the connection region that expose a portion of the magnetic track layer of the plurality of storage stacks; and forming the plurality of connection contact plugs that fill the plurality of connection contact holes and connect to a portion of the magnetic track layer. Attached Figure Description

[0009] The features will become readily understood by those skilled in the art through a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1A to 9D These are top views and cross-sectional views illustrating various stages in a method for manufacturing a storage device according to an embodiment;

[0011] Figure 9E This is an enlarged cross-sectional view showing the portion where the first connecting contact plug is connected to the magnetic track layer;

[0012] Figures 10A to 10C These are top views and cross-sectional views of a storage device according to an embodiment;

[0013] Figure 10D It is a cross-sectional view of the storage string of the storage device;

[0014] Figures 11A to 11C This is a top view showing the stages of a method for manufacturing a storage device according to an embodiment;

[0015] Figures 12A to 12C This is a cross-sectional view showing a portion of the storage string of a storage device according to an embodiment;

[0016] Figure 13A and Figure 13B This is a cross-sectional view showing the various stages in a method for manufacturing a storage device according to an embodiment;

[0017] Figures 14A to 14C This is a cross-sectional view showing a portion of the storage string of a storage device according to an embodiment;

[0018] Figure 15 This is a cross-sectional view showing a storage device according to an embodiment;

[0019] Figure 16 This is a cross-sectional view showing a storage device according to an embodiment;

[0020] Figure 17A This is a cross-sectional view illustrating a method of manufacturing a storage device according to an embodiment;

[0021] Figure 17B This is a cross-sectional view of a portion of the magnetic track layer of a storage device according to an embodiment;

[0022] Figure 18A This is a cross-sectional view illustrating a method of manufacturing a storage device according to an embodiment;

[0023] Figure 18B This is a cross-sectional view showing a portion of the magnetic track layer of a storage device according to an embodiment; and

[0024] Figures 19A to 19C This is a perspective view showing a storage device according to an embodiment. Detailed Implementation

[0025] Figures 1A to 9D These are top views and cross-sectional views illustrating various stages in a method for manufacturing a storage device according to an embodiment, and Figure 9E This is an enlarged cross-sectional view showing the portion where the first connecting contact plug connects to the magnetic track layer. Specifically, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A This is a top view illustrating the various stages of a method for manufacturing a storage device according to an embodiment, and Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B They are along Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A The cross-sectional view taken by line B-B', and Figure 1C , Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Figure 9C They are along 1A, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A The cross-sectional view of line C-C', and Figure 9D It is along Figure 9A A cross-sectional view of line D-D'.

[0026] Reference Figures 1A to 1C A substrate 110 is provided having a storage region MR, a first peripheral circuit region PRx, a second peripheral circuit region PRy, a first connection region CRx located between the storage region MR and the first peripheral circuit region PRx, and a second connection region CRy located between the storage region MR and the second peripheral circuit region PRy.

[0027] In some embodiments, the storage region MR may be a two-dimensional rectangle. A first connection region CRx and a first peripheral circuit region PRx may be positioned in a first horizontal direction (X-direction) based on the storage region MR, and a second connection region CRy and a second peripheral circuit region PRY may be positioned in a second horizontal direction (Y-direction) perpendicular to the first horizontal direction based on the storage region MR. The first connection region CRx and the second connection region CRy may be referred to as connection regions, and the first peripheral circuit region PRx and the second peripheral circuit region PRY may be referred to as peripheral circuit regions. The connection regions may be located between the storage region MR and the peripheral circuit regions.

[0028] For example, substrate 110 may include a semiconductor material, such as silicon (Si) or germanium (Ge). In another example, substrate 110 may include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Substrate 110 may include an active surface and a passive surface opposite to the active surface. Substrate 110 may include conductive regions located in the active surface, such as impurity-doped wells. Substrate 110 may have each of a variety of isolation structures (e.g., shallow trench isolation (STI) structures) in the active surface.

[0029] Multiple first driving elements TR1 can be formed in the first peripheral circuit region PRx, and multiple second driving elements TR2 can be formed in the second peripheral circuit region PRY. For example, the first driving element TR1 can be a recording element, and the second driving element TR2 can be a selection element.

[0030] Each of the plurality of first driving elements TR1 may include a first gate insulating layer 122 formed on a substrate 110, a first gate electrode 132 covering the first gate insulating layer 122, and a first source region 112a and a first drain region 112b formed in the substrate 110, with the first gate electrode 132 located between the first source region 112a and the first drain region 112b. Each of the plurality of second driving elements TR2 may include a second gate insulating layer 124 formed on a substrate 110, a second gate electrode 134 covering the second gate insulating layer 124, and a second source region 114a and a second drain region 114b formed in the substrate 110, with the second gate electrode 134 located between the second source region 114a and the second drain region 114b. An isolation structure may be formed around the plurality of first driving elements TR1 and the plurality of second driving elements TR2.

[0031] exist Figures 1A to 1C In the example shown, a plurality of first driving elements TR1 and a plurality of second driving elements TR2 are transistors. However, at least some of the driving elements TR1 and TR2 may include diodes or bidirectional threshold switch (OTS) elements.

[0032] Reference Figures 2A to 2C A base insulating layer 150 and an etch stop layer 210 covering a plurality of first driving elements TR1 and a plurality of second driving elements TR2 can be formed on the substrate 110. The base insulating layer 150 may be formed of oxide. However, the embodiments are not limited thereto. In some embodiments, the etch stop layer 210 may be formed of silicon nitride or aluminum oxide. However, the embodiments are not limited thereto.

[0033] Multiple magnetic track layers 220 can be formed on the etch stop layer 210. The multiple magnetic track layers 220 can be formed by forming a magnetic material layer on the etch stop layer 210 and patterning the magnetic material layer. An etching process can be performed to form the multiple magnetic track layers 220 by patterning the magnetic material layer, thereby exposing the etch stop layer 210. In some embodiments, each of the multiple magnetic track layers 220 can be formed above the memory region MR and the first connection region CRx. In some embodiments, each of the multiple magnetic track layers 220 can extend along the upper surface of the etch stop layer 210 with a uniform horizontal width. The multiple magnetic track layers 220 can be referred to as raceways. In the memory region MR, each of the multiple magnetic track layers 220 can have a two-dimensional vili-shaped folded structure. In the storage region MR, each of the plurality of magnetic track layers 220 may include an extended (e.g., linearly shaped) track layer 220L and a connecting track layer 220U connected to the extended track layer 220L (e.g., perpendicular to the track layer 220L). In the first connection region CRx, each of the plurality of magnetic track layers 220 may include a pad track layer 220P extending (e.g., collinearly) from the extended track layer 220L. In some embodiments, the extended track layer 220L and the pad track layer 220P may extend in a first horizontal direction (X direction).

[0034] The two extended track layers 220L and the connecting track layer 220U connecting the two extended track layers 220L can be U-shaped in two dimensions. In some embodiments, in the storage region MR, each of the plurality of magnetic track layers 220 can have a folded structure comprising at least two fibers formed by the plurality of extended track layers 220L and at least two connecting track layers 220U connecting the plurality of extended track layers 220L. For example, each of the plurality of magnetic track layers 220 may include a plurality of extended track layers 220L and a plurality of connecting track layers 220U, which are combined into at least two U-shapes that are adjacent to each other (e.g., in the Y direction) and connected to each other on one side. In the magnetic track layer 220, each fiber-like protrusion (i.e., the connecting track layer 220U) may be disposed in a first horizontal direction (X direction) or in a direction opposite to the first horizontal direction (X direction). However, in Figure 11A In the magnetic track layer 220a shown, each villous protrusion may be positioned in the second horizontal direction (Y direction) or in the opposite direction to the second horizontal direction (Y direction).

[0035] Each of the plurality of magnetic orbital layers 220 can extend in a first horizontal direction (X direction) from one end of the first connection region CRx to the other end of the storage region MR opposite to the first connection region CRx. For example, as Figure 2A and Figure 2B As shown, the first end of each magnetic track layer 220 can be located in the first peripheral circuit region PRx or the first connection region CRx, and the second end of each magnetic track layer 220 can be located (opposite to the first end) in the storage region MR, for example, at the edge of the storage region MR opposite to the first connection region CRx. For example, as Figure 2A and Figure 2B As shown, each magnetic orbital layer 220 can extend along the entire length of the storage region MR in a first horizontal direction (X direction). Each of the multiple magnetic orbital layers 220 having a folded structure with fluff set twice can extend from one end to the other.

[0036] Each of the multiple magnetic orbital layers 220 may include a free layer. The free layer may include at least one of a vertical magnetic material, a vertical magnetic material having an L10 structure, a CoPt alloy having a dense hexagonal close-packed lattice structure, and a vertical laminate. The vertical magnetic material may include at least one of iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd), boron (B), tantalum (Ta), tungsten (W), iridium (Ir), and cobalt (Co), for example, at least one of CoFeB, CoFeTb, CoFeGd, and CoFeDy. For example, the vertical magnetic material having an L10 structure may be Fe... 50 Pt 50 Fe 50 Pd 50 Co 50 Pt 50 Co 50 Pd 50 and Fe 50 Ni 50 At least one of them.

[0037] In some embodiments, each of the plurality of magnetic orbital layers 220 may have a synthetic antiferromagnetic (SAF) structure. For example, each of the plurality of magnetic orbital layers 220 may have a stacked structure of a first material layer, a second material layer, and a third material layer, wherein the first and third material layers may comprise ferromagnetic materials, and the second material layer may comprise a nonmagnetic material.

[0038] For example, the first and third material layers may comprise a vertically stacked body having perpendicular magnetic anisotropy. The vertically stacked body may comprise a stacked structure with alternating and repeating ferromagnetic layers or a stacked structure with alternating and repeating ferromagnetic and nonmagnetic layers. For example, the vertically stacked body may comprise (Co / Pt). n Layered structure, (CoFe / Pt) n Layered structure, (CoFe / Pd) n Layered structure, (Co / Pd) n Layered structure, (Co / Ni) n Layered structure, (CoNi / Pt) n Layered structure, (CoCr / Pt) n Layered structure and (CoCr / Pd) n At least one of the layered structures (here, n is a natural number). The second material layer may include a material capable of achieving Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling between the ferromagnetic layers, such as at least one of ruthenium (Ru), Ir, and rhodium (Rh).

[0039] In some embodiments, each of the plurality of magnetic orbital layers 220 may further include a seed layer and a spin orbital torque (SOT) sensing layer located between the etch stop layer 210 and the free layer. The seed layer may include at least one of a nonmagnetic metallic material (e.g., at least one of chromium (Cr), Ru, or Ta), a nonmagnetic compound (e.g., cobalt gallium (CoGa) or manganese gallium nitride (MnGaN)), and a nonmagnetic alloy (e.g., nickel aluminum (NiAl)). The SOT sensing layer may include at least one nonmagnetic metallic material, such as at least one of W, Pt, Ta, hafnium (Hf), rhenium (Re), Ir, gold (Au), silver (Ag), titanium (Ti), and copper (Cu). Additionally, the SOT sensing layer may include at least one topological insulating material, such as at least one selected from bismuth telluride (Bi₂Te₃), bismuth selenide (Bi₂Se₃), antimony telluride (Sb₂Te₃), molybdenum sulfide (MoS₂), molybdenum telluride (MoTe₂), tungsten sulfide (WS₂), and tungsten telluride (WTe₂). A topological insulating material can generally be defined as a material whose interior is insulating due to its regularity of crystallization, while the portion adjacent to the surface of the material is conductive.

[0040] Reference Figures 3A to 3COn the etch stop layer 210, a first interlayer insulating layer 250a may be formed surrounding the plurality of magnetic orbital layers 220. The first interlayer insulating layer 250a may be formed of, for example, an oxide. However, the embodiments are not limited thereto. The first interlayer insulating layer 250a may cover the side surfaces of the plurality of magnetic orbital layers 220 and may expose at least a portion of the upper surfaces of the plurality of magnetic orbital layers 220. In some embodiments, the upper surface of the first interlayer insulating layer 250a may be coplanar with the upper surfaces of the plurality of magnetic orbital layers 220.

[0041] Multiple readout units 230 may be arranged on different portions of the upper surface of each of the multiple magnetic orbital layers 220. Each readout unit 230 may include a tunnel barrier layer 232 and a fixing layer 234 formed on the magnetic orbital layer 220.

[0042] Multiple read units 230 can be arranged on a portion of each of the multiple magnetic track layers 220 arranged in the storage region MR, and can be arranged not on a portion of each of the multiple magnetic track layers 220 arranged in the first connection region CRx, that is, the multiple read units 230 can be arranged not on the pad track layer 220P. Figure 3A In the diagram, multiple read units 230 are shown arranged only on each extended track layer 220L. However, the embodiment is not limited to this; for example, some of the read units 230 may be arranged on each connecting track layer 220U.

[0043] Each of the multiple read units 230 may have, for example, a horizontal width along the Y direction, which is greater than the horizontal width of the magnetic track layer 220, such as... Figure 3A and Figure 3C As shown. In some embodiments, each of the plurality of reading units 230 may be formed on a portion of the upper surface of the magnetic track layer 220 and a portion of the upper surface of the first interlayer insulating layer 250a. For example, a portion of the reading unit 230 may extend beyond the upper surface of the magnetic track layer 220 along a second horizontal direction (Y direction) to overlap with a portion of the upper surface of the first interlayer insulating layer 250a.

[0044] The tunnel barrier layer 232 may comprise a non-magnetic insulating material. In some embodiments, the tunnel barrier layer 232 may comprise an oxide of at least one of magnesium (Mg), Ti, Al, magnesium zinc (MgZn), or magnesium boron (MgB), or a nitride of at least one of Ti or vanadium (V). For example, the tunnel barrier layer 232 may be a magnesium oxide (MgO) layer or a magnesium aluminum oxide (MgAlO) layer. In other embodiments, the tunnel barrier layer 232 may comprise multiple layers. For example, the tunnel barrier layer 232 may have a stacked structure such as Mg / MgO, MgO / Mg, MgO / MgAlO, MgAlO / MgO, Mg / MaAlO / Mg, MgO / MgAlO / MgO, or MgAlO / MgO / MaAlO. In some embodiments, the tunnel barrier layer 232 may have a NaCl crystal structure (e.g., a face-centered cubic lattice structure).

[0045] For example, the fixing layer 234 may include at least one of Fe, Co, Ni, Pd, and Pt. In some embodiments, the fixing layer 234 may be formed of a Co-M1 alloy (here, M1 is at least one metal selected from Pt, Pd, and Ni) or an Fe-M2 alloy (here, M2 is at least one metal selected from Pt, Pd, and Ni). In other embodiments, the fixing layer 234 may also include at least one of B, carbon (C), Cu, Ag, Au, Ru, Ta, and Cr. In some embodiments, the fixing layer 234 may include a material having perpendicular magnetic anisotropy (PMA). However, the embodiments are not limited thereto.

[0046] The magnetic orbital layer 220 can be arranged to contact the read unit 230, and a magnetic domain, which is a portion of the free layer included in the magnetic orbital layer 220 and perpendicularly overlaps with the read unit 230, can form a magnetic tunnel junction (MTJ) together with the read unit 230. For example, the resistance value of the MTJ can vary depending on the magnetization direction of the fixed layer 234 and the magnetization direction of the magnetic domains of the magnetic orbital layer 220. For example, when the magnetization direction of the fixed layer 234 and the magnetization direction of the magnetic domains of the magnetic orbital layer 220 are antiparallel, the MTJ can have a high resistance value and can store data "1". When the magnetization direction of the fixed layer 234 and the magnetization direction of the magnetic domains of the magnetic orbital layer 220 are parallel, the MTJ can have a low resistance value and can store data "0".

[0047] On the magnetic track layer 220, the spacing between multiple readout units 230 can have the same or similar values, which will refer to Figure 10D Provide a detailed description.

[0048] Reference Figures 4A to 4CA second interlayer insulating layer 250b may be formed around the plurality of read units 230 on the first interlayer insulating layer 250a and the plurality of magnetic track layers 220. The second interlayer insulating layer 250b may be formed of oxide. However, the embodiments are not limited thereto. The second interlayer insulating layer 250b may cover the side surfaces of the plurality of read units 230 and may expose at least a portion of the upper surface of the plurality of read units 230. In some embodiments, the upper surface of the second interlayer insulating layer 250b may be coplanar with the upper surface of the plurality of read units 230.

[0049] Multiple bit lines 260 can be formed on the second interlayer insulating layer 250b and the multiple read units 230. The multiple bit lines 260 can extend at uniform intervals along a second horizontal direction (Y direction) in a first horizontal direction (X direction). The multiple bit lines 260 can be formed of polycrystalline silicon doped with impurities, metals (e.g., at least one of W, Cu, Al, Ni, Co, Ti, and Ta), metal silicides (e.g., at least one of W silicide, Ni silicide, Co silicide, Ti silicide, and Ta silicide), conductive metal nitrides (e.g., at least one of Ti nitride and Ta nitride), or combinations thereof.

[0050] Multiple bit lines 260 may extend while intersecting at least a portion of multiple magnetic orbital layers 220. In some embodiments, each of the multiple magnetic orbital layers 220 may intersect with multiple bit lines 260. In some embodiments, each bit line 260 may intersect with a different portion of each of the multiple magnetic orbital layers 220.

[0051] Each of the multiple bit lines 260 can contact the upper surface of a different read unit 230 among the multiple read units 230 arranged on each of the multiple magnetic orbital layers 220. That is, the number of bit lines 260 intersecting with each of the multiple magnetic orbital layers 220 can be equal to the number of read units 230 arranged on each of the multiple magnetic orbital layers 220. For example, therefore, each bit line 260 can intersect with only one read unit 230 in each magnetic orbital layer 220.

[0052] Each of the plurality of bit lines 260 may extend to form over the memory region MR and the second connection region CRy. Each of the plurality of bit lines 260 may include a bit line pad unit 260P in the second connection region CRy. In some embodiments, the horizontal width of the bit line pad unit 260P may be greater than, for example, the horizontal width along the X direction of each of the plurality of bit lines 260 in the memory region MR.

[0053] Reference Figures 5A to 5CA third interlayer insulating layer 250c covering multiple bit lines 260 may be formed on the second interlayer insulating layer 250b. The third interlayer insulating layer 250c may cover the upper and side surfaces of the multiple bit lines 260. The third interlayer insulating layer 250c may be formed of, for example, an oxide. In some embodiments, the first interlayer insulating layer 250a, the second interlayer insulating layer 250b, and the third interlayer insulating layer 250c may be formed of the same or similar materials. The first interlayer insulating layer 250a, the second interlayer insulating layer 250b, and the third interlayer insulating layer 250c may be referred to as interlayer insulating layer 250.

[0054] Then, by repeatedly forming an etch stop layer 210, multiple magnetic track layers 220, multiple read cells 230, multiple bit lines 260, and an interlayer insulating layer 250, multiple memory stacks ST1, ST2, ST3, and ST4 are formed stacked in the vertical direction (Z direction). Each of the multiple memory stacks ST1, ST2, ST3, and ST4 can be formed by an etch stop layer 210, multiple magnetic track layers 220 disposed on the etch stop layer 210, multiple read cells 230 contacting the multiple magnetic track layers 220, multiple bit lines 260 contacting the upper surface of the multiple read cells 230, and an interlayer insulating layer 250 covering the multiple magnetic track layers 220, multiple read cells 230, and multiple bit lines 260 located on the etch stop layer 210.

[0055] Multiple storage stacks ST1, ST2, ST3 and ST4 may each include multiple storage strings MS1, MS2, MS3 and MS4, each storage string being formed by multiple magnetic track layers 220 and multiple read units 230.

[0056] Multiple memory strings MS1, MS2, MS3, and MS4, respectively included in multiple memory stacks ST1, ST2, ST3, and ST4, may overlap in the vertical direction (Z direction). In some embodiments, multiple magnetic track layers 220 of each memory stack in multiple memory stacks ST1, ST2, ST3, and ST4 overlap in the vertical direction (Z direction), and at least some of the read units 230 may not overlap. Because the multiple bit lines 260 included in multiple memory stacks ST1, ST2, ST3, and ST4 are arranged according to the arrangement of the multiple read units 230, the multiple bit lines 260 may overlap in the vertical direction (Z direction), and at least some of the bit lines 260 may not overlap.

[0057] exist Figure 5B and Figure 5C The diagram shows four memory stacks, ST1, ST2, ST3, and ST4, stacked together. However, the embodiments are not limited to this; for example, multiples of two or four memory stacks may be stacked.

[0058] Reference Figures 6A to 6C By removing a portion of multiple storage stacks ST1, ST2, ST3, and ST4, the multiple storage stacks ST1, ST2, ST3, and ST4 can form a stepped profile in the first connection region CRx and the second connection region Cry, i.e., including multiple steps. Each of the multiple storage stacks ST1, ST2, ST3, and ST4 can have a first step unit STAx and a second step unit STAy forming a stepped step plate in the first connection region CRx and the second connection region Cry. The first step unit STAx and the second step unit STAy of each of the multiple storage stacks ST1, ST2, ST3, and ST4 can protrude above the upper storage stack in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0059] Therefore, the horizontal length of the etch stop layer 210 of the multiple memory stacks ST1, ST2, ST3, and ST4 in the first horizontal direction (X direction) and the second horizontal direction (Y direction) can vary. The horizontal length of the etch stop layer 210 of the multiple memory stacks ST1, ST2, ST3, and ST4 in the first horizontal direction (X direction) and the second horizontal direction (Y direction) can decrease from the substrate 110 upwards. In addition, the horizontal length of the pad track layer 220P of the multiple memory stacks ST1, ST2, ST3, and ST4 in the first horizontal direction (X direction) can decrease from the substrate 110 upwards, and the horizontal length of the bit line pad cell 260P of the multiple memory stacks ST1, ST2, ST3, and ST4 in the second horizontal direction (Y direction) can also decrease from the substrate 110 upwards.

[0060] For example, the horizontal length of the etch stop layer 210, pad track layer 220P and bit line pad unit 260P of the bottommost memory stack ST1 can be the largest, and the horizontal length of the etch stop layer 210, pad track layer 220P and bit line pad unit 260P of the topmost memory stack ST4 can be the smallest.

[0061] exist Figure 6B and Figure 6CThe diagram shows that the upper surface of each of the first step unit STAx and the second step unit STAy is at the same horizontal level as the lower surface of the etch stop layer 210 thereon. However, the embodiments are not limited to this. In some embodiments, in a process in which multiple memory stacks ST1, ST2, ST3 and ST4 are formed in the first connection region CRx and the second connection region CRy such that the upper surface of each of the first step unit STAx and the second step unit STAy is at a horizontal level lower than the horizontal level of the lower surface of the etch stop layer 210 thereon (i.e., at a horizontal level close to the horizontal level of the substrate 110), a portion of the interlayer insulating layer 250 may be further removed in the second step unit STAy and the second step unit STAy.

[0062] Reference Figures 7A to 7C , can Figures 6A to 6C A filling insulating layer 300 is formed in the portion of the plurality of storage stacks ST1, ST2, ST3, and ST4 shown that has been partially removed. The filling insulating layer 300 may be formed of, for example, oxide. However, the embodiments are not limited thereto. In some embodiments, the interlayer insulating layer 250 and the filling insulating layer 300 may be formed of the same or similar materials.

[0063] Reference Figures 8A to 8C Multiple first contact holes THx are formed in the first peripheral circuit region PRx, exposing a portion of the first source region 112a and a portion of the first drain region 112b. Multiple second contact holes THy are formed in the second peripheral circuit region PRY, exposing a portion of the second source region 114a and a portion of the second drain region 114b. Multiple first connection contact holes CHx are formed in the first connection region CRx, exposing a portion of the pad track layer 220P of the multiple memory stacks ST1, ST2, ST3 and ST4. Multiple second connection contact holes CHy are formed in the second connection region CRy, exposing a portion of the bit line pad layer 260P of the multiple memory stacks ST1, ST2, ST3 and ST4. A common source trench CSH is formed in the memory region MR, exposing the substrate 110.

[0064] Multiple first contact holes THx and multiple second contact holes THY can pass through the filler insulating layer 300 and the base insulating layer 150. Multiple first connection contact holes CHx can pass through the filler insulating layer 300, the third interlayer insulating layer 250c, and the second interlayer insulating layer 250b. Multiple second connection contact holes CHy can pass through the filler insulating layer 300 and the third interlayer insulating layer 250c. A common source trench CSH can pass through multiple memory stacks ST1, ST2, ST3, and ST4 and the base insulating layer 150.

[0065] In some embodiments, a plurality of first contact holes THx, a plurality of second contact holes THY, a plurality of first connecting contact holes CHx, and a plurality of second connecting contact holes CHy can be formed simultaneously by an etching process. An etching process for forming the plurality of first contact holes THx, a plurality of second contact holes THY, a plurality of first connecting contact holes CHx, and a plurality of second connecting contact holes CHy can be performed, such that the etch stop layer 210 is exposed. In other embodiments, a plurality of first contact holes THx and a plurality of second contact holes THY can be formed simultaneously by an etching process, and a plurality of first connecting contact holes CHx and a plurality of second connecting contact holes CHy can be formed simultaneously by another etching process. In other embodiments, a plurality of first contact holes THx and a plurality of second contact holes THY can be formed simultaneously by an etching process, and a plurality of first connecting contact holes CHx and a plurality of second connecting contact holes CHy can be formed by a separate etching process; for example, each group of first connecting contact holes CHx and second connecting contact holes CHy can be formed by a separate etching process.

[0066] In some embodiments, the common source trench (CSH) can be formed by an etching process separate from the etching process that forms a plurality of first contact holes THx, a plurality of second contact holes THy, a plurality of first connection contact holes CHx, and a plurality of second connection contact holes CHy. In other embodiments, the common source trench (CSH) can be formed by an etching process that forms a plurality of first contact holes THx and a plurality of second contact holes THy.

[0067] For example, multiple first contact holes THx, multiple second contact holes THy, multiple first connection contact holes CHx, multiple second connection contact holes CHy, or a common source trench CSH can be formed by performing a high aspect ratio contact (HARC) etching process.

[0068] In some embodiments, such as Figure 9E As shown, a portion of the pad track layer 220P and a portion of the etch stop layer 210 may be exposed on the bottom surface of each of the plurality of first connection contact holes CHx. In other embodiments, only a portion of the pad track layer 220P may be exposed, and a portion of the etch stop layer 210 may not be exposed on the bottom surface of each of the plurality of first connection contact holes CHx.

[0069] Only a portion of the bit line pad unit 260P can be exposed on the bottom surface of each of the multiple second connection contact holes CHy.

[0070] A portion of the upper surface of substrate 110 may be exposed to the bottom surface of the common source trench (CSH). For example... Figure 9DAs shown, multiple magnetic orbital layers 220 can be exposed to the inner wall of the common source trench CSH. That is, the second end of the multiple magnetic orbital layers 220 or the portion adjacent to the second end (e.g., the end of the multiple magnetic orbital layers 220 located in the memory cell region MR or the portion adjacent to the end) can be exposed to (e.g., in direct contact with) the inner wall of the common source trench CSH.

[0071] In some embodiments, the plurality of first contact holes THx, the plurality of second contact holes THY, the plurality of first connecting contact holes CHx, and the plurality of second connecting contact holes CHy may have a circular or elliptical horizontal cross-section, for example, as shown in the top view ( Figure 9A As observed in [reference needed]. In some embodiments, the common source trench (CSH) in the storage region MR may have a strip-shaped horizontal cross-section extending in the second horizontal direction (Y direction) or a rectangular horizontal cross-section having a major axis in the second horizontal direction (Y direction), such as [reference needed]. Figure 9A As shown.

[0072] Reference Figures 9A to 9D It can form multiple first contact plugs TCx that fill multiple first contact holes THx, multiple second contact plugs TCy that fill multiple second contact holes THy, multiple first connection contact plugs MCx that fill multiple first connection contact holes CHx, multiple second connection contact plugs MCy that fill multiple second connection contact holes CHy, and a common source line CSL that fills a common source trench CSH.

[0073] The plurality of first contact plugs TCx, the plurality of second contact plugs TCy, the plurality of first connecting contact plugs MCx, the plurality of second connecting contact plugs MCy, and the common source line CSL can be formed of a conductive material. For example, the plurality of first contact plugs TCx, the plurality of second contact plugs TCy, the plurality of first connecting contact plugs MCx, the plurality of second connecting contact plugs MCy, and the common source line CSL can be formed of a metal, a conductive metal nitride, a transition metal, or a combination of the above metals. A conductive material covering multiple memory stacks ST1, ST2, ST3, and ST4 and a filling insulating layer 300 can be formed by filling multiple first contact holes THx, multiple second contact holes THY, multiple first connection contact holes CHx, multiple second connection contact holes CHy, and a common source trench CSH. Then, the portion of the conductive material covering the upper surface of the filling insulating layer 300 and the upper surface of the third interlayer insulating layer 250c of the uppermost memory stack ST4 is removed to form multiple first contact plugs TCx, multiple second contact plugs TCy, multiple first connection contact plugs MCx, multiple second connection contact plugs MCy, and a common source line CSL.

[0074] Multiple first contact plugs TCx, multiple second contact plugs TCy, multiple first connecting contact plugs MCx, multiple second connecting contact plugs MCy, and the common source line CSL can be formed of the same conductive material.

[0075] Multiple first contact plugs TCx can be electrically connected to the first source region 112a and the first drain region 112b of multiple first driving elements TR1, and multiple second contact plugs TCy can be electrically connected to the second source region 114a and the second drain region 114b of multiple second driving elements TR2. Multiple first connecting contact plugs MCx and a common source line CSL can be electrically connected to the first end and the second end of each of the multiple magnetic track layers 220, respectively. The common source line CSL can be electrically connected to the multiple magnetic track layers 220, and each of the multiple first connecting contact plugs MCx can be electrically connected to each of the multiple magnetic track layers 220. Each of the multiple first connecting contact plugs MCx and the common source line CSL can be located at both ends (i.e., the first end and the second end) in a first horizontal direction (X direction), and each of the multiple magnetic track layers 220 is located between the multiple first connecting contact plugs MCx and the common source line CSL. Multiple second connection contact plugs MCy can be connected to multiple bit line pad units 260P and can be electrically connected to multiple bit lines 260.

[0076] In some embodiments, the metal silicide layer for reducing contact resistance may be located between the first contact plug TCx and the first source region 112a, between the first contact plug TCx and the first drain region 112b, between the second contact plug TCy and the second source region 114a, between the second contact plug TCy and the second drain region 114b, and between the common source line CSL and the substrate 110.

[0077] Reference Figure 9E The first connecting contact plug MCx can be connected to the portion of the pad track layer 220P adjacent to the first end of the magnetic track layer 220. In some embodiments, such as in the second horizontal direction (Y direction), the horizontal width of the first connecting contact plug MCx can be greater than the horizontal width of the pad track layer 220P. Here, the horizontal width of the pad track layer 220P refers to the direction along which the magnetic track layer 220 extends ( Figure 9D The first horizontal direction (X direction) and the vertical direction ( Figure 9D The width in the second horizontal direction (Y direction).

[0078] The first connection contact plug MCx may surround a portion of the upper surface and a portion of the side surface of the pad track layer 220P. The lower surface of the first connection contact plug MCx may contact the pad track layer 220P and the etch stop layer 210, and the lowest surface of the first connection contact plug MCx may contact the etch stop layer 210.

[0079] Figures 10A to 10C This shows a top view and a cross-sectional view of a storage device according to an embodiment, and Figure 10D This is a cross-sectional view showing the memory string of the storage device. Figure 10B and Figure 10C They are respectively along Figure 10A Cross-sectional views of lines B-B' and C-C'.

[0080] Reference Figures 10A to 10C After forming a cover insulating layer 350 on multiple storage stacks ST1, ST2, ST3, and ST4 and a fill insulating layer 300, multiple vias VH can be formed that penetrate the cover insulating layer 350 and expose multiple first contact plugs TCx, multiple second contact plugs TCy, multiple first connection contact plugs MCx, multiple second connection contact plugs MCy, and at least a portion of the upper surface of the common source line CSL, as well as multiple via plugs VP filling the multiple vias VH. The cover insulating layer 350 can be formed, for example, of an oxide.

[0081] Multiple access plugs VP can be formed of a conductive material. For example, multiple access plugs VP can be formed of a metal, a conductive metal nitride, a transition metal, or a combination of the above metals. Each access plug in the multiple access plugs VP can be connected to at least one of multiple first contact plugs TCx, multiple second contact plugs TCy, multiple first connecting contact plugs MCx, multiple second connecting contact plugs MCy, and a common source line CSL.

[0082] The storage device 1 can be formed by arranging a first wiring ML1, a second wiring ML2, a third wiring ML3, a fourth wiring ML4, and a fifth wiring ML5 connected to at least one of a plurality of channel plugs VP on a covering insulating layer 350. In the first wiring ML1, the second wiring ML2, the third wiring ML3, the fourth wiring ML4, and the fifth wiring ML5, the first wiring ML1 electrically connects the first contact plug TCx connected to the first drain region 112b to the first connecting contact plug MCx; the second wiring ML2 electrically connects the second contact plug TCy connected to the second drain region 114b to the second connecting contact plug MCy; the third wiring ML3 electrically connects to the first contact plug TCx connected to the first source region 112a; the fourth wiring ML4 electrically connects to the second contact plug TCy connected to the second source region 114a; and the fifth wiring ML5 electrically connects to the common source line CSL.

[0083] Reference Figure 10D The storage string MS may include a magnetic track layer 220 and multiple read units 230. Figure 10D The storage string MS shown can be Figure 10B and Figure 10C One of the multiple storage strings MS1, MS2, MS3 and MS4 shown, and cut along the extension direction of the magnetic track layer 220.

[0084] Multiple magnetic domains (MDs) can be formed in the magnetic orbital layer 220, and domain walls (MDWs) can be located between two adjacent magnetic domains (MDs). In the multiple magnetic domains (MDs), the magnetic moments of electrons can be in the same direction. Domain walls (MDWs) are the boundaries between magnetic domains that can have different magnetization directions, and can be moved by a current or magnetic field applied to the magnetic orbital layer 220.

[0085] Reference Figures 10A to 10D A first contact plug TCx is connected to a pad track layer 220P adjacent to one end of the magnetic track layer 220, and a first drive element TR1 connected to the first contact plug MCx can provide a predetermined magnetic moment direction for each of the plurality of magnetic domains MD, such that data "0" or "1" can be stored in each of the plurality of magnetic domains MD. The first drive element TR1 can be part of a domain wall transport. The domain wall transport can include a power supply, and the domain wall transport can apply a pulsed current to the magnetic track layer 220 through the first drive element TR1. Through the domain wall transport, the domain wall MDW between every two magnetic domains in the plurality of magnetic domains MD can move in a predetermined direction. Due to the movement of the domain wall MDW, the magnetic domain MD passes through the read unit 130, thereby allowing data to be read.

[0086] A pulsed current is sequentially applied to a plurality of magnetic domains MD via a first connecting contact plug MCx electrically connected to the first driving element TRl, such that each of the plurality of magnetic domains MD can have a predetermined magnetic moment direction or magnetization direction. Additionally, the pulsed current is transmitted from the domain wall to the magnetic track layer 220 via the first connecting contact plug MCx, allowing the domain wall MDW to move. In other embodiments, in addition to the first connecting contact plug MCx, the domain wall transmission may also be connected to the magnetic track layer 220.

[0087] The read unit 230 can read data by the magnetic moment direction of each of the multiple magnetic domains MD. The read unit 230 can be a device utilizing the tunneling magnetoresistance (TMR) effect or the giant magnetoresistance (GMR) effect. The read unit 230 can be electrically connected to the second drive element TR2 via the bit line 260.

[0088] exist Figure 10C In this example, the second driving element TR2 is shown as a transistor. However, compared with... Figure 10C Unlike other components, the second driving element TR2 may include a diode or an OTS element.

[0089] Among the plurality of read units 230 arranged on the magnetic track layer 220, the read unit arrangement intervals S1, S2, ... which serve as the intervals between adjacent read units 230 in the direction of extension of the magnetic track layer 220, can have the same or similar values. That is, the number of magnetic domains MD between two adjacent read units 230 in the direction of extension of the magnetic track layer 220 can have the same or similar values.

[0090] In some embodiments, the first distance D1 between read units 230 adjacent to the first connecting contact plug MCx and the second distance D2 between read units 230 adjacent to the common source line CSL in the direction in which the magnetic track layer 220 extends can have a value equal to half of the read unit arrangement intervals S1, S2, ... or greater than half of the read unit arrangement intervals S1, S2, ... In this case, the domain walls MDW located between the plurality of magnetic domains MD can move bidirectionally in the direction in which the magnetic track layer 220 extends.

[0091] In some embodiments, the first distance D1 between read units 230 adjacent to the first connecting contact plug MCx and the second distance D2 between read units 230 adjacent to the common source line CSL in the direction in which the magnetic track layer 220 extends can have a value equal to or greater than the read unit arrangement intervals S1, S2, ... In this case, the domain walls MDW located between the plurality of magnetic domains MD can move unidirectionally in the direction in which the magnetic track layer 220 extends.

[0092] According to an embodiment, the storage device 1 may be a track storage device comprising a plurality of magnetic track layers 220. Each of the plurality of magnetic track layers 220 of the storage device 1 extends two-dimensionally and may have a folded structure in which each of the plurality of magnetic track layers 220 is at least two fluffy shapes, for example, folded sequentially into a plurality of U-shapes aligned and connected to each other. The plurality of magnetic track layers 220 of the storage device 1 may be arranged on the same plane or may overlap in the vertical direction (Z direction).

[0093] Because the storage device 1 according to the embodiment includes multiple storage stacks ST1, ST2, ST3 and ST4 having multiple storage strings MS1, MS2, MS3 and MS4 formed by multiple magnetic track layers 220 and multiple read units 230, the storage device 1 can be a three-dimensional storage device capable of storing data in three dimensions.

[0094] In the storage device 1 according to an embodiment, since steps are formed in each of the multiple storage stacks ST1, ST2, ST3, and ST4 in the first connection region CRx and the second connection region Cry, multiple first connection contact plugs MCx connected to the multiple magnetic track layers 220 of each of the multiple storage stacks ST1, ST2, ST3, and ST4, and multiple second connection contact plugs MCy connected to the multiple bit lines 260 of each of the multiple storage stacks ST1, ST2, ST3, and ST4, can be formed by photomask and etching processes. In some embodiments, multiple first contact plugs TCx connected to the first driving element TR1, multiple second contact plugs TCy connected to the second driving element TR2, multiple first connection contact plugs MCx connected to the multiple magnetic track layers 220, and multiple second connection contact plugs MCy connected to the multiple bit lines 260 can be formed by photomask and etching processes. Therefore, the manufacturing time and cost of the storage device 1 can be reduced. Furthermore, in the storage device 1 according to the embodiment, since the magnetic track layer 220 is arranged on the etch stop layer 210, the batch production rate of the process for forming a track storage device including multiple magnetic track layers 220 can be improved.

[0095] The magnetic track layer 220 of the storage device 1 according to the embodiment may have a two-dimensional, fluffy, folded structure. Therefore, the pitch of the multiple bit lines 260 connected to the multiple read units 230 arranged at equal or similar intervals can be freely controlled in the direction in which the magnetic track layer 220 extends. Thus, the process margin for forming the multiple bit lines 260 can be increased.

[0096] Because the storage device 1 according to the embodiment can have at least two fluffy folded structures in two dimensions, the first connecting contact plugs MCx and the common source line CSL connected to both ends of the magnetic track layer 220 can be arranged on opposite sides in the storage region MR. Therefore, because the wiring structure for driving the storage device 1 can be freely arranged, the storage device 1 can efficiently store large amounts of data.

[0097] Figures 11A to 11C This is a top view illustrating a method of manufacturing a storage device according to an embodiment. Previous references will not be repeated. Figures 10A to 10D Given Figures 11A to 11C The description.

[0098] Reference Figure 11A Multiple magnetic track layers 220a can be formed on the etch stop layer 210. In some embodiments, each of the multiple magnetic track layers 220a can be formed over the storage region MR and the first connection region CRx. In some embodiments, each of the multiple magnetic track layers 220a can extend with a uniform horizontal width. In the storage region MR, each of the multiple magnetic track layers 220a can have a folded structure in which each of the multiple magnetic track layers 220a is two-dimensional fluffy. In the storage region MR, each of the multiple magnetic track layers 220a can include an extended track layer 220La and a connection track layer 220Ua connected to the extended track layer 220La. In the first connection region CRx, each of the multiple magnetic track layers 220a can include a pad track layer 220Pa extending from the extended track layer 220La. In some embodiments, the pad track layer 220Pa can extend in a first horizontal direction (X direction), and the extended track layer 220La can extend in a second horizontal direction (Y direction).

[0099] The two extended track layers 220La and the connecting track layer 220Ua connecting the two extended track layers 220La can be U-shaped in two dimensions. In some embodiments, in the storage region MR, each of the plurality of magnetic track layers 220a can have a folded structure in which each of the plurality of magnetic track layers 220a is at least two-pile-like to include the plurality of extended track layers 220La and at least two connecting track layers 220Ua connecting the plurality of extended track layers 220La, for example, to have a structure having at least two U-shapes that are adjacent to each other (e.g., along the X direction) and connected to each other on one side. Each of the plurality of magnetic track layers 220a can extend from a first end at the first connecting region CRx to a second end in the storage region MR located in the first horizontal direction (X direction) opposite to the first connecting region CRx.

[0100] exist Figure 2A In the magnetic track layer 220 shown, each fluffy protrusion can be provided in the first horizontal direction (X direction) or in the opposite direction to the first horizontal direction (X direction), i.e., connecting the track layer 220U. However, in Figure 11A In the magnetic track layer 220a shown, each fluffy protrusion can be provided in the second horizontal direction (Y direction) or in the opposite direction to the second horizontal direction (Y direction), i.e., connecting track layers 220a. Therefore, each of the plurality of magnetic track layers 220a can extend from the first end to the second end through a folded structure in which each of the plurality of magnetic track layers 220a is an integer of at least two fluffy protrusions. Because, apart from the extended shape, the magnetic track layer 220a and... Figures 2A to 2C The magnetic orbital layer 220 shown is almost identical, so its detailed description will not be repeated.

[0101] Reference Figure 11B A first interlayer insulating layer 250a may be formed on the etch stop layer 210 surrounding the plurality of magnetic orbital layers 220a. The first interlayer insulating layer 250a may be formed of, for example, oxide. The first interlayer insulating layer 250a may cover the side surfaces of the plurality of magnetic orbital layers 220a and may expose at least a portion of the upper surfaces of the plurality of magnetic orbital layers 220a. In some embodiments, the upper surface of the first interlayer insulating layer 250a may be coplanar with the upper surfaces of the plurality of magnetic orbital layers 220a.

[0102] On the upper surface of each of the plurality of magnetic track layers 220a, a plurality of read units 230 may be arranged. The plurality of read units 230 may be arranged in the storage region MR on a portion of each of the plurality of magnetic track layers 220a, and may not be arranged in the first connection region CRx on a portion of each of the plurality of magnetic track layers 220a (i.e., pad track layer 220P). In some embodiments, the plurality of read units 230 may be arranged on the connection track layer 220Ua, and may not be arranged on the extension track layer 220La.

[0103] exist Figure 11B In this embodiment, multiple reading units 230 are shown arranged only on the connecting track layer 220Ua located in the opposite direction of the second horizontal direction (Y direction) among the multiple connecting track layers 220Ua. However, the embodiment is not limited to this. In some embodiments, the multiple reading units 230 may be arranged only on the connecting track layer 220Ua located in the second horizontal direction (Y direction) among the multiple connecting track layers 220Ua. In other embodiments, some of the multiple reading units 230 may be arranged on the connecting track layer 220Ua located in the second horizontal direction (Y direction), and other reading units of the multiple reading units 230 may be arranged on the connecting track layer 220Ua located in the opposite direction of the second horizontal direction (Y direction).

[0104] Each of the plurality of read units 230 may, for example, have a width greater than the horizontal width of the magnetic track layer 220a in the Y direction. In some embodiments, each of the plurality of read units 230 may be formed on a portion of the upper surface of the magnetic track layer 220a and a portion of the upper surface of the first interlayer insulating layer 250a. The magnetic track layer 220a may be arranged to contact the read unit 230, and a magnetic domain that is a portion of the free layer included in the magnetic track layer 220a that perpendicularly overlaps with the read unit 230 may form a magnetic tunnel junction (MTJ) together with the read unit 230.

[0105] Reference Figure 11C A second interlayer insulating layer 250b may be formed around the plurality of read units 230 on the first interlayer insulating layer 250a and the plurality of magnetic track layers 220a. The second interlayer insulating layer 250b may cover the side surfaces of the plurality of read units 230 and may expose at least a portion of the upper surface of the plurality of read units 230. In some embodiments, the upper surface of the second interlayer insulating layer 250b may be coplanar with the upper surface of the plurality of read units 230.

[0106] Multiple bit lines 260a can be formed on the second interlayer insulating layer 250b and the multiple read units 230. The multiple bit lines 260a can extend at uniform intervals in the first horizontal direction (X direction) along the second horizontal direction (Y direction).

[0107] Each bit line in the plurality of bit lines 260a can contact the upper surface of a different read unit 230 among the plurality of read units 230 arranged on each of the plurality of magnetic orbital layers 220a. That is, the number of bit lines 260a intersecting with each of the plurality of magnetic orbital layers 220a can be equal to the number of read units 230 arranged on each of the plurality of magnetic orbital layers 220a.

[0108] Each of the plurality of bit lines 260a may extend to form above the memory region MR and the second connection region CRy. Each of the plurality of bit lines 260a may include a bit line pad unit 260Pa in the second connection region CRy. In some embodiments, the horizontal width of the bit line pad unit 260Pa may be greater than the horizontal width of each of the plurality of bit lines 260a in the memory region MR.

[0109] Then, it can be done by... Figures 5A to 10D The method described herein is similar to the method used to form a storage device. It can be formed by referring to... Figures 11A to 11C The storage device formed by the described method is such that the spacing between the plurality of read units 230 is uniform, and because each of the plurality of read units 230 is arranged on the connecting track layer 220Ua of the magnetic track layer 220a, reference is made to... Figures 5A to 5C The described multiple bit lines 260 can have uniform spacing in a first horizontal direction (X direction) on a magnetic orbital layer 220a.

[0110] Figures 12A to 12C This is a cross-sectional view showing a portion of the storage string of a storage device according to an embodiment.

[0111] Reference Figure 12A The storage string MS may include a magnetic track layer 220 and multiple read units 230. The storage string MS may be... Figure 10B and Figure 10C One of the multiple storage strings MS1, MS2, MS3, and MS4 shown, for example, storage string MS could be... Figure 10D The amplified portion of the storage string MS in the memory. In detail, as... Figure 12AAs shown, the magnetic track layer 220 can extend with a uniform horizontal width. Multiple readout units 230 can be arranged on the upper surface of the magnetic track layer 220. Each readout unit 230 may include a tunnel barrier layer 232 and a fixing layer 234 formed on the magnetic track layer 220. Bit lines 260 can be formed on the readout units 230. The readout units 230 can be located between the magnetic track layer 220 and the bit lines 260.

[0112] The magnetic track layer 220 can extend in a folded structure, in which, as Figure 2A The magnetic orbital layer 220 shown or Figure 11A Similar to the magnetic orbital layer 220a shown, the magnetic orbital layer 220 is at least two fluffy structures in two dimensions. The bit line 260 may extend in one direction.

[0113] The tunnel barrier layer 232 and the fixing layer 234 forming the reading unit 230 can be as follows: Figure 3A or Figure 11B The embodiment is shown as a two-dimensional rectangle. However, the embodiment is not limited to this; for example, the tunnel barrier layer 232 and the fixing layer 234 may be circular or polygonal in two dimensions.

[0114] Reference Figure 12B The storage string MSa may include a magnetic track layer 220 and a read unit 230a. The storage string MSa may be... Figure 10B and Figure 10C One of the multiple memory strings MS1, MS2, MS3, and MS4 shown. Read unit 230a may include a tunnel barrier layer 232a and a fixing layer 234a formed on the magnetic track layer 220. Bit line 260 may be formed on read unit 230a. Read unit 230a may be located between the magnetic track layer 220 and bit line 260.

[0115] like Figure 12A Similar to the fixed layer 234 shown, the fixed layer 234a can be circular, rectangular, or polygonal in two dimensions. The tunnel barrier layer 232a can extend while covering the upper surface of the magnetic track layer 220. That is, the two-dimensional shape of the tunnel barrier layer 232a can be similar to the two-dimensional shape of the magnetic track layer 220. That is, the tunnel barrier layer 232a can extend in a manner in which the tunnel barrier layer 232a is at least two fluffy folded structures in two dimensions. That is, the plurality of readout units 230a can include a plurality of fixed layers 234a arranged on the magnetic track layer 220 and spaced apart from each other, as well as the portion of the tunnel barrier layer 232a located between the magnetic track layer 220 and the plurality of fixed layers 234a.

[0116] Reference Figure 12C The storage string (MSb) may include a magnetic track layer 220 and a read unit 230b. The storage string (MSb) may be... Figure 10Band Figure 10C One of the multiple memory strings MS1, MS2, MS3, and MS4 shown. Read unit 230b may include a tunnel barrier layer 232b, a polarization enhancement layer 234E, and a fixing layer 234b formed on the magnetic track layer 220. Bit line 260 may be formed on read unit 230b. Read unit 230b may be located between magnetic track layer 220 and bit line 260.

[0117] The planar shapes of the tunnel barrier layer 232b and the fixed layer 234b can be consistent with... Figure 12B The tunnel barrier layer 232a and the fixed layer 234a shown have nearly identical planar shapes. The polarization enhancement layer 234E can extend while covering the upper surface of the tunnel barrier layer 232b. That is, the planar shape of the polarization enhancement layer 234E can be nearly identical to the planar shapes of the magnetic orbital layer 220 and the tunnel barrier layer 232b. The fixed layer 234b can be disposed on a portion of the upper surface of the polarization enhancement layer 234E. The polarization enhancement layer 234E can be formed of the same or similar material as the fixed layer 234b. The polarization enhancement layer 234E can increase the tunneling magnetoresistance effect in the MTJ formed in the memory string MSb.

[0118] Figure 13A and Figure 13B This is a cross-sectional view illustrating a method for manufacturing a storage device according to an embodiment.

[0119] Reference Figure 13A and Figure 13B The bottommost storage stack ST1a may include multiple bit lines 262 extending at uniform intervals in a first horizontal direction (X direction) along a second horizontal direction (Y direction), a first interlayer insulating layer 252a surrounding the multiple bit lines 262, multiple read cells 240 disposed on the multiple bit lines 262, an etch stop layer 212 surrounding the multiple read cells 240 while covering the upper surface of the first interlayer insulating layer 252a and the upper surface of the multiple bit lines 262, multiple magnetic track layers 222 disposed on the etch stop layer 212 and contacting the upper surface of the multiple read cells 240, and a second interlayer insulating layer 252b covering the multiple magnetic track layers 222 on the etch stop layer 212.

[0120] A memory stack ST1 (see reference) is arranged from bottom to top with multiple magnetic track layers 220, multiple read units 230, and multiple bit lines 260. Figures 1A to 10D The description is different; in storage stack ST1a, such as... Figure 13A and Figure 13BAs shown, multiple magnetic track layers 222, multiple read units 240, and multiple bit lines 262 can be arranged from top to bottom, i.e., in the reverse order of the order in the memory stack ST1. The multiple magnetic track layers 222, multiple read units 240, and multiple bit lines 262 can be formed of the same or similar materials as the multiple magnetic track layers 220, multiple read units 230, and multiple bit lines 260, respectively. The planar shape of the multiple magnetic track layers 222, multiple read units 240, and multiple bit lines 262 (e.g., in a cross-sectional view) can be nearly identical to the planar shape of the multiple magnetic track layers 220, multiple read units 230, and multiple bit lines 260.

[0121] The first interlayer insulating layer 252a and the second interlayer insulating layer 252b may be formed of oxide. However, the embodiments are not limited thereto. The first interlayer insulating layer 252a may cover the side surfaces of the plurality of bit lines 262 and may expose at least a portion of the upper surfaces of the plurality of bit lines 262. In some embodiments, the upper surface of the first interlayer insulating layer 252a and the upper surfaces of the plurality of bit lines 262 may be coplanar. The second interlayer insulating layer 252b may cover the upper surfaces and side surfaces of the plurality of magnetic track layers 222. The first interlayer insulating layer 252a and the second interlayer insulating layer 252b may be referred to as interlayer insulating layer 252.

[0122] The bottommost storage stack ST1a can have a storage string MSR1 formed by multiple magnetic track layers 222 and multiple read units 240.

[0123] In some embodiments, the etch stop layer 212 may be formed of, for example, silicon nitride or aluminum oxide. The etch stop layer 212 may cover the side surfaces of the plurality of read units 240. In some embodiments, the upper surface of the etch stop layer 212 may be coplanar with the upper surfaces of the plurality of read units 240. The read unit 240 may include a fixing layer 244 and a tunnel barrier layer 242.

[0124] Then, it can be done by referring to... Figures 5A to 10D The method described is similar to the method used to form a storage device. (See reference...) Figures 1A to 10D The storage device 1 described has multiple magnetic track layers 220, multiple read units 230, and multiple bit lines 260 arranged differently from bottom to top in multiple storage stacks ST1, ST2, ST3, and ST4, as described by reference. Figure 13A and Figure 13BIn the memory device formed by the described method, among multiple memory stacks, similar to the bottommost memory stack ST1a, multiple magnetic track layers 222, multiple read cells 240, and multiple bit lines 262 can be arranged from top to bottom. The multiple magnetic track layers 222, multiple read cells 240, and multiple bit lines 262 can be formed of the same or similar materials as the multiple magnetic track layers 220, multiple read cells 230, and multiple bit lines 260, respectively. The planar shapes of the multiple magnetic track layers 222, multiple read cells 240, and multiple bit lines 262 can be substantially the same as the planar shapes of the multiple magnetic track layers 220, multiple read cells 230, and multiple bit lines 260, respectively.

[0125] Figures 14A to 14C This is a cross-sectional view showing a portion of the storage string of a storage device according to an embodiment.

[0126] Reference Figure 14A The memory string (MSR) can be formed by a magnetic track layer 222 and a read unit 240. The memory string (MSR) can be... Figures 13A to 13B The storage string MSR1 shown, or through... Figure 13A and Figure 13B This is one of a plurality of memory strings formed by the method described herein. Magnetic track layer 222 may extend with a uniform horizontal width. Read unit 240 may be disposed on the lower surface of magnetic track layer 222. Read unit 240 may include a tunnel barrier layer 242 and a fixing layer 244 formed on the lower surface of magnetic track layer 222. Bit line 262 may be formed below read unit 240. Read unit 240 may be located between magnetic track layer 222 and bit line 262.

[0127] The magnetic track layer 222 can extend in a folded structure, in which, as Figure 2A The magnetic orbital layer 220 shown or as Figure 11A Similar to the magnetic orbital layer 220a shown, the magnetic orbital layer 222 is at least two fluffy structures in two dimensions. The bit line 262 may extend in one direction.

[0128] The tunnel barrier layer 242 and the fixing layer 244 forming the reading unit 240 can be as follows: Figure 3A or Figure 11B The two-dimensional rectangle shown is an example. However, the embodiments are not limited to this. In some embodiments, the tunnel barrier layer 242 and the fixing layer 244 may be circular or polygonal in two dimensions.

[0129] Reference Figure 14B The storage string MSRa can be formed by a magnetic track layer 222 and a read unit 240a. The storage string MSRa can be... Figure 13A and Figure 13B The storage string MSR1 shown, or through... Figure 13A and Figure 13B This is one of a plurality of memory strings formed by the method described herein. The read unit 240a may include a tunnel barrier layer 242a and a fixing layer 244a formed on the lower surface of the magnetic track layer 222. A bit line 262 may be formed below the read unit 240a. The read unit 240a may be located between the magnetic track layer 222 and the bit line 262.

[0130] and Figure 14A Similar to the fixed layer 234 shown, the fixed layer 244a can be circular, rectangular, or polygonal in two dimensions. The tunnel barrier layer 242a can extend while covering the lower surface of the magnetic track layer 222. That is, the planar shape of the tunnel barrier layer 242a can be similar to the planar shape of the magnetic track layer 222. That is, the tunnel barrier layer 242a can extend in a two-dimensional manner as at least two fluffy folded structures. That is, the reading unit 240a can be formed by a plurality of fixed layers 244a arranged on the magnetic track layer 222 at intervals from each other and the portion of the tunnel barrier layer 242a located between the magnetic track layer 222 and the plurality of fixed layers 244a.

[0131] Reference Figure 14C The memory string MSRb can be formed by magnetic track layer 222 and read unit 240b. The memory string MSRb can be... Figure 13A and Figure 13B The storage string MSR1 shown, or through... Figure 13A and Figure 13B This is one of a plurality of memory strings formed by the method described herein. The read unit 240b may include a tunnel barrier layer 242b, a polarization enhancement layer 244E, and a fixing layer 244b formed on the magnetic track layer 222. A bit line 262 may be formed on the read unit 240b. The read unit 240b may be located between the magnetic track layer 222 and the bit line 262.

[0132] The planar shapes of the tunnel barrier layer 242b and the fixed layer 244b can be consistent with... Figure 14B The tunnel barrier layer 242a and the fixed layer 244a shown have nearly identical planar shapes. The polarization enhancement layer 244E can extend while covering the lower surface of the tunnel barrier layer 242b. That is, the planar shape of the polarization enhancement layer 244E can be nearly identical to the planar shapes of the magnetic orbital layer 222 and the tunnel barrier layer 242b. The fixed layer 244b can be disposed on a portion of the lower surface of the polarization enhancement layer 244E. The polarization enhancement layer 244E can be formed of the same or similar material as the fixed layer 244b. The polarization enhancement layer 244E can increase the tunneling magnetoresistance effect in the MTJ formed in the memory string MSRb.

[0133] Figure 15 This is a cross-sectional view showing a storage device according to an embodiment.

[0134] Reference Figure 15 The storage device 2 may include a substrate 110, a base insulating layer 150 located on the substrate 110, and a plurality of storage stacks ST1, ST2, ST3, and ST4 stacked on the base insulating layer 150 in a vertical direction (Z direction). The plurality of storage stacks ST1, ST2, ST3, and ST4 of the storage device 2 may not form steps in the first connection region CRx. In some embodiments, the plurality of storage stacks ST1, ST2, ST3, and ST4 of the storage device 2 may form steps in the second connection region CRy, such as... Figure 10C As shown in storage device 1. In other embodiments, the plurality of storage stacks ST1, ST2, ST3 and ST4 of storage device 2 may not form steps in the second connection region CRy.

[0135] Multiple first driving elements TR1a can be formed on substrate 110. At least some of the multiple first driving elements TR1a can be located beneath multiple memory stacks ST1, ST2, ST3, and ST4. Figure 10A and Figure 10B Compared to the multiple first driving elements TR1 (which are arranged in the first peripheral circuit region PRx, which is a portion of the substrate excluding the storage region MR and the first connection region CRx), Figure 15 Multiple first driving elements TR1a can be arranged in the storage region MR or above the storage region MR and the second connection region CRy.

[0136] Storage device 2 may have multiple second drive elements TR2 arranged in the second peripheral circuit region PRY, such as Figure 10A and Figure 10C As shown. However, the storage device 2 may have multiple second driving elements arranged in the storage region MR as multiple first driving elements TR1a, or arranged above the storage region MR and the second connection region CRy.

[0137] The storage device 2 may include a first connection contact plug MCxa disposed in a first connection region CRx and connected to the lower surface of the pad track layer 220P. The first connection contact plug MCxa can be connected to one of a plurality of first drive elements TR1a via an etch stop layer 210 and a base insulating layer 150. A first contact plug MCxa can electrically connect one of the plurality of first drive elements TR1a through at least a portion of the base insulating layer 150 to a third wiring ML3a. The third wiring ML3a is shown disposed in the middle portion of the base insulating layer 150 in the vertical direction (Z direction). However, the embodiment is not limited thereto. For example, the third wiring ML3a may be disposed on the upper surface of the base insulating layer 150. In other embodiments, the storage device 2 may not include the first contact plug MCxa, and the third wiring ML3a may extend along the upper surface of the substrate 110. The remaining first drive elements among the plurality of first drive elements TR1a may have a third wiring ML3a and / or a first electrical path EP1 similar to the first contact plug TCxa and a second electrical path EP2 similar to the first connecting contact plug MCxa.

[0138] Figure 16 This is a cross-sectional view showing a storage device according to an embodiment.

[0139] Reference Figure 16 The storage device 3 may include a substrate 110, a base insulating layer 150 on the substrate 110, and a plurality of storage stacks ST1, ST2, ST3, and ST4 stacked on the base insulating layer 150 in a vertical direction (Z direction). The plurality of storage stacks ST1, ST2, ST3, and ST4 of the storage device 3 may form steps in a first connection region CRx. The storage device 3 also includes a bonding insulating layer 355 on the plurality of storage stacks ST1, ST2, ST3, and ST4, and a bonding substrate 510 bonded to the bonding insulating layer 355. A plurality of first driving elements TR1b may be formed on the bonding substrate 510. Each of the plurality of first driving elements TR1b may include a first gate insulating layer 522 formed on the bonding substrate 510, a first gate electrode 532 covering the upper surface of the first gate insulating layer 522, and a first source region 512a and a first drain region 512b formed on the bonding substrate 510, wherein the first gate electrode 532 is located between the first source region 512a and the first drain region 512b. The bonding insulating layer 355 may cover the plurality of first driving elements TR1b on the bonding substrate 510.

[0140] Storage device 3 may have multiple second drive elements TR2 arranged in the second peripheral circuit region PRY, such as Figure 10A and Figure 10CAs shown. However, the storage device 3 may have multiple second driving elements formed on the bonding substrate 510, such as multiple first driving elements TR1b.

[0141] Storage device 3 may include a first connection contact plug MCx, which is disposed in a first connection region CRx and connected to the upper surface of pad track layer 220P. A first wiring ML1b, a third wiring ML3b, and a fifth wiring ML5b may be disposed on a filling insulating layer 300 and multiple storage stacks ST1, ST2, ST3, and ST4. The first wiring ML1b may be connected to the connection contact plug MCx. The fifth wiring ML5b may be connected to a common source line CSL.

[0142] Multiple vias VHb can penetrate the bonding insulating layer 355 to expose at least a portion of the upper surfaces of the first wiring ML1b and the third wiring ML3b to the bottom surfaces of the multiple vias VHb, and multiple plugs VPb can fill the multiple vias VHb. Some of the plugs VPb can electrically connect the first drain region 512b to the first wiring ML1b, and other plugs VPb can electrically connect the first source region 512a to the third wiring ML3b.

[0143] The third wiring ML3b can be connected to one of the multiple first drive elements TR1b via one of the multiple path plugs VPb. The first connection contact plug MCx can be connected to one of the multiple first drive elements TR1b via the first wiring ML1b and one of the multiple path plugs VPb.

[0144] The remaining first drive elements among the plurality of first drive elements TR1b may have a third wiring ML3b and a first electrical path EP1a similar to the access plug VPb, as well as a first wiring ML1b connected to the first connection contact plug MCxa and a second electrical path EP2a similar to the access plug VPb.

[0145] The storage device 3 can be formed by forming a plurality of first driving elements TR1b on a bonding substrate 510 and then bonding the bonding substrate 510 to a substrate 110 on which a plurality of storage stacks ST1, ST2, ST3 and ST4 are formed. In some embodiments, the bonding substrate 510 can be bonded to the substrate 110 after forming a bonding insulating layer 355 on the bonding substrate 510. In other embodiments, the bonding substrate 510 can be bonded to the substrate 110 after forming a portion of the bonding insulating layer 355 on the bonding substrate 510 and the remaining portion of the bonding insulating layer 355 on the filling insulating layer 300 and the plurality of storage stacks ST1, ST2, ST3 and ST4.

[0146] In the storage device 3 according to the embodiment, since a plurality of first driving elements TRlb are additionally formed on the bonding substrate 510, an additional area for forming the plurality of first driving elements TRlb is not required. Therefore, the horizontal area of ​​the storage device 3 can be minimized.

[0147] Figure 17A This is a cross-sectional view illustrating a method of manufacturing a storage device according to an embodiment, and Figure 17B This is a cross-sectional view of a portion of the magnetic track layer of a storage device according to an embodiment.

[0148] Reference Figure 17A Multiple magnetic track layers 220b can be formed on the etch stop layer 210. In some embodiments, each of the multiple magnetic track layers 220b can be formed over the storage region MR and the first connection region CRx.

[0149] In the storage region MR, each of the plurality of magnetic track layers 220b may include an extended track layer 220L and a connecting track layer 220U connected to the extended track layer 220L. In the first connection region CRx, each of the plurality of magnetic track layers 220b may include a pad track layer 220PW extending from the extended track layer 220L. In some embodiments, the extended track layer 220L and the pad track layer 220PW may extend in a first horizontal direction (X direction).

[0150] In some embodiments, the extended track layer 220L and the connecting track layer 220U of each of the plurality of magnetic track layers 220b can extend with a uniform horizontal width, and the horizontal width of the pad track layer 220PW can be greater than the horizontal width of the extended track layer 220L and the connecting track layer 220U.

[0151] Reference Figure 17B The first connecting contact plug MCx can be connected to the portion of the pad track layer 220PW adjacent to one end of the magnetic track layer. In some embodiments, the horizontal width of the pad track layer 220PW can be greater than the horizontal width of the first connecting contact plug MCx.

[0152] The first connection contact plug MCx can contact a portion of the upper surface of the pad track layer 220PW, and can be in contact with the etch stop layer 210 without contacting it.

[0153] Figure 18A This is a cross-sectional view illustrating a method of manufacturing a storage device according to an embodiment, and Figure 18B This is a cross-sectional view of a portion of the magnetic track layer of a storage device according to an embodiment.

[0154] Reference Figure 18A Multiple magnetic track layers 220c can be formed on the etch stop layer 210. In some embodiments, each of the multiple magnetic track layers 220c can be formed over the storage region MR and the first connection region CRx.

[0155] In the storage region MR, each of the plurality of magnetic track layers 220c may include an extended track layer 220L and a connection track layer 220U connected to the extended track layer 220L. In the first connection region CRx, each of the plurality of magnetic track layers 220c may include a pad track layer 220PL extending from the extended track layer 220L. In some embodiments, the extended track layer 220L may extend in a first horizontal direction (X direction).

[0156] In some embodiments, the extended track layer 220L and connecting track layer 220U of each of the plurality of magnetic track layers 220c can extend with a uniform horizontal width. In some embodiments, the pad track layer 220PL can be rectangular. The values ​​of the major axis width and minor axis width of the pad track layer 220PL can be greater than the values ​​of the horizontal width of the extended track layer 220L and the connecting track layer 220U.

[0157] Reference Figure 18B The first connection contact plug MCx can be connected to the portion of the pad track layer 220PL adjacent to one end of the magnetic track layer. The first connection contact plug MCx can contact a portion of the upper surface of the pad track layer 220PL and can be in contact with the etch stop layer 210 without contacting it.

[0158] Figures 19A to 19C This is a perspective view showing a storage device according to an embodiment. Specifically, Figures 19A to 19C This is a perspective view showing the first connection area of ​​the storage device.

[0159] Reference Figure 19A The plurality of storage stacks ST1, ST2, ST3 and ST4 of the storage device 10 may form steps in a first horizontal direction (X direction). In some embodiments, the horizontal width of the first connection contact plug MCx may be greater than the horizontal width of the pad track layer 220P.

[0160] When provided Figure 17A When the pad track layer 220PW is shown, multiple memory stacks ST1, ST2, ST3, and ST4 can form steps in the first horizontal direction (X direction). In this case, the horizontal width of the pad track layer 220PW can be greater than the horizontal width of the first connection contact plug MCx.

[0161] Reference Figure 19BThe multiple storage stacks ST1, ST2, ST3, and ST4 of the storage device 12 can form steps in a first horizontal direction (X direction). In some embodiments, the horizontal width of each of the multiple pad track layers 220PL can be greater than the horizontal width of each of the multiple first connection contact plugs MCx.

[0162] Multiple first connection contact plugs MCx can be arranged on multiple pad track layers 220PL in the second horizontal direction (Y direction) while being shifted in different memory stacks among multiple memory stacks ST1, ST2, ST3 and ST4.

[0163] Reference Figure 19C The multiple storage stacks ST1, ST2, ST3, and ST4 of the storage device 14 can form steps in a first horizontal direction (X direction) and a second horizontal direction (Y direction). In some embodiments, the horizontal width of each of the multiple pad track layers 220PL can be greater than the horizontal width of each of the multiple first connection contact plugs MCx.

[0164] In some of the memory stacks ST1, ST2, ST3, and ST4, multiple pad track layers 220PL can cover the entire etch stop layer 210 of the stepped step plate, and in other memory stacks ST1, ST2, ST3, and ST4, multiple pad track layers 220PL can cover a portion of the etch stop layer 210 of the stepped step plate. For example, in the uppermost and lowermost memory stacks ST1 and ST4, which are located in the multiple memory stacks ST1, ST2, ST3, and ST4, multiple pad track layers 220PL can cover a portion of the etch stop layer of the stepped step plate, and in other memory stacks ST2 and ST3, multiple pad track layers 220PL can cover the entire etch stop layer 210 of the stepped step plate.

[0165] By summarizing and reviewing, the embodiments relate to a storage device including a race track, thereby achieving high integrity. Additionally, the embodiments relate to a method of manufacturing a storage device including a race track.

[0166] That is, according to the embodiment, because each of the multiple memory stacks having a magnetic track layer has a stepped shape, the connection contact plugs connecting the multiple memory stacks can be formed by performing photolithography, thereby reducing manufacturing costs. Furthermore, because the magnetic track layer is arranged on an etch stop layer, the batch production rate of the process can be improved, and because the magnetic track layer has a two-dimensional fluffy folded structure, the bit line pitch can be freely controlled, thereby increasing process margin.

[0167] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing of this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A storage device, the storage device comprising: Substrate, the substrate including storage regions and connectivity regions; A magnetic orbital layer extends over the storage region and the connection region of the substrate, and the magnetic orbital layer has a two-dimensional fluffy folded structure; Multiple readout units, each readout unit comprising multiple fixed layers and a tunnel barrier layer located between the magnetic orbital layer and each of the multiple fixed layers; and Multiple bit lines extend over different read units among a plurality of read units, the plurality of read units being located between the magnetic track layer and a corresponding bit line among the plurality of bit lines. The magnetic orbital layer includes: Multiple extended orbital layers, the multiple extended orbital layers extending in one direction above the storage region of the substrate; At least two connecting orbital layers, the at least two connecting orbital layers connecting two of the plurality of extended orbital layers above the storage region of the substrate, to define the two-dimensional fluffy folded structure of the magnetic orbital layers; and A pad track layer is located above the connection area of ​​the substrate and extends from a respective extended track layer of the plurality of extended track layers.

2. The storage device according to claim 1, further comprising: A first connecting contact plug is connected to a first end of the magnetic track layer; and A common source line is connected to a second end of the magnetic track layer, the first end and the second end are opposite each other in a first horizontal direction, and the magnetic track layer is located between the first connecting contact plug and the common source line.

3. The storage device according to claim 2, wherein, Each of the plurality of extended orbit layers extends in the first horizontal direction, and each of the plurality of bit lines extends in a second horizontal direction perpendicular to the first horizontal direction.

4. The storage device according to claim 3, wherein, Each of the plurality of read units is arranged on a portion of each of the plurality of extended track layers.

5. The storage device according to claim 2, wherein, Each of the plurality of extended orbit layers extends in a second horizontal direction perpendicular to the first horizontal direction, and each of the plurality of bit lines extends in the second horizontal direction.

6. The storage device according to claim 5, wherein, Each of the plurality of read units is arranged on a portion of each of the at least two connecting track layers.

7. The storage device of claim 1, further comprising an etch stop layer on the substrate, the magnetic track layer extending along the upper surface of the etch stop layer.

8. The storage device according to claim 7, wherein, The plurality of reading units are arranged on the upper surface of the magnetic track layer.

9. The storage device according to claim 7, wherein, The plurality of readout units are arranged on the lower surface of the magnetic track layer, and the etch stop layer surrounds the plurality of readout units.

10. A storage device, the storage device comprising: A substrate having a storage region and a connection region, the storage region and the connection region being adjacent to each other along a first horizontal direction; Multiple memory stacks are located on the substrate. Each of the multiple memory stacks has a stepped profile in the connection region and includes a magnetic track layer extending in a folded structure above the memory region and the connection region. The folded structure is two-dimensional fluffy. The magnetic track layer includes: Multiple extended orbital layers, the multiple extended orbital layers extending two-dimensionally in one direction, and At least two connecting track layers, wherein the at least two connecting track layers connect two of the plurality of extended track layers; Multiple readout units, each readout unit comprising multiple fixed layers and a tunnel barrier layer located between the magnetic orbital layer and each of the multiple fixed layers; Multiple bit lines extend over different read units among the multiple read units, which are located between the magnetic track layer and the corresponding bit lines among the multiple bit lines; A plurality of connection contact plugs are located in the connection region, each of the plurality of connection contact plugs being connected to a pad track layer at a first end of a corresponding magnetic track layer of the plurality of storage stacks; and A common source line is located in the storage region and is connected to the second end of a corresponding magnetic track layer of the plurality of storage stacks, the first end and the second end being spaced apart from each other along the first horizontal direction.

11. The storage device according to claim 10, wherein, Each of the plurality of extended orbit layers extends in the first horizontal direction, and each of the plurality of bit lines extends in a second horizontal direction perpendicular to the first horizontal direction.

12. The storage device according to claim 10, wherein, Each of the plurality of extended orbit layers and each of the plurality of bit lines extends in a second horizontal direction perpendicular to the first horizontal direction.

13. The storage device according to claim 10, wherein, The magnetic track layer extends with a uniform horizontal width.

14. The storage device according to claim 10, wherein, The horizontal width of the pad track layer of the corresponding magnetic track layer is greater than the horizontal width of each of the plurality of extended track layers and the horizontal width of each of the at least two connecting track layers.

15. The storage device according to claim 10, wherein, Each of the plurality of memory stacks further includes an etch stop layer, the magnetic track layer extends along the upper surface of the etch stop layer, and the plurality of read units are located on the upper surface of the magnetic track layer.

16. The storage device of claim 10, further comprising an etch stop layer surrounding the plurality of read units, the plurality of read units being located on the lower surface of the magnetic track layer.

17. A storage device, the storage device comprising: The substrate includes a storage region, a first connection region in a first horizontal direction of the storage region, and a second connection region in a second horizontal direction perpendicular to the first horizontal direction of the storage region. Multiple memory stacks are located on the substrate, each of the multiple memory stacks having a stepped profile in the first connection region and the second connection region, and including an etch stop layer stacked on the substrate; A magnetic orbital layer, the magnetic orbital layer extending along the upper surface of the etch stop layer above the storage region and the first connection region in a folded structure, the folded structure being two-dimensional fluffy, the magnetic orbital layer comprising: Multiple extended orbital layers, which extend two-dimensionally in one direction. At least two connecting orbital layers, wherein the at least two connecting orbital layers connect two of the plurality of extended orbital layers, and Multiple magnetic domains; Multiple readout units, each readout unit comprising multiple fixed layers and a tunnel barrier layer located between the magnetic orbital layer and each of the multiple fixed layers; Multiple bit lines extend over different readout units among the multiple readout units, the multiple readout units being located between the magnetic orbital layer and a corresponding bit line among the multiple bit lines to define a magnetic tunnel junction; A plurality of first connection contact plugs are located in the first connection region, and each of the plurality of first connection contact plugs is connected to a pad track layer at a first end of a corresponding magnetic track layer. A common source line, the common source line being connected to a second end of the magnetic track layer in the storage region opposite the first connection region in the first horizontal direction; and A plurality of second connection contact plugs are located in the second connection region, and each of the plurality of second connection contact plugs is connected to a bit line pad unit that is part of the bit line.

18. The storage device according to claim 17, wherein, In the direction in which the magnetic track layer extends, the distance between the common source pole line and the read unit adjacent to the common source pole line among the plurality of read units is equal to or greater than 1 / 2 of the distance between two adjacent read units among the plurality of read units.

19. The storage device according to claim 17, wherein, In the direction in which the magnetic track layer extends, the distance between the first connecting contact plug and the reading unit adjacent to the first connecting contact plug among the plurality of reading units is equal to or greater than 1 / 2 of the distance between two adjacent reading units among the plurality of reading units.

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