Method and system for testing integrated circuits

Abstract

The invention relates to a method and a system for testing an integrated circuit comprising logic gates, logic flip-flops and rewritable memory, the integrated circuit comprising an internal frequency, the integrated circuit being configurable in an operating mode called scan chain mode. According to the invention: the integrated circuit is placed in the scan chain mode; the rewritable memory is isolated from the logic gates and the logic flip-flops by means of an isolation mechanism; the isolation mechanism is clocked (Clk) by an external frequency; the periodicity of the external frequency is changed; the content of the rewritable memory is read (300) and compared with a value; the access time of the rewritable memory is determined (300) from the comparison.

Description

Technical Field

[0001] This invention relates to a method and system for testing integrated circuits configured on a silicon wafer. Background Technology

[0002] Integrated circuits are fabricated on silicon wafers. A silicon wafer contains a large number of integrated circuits, typically thousands.

[0003] Testing integrated circuits involves checking their functionality by ensuring that transistors are correctly connected together to form the desired function. The manufacturing process of integrated circuits can introduce various faults in one or more transistors or at their connections. These faults must be detected because they can impair the performance of the integrated circuit.

[0004] Some integrated circuits consist of logic gates, logic flip-flops, and at least one rewritable memory (e.g., flash memory).

[0005] Some integrated circuits have selectably parameterizable internal frequencies, which are used by logic gates and are used to time the operation of all logic flip-flops and rewritable memories.

[0006] Access time of rewritable memory is a crucial element that must be tested and proven to be satisfactory. Typically, the frequency of the rewritable memory is increased until data that does not correspond to the expected content is obtained at the output of the rewritable memory.

[0007] When the same internal frequency is used throughout the integrated circuit, the frequency cannot be increased to characterize the access time of the rewritable memory, because increasing the frequency of such an internal frequency may also cause logic gates or flip-flops to fail, which would make the result of the rewritable memory access time qualification incorrect.

[0008] The present invention aims to determine the access time of a rewritable memory contained in an integrated circuit, which is timed by an internal frequency, and the integrated circuit is also composed of logic flip-flops and logic gates. Summary of the Invention

[0009] Therefore, according to the first aspect, the present invention proposes a system for testing integrated circuits, the integrated circuit including logic gates, logic flip-flops, and rewritable memory, the integrated circuit including an internal frequency used by the logic gates to time the operation of all the logic gates and the rewritable memory, the integrated circuit being configurable in an operating mode called a scan chain mode, wherein all components of the flip-flops are connected in a series one after another to test the operation of the logic gates and the flip-flops, characterized in that the system includes:

[0010] The mechanism used to place the integrated circuit in the scan chain mode;

[0011] A mechanism for isolating the rewritable memory from the logic gate and the logic flip-flop;

[0012] A mechanism for timing the mechanism used to isolate the rewritable memory from the logic gate and the logic flip-flop by means of an external frequency;

[0013] A mechanism for changing the periodicity of this external frequency;

[0014] A mechanism for reading the contents of the rewritable memory and for comparing the value with a predetermined value;

[0015] A mechanism used to determine the access time of the rewritable memory based on the result of the comparison.

[0016] The present invention also relates to a method for testing an integrated circuit, the integrated circuit including logic gates, logic flip-flops, and rewritable memory, the integrated circuit including an internal frequency used by the logic gates and for timing the operation of all the logic flip-flops and the rewritable memory, the integrated circuit being configurable in an operating mode called a scan chain mode, wherein all components of the flip-flops are connected in a series one after another to test the operation of the logic gates and the flip-flops, characterized in that the method includes the following steps:

[0017] Place the integrated circuit in this scan chain mode;

[0018] Isolate the rewritable memory from the logic gate and the logic flip-flop;

[0019] The means for isolating the rewritable memory from the logic gate and the logic flip-flop is timed by an external frequency;

[0020] Change the periodicity of this external frequency;

[0021] Read the contents of the rewritable memory and compare the value with a predetermined value;

[0022] The access time of the rewritable memory is determined based on the result of this comparison.

[0023] Therefore, the access time of the rewritable memory can be determined by using this scan chain mode, thereby avoiding the need to add a dedicated system.

[0024] According to a specific embodiment of the invention, the isolation mechanism comprises a multiplexer disposed at the input and output of at least one register for controlling the addressing of the rewritable memory and a register for controlling the reading of the rewritable memory. Therefore, depending on the cycle of the common scan chain mode or the access time measurement mode during operation, the input of the rewritable memory is isolated from or connected to the control register, respectively. According to a specific embodiment of the invention, the output of the register controlling the addressing of the rewritable memory is connected to the input of the multiplexer disposed at the input of the rewritable memory.

[0025] Therefore, during this read cycle, the value previously loaded into the address control register is retained. In this mode, it is the access time that is determinable in relation to the startup of the read control register.

[0026] According to a specific embodiment of the present invention, the output of the register that controls the addressing of the rewritable memory is connected to an inverter, and the output of the inverter is connected to the input of a multiplexer located at the input of the rewritable memory.

[0027] Therefore, during this read cycle, the value previously loaded into the address control cache is made inversely proportional to the value. In this mode, it is the determinate access time related to the startup of the address control cache and the access time related to the read control cache.

[0028] According to a specific embodiment of the present invention, the multiplexer located at the input of the control buffer is controlled by a first logic signal, and the multiplexer located at the output of the control buffer is controlled by a second logic signal different from the first logic signal.

[0029] Therefore, the multiplexer located at the output of the control register is used in simple scan chain mode to isolate the rewritable memory from the rest of the circuit, and is used during the read cycle in access time measurement mode to connect the rewritable register to the control register. The multiplexer located at the input of the control register is used only in access time measurement mode to control the contents of the register during the read cycle.

[0030] According to a specific embodiment of the invention, the output of the rewritable memory is connected to another multiplexer, which in turn is connected to an output buffer.

[0031] Therefore, the value read from this rewritable memory can be captured so that it can be transmitted to the tester, which can then compare it with the expected value.

[0032] The present invention also relates to a computer program stored on an information carrier, the program including instructions for using the aforementioned method when the program is loaded into and executed by a computer system. Attached Figure Description

[0033] The features and other characteristics of the present invention described above will become clearer by reading the following description of exemplary embodiments, wherein the description is made with reference to the accompanying drawings, wherein:

[0034] Figure 1 A system for testing integrated circuits on silicon wafers is shown;

[0035] Figure 2 The architecture of the test apparatus according to the present invention is shown;

[0036] Figure 3 The architecture of an integrated circuit according to the present invention is shown;

[0037] Figure 4 A first example of the architecture of a module for isolating and testing a rewritable memory according to the present invention is shown;

[0038] Figure 5 A timing diagram of signals used by a module for isolating and testing a rewritable memory is shown in a first exemplary embodiment of the invention.

[0039] Figure 6 A second example of the architecture for isolating and testing a rewritable memory according to the present invention is shown;

[0040] Figure 7 A timing diagram of signals used by a module for isolating and testing a rewritable memory is shown in a second exemplary embodiment according to the present invention;

[0041] Figure 8 A third example of the architecture for isolating and testing a module for rewritable memory according to the present invention is shown;

[0042] Figure 9 A timing diagram of signals used by a module for isolating and testing a rewritable memory is shown in a third exemplary embodiment according to the present invention;

[0043] Figure 10 An example of the algorithm according to the present invention is shown. Detailed Implementation

[0044] Figure 1 This shows a system used for testing integrated circuits on a silicon wafer.

[0045] exist Figure 1In this tester, Te uses multiple probe cards that contact a rectangular area of ​​a group of integrated circuits being tested simultaneously to test the integrated circuits CI of a silicon wafer DUT.

[0046] Tester Te is, for example, a computer used to control one or more probe cards. Tester Te tests whether integrated circuits meet specifications and can configure and adjust the parameters of integrated circuits.

[0047] Each integrated circuit has at least two contact regions, each contact region in Figure 1 The contact area, represented by a black square, is used to test the integrated circuit. The tester Te uses a probe to control various tests and another probe to provide an external frequency to characterize the access time of the rewritable memory contained in the integrated circuit. Figure 1 In this method, a probe card including probes Cp1a, Cp1b, Cp2a, and Cp2b is used to simultaneously test two integrated circuits. Of course, simultaneously testing a large number of integrated circuits... Figure 1 The examples in the text are merely simplifications of the actual situation. Similarly, for the sake of simplification, in Figure 1 Only seven integrated circuits are shown in the image. Of course, there are a large number of integrated circuits on the silicon wafer DUT.

[0048] To detect faults in an integrated circuit (IC), it is necessary to examine the performance of its functions. A function is executed by a set of logic gates and their connections. The performance of a function is determined by the signals at its input terminals. One method involves chaining all or some of the flip-flops of one or more functions of the IC together in a specific state. This grouping is called a "scan chain." Since it is a flip-flop, for example, they will be updated at each frequency of events. Therefore, a flip-flop will update the flip-flop that follows it, and will be updated by the flip-flop that precedes it: this action is called "scan loading." By fixing the values ​​of the flip-flops, the inputs of various combinatorial clouds of the IC can be fixed. A combinatorial cloud consists of a set of logic gates that do not perform switching functions.

[0049] To capture the output of the combined cloud, the interlocking of triggers can be disabled, allowing their inputs to be directly connected to the output of the combined cloud. All triggers are updated by applying an event (e.g., a frequency) to them: this action is called "scan capture".

[0050] To retrieve the updated trigger's contents, restart its chain, and apply the same number of events as the trigger to the "scan chain," this action is called "scan discharging." It should be noted that scan discharging can correspond to a subsequent scan load in the scan chain.

[0051] The tool for automatically generating test vectors (ATPG, Automatic Test Pattern Generator) provides the values ​​applied during "scan loading", the timing of "scan capture" application, and the expected values ​​during "scan unloading".

[0052] Figure 2 This illustrates the architecture of the testing apparatus or tester according to the present invention. The tester Te includes:

[0053] Processor, microprocessor, or microcontroller 200;

[0054] Volatile memory 203;

[0055] ROM memory 202;

[0056] Interface 205 includes at least one probe card;

[0057] The communication bus 201 connects the processor 200 to the ROM memory 202, the RAM memory 203, and the interface 205.

[0058] Processor 200 is capable of executing instructions loaded from ROM memory 202, external memory (not shown), or storage media into volatile memory 203. When the tester Te is started, processor 200 is capable of reading instructions from volatile memory 203 and executing them. These instructions constitute a computer program that causes processor 200 to implement an integrated circuit test program.

[0059] All or part of a test program can be implemented in software by executing a set of instructions by a programmable machine (e.g., a DSP (Digital Signal Processor) or a microcontroller), or in hardware by a machine or a dedicated component (e.g., an FPGA (Field Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit)).

[0060] Figure 3 This illustrates the integrated circuit architecture according to the present invention. The integrated circuit CI includes an input / output Cp1a connected to the control module 300.

[0061] The control module 300 receives commands from the tester Te via input / output Cp1a, and receives the external frequency of the tester Te via input Cp1b.

[0062] For module 310 used for isolating and testing rewritable memory, control module 300 generates signals represented as Eq1, Eq2, ScMo, Sch and external frequency Clk according to the received commands.

[0063] The control module 300 is configured to receive data from the module 310 used for isolating and testing the rewritable memory.

[0064] The integrated circuit CI includes a set of logic gates and flip-flops 320.

[0065] During normal operation of the integrated circuit CI, the rewritable memory is connected to this set of logic gates and flip-flops 320. According to the present invention, during testing of the access time of the rewritable memory, the rewritable memory is isolated from all logic gates and flip-flops 320.

[0066] The control module 300 is capable of reading and executing instructions. These instructions constitute a computer program that causes the control module 300 to perform actions related to... Figure 8 All or part of the method described.

[0067] about Figure 8 All or part of the described method can be implemented in software by executing a set of instructions by a programmable machine (e.g., a DSP (digital signal processor) or a microcontroller), or in hardware by a machine or dedicated component.

[0068] Figure 4 This illustrates a first example of an architecture for isolating and testing a rewritable memory according to the present invention.

[0069] Module 310 for isolating and testing rewritable memory includes multiplexers 400, 401, 402, 403 and 404, which isolate rewritable memory 410 during access times characterizing rewritable memory 410.

[0070] Multiplexers 400 and 401 are controlled by signal Eq2. Signal Eq2 is high when signal ScMo is high, when the signal called "Scan_taa" is high, and when the signal called "capture" is high.

[0071] The ScMo signal is used to control the scan chain mode.

[0072] The capture signal is a commonly used scan capture signal.

[0073] The signal scan_taa is a signal used according to the present invention when it is desired to characterize the access time of the rewritable memory 410.

[0074] Module 310 for isolating and testing rewritable memory includes three control registers 420, 421 and 422.

[0075] The control register 420 is a register that can be programmed, erased, and placed in a low-power mode and an internal test mode of the rewritable memory 410.

[0076] The control register 420 is a register that controls the addressing of the rewritable memory 410.

[0077] The control register 422 is a register that controls the reading of the rewritable memory 410.

[0078] The output of the multiplexer 400 is connected to the input of the control buffer 421. The output of the control buffer 421 is connected to the first input of the multiplexer 403 and the first input of the multiplexer 400.

[0079] When signal Eq2 is high, the output of control buffer 420 is directed to the input of control buffer 421. When signal Eq2 is low, the signal represented as Fon1, connected to the second input of multiplexer 400, is directed to the input of control buffer 421.

[0080] The signal Fon1 represents the signal applied to the input of the control register 421 during normal operation of the integrated circuit (i.e., when the rewritable memory 410 is not in the process of being tested for access).

[0081] The output of the multiplexer 401 is connected to the control buffer 422. The output of the control buffer 422 is connected to the first input of the multiplexer 404.

[0082] When signal Eq2 is high, signal Act, connected to the first input of multiplexer 401, is directed to the input of control buffer 422. When signal Eq2 is low, signal Fon2, connected to the second input of multiplexer 401, is directed to the input of control buffer 422.

[0083] The signal Act is the signal that initiates the control of the rewritable memory 410 to read its contents at the memory address provided by the control register 421.

[0084] Signal Fon2 represents a signal applied to the input of control register 422 during normal operation of the integrated circuit (i.e., when the rewritable memory 410 is not in the process of being tested for access).

[0085] The external frequency Clk and signal Sch are transmitted to control buffers 420, 421 and 422.

[0086] The signal Sch is used to load the required value into the control buffers 420, 421 and 422 via the scan chain.

[0087] The second input of multiplexers 402, 403, and 404 is connected to a signal denoted as In. The function of signal In is to disable the function.

[0088] Multiplexer 402 is controlled by signal ScMo, while multiplexers 403 and 404 are controlled by signal Eq1.

[0089] Signal Eq1 is high when signal ScMo is high and signal "Scan_taa" is low or when the capture signal is low.

[0090] The capture signal is a commonly used signal for controlling the capture of the scan chain.

[0091] The outputs of multiplexers 402, 403 and 404 are connected to rewritable memory 410.

[0092] When signal Eq1 is high, signal In is directed to rewritable memory 410. When signal Eq1 is low, the output of control register 421 is directed to rewritable memory 410.

[0093] When signal Eq1 is high, signal In is directed to rewritable memory 410. When signal Eq1 is low, the output of control register 422 is directed to rewritable memory 410.

[0094] When the signal ScMo is high, the signal In is directed to the rewritable memory 410. When the signal ScMo is low, the output of the control register 420 is directed to the rewritable memory 410.

[0095] The output of the rewritable memory 410 is connected to the first input of the multiplexer 405. The second input of the multiplexer 405 is connected to a signal denoted as Otr.

[0096] In the case of use in the standard scan chain mode, the output of the rewritable memory 410 cannot be connected to the scan chain because its value is unpredictable. The signal Otr can redirect known and controllable data to the output buffer 430.

[0097] The output of the multiplexer 405 is connected to the input of the output buffer 430, which is controlled by an external frequency Clk.

[0098] During the test of access time of rewritable memory 410, data output from control register is transmitted to control module 300.

[0099] Figure 5 A timing diagram showing the signals used by a module for isolating and testing a rewritable memory in a first exemplary embodiment according to the present invention.

[0100] Figure 5 The signal displayed is from the external frequency Clk, signals Eq1 and Eq2, signal 421_out output from control buffer 421, signal 422_out output from control buffer 422, signal 403_out output from multiplexer 403, signal 404_out output from multiplexer 404, signal 410_out output from rewritable memory 410, and signal Do output from output buffer 430.

[0101] Control register 421 is triggered by the rising edge of frequency Clk, and control register 422 is triggered by the falling edge of frequency Clk.

[0102] The address output from control register 421 is the predetermined address ADD1. When signal Eq1 goes low and signal Eq2 goes high, as long as signal Eq1 remains low and signal Eq2 remains high, signal 403_out becomes valid and indicates address ADD1. The address ADD1 of the rewritable memory 410 is addressed.

[0103] When signal Eq1 goes low and signal Eq2 goes high, signal 404_out becomes valid at the next rising edge of external frequency Clk and indicates a command to read the contents of rewritable memory 410 at address ADD1. It remains valid as long as signal Eq1 remains low and signal Eq2 remains high.

[0104] The contents D of the rewritable memory 410 at address ADD1 appear at output 410_out with a delay Ta representing the access time of the rewritable memory 410.

[0105] Then, data D appears at the output Do of output buffer 430 at the next rising edge of frequency Clk.

[0106] Therefore, when the period Pe of the external frequency Clk becomes less than the access time of the rewritable memory 410, the content D of the rewritable memory 410 at address ADD1 no longer appears at the output of the rewritable memory 410, and the data D no longer appears at the output Do of the output buffer 430 at the next rising edge of the frequency Clk.

[0107] Figure 6 This illustrates a second example of the architecture of a module for isolating and testing a rewritable memory according to the present invention.

[0108] Module 310 for isolating and testing rewritable memory includes multiplexers 600, 601, 602, 603 and 604, which isolate rewritable memory 610 during access times characterizing rewritable memory 610.

[0109] Multiplexers 600 and 601 are controlled by signal Eq2. Signal Eq2 is high when signal ScMo is high, when the signal called "Scan_taa" is high, and when the signal called "capture" is high.

[0110] The ScMo signal is used to control the scan chain mode.

[0111] The capture signal is a commonly used scan capture signal.

[0112] The signal scan_taa is a signal used according to the present invention when it is desired to characterize the access time of the rewritable memory 610.

[0113] Module 310 for isolating and testing rewritable memory includes three control registers 620, 621 and 622.

[0114] The control register 620 is a register that can be programmed, erased, and placed in a low-power mode and a mode for internal testing of the rewritable memory 610.

[0115] The control register 621 is a register that controls the addressing of the rewritable memory 610.

[0116] The control register 622 is a register that controls the reading of the rewritable memory 610.

[0117] The output of the multiplexer 600 is connected to the control buffer 621. The output of the control buffer 621 is connected to the first input of the multiplexer 603 and the input of the inverter 640, and the output of the inverter 640 is connected to the first input of the multiplexer 600.

[0118] When signal Eq2 is high, the inverted output of control buffer 621 is directed to the input of control buffer 621. When signal Eq2 is low, the signal represented as Fon1, connected to the second input of multiplexer 600, is directed to the input of control buffer 621.

[0119] Signal Fon1 represents the signal applied to the input of control register 621 during normal operation of the integrated circuit (i.e., when the rewritable memory 610 is not under test during access). The output of multiplexer 601 is connected to control register 622. The output of control register 622 is connected to the first input of multiplexer 604.

[0120] When signal Eq2 is high, signal Act, connected to the first input of multiplexer 601, is directed to the input of control buffer 622. When signal Eq2 is low, signal Fon2, connected to the second input of multiplexer 601, is directed to the input of control buffer 622.

[0121] The signal Act is the signal that initiates the control of the rewritable memory 610 to read its contents at the memory address provided by the control register 621.

[0122] Signal Fon2 represents the signal applied to the input of control register 621 during normal operation of the integrated circuit (i.e., when the rewritable memory 610 is not in the process of being tested for access). External frequency Clk and signal Sch are transmitted to control registers 620, 621, and 622.

[0123] The signal Sch is used to load the required value into control buffers 620, 621, and 622 via the scan chain.

[0124] The second input of multiplexers 602, 603, and 604 is connected to a signal denoted as In. The function of signal In is to disable the function.

[0125] Multiplexer 602 is controlled by signal ScMo, while multiplexers 603 and 604 are controlled by signal Eq1.

[0126] Signal Eq1 is high when signal ScMo is high and signal "Scan_taa" is low or when the capture signal is low.

[0127] The capture signal is a commonly used signal for controlling the capture of the scan chain.

[0128] The outputs of multiplexers 602, 603 and 604 are connected to rewritable memory 610.

[0129] When signal Eq1 is high, signal In is directed to rewritable memory 610. When signal Eq1 is low, the output of control register 621 is directed to rewritable memory 610.

[0130] When signal Eq1 is high, signal In is directed to rewritable memory 610. When signal Eq1 is low, the output of control register 622 is directed to rewritable memory 610.

[0131] When the ScMo signal is high, the In signal is directed to the rewritable memory 610. When the ScMo signal is low, the output of the control register 620 is directed to the rewritable memory 610.

[0132] The output of the rewritable memory 610 is connected to the first input of the multiplexer 605. The second input of the multiplexer 605 is connected to a signal denoted as Otr.

[0133] In the case of use in the standard scan chain mode, the output of the rewritable memory 610 cannot be connected to the scan chain because its value is unpredictable. The signal Otr can redirect known and controllable data to the output buffer 630.

[0134] The output of the multiplexer 605 is connected to the input of the output buffer 630, which is controlled by an external frequency Clk.

[0135] During the test of access time of rewritable memory 610, data output from control register is transmitted to control module 300.

[0136] Figure 7 A timing diagram showing the signals used by the module for isolating and testing the rewritable memory in a second embodiment according to the present invention.

[0137] Figure 7 The external frequency signal Clk, signals Eq1 and Eq2, signal 621_out output from control buffer 621, signal 622_out output from control buffer 622, signal 603_out output from multiplexer 603, signal 604_out output from multiplexer 604, signal 610_out output from rewritable memory 610, and signal Do output from output buffer 630 are displayed.

[0138] Control register 621 is triggered by the rising edge of frequency Clk, and control register 622 is triggered by the falling edge of frequency Clk.

[0139] When signal Eq2 is at level 1, the output of control buffer 621 is connected to its input via inverter gate 640. The address output from control buffer 621 is changed from address AD1 to the complement of address AD1 at each rising edge, or from the complement of address AD1 to address AD1 at each rising edge.

[0140] The address output from control register 621 is the predetermined address AD1 or its complement! AD1. When signal Eq1 goes low and signal Eq2 goes high, as long as signal Eq1 remains low and signal Eq2 remains high, signal 603_out becomes valid and indicates address AD1 or its complement! AD1. The address AD1 of the rewritable memory 610 is addressed.

[0141] This configuration allows testing the access time of the rewritable memory 610 in the configuration with the maximum access time.

[0142] When signal Eq1 goes low and signal Eq2 goes high, signal 604_out becomes valid at the next rising edge of external frequency Clk and indicates a command to read the contents of rewritable memory 610 at address AD1 and at the subsequent rising edge, and remains valid as long as signal Eq1 remains low and signal Eq2 remains high.

[0143] The contents of the rewritable memory 610 at address AD1, D, appear at output 610_out with a delay Ta representing the access time of the rewritable memory 610, and at the subsequent rising edge of frequency Clk, the contents of the rewritable memory 610 at address AD1, D, appear at output 610_out with the same delay Ta' representing the access time of the rewritable memory 610.

[0144] Then, data item D or ! D appears at the output Do of output buffer 430 at the next rising edge of frequency Clk.

[0145] Therefore, when the period Pe of the external frequency Clk becomes less than the access time of the rewritable memory 410, the content D of the rewritable memory 410 at address AD1 no longer appears at the output of the rewritable memory 410, and the data item D no longer appears at the output Do of the output buffer 630 at the next rising edge of the frequency Clk.

[0146] Figure 8 This illustrates a third example of the architecture for isolating and testing a module for rewritable memory according to the present invention.

[0147] Module 310 for isolating and testing rewritable memory includes an internal test module 840 and multiplexers 850, 800, 801, 802, 803, and 804, which isolate rewritable memory 810 during access times characterizing rewritable memory 810. Module 310 for isolating and testing rewritable memory includes three control buffers 820, 821, and 822.

[0148] The internal test module 840 can characterize the impact of each data item transferred by control registers 820, 821, and 822 on the access time of the rewritable memory 810. The internal test module 840 is controlled by the signal Eq2. The signal Eq2 is high when the signal ScMo is high, when the signal called "Scan_taa" is high, and when the signal called "capture" is high.

[0149] The multiplexers 850, 800 and 801 are controlled by signal Eq2.

[0150] The ScMo signal is used to control the scan chain mode.

[0151] The capture signal is a commonly used scan capture signal.

[0152] The signal scan_taa is a signal used according to the present invention when it is desired to characterize the access time of the rewritable memory 810.

[0153] The control register 820 is a register that can be programmed, erased, and placed in a low-power mode and a mode for internal testing of the rewritable memory 810.

[0154] The output of the multiplexer 850 is connected to the control buffer 820. The output of the control buffer 820 is connected to the first input of the multiplexer 802.

[0155] The first input of the multiplexer 850 is connected to the output 846 of the internal test module 840, while the second input of the multiplexer 850 is connected to the signal Fon1.

[0156] When signal Eq2 is high, the output 846 of the internal test module 840 is connected to the input of the control buffer 820. When signal Eq2 is low, the signal represented by Fon1 is directed to the input of the control buffer 820.

[0157] The signal Fon1 represents the signal applied to the input of the control register 820 during normal operation of the integrated circuit (i.e., when the rewritable memory 810 is not in the process of being tested for access).

[0158] The output of the multiplexer 801 is connected to the control buffer 822. The output of the control buffer 822 is connected to the first input of the multiplexer 804.

[0159] The output of the multiplexer 800 is connected to the control buffer 821. The output of the control buffer 821 is connected to the first input of the multiplexer 803.

[0160] When signal Eq2 is high, the output 844 of the internal test module 840 is connected to the input of the control buffer 821. When signal Eq2 is high, the signal represented as Fon1, connected to the second input of the multiplexer 800, is directed to the input of the control buffer 821.

[0161] The signal Fon1 represents the signal applied to the input of the control register 821 during normal operation of the integrated circuit (i.e., when the rewritable memory 810 is not in the process of being tested for access).

[0162] The output of the multiplexer 801 is connected to the control buffer 822. The output of the control buffer 822 is connected to the first input of the multiplexer 804.

[0163] When signal Eq2 is high, the output 842 of the internal test module 840 is connected to the input of the control buffer 822. When signal Eq2 is low, the signal represented as Fon2, connected to the second input of the multiplexer 801, is directed to the input of the control buffer 822.

[0164] Output 842 is a signal that enables the control of the rewritable memory 810 to read its contents at the memory address provided by the control register 821.

[0165] Signal Fon2 represents the signal applied to the input of control register 821 during normal operation of the integrated circuit (i.e., when the rewritable memory 810 is not in the process of being tested for access). External frequency Clk and signal Sch are transmitted to control registers 820, 821, and 822.

[0166] The signal Sch is used to load the required value into the control buffers 820, 821, and 822 via the scan chain.

[0167] The second input of multiplexers 802, 803, and 804 is connected to a signal denoted as In. The function of signal In is to disable the function.

[0168] Multiplexer 802 is controlled by signal ScMo, while multiplexers 803 and 804 are controlled by signal Eq1.

[0169] Signal Eq1 is high when signal ScMo is high and signal "Scan_taa" is low or when the capture signal is low.

[0170] The capture signal is a commonly used signal for controlling the capture of the scan chain.

[0171] The outputs of multiplexers 802, 803 and 804 are connected to rewritable memory 810.

[0172] When signal Eq1 is high, signal In is directed to rewritable memory 810. When signal Eq1 is low, the output of control register 821 is directed to rewritable memory 810.

[0173] When signal Eq1 is high, signal In is directed to rewritable memory 810. When signal Eq1 is low, the output of control register 822 is directed to rewritable memory 810.

[0174] When the ScMo signal is high, the In signal is directed to the rewritable memory 810. When the ScMo signal is low, the output of the control register 820 is directed to the rewritable memory 810.

[0175] The output of the rewritable memory 810 is connected to the first input of the multiplexer 805. The second input of the multiplexer 805 is connected to a signal denoted as Otr.

[0176] In the case of use in the standard scan chain mode, the output of the rewritable memory 810 cannot be connected to the scan chain because its value is unpredictable. The signal Otr can redirect known and controllable data to the output buffer 830.

[0177] The output of the multiplexer 805 is connected to the input of the output buffer 830, which is controlled by an external frequency Clk.

[0178] During the test of access time of rewritable memory 810, data output from control register is transmitted to internal test module 840.

[0179] Figure 9 This diagram shows a timing diagram of signals used by a module for isolating and testing a rewritable memory according to a third exemplary embodiment of the present invention.

[0180] Figure 9 The signal displayed is from the external frequency Clk, signals Eq1 and Eq2, signal 821_out output from control buffer 821, signal 822_out output from control buffer 822, signal 803_out output from multiplexer 803, signal 804_out output from multiplexer 804, signal 810_out output from rewritable memory 810, and signal Do output from output buffer 830.

[0181] Control register 821 is triggered by the rising edge of frequency Clk, and control register 822 is triggered by the falling edge of frequency Clk.

[0182] Based on signal 844 provided by the internal test module, the address output from control register 421 changes from A1 to An. When signal Eq1 goes low and signal Eq2 goes high, as long as signal Eq1 remains low and signal Eq2 remains high, signal 803_out becomes valid, indicating addresses A1 to An. The addresses A1 to An of the rewritable memory 810 are addressed sequentially at each beat of frequency Clk.

[0183] When signal Eq1 goes low and signal Eq2 goes high, signal 804_out becomes valid at the next rising edge of external frequency Clk and indicates a command to read the contents of rewritable memory 810 at consecutive addresses A1 to An. It remains valid as long as signal Eq1 remains low and signal Eq2 remains high.

[0184] The contents d1 to dn of the rewritable memory 810 at addresses A1 to An appear sequentially in output 810_out with a delay representing the access time of the rewritable memory 810.

[0185] Then, the data dl to dn appear at the output Do of the output buffer 830 at the next rising edge of the frequency Clk.

[0186] Therefore, when the period Pe of the external frequency Clk becomes less than the access time of the rewritable memory 810, the contents of the rewritable memory 810 no longer appear at the output of the rewritable memory 810, and the data item no longer appears at the output Do of the output buffer 830 at the next rising edge of the frequency Clk.

[0187] Figure 10 Examples of algorithms according to the present invention are shown.

[0188] In step E100, the control module 300 enters the scan chain mode.

[0189] In step E101, the tester Te determines the periodicity of the external frequency based on predetermined parameters: the start period and the decrease during each repetition.

[0190] In step E102, the control module 300 generates signals Eq1 and Eq2. Signal Eq1 is set to a low level, while signal Eq2 is set to a high level. This effectively isolates the rewritable memory from all logic gates and flip-flops 320.

[0191] In step E103, the control module 300, based on the reference... Figure 4 The first embodiment waits for the two rising edges of the external frequency Clk or, based on a reference... Figure 6 The second embodiment described above waits for the three rising edges of the external frequency Clk.

[0192] In step E104, the control module 300 sets signal Eq1 to a high level and signal Eq2 to a low level.

[0193] In step E105, the control module 300 reads the output Do from the output buffer.

[0194] In step E106, the tester Te checks whether the data item read at output Do is equal to the data item stored at address Add1 or AD1 in the rewritable memory.

[0195] If so, the period of the external frequency Clk is stored in step E107, and the method returns to step E101, or the periodicity of the external frequency is reduced.

[0196] If not, the method proceeds to step E108, and the access time of the rewritable memory is considered to be equal to the last cycle of the stored frequency Clk.

[0197] Explanation of reference numerals in the attached figures

[0198] 200: Processor

[0199] 201: Communication Bus

[0200] 202: ROM memory

[0201] 203: Volatile Memory

[0202] 205: Interface

[0203] 300: Control Module

[0204] 310: Module for isolating and testing rewritable memory

[0205] 320: Logic gates and flip-flops

[0206] 400: Multitasking

[0207] 401: Multitasking

[0208] 402: Multitasking

[0209] 403: Multitasking

[0210] 404: Multitasking

[0211] 410: Rewritable memory

[0212] 420: Control Cache

[0213] 421: Control Buffer

[0214] 422: Control Buffer

[0215] 430: Output buffer

[0216] 403_out: signal

[0217] 404_out: signal

[0218] 410_out: signal

[0219] 421_out: signal

[0220] 422_out: signal

[0221] 600: Multitasking

[0222] 601: Multitasking

[0223] 602: Multitasking

[0224] 603: Multitasking

[0225] 604: Multitasking

[0226] 603_out: signal

[0227] 604_out: signal

[0228] 610_out: signal

[0229] 610: Rewritable memory

[0230] 620: Control Cache

[0231] 621: Control Buffer

[0232] 622: Control Cache

[0233] 630: Output buffer

[0234] 640: Inverter

[0235] 800: Multitasking

[0236] 801: Multitasking

[0237] 802: Multitasking

[0238] 803: Multitasking

[0239] 804: Multitasking

[0240] 810: Rewritable Memory

[0241] 820: Control Cache

[0242] 821: Control Buffer

[0243] 822: Control Cache

[0244] 830: Output buffer

[0245] 840: Internal Testing Module

[0246] 803_out: signal

[0247] 804_out: signal

[0248] 810_out: signal

[0249] 821_out: signal

[0250] 822_out: signal

[0251] 842: Output of internal test module 840

[0252] 844: Output of the internal test module 840

[0253] 846: Output of internal test module 840

[0254] 850: Multitasking

[0255] ! AD1: Two's complement

[0256] ! D1: Content

[0257] Act: Signal

[0258] AD1: Address

[0259] Add1: Address

[0260] ADD1: Reservation Address

[0261] AN: Address

[0262] CI: Integrated Circuits

[0263] Clk: External frequency

[0264] Cp1a: probe

[0265] Cp1b: probe

[0266] Cp2a: probe

[0267] Cp2b: probe

[0268] D: Content

[0269] Do: signal

[0270] DUT: Silicon Wafer

[0271] E100: Steps

[0272] E101: Steps

[0273] E102: Steps

[0274] E103: Steps

[0275] E104: Steps

[0276] E105: Steps

[0277] E106: Steps

[0278] E107: Steps

[0279] E108: Steps

[0280] Eq1: Signal

[0281] Eq2: Signal

[0282] Fon1: Signal

[0283] Fon2: Signal

[0284] In:signal

[0285] Otr: signal

[0286] Pe: Period

[0287] scan_taa: signal

[0288] Sch: signal

[0289] ScMo: signal

[0290] Ta: Delay

[0291] Ta': Delay

[0292] Te: Tester.

Claims

1. A system for testing an integrated circuit, the integrated circuit including logic gates, logic flip-flops, and rewritable memory, the integrated circuit including an internal frequency used by the logic gates and for timing the operation of all the logic gates and the rewritable memory, the integrated circuit being configurable in an operating mode called a scan chain mode, wherein all components of the logic flip-flops are connected in a series for testing the operation of the logic gates and the logic flip-flops, characterized in that... The system includes: Mechanism (300) for placing the integrated circuit in the scan chain mode; Mechanism (310) for isolating the rewritable memory from the logic gate and the logic flip-flop; A mechanism for timing the mechanism used to isolate the rewritable memory from the logic gate and the logic flip-flop by means of an external frequency of the tester; A mechanism for changing the periodicity of this external frequency; A mechanism (300) for reading the value of the rewritable memory and comparing the value with a predetermined value; The mechanism (300) used to determine the access time of the rewritable memory based on the result of the comparison. The isolation mechanism consists of a multiplexer, which is located at the input and output of at least one address control register that controls the addressing of the rewritable memory and a read control register that controls the reading of the rewritable memory.

2. The system according to claim 1, wherein, The output of the addressing control register that controls the addressing of the rewritable memory is connected to the input of the multiplexer located at the input of the rewritable memory.

3. The system according to claim 1, wherein, The output of the address control register that controls the addressing of the rewritable memory is connected to the inverter, and the output of the inverter is connected to the input of the multiplexer located at the input of the address control register.

4. The system according to any one of claims 1 to 3, wherein, The multiplexer located at the input of the address control register and the read control register is controlled by a first logic signal, while the multiplexer located at the output of the address control register and the read control register is controlled by a second logic signal that is different from the first logic signal.

5. The system according to any one of claims 1 to 4, wherein, The output of the rewritable memory is connected to another multiplexer, which in turn is connected to the output buffer.

6. A method for testing an integrated circuit, the integrated circuit including logic gates, logic flip-flops, and rewritable memory, the integrated circuit including an internal frequency used by the logic gates and for timing the operation of all the logic flip-flops and the rewritable memory, the integrated circuit being configurable in an operating mode called a scan chain mode, wherein all components of the logic flip-flops are connected in a series to test the operation of the logic gates and the logic flip-flops, characterized in that... The method includes the following steps: Place the integrated circuit in this scan chain mode; A multiplexer is used to isolate the rewritable memory from the logic gate and the logic flip-flop. The multiplexer is located at the input and output of at least one address control register that controls the addressing of the rewritable memory and a read control register that controls the reading of the rewritable memory. The mechanism used to isolate the rewritable memory from the logic gate and the logic flip-flop is timed by an external frequency; Change the periodicity of the external frequency of the tester; Read the value from the rewritable memory and compare it with a predetermined value; The access time of the rewritable memory is determined based on the result of this comparison.

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