Microelectronic device including contact structure, and related electronic system and method

Abstract

The present application relates to microelectronic devices including contact structures, and related electronic systems and methods. A microelectronic device includes a stacked structure, the stacked structure including alternating conductive structures and insulating structures arranged in layers, each of the layers individually including conductive structures and insulating structures; a memory cell string extending vertically through the stacked structure, the memory cell string including a channel material extending vertically through the stacked structure; another stacked structure vertically overlying the stacked structure and including alternating levels of other conductive structures and other insulating structures, the other stacked structure including pillars vertically overlying the memory cell string, each pillar including another channel material electrically connected to the channel material of the memory cell string; and a conductive contact structure vertically overlying the other stacked structure.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 877,233, filed on May 18, 2020, for "MICROELECTRONIC DEVICES INCLUDING CONTACT STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS." Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More specifically, the present disclosure relates to microelectronic devices and apparatus including self-aligned contact structures with enlarged areas, and to related electronic systems and methods for forming microelectronic devices. Background Art

[0004] An ongoing goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as nonvolatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in nonvolatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. A conventional vertical memory array includes vertical memory strings extending through openings in a stack of conductive structure (e.g., word line) layers and dielectric materials at each junction of the vertical memory string with the conductive structure. By building the array upward (e.g., longitudinally, vertically) on the die, this configuration allows a greater number of switching devices (e.g., transistors) to be positioned per unit of die area (i.e., the length and width of the active surface consumed) compared to structures having a conventional planar (e.g., two-dimensional) arrangement of transistors.

[0005] Conventional vertical memory arrays include electrical connections between conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for write, read, or erase operations. One method of forming such electrical connections includes forming a so-called at least one "staircase" (or "stair step") structure at an edge (e.g., a horizontal end) of a conductive structure layer. The staircase structure includes individual "steps" that provide contact areas for the conductive structure, on which a conductive contact structure can be positioned to provide an electrical path to the conductive structure.

[0006] As vertical memory array technology has advanced, additional memory density has been provided by forming a vertical memory array that includes a stack that includes additional conductive structure layers and, therefore, includes additional staircase structures and / or additional steps in individual staircase structures associated therewith. As the number of layers of conductive structures increases, the processing conditions for forming aligned contacts with various components of the microelectronic device become increasingly difficult. Additionally, other techniques for increasing memory density have been to reduce the spacing between adjacent vertical memory strings. However, reducing the spacing between adjacent vertical memory strings can increase the difficulty of forming individual electrical connections to the vertical memory strings without shorting to adjacent vertical memory strings. Summary of the invention

[0007] In some embodiments, a microelectronic device includes a stacked structure, the stacked structure including alternating conductive structures and insulating structures arranged in layers, each of the layers individually including a conductive structure and an insulating structure; a memory cell string extending vertically through the stacked structure, the memory cell string including a channel material extending vertically through the stacked structure; another stacked structure vertically overlying the stacked structure and including alternating levels of other conductive structures and other insulating structures, the other stacked structure including pillars vertically overlying the memory cell string, each pillar including another channel material electrically connected to the channel material of the memory cell string; and a conductive contact structure vertically overlying the other stacked structure, each conductive contact structure including a conductive contact extending at least partially into the pillar and a portion extending outside the pillar having a larger cross-sectional area than the pillar.

[0008] In other embodiments, a method of forming a microelectronic device includes: forming a first stacked structure including alternating levels of insulating structures and other insulating structures; forming a first pillar including channel material extending through the first stacked structure; forming a second stacked structure on the first stacked structure, the second stacked structure including alternating levels of additional insulating structures and sacrificial structures; forming a second pillar through the second stacked structure, the second pillar including additional channel material extending vertically through the second pillar and electrically connected to the channel material of the first pillar; forming a conductive material in the second pillar; growing additional conductive material on the second pillar to form a conductive contact; and at least partially replacing the sacrificial structure with a conductive material.

[0009] In a further embodiment, a microelectronic device includes: a stacked structure comprising alternating layers of conductive structures and insulating structures; a memory cell string extending through the stacked structure, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the stacked structure; and a conductive contact structure electrically connected to the channel material of one of the memory cell strings, the conductive contact structure having a larger cross-sectional area than the at least one dielectric material and the channel material of the string.

[0010] In other embodiments, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device and including at least one microelectronic device structure. The at least one microelectronic device structure includes: a memory cell string extending through alternating levels of insulating structures and conductive structures; a pillar within a stacked structure, the stacked structure including alternating levels of insulating structures and conductive structures, the pillar being laterally aligned with the memory cell string; and a conductive contact structure electrically connected to a channel material extending vertically through the memory cell string and the pillar, the conductive contact structure having a larger lateral dimension than the memory cell string. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1A to 1N is a simplified cross-sectional view showing a method of forming a microelectronic device structure according to an embodiment of the present disclosure ( Figure 1A , Figure 1C , Figure 1D , Figure 1F , Figure 1G , Fig. 1I , Figure 1K , Figure 1L , Figure 1M and Figure 1N ) and top view ( Figure 1B , Figure 1E , Figure 1H and Figure 1J );

[0012] Fig.1O and Figure 1P is a simplified cross-sectional view of a memory cell according to an embodiment of the present disclosure;

[0013] Figure 2 is a partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0014] Figure 3 is a block diagram of an electronic system according to an embodiment of the present disclosure; and

[0015] Figure 4 is a processor-based system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The descriptions contained herein are not meant to be actual views of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but are merely idealized representations used to describe the embodiments herein. Elements and features common between the drawings may retain the same numerical designations, except that for ease of the following description, the reference numerals begin with the number of the drawing that introduces or most fully describes the element.

[0017] The following description provides specific details, such as material type, material thickness, and processing conditions, in order to provide a comprehensive description of the embodiments described herein. However, it will be appreciated by those skilled in the art that the embodiments disclosed herein can be practiced without using these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device (e.g., a DRAM memory device)), an apparatus, or an electronic system, or a complete microelectronic device, an apparatus, or an electronic system containing a self-aligned contact structure, wherein the self-aligned contact structure has a relatively large lateral dimension (e.g., area, cross-sectional area) relative to a vertical memory string or pillar associated with the contact structure. The structure described below does not form a complete microelectronic device, an apparatus, or an electronic system. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete microelectronic device, an apparatus, or an electronic system from these structures can be performed by conventional techniques.

[0018] The materials described herein may be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the material may be grown in situ. Depending on the specific material to be formed, one of ordinary skill in the art may select a technique for depositing or growing the material. Removal of the material may be accomplished by any suitable technique, including but not limited to etching, grinding planarization (e.g., chemical mechanical planarization), or other known methods, unless the context indicates otherwise.

[0019] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" refer to the major plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in which or on which one or more structures and / or features are formed, and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of a substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0020] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses to the extent that a given parameter, property, or condition is satisfied with a certain degree of variation (such as within an acceptable tolerance) as would be understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0021] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes numerical values ​​and the degree of variance of the numerical value that will be understood by a person of ordinary skill in the art to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0022] As used herein, spatially relative terms (e.g., "under," "below," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," "right," etc.) may be used for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. Unless otherwise indicated, spatially relative terms are intended to encompass different orientations of materials other than the orientation depicted in the drawings. For example, if the material in the drawings is inverted, an element described as being "under" or "below" or "below" or "below" or at its "bottom" of other elements or features will be oriented as being "above" or at its "top" of other elements or features. Thus, the term "below" may include both above and below orientations, depending on the context in which the term is used, which is apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.), and the spatially relative descriptors used herein are interpreted accordingly.

[0023] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality, but is not necessarily limited to memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory in the form of DRAM, NAND, etc., but also, by way of example only, includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device that combines logic and memory, or a graphics processing unit (GPU) that incorporates memory.

[0024] According to embodiments described herein, a microelectronic device includes a stacked structure including alternating conductive structures and insulating structures arranged in layers, each of the layers including a conductive structure and an insulating structure. A memory cell string may extend through the stacked structure and may include, for example, a channel material extending through the stacked structure. The memory cells of the memory cell string may be located at the intersection between the conductive structure and the channel material, and adjacent memory cells of each string are separated from each other by one of the insulating structures. In some embodiments, the string may include strings that are laterally aligned with each other and other strings that are at least laterally offset from each other. In some embodiments, the string may be arranged in a woven pattern. Another stacked structure may vertically overlie the stacked structure and the memory cell string, and may include a contact structure for providing electrical communication between a conductive line (e.g., an access line) and a corresponding string of memory cells. Other stacked structures may include pillars, the pillars including a channel material on each of the memory cell strings vertically overlaid on the stacked structure. In some embodiments, the channel material of the pillars is substantially aligned with the channel material of the memory cell string. The contact structure can include a lateral dimension (e.g., area, cross-sectional area) that is greater than the lateral dimension of the pillar and can facilitate improved formation (e.g., alignment) of the contact structure to the memory cell string. The increased lateral dimension can facilitate forming an electrical connection to the contact structure and, in turn, to the associated memory cell string.

[0025] A microelectronic device may be formed by forming a first pillar including a channel material extending through a stacked structure and forming another stacked structure on the stacked structure. The stacked structure may include a layer including alternating insulating structures and other insulating structures. Another stacked structure may include an alternating insulating structure and a sacrificial structure. The sacrificial structure may be configured to be replaced with a conductive material to form a conductive structure. In some embodiments, the sacrificial structure includes polysilicon. A second pillar including a channel material may be formed to pass through another stacked structure and on the first pillar and laterally aligned with the first pillar. The channel material of the second pillar may be electrically connected to the channel material of the first pillar. In some embodiments, the channel material is substantially continuous through the first pillar and the second pillar. The second pillar may be at least partially filled with an insulating material. The sacrificial material may be formed on the insulating material and may fill the remaining portion of the second pillar. After forming the sacrificial material, at least a portion (e.g., an upper portion) of the sacrificial material may be removed and replaced with a conductive material. In some embodiments, the sacrificial material is directly converted into a conductive material. In other embodiments, the sacrificial material is removed, for example, by etching, and a conductive material is formed on the remaining portion of the sacrificial material. The conductive material may form a seed material upon which additional conductive material may be grown to increase the size (eg, lateral size, such as cross-sectional area) of the conductive material and form a self-aligned conductive contact having a larger size than the first pillar or the second pillar.

[0026] After forming the conductive contact, a portion of another stacked structure between adjacent pillars may be removed to form a select gate structure groove. In addition, a portion of another stacked structure located between adjacent second pillar groups may be removed to form an additional groove. After forming the select gate structure groove and the additional groove, the sacrificial structure may be replaced (e.g., converted or removed and replaced) by a conductive material passing through the select gate structure groove and the additional groove to form a conductive structure. For example, the sacrificial structure may be converted to a conductive material. In other embodiments, the sacrificial structure is removed, for example, by etching, and a conductive material is formed at a position corresponding to the sacrificial structure to form a conductive structure. After forming the conductive structure, the select gate structure groove and the additional groove may be filled with a dielectric material. A replacement gate groove may be formed through another stacked structure and the stacked structure. Other insulating structures of the stacked structure may be removed, for example, by wet etching. After removing the other insulating structures, a conductive structure may be formed at a position corresponding to the other insulating structures to form a memory cell string, each memory cell being located at the intersection between the conductive structure and the channel material. The conductive contact structure may be electrically connected to a conductive line (e.g., an access line, a bit line, a digit line) to electrically couple the memory cell string to the conductive line.

[0027] The increased area of ​​the conductive contact can facilitate forming an electrical connection between the conductive line and the conductive contact without having to reposition or shift the conductive contact relative to the memory cell string. In addition, compared to conventional microelectronic devices in which the conductive contact is formed after replacing the other insulating structure with the conductive structure, forming the conductive contact before replacing the other insulating structure can help improve the alignment between the conductive contact and the second pillar and the associated memory cell string. For example, replacing the other insulating structure with the conductive structure may undesirably cause bending (also known as "block bending") of the microelectronic device (e.g., a stacked structure), which increases the difficulty of forming the conductive contact to the memory cell string. However, forming the conductive contact before replacing the other insulating structure with the conductive structure and forming the conductive contact to have an increased size can help improve the alignment of the conductive contact with the memory cell string.

[0028] Figures 1A to 1N A method of forming a microelectronic device structure according to an embodiment of the present disclosure is shown. Figure 1A is a simplified cross-sectional view of a microelectronic device structure 100 according to an embodiment of the present disclosure. Figure 1B yes Figure 1A 1 is a top view of a microelectronic device structure 100 . Figure 1A The cross section is along Figure 1B The microelectronic device structure 100 may include a stacked structure 101 including insulating structures 104 and other insulating structures 106 in a vertical (e.g., in the Z direction) alternating order arranged in layers 102. Each of the layers 102 may individually include a level of insulating structure 104 that is directly vertically adjacent to a level of other insulating structure 106. The insulating structures 104 of the stacked structure 101 may also be referred to herein as “insulating materials,” and the other insulating structures 106 of the stacked structure 101 may also be referred to herein as “other insulating materials.”

[0029] In some embodiments, the number (e.g., quantity) of layers 102 of the stacked structure 101 may be in the range of 32 to 256 of the layers 102. In some embodiments, the stacked structure 101 includes 128 layers 102. However, the present disclosure is not limited thereto, and the stacked structure 101 may include a different number of layers 102. Furthermore, in some embodiments, the stacked structure 101 includes a first deck structure that vertically covers the source structure 107 and includes a layer 102 of an insulating structure 104 and other insulating structures 106, and a second deck structure on the first deck structure, the second deck structure including a layer 102 of the insulating structure 104 and other insulating structures 106. For example, the stacked structure 101 may include a dual-deck 3D NAND device (e.g., a 3D NAND flash memory device).

[0030] The layers of the insulating structure 104 may be formed of, for example, at least one dielectric material and include at least one dielectric material, such as one or more oxide materials (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), and aluminum oxide (Al2O3)). In some embodiments, the insulating structure 104 is formed of and includes silicon dioxide.

[0031] The levels of the other insulating structures 106 may be formed of and include an insulating material that is different from the insulating structure 104 and exhibits an etching selectivity relative to the insulating structure. In some embodiments, the other insulating structures 106 are formed of and include a nitride material (e.g., silicon nitride (Si3N4)) or an oxynitride material (e.g., silicon oxynitride). In some embodiments, the other insulating structures 106 include silicon nitride.

[0032] The stacked structure 101 may be formed on a source structure 107 (e.g., a source plate). The source structure 107 may be formed of and include a semiconductor material such as one of a P-type conductive material (e.g., polysilicon doped with at least one P-type dopant (e.g., boron ions)) or an N-type conductive material (e.g., polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorus ions, antimony ions)). Figure 1A The stack structure 101 is described and illustrated as including the stack structure 101 directly on (e.g., on) the source structure 107, but the disclosure is not limited thereto. In other embodiments, the stack structure 101 is overlaid on a deck structure that includes an additional layer 102 of insulating structure 104 and other insulating structures 106 separated from the stack structure 101 by at least one dielectric material.

[0033] Dielectric material 108 may be disposed on the uppermost layer of layer 102. Dielectric material 108 may be formed of and include an electrically insulating material, such as one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, dielectric material 108 includes the same material composition as insulating structure 104. In some embodiments, dielectric material 108 includes silicon dioxide.

[0034] The pillars 110 of material may extend vertically (e.g., in the Z direction) through the stacked structure 101. As will be described herein, the material of the pillars 110 may form a memory cell (e.g., a string of NAND memory cells). The pillars 110 may each individually include an insulating material 112, a dielectric material 114 horizontally adjacent to the insulating material 112, a channel material 116 horizontally adjacent to the insulating material 112, a tunnel dielectric material (also referred to as a "tunneling dielectric material") 118 horizontally adjacent to the channel material 116, a memory material 120 horizontally adjacent to the tunnel dielectric material 118, and a dielectric blocking material (also referred to as a "charge blocking material") 122 horizontally adjacent to the memory material 120. The dielectric blocking material 122 may be horizontally adjacent to one of the levels of the other insulating structures 106 of one of the layers 102 of the stacked structure 101. The dielectric material 114 may be horizontally inserted between the insulating material 112 and the channel material 116; the channel material 116 may be horizontally inserted between the dielectric material 114 and the tunnel dielectric material 118; the tunnel dielectric material 118 may be horizontally inserted between the channel material 116 and the memory material 120; the memory material 120 may be horizontally inserted between the tunnel dielectric material 118 and the dielectric barrier material 122; and the dielectric barrier material 122 may be horizontally inserted between the memory material 120 and a level of another insulating structure 106.

[0035] The insulating material 112 may be formed of an electrically insulating material and include an electrically insulating material such as phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), oxynitrides (e.g., silicon oxynitride), dielectric carbonitride materials (e.g., silicon carbonitride (SiCN)), dielectric carbon oxynitride materials (e.g., silicon carboxynitride (SiOCN)), or combinations thereof. In some embodiments, the insulating material 112 includes silicon dioxide.

[0036] Dielectric material 114 may be formed from and include one or more of the materials described above with reference to insulating material 112. In some embodiments, dielectric material 114 includes the same material composition as insulating material 112. In some embodiments, dielectric material 114 includes silicon dioxide.

[0037] The channel material 116 may be formed of and include one or more of a semiconductor material (at least one elemental semiconductor material, such as polysilicon; at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials) and an oxide semiconductor material. In some embodiments, the channel material 116 includes amorphous silicon or polysilicon. In some embodiments, the channel material 116 includes a doped semiconductor material.

[0038] The tunnel dielectric material 118 may be formed of and include a dielectric material through which charge tunneling may be performed under appropriate electrical bias conditions, such as by hot carrier injection or by charge transfer caused by Fowler-Nordheim tunneling. As non-limiting examples, the tunnel dielectric material 118 may be formed of and include one or more of silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In some embodiments, the tunnel dielectric material 118 includes silicon dioxide. In other embodiments, the tunnel dielectric material 118 includes silicon oxynitride.

[0039] The memory material 120 may include a charge trapping material or a conductive material. The memory material 120 may be formed of and include one or more of silicon nitride, silicon oxynitride, polysilicon (doped polysilicon), conductive materials (tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and alloys thereof, or metal silicides (e.g., tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide or combinations thereof), semiconductor materials polycrystalline or amorphous semiconductor materials (including at least one element semiconductor element or at least one compound semiconductor material), conductive nanoparticles (e.g., ruthenium nanoparticles), metal dots. In some embodiments, the memory material 120 includes silicon nitride.

[0040] The dielectric barrier material 122 may be formed of and include a dielectric material such as one or more of an oxide (eg, silicon dioxide), a nitride (silicon nitride), and an oxynitride (silicon oxynitride), or another material. In some embodiments, the dielectric barrier material 122 includes silicon oxynitride.

[0041] In some embodiments, tunnel dielectric material 118, memory material 120, and dielectric barrier material 122 together may include a structure configured to trap charge, such as an oxide-nitride-oxide (ONO) structure. In some such embodiments, tunnel dielectric material 118 includes silicon dioxide, memory material 120 includes silicon nitride, and dielectric barrier material 122 includes silicon dioxide.

[0042] refer to Figure 1B , the pillars 110 may include some pillars 110 that are aligned with each other (e.g., in the Y direction) and pillars 110 that are offset from each other (e.g., in the Y direction). Thus, the pillars 110 may be arranged in a so-called weaving pattern (e.g., a hexagonal close-packed arrangement), which may facilitate an increased density of the pillars 110 (and the resulting memory cell string) in the stacked structure 101.

[0043] refer to Figure 1C After forming pillar 110, a portion of pillar 110 may be removed to recess pillar 110 relative to the uppermost surface of dielectric material 108. In some embodiments, channel material 124 may be formed within the recess and electrically connected to channel material 116. Channel material 124 may include one or more of the materials described above with reference to channel material 116. In some embodiments, channel material 124 includes the same material composition as channel material 116. Because channel material 124 may include the same material composition as channel material 116, as used herein, channel material 116 may refer to channel material 116. Figure 1A Both channel material 116 and channel material 124 are depicted.

[0044] Continue to refer Figure 1C , after forming the channel material 124, another dielectric material 126 may be formed on the insulating material 112 and on the channel material 124 and within the remaining portion of the recess adjacent to the channel material. The other dielectric material 126 may include one or more of the materials described above with reference to the dielectric material 114. In some embodiments, the other dielectric material 126 includes silicon dioxide. Because the other dielectric material 126 may include the same material composition as the dielectric material 114, as used herein, the dielectric material 114 may be used to refer to both the dielectric material 114 and the other dielectric material 126.

[0045] refer to Figure 1D , before forming the additional channel material 124 ( Figure 1C ) and other dielectric materials 126 ( Figure 1C ), another stack structure 105 may be formed on the stack structure 101. The another stack structure 105 may include alternating levels of insulating structures 104 and sacrificial structures 128 formed on the etch stop material 125. Figure 1E yes Figure 1D FIG. 1 is a simplified top view of a microelectronic device structure 100 .

[0046] The etch stop material 125 may be formed of and include, for example, a material exhibiting an etch selectivity with respect to the insulating structure 104 and the sacrificial structure 128. In some embodiments, the etch stop material 125 includes a carbon-containing material such as silicon carbonitride (SiCN).

[0047] The sacrificial structure 128 may be formed of and include a sacrificial material having a different etch selectivity than the insulating structure 104. The sacrificial material of the sacrificial structure 128 may, for example, be selectively etched relative to the electrically insulating material of the insulating structure during mutual exposure to an etchant. As non-limiting examples, the sacrificial structure 128 may be formed of and include silicon, doped silicon, polysilicon, doped polysilicon, or silicon nitride. In embodiments where the sacrificial structure 128 is doped, the dopant may include at least one N-type dopant (e.g., one or more of phosphorus (P), arsenic (Ar), antimony (Sb), and bismuth (Bi)), at least one P-type dopant (e.g., one or more of boron (B), aluminum (Al), and gallium (Ga)), carbon (C), fluorine (F), chlorine (Cl), bromine (Br), hydrogen (H), deuterium ( 2 In some embodiments, the sacrificial structure 128 includes polysilicon.

[0048] After forming another stacked structure 105, an opening may be formed through another stacked structure 105 to expose a portion of the pillar 110 of the stacked structure 101. After forming the opening, a liner material 130 may be formed on a surface (e.g., a sidewall) of the opening. In some embodiments, after forming the liner material 130, a laterally extending portion of the liner material 130 may be removed, for example, by dry etching (e.g., reactive ion etching (RIE)).

[0049] The liner material 130 may be formed of and include, for example, an insulating material, such as one or more of the materials described above with reference to the dielectric material 114. In some embodiments, the liner material 130 includes silicon dioxide.

[0050] After forming the liner material 130, the channel material 132 may be formed on the side of the liner material 130 and in contact with the channel material 116. The channel material 132 may include one or more of the same materials described above with reference to the channel material 116. In some embodiments, the channel material 132 includes the same material composition as the channel material 116. In some embodiments, the channel material 132 may be continuous with the channel material 116. In some such embodiments, the channel material 132 in the stacked structure 105 may be substantially laterally aligned with the channel material 116 within the pillars 110 of the stacked structure 101 (e.g., in the X direction, in the Y direction, or both). Since the channel material 132 may include the same material composition as the channel material 116, as used herein, the channel material 116 refers to the channel material 116 and the channel material 132.

[0051] After forming channel material 132, portions of the opening may be filled with insulating material 134. Insulating material 134 may be formed of and include one or more of the materials described above with reference to dielectric material 114. In some embodiments, insulating material 134 includes the same material composition as dielectric material 114. In some embodiments, insulating material 134 includes silicon dioxide.

[0052] Continue to refer Figure 1D , a sacrificial material 136 may be formed on the insulating material 134. The sacrificial material 136 may include one or more of the materials described above with reference to the sacrificial structure 128. In some embodiments, the sacrificial material 136 includes the same material composition as the sacrificial structure 128. In some embodiments, the sacrificial material 136 includes polysilicon.

[0053] The liner material 130, channel material 132, insulating material 134, and sacrificial material 136 within the further stacked structure 105 may include pillars 135. The pillars 135 may be substantially laterally aligned with the pillars 110 of the stacked structure 101 (eg, in the X direction and in the Y direction).

[0054] The microelectronic device structure 100 may be exposed to a chemical mechanical planarization (CMP) process to remove portions of the liner material 130 , the channel material 132 , the insulating material 134 , and the sacrificial material 136 from the uppermost surface of the insulating structure 104 .

[0055] refer to Figure 1F , a portion of the sacrificial material 136 may be replaced with a conductive material 138 to form a contact structure (also referred to herein as a “conductive contact structure” or “conductive contact structure”) 140 including the conductive material 138. In some embodiments, a portion of the sacrificial material 136 may be removed, for example, by exposing a portion of the sacrificial material 136 to one or more etchants (e.g., a dry etchant) to selectively remove the sacrificial material 136 and recess the sacrificial material 136 relative to the uppermost insulating structure 104.

[0056] In other embodiments, a portion of the sacrificial material 136 is converted into a conductive material 138. As a non-limiting example, the sacrificial material 136 may be treated with one or more chemicals that promote the conversion of the sacrificial material 136 (e.g., silicon material, polysilicon material) into tungsten (e.g., β-phase tungsten, α-phase tungsten). As a non-limiting example, if the sacrificial material 136 includes a doped silicon material, such as doped polysilicon, the sacrificial material 136 may be treated with tungsten hexafluoride (WF6) to form the conductive material 138. In some such embodiments, the silicon (Si) of the sacrificial material 136 may react with the WF6 to produce tungsten (W) and silicon tetrafluoride (SiF4). The produced SiF4 is removed as a gas. The produced W remains with any dopant of the sacrificial material 136 to form the conductive material 138. The sacrificial material 136 may be treated with WF6 at a temperature in the range of about 200° C. to about 500° C., for example, using conventional CVD equipment.

[0057] In some embodiments, the conductive material 138 includes tungsten. In some embodiments, the conductive material 138 includes β-phase tungsten. The β-phase tungsten has a metastable A15 cubic structure. The grains of the β-phase tungsten may have a generally columnar shape. The tungsten contained in the conductive material 138 may exist only in the β-phase, or may exist in the β-phase and the α-phase. If present, the α-phase tungsten has a metastable body-centered cubic structure. The grains of the α-phase tungsten may have a generally equidistant shape. If the conductive material 138 contains β-phase tungsten and α-phase tungsten, the amount of β-phase tungsten contained in the conductive material 138 may be different from the amount of α-phase tungsten contained in the conductive material 138, or may be substantially the same as the amount of α-phase tungsten contained in the conductive material 138. In some embodiments, the amount of β-phase tungsten contained in the conductive material 138 is greater than the amount of α-phase tungsten contained in the conductive material 138. For example, at least a majority (e.g., greater than 50%, such as greater than or equal to about 60%, greater than or equal to about 70%, greater than or equal to about 80%, greater than or equal to about 90%, greater than or equal to about 95%, or greater than or equal to about 99%) of the tungsten contained in the conductive material 138 may exist in the β phase. In embodiments where the sacrificial material 136 includes one or more dopants, the conductive material 138 may include tungsten and the one or more dopants.

[0058] See also Figure 1G and Figure 1H, the conductive material 138 within the pillar 135 can be used as a seed material to form additional conductive material 139 and increase the size of the contact structure 140. In some embodiments, the additional conductive material 139 grows asymmetrically. In some such embodiments, the lateral dimension of the additional conductive material 139 (e.g., in the X direction, in the Y direction, or both) can grow faster than the vertical dimension (e.g., in the Z direction). Growing the additional conductive material 139 can form a conductive material having a lateral dimension (in the X direction, in the Y direction, or both) that is larger than the pillar 135. Therefore, the contact area of ​​the contact structure 140 can be increased relative to the size of the pillar 135. In some embodiments, the additional conductive material 139 extends vertically above the pillar 135. In other words, the additional conductive material 139 (and the associated contact structure 140) extends vertically above the highest level of the insulating structure 104.

[0059] The contact structure may have a dimension D (e.g., diameter) in the range of about 100 nm to about 150 nm, such as about 100 nm to about 110 nm, about 110 nm to about 120 nm, about 120 nm to about 130 nm, or about 130 nm to about 150 nm. In some embodiments, the dimension is about 100 nm. In other embodiments, the dimension is greater than about 100 nm, such as greater than about 120 nm. However, the present disclosure is not limited thereto, and the dimension D may be different from the described dimensions.

[0060] The additional conductive material 139 may include the same material composition as the conductive material 138. In some embodiments, the additional conductive material 139 includes tungsten.

[0061] In some embodiments, the conductive material 138 is exposed to one or more of CVD, ALD, PVD, PECVD, and LPCVD to grow the additional conductive material 139. The additional conductive material 139 may be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD).

[0062] The conductive material 138 may be exposed to tungsten hexafluoride (WF6), disilane (Si2H6), hexacarbonyl tungsten (W(CO6)), bis(tert-butylimino)bis(tert-butylamino)tungsten ((C4H9NH2)W(C4H9N)2), bis(tert-butylimino)bis(dimethylamino)tungsten (VI) (((CH3)3CN)2W(N(CH3)2)2), bis(cyclopentadienyl) dihydride tungsten (IV) (C 10 H 12W) or another tungsten precursor to grow the additional conductive material 139. In some embodiments, the additional conductive material 139 is formed by sequentially exposing the conductive material 138 to WF6 and Si2H6.

[0063] See also Fig. 1I After the additional conductive material 139 is grown, a select gate structure trench (eg, slit) 142 and an additional trench (eg, slit) 144 may be formed through the further stacked structure 105 . Figure 1J yes Fig. 1I 1 is a top view of a microelectronic device structure 100 . Fig. 1I The cross section is along Figure 1J The section line II is taken.

[0064] refer to Fig. 1I and Figure 1J , a select gate structure trench 142 and an additional trench 144 may be formed through the further stacked structure 105 and expose a portion of the etch stop material 125. The select gate structure trench 142 and the additional trench 144 may be formed by, for example, exposing the microelectronic device structure 100 to one or more etchants to selectively remove the insulating structure 104 and the sacrificial structure 128 without substantially removing the conductive material 138 of the contact structure 140.

[0065] The select gate structure trench 142 can be formed between adjacent (eg, in the X-direction and the Y-direction) contact structures 140. The select gate structure trench 142 can extend in the X-direction along the length of the microelectronic device structure 100. Figure 1J In some embodiments, approximately half of each of the contact structures 140 may overlie the select gate structure trench 142, and approximately half of each of the contact structures 140 may overlie the rest of the microelectronic device structure 100 (e.g., the insulating structure 104). In other words, approximately half of each of the contact structures 140 may be laterally aligned with the select gate structure trench 142 (e.g., in the X direction, in the Y direction, or in both), and approximately the other half of each of the contact structures 140 may not be aligned with the select gate structure trench 142. In some such embodiments, forming the select gate structure trench 142 may include forming a plurality of contact structures 140 and associated pillars 135 ( Fig. 1I ) and pillar 110( Fig. 1I ) to form a selection gate structure groove 142.

[0066] The width W1 of the select gate structure groove 142 can be in the range of about 30 nm to about 150 nm, such as about 30 nm to about 50 nm, about 50 nm to about 75 nm, about 75 nm to about 100 nm, or about 100 nm to about 150 nm. In some embodiments, the width W1 is about 100 nm. In other embodiments, the width W1 is greater than about 100 nm. However, the present disclosure is not limited thereto, and the width W1 can be different from the described width.

[0067] Continue to refer Fig. 1I and Figure 1J , can be between adjacent selection gate structure grooves 142 (eg, in the Y direction) and between adjacent pillars 135 groups ( Fig. 1I ) form additional grooves 144. For example, the additional grooves 144 can divide the microelectronic device structure 100 into blocks 143, each block 143 including the first group of pillars 135 and the contact structure 140.

[0068] The width W2 of the additional groove 144 may be in a range from about 100 nm to about 400 nm, for example, from about 100 nm to about 200 nm, from about 200 nm to about 300 nm, or from about 300 nm to about 400 nm. In some embodiments, the width W2 of the additional groove 144 may be greater than the width W1 of the select gate structure groove 142. In some embodiments, the width W2 is about 200 nm to about 300 nm. However, the present disclosure is not limited thereto, and the width W2 of the additional groove 144 may be different from the described width.

[0069] refer to Figure 1K , through the selection gate structure groove 142 and the additional groove 144, the sacrificial structure 128 ( Fig. 1I ) may be at least partially replaced by conductive structure 146. Sacrificial structure 128 may be at least partially removed as described above with reference to the removal of sacrificial material 136. For example, sacrificial structure 128 may be removed by exposing sacrificial structure 128 to one or more etchants (e.g., dry etchants) to selectively remove the sacrificial material relative to insulating structure 104 and recess sacrificial structure 128.

[0070] In other embodiments, the sacrificial structure 128 is at least partially converted to a conductive material to form the conductive structure 146. As a non-limiting example, the sacrificial structure 128 may be treated with one or more chemicals that promote the conversion of the sacrificial structure 128 (e.g., silicon material, polysilicon material) into tungsten (e.g., β-phase tungsten, α-phase tungsten), as described above with reference to the conversion of the sacrificial material 136 to the conductive material 138. As a non-limiting example, if the sacrificial structure 128 includes a doped silicon material, such as doped polysilicon, the sacrificial structure 128 may be treated with tungsten hexafluoride (WF6) to form the conductive structure 146. In some such embodiments, the silicon (Si) of the sacrificial structure 128 may react with the WF6 to produce tungsten (W) and silicon tetrafluoride (SiF4). The produced SiF4 is removed as a gas. The produced W retains any dopants of the sacrificial structure 128 to form the conductive structure 146. The sacrificial structure 128 may be treated with WF6 at a temperature in the range of about 200° C. to about 500° C., for example, using conventional CVD equipment.

[0071] In some embodiments, the conductive structure 146 is formed in substantially the same manner as the conductive material 138 that forms the contact structure 140 .

[0072] In some embodiments, the conductive structure 146 includes tungsten. In some embodiments, the conductive structure 146 includes the same material composition as the contact structure 140. In some embodiments, for example, where the sacrificial structure 128 includes polysilicon, forming the conductive structure 146 may include converting the polysilicon of the sacrificial structure 128 into a conductive structure 146 including tungsten.

[0073] Conductive structure 146 may include a so-called select gate structure (eg, a select drain structure (SDS)). As will be described herein, conductive structure 146 may be used to select memory cells of a particular string of memory cells. Figure 1K Four conductive structures 146 are shown, but the present disclosure is not limited in this regard. The microelectronic device structure 100 can include any number of conductive structures 146, such as less than four conductive structures 146 (e.g., one conductive structure 146, two conductive structures 146, three conductive structures 146) or more than four conductive structures 146 (e.g., five conductive structures 146, six conductive structures 146, seven conductive structures 146, eight or more conductive structures 146).

[0074] refer to Figure 1L, after the conductive structure 146 is formed through the select gate structure trench 142 and the additional trench 144, the select gate structure trench 142 and the additional trench 144 may be filled with a dielectric material 148. In some embodiments, the dielectric material 148 is formed on the uppermost insulating structure 104. The dielectric material 148 may cover and substantially surround the contact structure 140. In some embodiments, the dielectric material 148 extends into and through another stacked structure 105. For example, the dielectric material 148 may be located between adjacent conductive contact structures 140 (between the select gate structure trench 142 ( Fig. 1I , Figure 1J )'s position corresponds to the position of ).

[0075] Dielectric material 148 may be formed of and include an electrically insulating material, such as one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, dielectric material 148 includes silicon dioxide.

[0076] refer to Figure 1M After forming the dielectric material 148, a replacement gate trench 150 may be formed at a position corresponding to the additional trench 144. The replacement gate trench 150 may extend through the further stacked structure 105 and the stacked structure 101. In some embodiments, the replacement gate trench 150 exposes a portion of the source structure 107.

[0077] After forming the replacement gate trench 150, the other insulating structures 106 of the stacked structure 101 may be removed through the replacement gate trench 150 as part of a so-called "replacement gate" or "gate last" process. As a non-limiting example, the other insulating structures 106 may be removed by exposing the other insulating structures 106 to a wet etchant including one or more of phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or another material. In some embodiments, the other insulating structures 106 are removed by exposing the other insulating structures 106 to a so-called "wet nitride strip" including a wet etchant containing phosphoric acid.

[0078] refer to Figure 1N , after removing other insulating structures 106 ( Figure 1L ), a conductive structure 152 may be formed between adjacent insulating structures 104 at positions corresponding to positions of other insulating structures 106 to form a microelectronic device 100 including a stacked structure 101 including layers 156 of alternating levels of insulating structures 104 and conductive structures 152.

[0079] The conductive structure 152 may be formed of a conductive material and include a conductive material, such as at least one conductive material, such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, metal-containing materials (such as metal nitrides, metal silicides, metal carbides, metal oxides), including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof, conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, other materials exhibiting conductivity, or combinations thereof. In some embodiments, conductive structure 152 includes tungsten. In some embodiments, conductive structure 152 includes a different material composition than contact structure 140 and conductive structure 146.

[0080] In some embodiments, the conductive structure 152 may include a conductive liner material surrounding the conductive structure 152, for example, between the conductive structure 152 and the insulating structure 104. The conductive liner material may include, for example, a seed material that may form the conductive structure 152. The conductive liner material may be formed of, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material and include the material. In some embodiments, the conductive liner material includes titanium nitride.

[0081] After forming the conductive structure 152, the replacement gate trench 150 may be filled with a dielectric material 158. The dielectric material 158 may extend through the other stacked structure 105 and the stacked structure 101. In addition, the dielectric material 158 may be located between adjacent blocks 143 ( Figure 1J ).

[0082] Dielectric material 158 may be formed of and include one or more of the materials described above with reference to dielectric material 148. For example, dielectric material 158 may be formed of and include one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, dielectric material 158 includes the same material composition as dielectric material 148. In some embodiments, dielectric material 158 includes silicon dioxide.

[0083] The formation of conductive structure 152 can form a string 160 of memory cells 162 located at the intersection of channel material 116 and conductive structure 152. Vertically adjacent memory cells 162 of string 160 can be separated from each other by one of the levels of insulating structure 104.

[0084] Fig.1O yes Figure 1N A simplified enlarged view of the box O of FIG. Figure 1A One of the memory cells 162. Reference Fig.1O and Figure 1A , each memory cell 162 may include an insulating material 112, a dielectric material 114 horizontally adjacent to the insulating material 112, a channel material 116 horizontally adjacent to the insulating material 112, a tunnel dielectric material 118 horizontally adjacent to the channel material 116, a memory material 120 horizontally adjacent to the tunnel dielectric material 118, and a dielectric barrier material 122 horizontally adjacent to the memory material 120. The dielectric barrier material 122 may be horizontally adjacent to one of the levels of the conductive structure 152. The channel material 116 may be horizontally inserted between the insulating material 112 and the tunnel dielectric material 118; the tunnel dielectric material 118 may be horizontally inserted between the channel material 116 and the memory material 120; the memory material 120 may be horizontally inserted between the tunnel dielectric material 118 and the dielectric barrier material 122; and the dielectric barrier material 122 may be horizontally inserted between the memory material 120 and the level of the conductive structure 152. Conductive liner material 153 (not shown for clarity) Figure 1N ) may be located between the conductive structure 152 and the insulating structure 104. As described above, the conductive structure 152 may include one or more of a metal (eg, titanium, tantalum), a metal nitride (eg, tungsten nitride, titanium nitride, tantalum nitride).

[0085] After forming the dielectric material 158, the microelectronic device structure 100 can be completed by, for example, forming a conductive line (e.g., an access line, such as a bit line or a digit line) in electrical communication with the contact structure 140. In some embodiments, the conductive line is formed directly on the contact structure 140. Because the contact structure 140 includes the additional conductive material 139 and has an area greater than the area of ​​the pillar 135, the contact structure 140 can facilitate the formation of a conductive line aligned with the contact structure 140 and the string 160 of the memory cell 162 located directly above the pillar 135. Forming the contact structure 140 by growing the additional conductive material 139 from the conductive material 138 can form a self-aligned contact aligned with the memory string 160. The contact structure 140 can be formed without masking materials and photolithography techniques to align the contact structure 140 with the pillar 135 or with the string 160.

[0086] In addition, when forming the replacement gate trench 150 ( Figure 1M ) and before using the conductive structure 152 ( Figure 1N ) replaces the insulating structure 104 ( Figure 1L) can facilitate improved alignment between the contact structure 140 and the string 160 of memory cells 162. In comparison, during conventional fabrication of microelectronic device structures, the conductive structure (e.g., conductive structure 152) can be formed before the contact structure (e.g., contact structure 140) is formed. However, the formation of the conductive structure may induce stress in the stack structure 101 and the further stack structure 105, resulting in so-called "block bowing". The block bowing may cause the upper portion of the stack structure to be laterally offset from the lower portion of the stack structure, thereby increasing the difficulty of contact alignment for forming contacts with the memory cell string and the access line.

[0087] Although it has Figure 1N and Fig.1O The memory cell 162 is described and illustrated as including various materials, but the present disclosure is not limited thereto. Figure 1P FIG. 1 is a simplified enlarged view of a memory cell 170 according to an embodiment of the present disclosure. The memory cell 170 may be replaced Figure 1N One or more of the memory cells 162. Figure 1P , memory cell 170 may include insulating material 112 and channel material 116 as described above with reference to memory cell 162. Memory cell 170 may further include a first dielectric material (e.g., tunnel dielectric material) 172 horizontally adjacent to channel material 116, a second dielectric material (e.g., charge trapping material) 174 horizontally adjacent to first dielectric material 172, and a third dielectric material (e.g., charge blocking material) 176 horizontally adjacent to second dielectric material 174 and conductive structure 152. In some embodiments, first dielectric material 172 includes an oxide material (e.g., silicon dioxide), second dielectric material 174 includes a nitride material (e.g., silicon nitride), and third dielectric material 176 includes an oxide material (e.g., silicon dioxide).

[0088] although Fig.1O and Figure 1P The memory cells 162, 170 have been illustrated and described as having a particular configuration, but the present disclosure is not limited thereto. In other embodiments, the memory cells 162, 170 may comprise suitable memory cells that may form part of a NAND string, for example.

[0089] Figure 2 A partial cross-sectional perspective view of a portion of a microelectronic device 201 (eg, a memory device such as a dual-deck 3D NAND flash memory device) including a microelectronic device structure 200 is shown. The microelectronic device structure 200 may be substantially similar to the previously described microelectronic device structure 201 of FIG. Figures 1A to 1N The microelectronic device structure 100 is described. Figure 2As shown, the microelectronic device structure 200 may include a stepped structure 220, which defines a step for connecting the access line 206 to the conductive layer 205 (eg, a conductive layer, a conductive plate, such as the conductive structure 152 ( Figure 1N )) contact regions. The microelectronic device structure 200 may include memory cells 203 (eg, memory cells 162 ( Figure 1N , Fig.1O ), memory unit 170 ( Figure 1P )) of the vertical string 207 (e.g., string 160 ( Figure 1N )). The vertical strings 207 may extend vertically (eg, in the Z direction) and orthogonally to the conductive lines and layers 205, such as the data lines 202, the source layers 204 (eg, the source structures 107 ( Figure 1N )), conductive layer 205, access line 206, first selection gate 208 (eg, upper selection gate, drain selection gate (SGD), such as conductive structure 146 ( Figure 1N )), select line 209 and second select gate 210 (e.g., lower select gate, source select gate (SGS)). Select gate 208 can be horizontally divided (e.g., in the Y direction) into grooves 230 (e.g., formed in replacement gate grooves 150 ( Figure 1M ) in the dielectric material 158) are horizontally separated from each other (eg, in the Y direction) by a plurality of blocks 232 (eg, blocks 143 ( Figure 1J )).

[0090] As shown, vertical conductive contacts 211 can electrically couple components to each other. For example, the selection line 209 can be electrically coupled to the first selection gate 208, and the access line 206 can be electrically coupled to the conductive layer 205. The microelectronic device 201 can also include a control unit 212 located below the memory array, and the control unit can include at least one of a string driver circuit system, a transmission gate, a circuit system for a selection gate, a circuit system for selecting a conductive line (e.g., a data line 202, an access line 206), a circuit system for amplifying a signal, and a circuit system for sensing a signal. For example, the control unit 212 can be electrically coupled to the data line 202, the source layer 204, the access line 206, the first selection gate 208, and the second selection gate 210. In some embodiments, the control unit 212 includes a CMOS (complementary metal oxide semiconductor) circuit system. In these embodiments, the control unit 212 is characterized by having a "CMOS under array" ("CuA") configuration.

[0091] The first select gates 208 may extend horizontally in a first direction (e.g., the X-direction) and may be coupled to a respective first set of vertical strings 207 of memory cells 203 at a first end (e.g., an upper end) of the vertical strings 207. The second select gates 210 may be formed in a substantially planar configuration and may be coupled to the vertical strings 207 of memory cells 203 at a second, opposite end (e.g., a lower end).

[0092] The data line 202 (e.g., a bit line) may extend horizontally in a second direction (e.g., a Y direction) at an angle (e.g., perpendicular) to the first direction in which the first selection gate 208 extends. The data line 202 may be coupled to a respective second group of vertical strings 207 at a first end (e.g., an upper end) of the vertical strings 207. The first group of vertical strings 207 coupled to the respective first selection gates 208 may share a particular vertical string 207 with the second group of vertical strings 207 coupled to the respective data line 202. Thus, a particular vertical string 207 may be selected at an intersection of a particular first selection gate 208 and a particular data line 202. Thus, the first selection gate 208 may be used to select a memory cell 203 of a string 207 of memory cells 203.

[0093] Conductive layers 205 (e.g., word line plates) may extend in respective horizontal planes. Conductive layers 205 may be stacked vertically such that each conductive layer 205 is coupled to all vertical strings 207 of memory cells 203, and the vertical strings 207 of memory cells 203 extend vertically through the stack of conductive layers 205. Conductive layers 205 may be coupled to or may form control gates of memory cells 203 coupled to conductive layers 205. Each conductive layer 205 may be coupled to one memory cell 203 of a particular vertical string 207 of memory cells 203.

[0094] The first select gate 208 and the second select gate 210 are operable to select a particular vertical string 207 of memory cells 203 between a particular data line 202 and the source layer 204. Thus, a particular memory cell 203 can be selected and electrically coupled to the data line 202 by operation (e.g., by selection) of the appropriate first select gate 208, second select gate 210, and conductive layer 205 coupled to the particular memory cell 203.

[0095] Step structure 220 may be configured to provide electrical connections between access lines 206 and layers 205 through vertical conductive contacts 211. In other words, a particular level of layer 205 may be selected via access lines 206 in electrical communication with corresponding conductive contacts 211 that are in electrical communication with the particular layer 205.

[0096] The data line 202 may be connected to a conductive contact structure 234 (eg, contact structure 140 ( Figure 1N)) is electrically coupled to the vertical string 207. As described above with reference Figure 1N As described above, the conductive contact structure 234 may present a relatively large area for forming an aligned contact between the data line 202 and the vertical string 207 of memory cells 203 .

[0097] Therefore, in some embodiments, a microelectronic device includes a stacked structure, the stacked structure including alternating conductive structures and insulating structures arranged in layers, each of the layers individually including a conductive structure and an insulating structure; a memory cell string that extends vertically through the stacked structure, the memory cell string including a channel material that extends vertically through the stacked structure; another stacked structure that vertically overlies the stacked structure and includes alternating levels of other conductive structures and other insulating structures, the other stacked structure including pillars that vertically overlie the memory cell string, each pillar including another channel material that is electrically connected to the channel material of the memory cell string; and a conductive contact structure that vertically overlies the other stacked structure, each conductive contact structure including a conductive contact that extends at least partially into the pillar and a portion that extends outside the pillar and has a larger cross-sectional area than the pillar.

[0098] Therefore, in some embodiments, a microelectronic device includes: a stacked structure comprising alternating layers of conductive structures and insulating structures; a memory cell string extending through the stacked structure, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the stacked structure; and a conductive contact structure electrically connected to the channel material of one of the memory cell strings, the conductive contact structure having a larger cross-sectional area than the at least one dielectric material and the channel material of the string.

[0099] Thus, in some embodiments, a method of forming a microelectronic device includes: forming a first stacked structure including alternating levels of insulating structures and other insulating structures; forming a first pillar including channel material extending through the first stacked structure; forming a second stacked structure on the first stacked structure, the second stacked structure including alternating levels of additional insulating structures and sacrificial structures; forming a second pillar through the second stacked structure, the second pillar including additional channel material extending vertically through the second pillar and electrically connected to the channel material of the first pillar; forming a conductive material in the second pillar; growing additional conductive material on the second pillar to form a conductive contact; and at least partially replacing the sacrificial structure with a conductive material.

[0100] Microelectronic devices including microelectronic devices (e.g., microelectronic device 201) and microelectronic device structures (e.g., microelectronic device structures 100, 200) including self-aligned contact structures 140 with increased dimensions may be used in embodiments of the electronic systems of the present disclosure. For example, Figure 3 303 is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet (e.g., or Tablets), electronic books, navigation devices, etc. The electronic system 303 includes at least one memory device 305. For example, the memory device 305 may include a microelectronic device structure previously described herein (e.g., microelectronic device structure 100, 200) or a microelectronic device structure previously described herein. Figures 1A to 1N and Figure 2 Embodiments of microelectronic devices (eg, microelectronic device 201 ) are described that include a self-aligned contact structure 140 having increased dimensions.

[0101] The electronic system 303 may further include at least one electronic signal processor device 307 (commonly referred to as a "microprocessor"). The electronic signal processor device 307 may optionally include an embodiment of a microelectronic device or microelectronic device structure previously described herein (e.g., previously described with reference to Figures 1A to 1N and Figure 2 The electronic system 303 may further include one or more input devices 309 for inputting information into the electronic system 303 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 309 and the output device 311 may include a single touch screen device, which may be used to input information to the electronic system 303 and output visual information to the user. The input device 309 and the output device 311 may be electrically connected to one or more of the memory device 305 and the electronic signal processor device 307.

[0102] refer to Figure 4, a processor-based system 400 is shown. The processor-based system 400 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures, including one or more of the microelectronic device 201 or the microelectronic device structures 100, 200). The processor-based system 400 may be any of various types, such as a computer, a pager, a cellular phone, a personal organizer, a control circuit, or other electronic device. The processor-based system 400 may include one or more processors 402 (e.g., microprocessors) to control system functions and processing of requests in the processor-based system 400. The processor 402 and other subcomponents of the processor-based system 400 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of the microelectronic device 201 or the microelectronic device structures 100, 200).

[0103] The processor-based system 400 may include a power source 404 in operable communication with the processor 402. For example, if the processor-based system 400 is a portable system, the power source 404 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. The power source 404 may also include an AC adapter; thus, for example, the processor-based system 400 may be plugged into a wall outlet. The power source 404 may also include a DC adapter so that the processor-based system 400 may be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0104] Depending on the functions performed by the processor-based system 400, various other devices can be coupled to the processor 402. For example, a user interface 406 can be coupled to the processor 402. The user interface 406 can include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touch screens, voice recognition systems, microphones, or combinations thereof. A display 408 can also be coupled to the processor 402. The display 408 can include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. In addition, an RF subsystem / baseband processor 410 can also be coupled to the processor 402. The RF subsystem / baseband processor 410 can include an antenna coupled to an RF receiver and an RF transmitter (not shown). A communication port 412 or more communication ports 412 can also be coupled to the processor 402. The communications port 412 may be adapted to couple to one or more peripheral devices 414, such as a modem, printer, computer, scanner, or camera, or to a network, such as a local area network, a remote area network, an intranet, or the Internet.

[0105] The processor 402 can control the processor-based system 400 by implementing software programs stored in the memory. The software programs may include, for example, an operating system, database software, drawing software, word processing software, media editing software, or media playback software. The memory may be operably coupled to the processor 402 to store and facilitate the execution of various programs. For example, the processor 402 may be coupled to a system memory 416, which may include one or more of a spin torque transfer magnetic random access memory (STT-MRAM), a magnetic random access memory (MRAM), a dynamic random access memory (DRAM), a static random access memory (SRAM), a racetrack memory, and other known memory types. The system memory 416 may include volatile memory, non-volatile memory, or a combination thereof. The system memory 416 is typically large so that it can store dynamically loaded applications and data. In some embodiments, the system memory 416 may include a semiconductor device, such as the above-mentioned microelectronic device and microelectronic device structure (e.g., microelectronic device 201 and microelectronic device structure 100, 200) or a combination thereof.

[0106] The processor 402 may also be coupled to a non-volatile memory 418, which does not mean that the system memory 416 must be volatile. The non-volatile memory 418 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory for use in conjunction with the system memory 416. The size of the non-volatile memory 418 is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. In addition, the non-volatile memory 418 may include high-capacity memory, such as disk drive memory, such as a hybrid drive including resistive memory or other types of non-volatile solid-state memory. The non-volatile memory 418 may include a microelectronic device, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 201 and microelectronic device structures 100, 200) or a combination thereof.

[0107] Thus, in at least some embodiments, an electronic device includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a memory cell string extending through alternating levels of insulating structures and conductive structures; a pillar within a stacked structure, the stacked structure including alternating levels of insulating structures and conductive structures, the pillar being laterally aligned with the memory cell string; and a conductive contact structure electrically connected to a channel material extending vertically through the memory cell string and the pillar, the conductive contact structure having a lateral dimension larger than the memory cell string.

[0108] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0109] Embodiment 1: A microelectronic device, comprising: a stacked structure comprising alternating conductive structures and insulating structures arranged in layers, each of the layers individually comprising a conductive structure and an insulating structure; a memory cell string extending vertically through the stacked structure, the memory cell string comprising a channel material extending vertically through the stacked structure; another stacked structure vertically overlying the stacked structure and comprising alternating levels of other conductive structures and other insulating structures, the other stacked structure comprising pillars vertically overlying the memory cell string, each pillar comprising another channel material electrically connected to the channel material of the memory cell string; and a conductive contact structure vertically overlying the other stacked structure, each conductive contact structure comprising a conductive contact extending at least partially into the pillar and a portion extending outside the pillar having a larger cross-sectional area than the pillar.

[0110] Embodiment 2: The microelectronic device of Embodiment 1, wherein the other conductive structure of the another stacked structure comprises a different material composition than the conductive structure of the stacked structure.

[0111] Embodiment 3: The microelectronic device of Embodiment 1 or Embodiment 2, wherein the conductive structure of the stacked structure comprises a different material composition than the conductive contact structure.

[0112] Embodiment 4: The microelectronic device of any one of Embodiments 1 to 3, wherein the conductive contact structure comprises tungsten.

[0113] Embodiment 5: The microelectronic device according to any one of Embodiments 1 to 4, further comprising an insulating material between at least two of the pillars that are horizontally adjacent to each other and extend vertically into the another stacked structure.

[0114] Embodiment 6: The microelectronic device of Embodiment 5, wherein approximately half of each conductive contact structure overlies the insulating material extending vertically into the another stacked structure.

[0115] Embodiment 7: The microelectronic device of any one of Embodiments 1 to 6, wherein the other conductive structure of the another stacked structure comprises a select gate structure.

[0116] Embodiment 8: A microelectronic device according to any one of Embodiments 1 to 7, wherein at least one of the memory cell strings is laterally offset from at least one other of the memory cell strings and laterally aligned with at least one additional of the memory cell strings.

[0117] Embodiment 9: The microelectronic device of any one of Embodiments 1 to 8, further comprising a conductive line in electrical communication with the conductive contact structure.

[0118] Embodiment 10: A microelectronic device according to any one of embodiments 1 to 9, wherein: the conductive structure of the stacked structure is in contact with a conductive pad material; and the other conductive structure of the other stacked structure is in direct contact with the other insulating structure of the other stacked structure.

[0119] Embodiment 11: The microelectronic device of any of Embodiments 1 to 10, wherein approximately half of each conductive contact structure is aligned with the insulating material extending into the other stacked structure.

[0120] Embodiment 12: A method for forming a microelectronic device, the method comprising: forming a first stacking structure including alternating levels of insulating structures and other insulating structures; forming a first pillar including channel material extending through the first stacking structure; forming a second stacking structure on the first stacking structure, the second stacking structure including alternating levels of additional insulating structures and sacrificial structures; forming a second pillar passing through the second stacking structure, the second pillar including additional channel material extending vertically through the second pillar and electrically connected to the channel material of the first pillar; forming a conductive material in the second pillar; growing additional conductive material on the second pillar to form a conductive contact; and at least partially replacing the sacrificial structure with a conductive material.

[0121] Embodiment 13: The method according to Embodiment 12, wherein forming a conductive material in the second pillar comprises: forming a sacrificial material in the second pillar; and replacing at least some of the sacrificial material in the second pillar with the conductive material.

[0122] Embodiment 14: The method of Embodiment 13, wherein replacing at least some of the sacrificial material in the second pillar with a conductive material comprises converting polysilicon to tungsten.

[0123] Embodiment 15: The method of Embodiment 13 or Embodiment 14, wherein forming a sacrificial material in the second pillar comprises forming polysilicon in the second pillar.

[0124] Embodiment 16: The method of any one of Embodiments 12 to 14, further comprising removing the other insulating structures and forming conductive structures at locations corresponding to the other insulating structures.

[0125] Embodiment 17: A method according to Embodiment 16, wherein removing the other insulating structures and forming a conductive structure at a position corresponding to the other insulating structures includes removing the other insulating structures and forming a conductive structure at a position corresponding to the other insulating structures after replacing the sacrificial structure with a conductive material.

[0126] Embodiment 18: The method of Embodiment 16 or Embodiment 17, wherein removing the other insulating structures comprises: forming a trench through the first stack and the second stack; and exposing the insulating structures to a wet etchant through the trench.

[0127] Embodiment 19: The method of any one of Embodiments 12 to 18, wherein replacing the sacrificial structure with a conductive material comprises converting a sacrificial structure comprising polysilicon to a conductive material comprising tungsten.

[0128] Embodiment 20: A microelectronic device comprising: a stacked structure comprising alternating layers of conductive structures and insulating structures; a memory cell string extending through the stacked structure, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the stacked structure; and a conductive contact structure electrically connected to the channel material of one of the memory cell strings, the conductive contact structure having a larger cross-sectional area than the at least one dielectric material and the channel material of the string.

[0129] Embodiment 21: The microelectronic device of Embodiment 20, wherein the conductive contact structure comprises beta-phase tungsten.

[0130] Embodiment 22: The microelectronic device of Embodiment 20 or Embodiment 21, further comprising a dielectric material extending through the stack structure and separating a first group of memory cell strings from a second group of memory cell strings.

[0131] Embodiment 23: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device structure, the at least one microelectronic device structure comprising: a memory cell string extending through alternating levels of insulating structures and conductive structures; a pillar within a stacked structure, the stacked structure comprising alternating levels of insulating structures and conductive structures, the pillar being laterally aligned with the memory cell string; and a conductive contact structure electrically connected to a channel material extending vertically through the memory cell string and the pillar, the conductive contact structure having a lateral dimension larger than the memory cell string.

[0132] Although certain illustrative embodiments have been described in conjunction with the accompanying drawings, those skilled in the art will recognize and appreciate that the embodiments encompassed by the present disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure, such as those claimed below, including legal equivalents. Additionally, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present disclosure.

Claims

1. A microelectronic device comprising: a stacked structure comprising alternating conductive structures and insulating structures arranged in layers, each of the layers individually comprising a conductive structure and an insulating structure, the conductive structures individually being in contact with a conductive liner material; a memory cell string extending vertically through the stacked structure, the memory cell string comprising a channel material extending vertically through the stacked structure; another stacked structure vertically overlying the stacked structure and comprising alternating levels of other conductive structures and other insulating structures, the other conductive structures directly contacting the other insulating structures, the other stacked structure comprising pillars vertically overlying the memory cell string, each pillar comprising another channel material in electrical communication with the channel material of the memory cell string; Conductive contact structures vertically overlying the other stacked structure, each conductive contact structure comprising a conductive contact extending at least partially into the pillar and a portion extending outside the pillar having a larger cross-sectional area than the pillar; as well as The conductive wire is vertically located on the conductive contact structure and is electrically connected to the conductive contact structure. 2 . The microelectronic device of claim 1 , wherein the other conductive structure of the further stacked structure comprises a different material composition than the conductive structure of the stacked structure. 3 . The microelectronic device of claim 1 , wherein the conductive structure of the stacked structure comprises a different material composition than the conductive contact structure. The microelectronic device of claim 1 , wherein the conductive contact structure comprises tungsten. 5 . The microelectronic device of claim 1 , further comprising an insulating material between at least two of the pillars that are horizontally adjacent to each other and that extends vertically into the another stacked structure and terminates vertically above the stacked structure.

6. The microelectronic device of claim 5, wherein approximately half of each conductive contact structure overlies the insulating material extending vertically into the other stacked structure.

7. The microelectronic device of claim 1, wherein the other conductive structure of the another stacked structure comprises a select gate structure.

8. A microelectronic device according to claim 1, wherein at least one of the memory cell strings is laterally offset from a nearest memory cell string in the memory cell strings in a first lateral direction and is laterally aligned with a nearest additional memory cell string in the memory cell strings in a second lateral direction.

9. The microelectronic device of claim 1, wherein approximately half of each conductive contact structure is aligned with the insulating material extending into the other stacked structure.

10. The microelectronic device of claim 1, wherein the other conductive structures and the conductive contact structures comprise substantially the same material composition, the conductive contact structures extending into lateral boundaries of the other conductive structures.

11. A method of forming a microelectronic device, the method comprising: forming a stacked structure including alternating layers of insulating structures and other insulating structures; forming a first pillar comprising a channel material extending through the stack; forming another stacked structure on the stacked structure, the other stacked structure comprising alternating levels of other insulating structures and other sacrificial structures; forming a second pillar through the another stacked structure, the second pillar comprising additional channel material extending vertically through the second pillar and in electrical communication with the channel material of the first pillar; forming a conductive material in the second pillar; growing additional conductive material on the second pillar to form a conductive contact structure; At least partially replacing the sacrificial structure with a conductive material to form other conductive structures, the conductive contact structures vertically overlying the other stacked structure, each of the conductive contact structures comprising a conductive contact extending at least partially into the second pillar and a portion extending outside the second pillar having a larger cross-sectional area than the second pillar; removing the other insulating structures and forming a conductive structure at a position corresponding to the other insulating structures; The stacked structure includes alternating conductive structures and insulating structures arranged in layers, the conductive structures individually contacting the conductive liner material, each of the layers individually including a conductive structure and an insulating structure; a memory cell string extending vertically through the stacked structure, the memory cell string comprising the channel material extending vertically through the stacked structure; the other stacked structure vertically overlying the stacked structure and comprising alternating levels of the other conductive structures and the other insulating structures, the other conductive structures directly contacting the other insulating structures, the other stacked structure comprising the second pillars vertically overlying the memory cell string, each of the second pillars comprising another channel material in electrical communication with the channel material of the memory cell string; and A conductive line is formed, which is vertically located on the conductive contact structure and is electrically connected to the conductive contact structure.

12. The method of claim 11, wherein forming a conductive material in the second pillar comprises: forming a sacrificial material in the second pillar; as well as At least some of the sacrificial material in the second pillar is replaced with the conductive material.

13. The method of claim 12, wherein replacing at least some of the sacrificial material in the second pillar with a conductive material comprises converting polysilicon to tungsten.

14. The method of claim 12, wherein forming a sacrificial material in the second pillar comprises forming polysilicon in the second pillar.

15. The method of claim 11, wherein removing the other insulating structures and forming the conductive structures at positions corresponding to the other insulating structures comprises removing the other insulating structures and forming the other conductive structures at positions corresponding to the other insulating structures after replacing the sacrificial structures with conductive materials.

16. The method of claim 11, wherein removing the other insulating structures comprises: forming a slot through the stack and the further stack; as well as The insulating structure is exposed to a wet etchant through the trench.

17. The method of claim 11, wherein replacing the sacrificial structure with a conductive material comprises converting a sacrificial structure comprising polysilicon to a conductive material comprising tungsten.

18. A microelectronic device comprising: a stacked structure comprising alternating layers of conductive structures and insulating structures, the conductive structures individually being in contact with a conductive liner material; a memory cell string extending through the stack structure, the memory cell string comprising at least one dielectric material and a channel material extending vertically through the stack structure; another stacked structure vertically overlying the stacked structure and comprising alternating levels of other conductive structures and other insulating structures, the other conductive structures directly contacting the other insulating structures; as well as A conductive contact structure electrically connected to the channel material of one of the memory cell strings, the conductive contact structure comprising a first portion extending into the stacked structure and a second portion vertically located above the stacked structure and having a larger cross-sectional area than the at least one dielectric material and the channel material of the memory cell string, the first portion and the second portion comprising substantially the same material composition, the conductive contact structure comprising tungsten of a different phase from the conductive structure of the stacked structure.

19. The microelectronic device of claim 18, wherein the conductive contact structure includes a greater amount of beta-phase tungsten than alpha-phase tungsten.

20. The microelectronic device of claim 18, further comprising a dielectric material extending through the stacked structure and separating a first group of memory cell strings from a second group of memory cell strings.

21. The microelectronic device according to claim 18, further comprising a conductive line vertically covering the second portion, the second portion being vertically located between the first portion and the conductive line.

22. An electronic system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; as well as a memory device operatively coupled to the processor device and comprising at least one microelectronic device structure, the at least one microelectronic device structure comprising: a string of memory cells extending through alternating levels of insulating and conductive structures; a pillar within a stacked structure, the stacked structure vertically overlying the memory cell string and comprising alternating levels of other insulating structures and other conductive structures, the pillar being laterally aligned with the memory cell string, the other conductive structures of the pillar comprising a different material composition than the conductive structures of the memory cell string; a conductive contact structure electrically connected to a channel material extending vertically through the memory cell string and the pillar, the conductive contact structure having a larger lateral dimension than the memory cell string in a first lateral direction and a second lateral direction, the conductive contact structure including a material composition different from that of the channel material, each of the conductive contact structures extending at least partially into the stacked structure; and A select gate trench extends vertically through the alternating levels of the further insulating structures and the further conductive structures and terminates before the stacked structure, the conductive contact structure extending laterally into lateral boundaries of the select gate trench.

23. The electronic system of claim 22, wherein the conductive contact structures individually comprise tungsten, greater than or equal to about 60% of the tungsten comprising beta-phase tungsten.

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